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dt-bindings: net: Convert amd,xgbe-seattle-v1a to DT schema
Convert amd,xgbe-seattle-v1a binding to DT schema format. It's a
straight-forward conversion.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20251013213049.686797-2-robh@kernel.org
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
authored by
Rob Herring (Arm)
and committed by
Paolo Abeni
00922eea
6608b952
+147
-76
+147
Documentation/devicetree/bindings/net/amd,xgbe-seattle-v1a.yaml
+147
Documentation/devicetree/bindings/net/amd,xgbe-seattle-v1a.yaml
···
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/amd,xgbe-seattle-v1a.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: AMD XGBE Seattle v1a
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maintainers:
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- Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
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allOf:
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- $ref: /schemas/net/ethernet-controller.yaml#
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properties:
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compatible:
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const: amd,xgbe-seattle-v1a
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reg:
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items:
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- description: MAC registers
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- description: PCS registers
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- description: SerDes Rx/Tx registers
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- description: SerDes integration registers (1/2)
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- description: SerDes integration registers (2/2)
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+
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interrupts:
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description: Device interrupts. The first entry is the general device
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interrupt. If amd,per-channel-interrupt is specified, each DMA channel
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interrupt must be specified. The last entry is the PCS auto-negotiation
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interrupt.
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minItems: 2
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maxItems: 6
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+
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clocks:
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items:
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- description: DMA clock for the device
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- description: PTP clock for the device
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clock-names:
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items:
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- const: dma_clk
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- const: ptp_clk
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+
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iommus:
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maxItems: 1
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phy-mode: true
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dma-coherent: true
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amd,per-channel-interrupt:
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description: Indicates that Rx and Tx complete will generate a unique
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interrupt for each DMA channel.
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type: boolean
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amd,speed-set:
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description: >
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Speed capabilities of the device.
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0 = 1GbE and 10GbE
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1 = 2.5GbE and 10GbE
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [0, 1]
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amd,serdes-blwc:
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description: Baseline wandering correction enablement for each speed.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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minItems: 3
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maxItems: 3
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items:
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enum: [0, 1]
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amd,serdes-cdr-rate:
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description: CDR rate speed selection for each speed.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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items:
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- description: CDR rate for 1GbE
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- description: CDR rate for 2.5GbE
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- description: CDR rate for 10GbE
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+
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amd,serdes-pq-skew:
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description: PQ data sampling skew for each speed.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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items:
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- description: PQ skew for 1GbE
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- description: PQ skew for 2.5GbE
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- description: PQ skew for 10GbE
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+
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amd,serdes-tx-amp:
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description: TX amplitude boost for each speed.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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items:
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- description: TX amplitude for 1GbE
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- description: TX amplitude for 2.5GbE
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- description: TX amplitude for 10GbE
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+
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amd,serdes-dfe-tap-config:
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description: DFE taps available to run for each speed.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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items:
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- description: DFE taps available for 1GbE
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- description: DFE taps available for 2.5GbE
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- description: DFE taps available for 10GbE
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amd,serdes-dfe-tap-enable:
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description: DFE taps to enable for each speed.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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items:
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- description: DFE taps to enable for 1GbE
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- description: DFE taps to enable for 2.5GbE
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- description: DFE taps to enable for 10GbE
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- phy-mode
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+
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unevaluatedProperties: false
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examples:
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- |
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ethernet@e0700000 {
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compatible = "amd,xgbe-seattle-v1a";
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reg = <0xe0700000 0x80000>,
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<0xe0780000 0x80000>,
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<0xe1240800 0x00400>,
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<0xe1250000 0x00060>,
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<0xe1250080 0x00004>;
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interrupts = <0 325 4>,
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<0 326 1>, <0 327 1>, <0 328 1>, <0 329 1>,
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<0 323 4>;
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amd,per-channel-interrupt;
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clocks = <&xgbe_dma_clk>, <&xgbe_ptp_clk>;
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clock-names = "dma_clk", "ptp_clk";
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phy-mode = "xgmii";
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mac-address = [ 02 a1 a2 a3 a4 a5 ];
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amd,speed-set = <0>;
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amd,serdes-blwc = <1>, <1>, <0>;
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amd,serdes-cdr-rate = <2>, <2>, <7>;
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amd,serdes-pq-skew = <10>, <10>, <30>;
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amd,serdes-tx-amp = <15>, <15>, <10>;
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amd,serdes-dfe-tap-config = <3>, <3>, <1>;
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amd,serdes-dfe-tap-enable = <0>, <0>, <127>;
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};
-76
Documentation/devicetree/bindings/net/amd-xgbe.txt
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Documentation/devicetree/bindings/net/amd-xgbe.txt
···
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* AMD 10GbE driver (amd-xgbe)
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Required properties:
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- compatible: Should be "amd,xgbe-seattle-v1a"
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- reg: Address and length of the register sets for the device
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- MAC registers
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- PCS registers
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- SerDes Rx/Tx registers
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- SerDes integration registers (1/2)
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- SerDes integration registers (2/2)
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- interrupts: Should contain the amd-xgbe interrupt(s). The first interrupt
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listed is required and is the general device interrupt. If the optional
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amd,per-channel-interrupt property is specified, then one additional
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interrupt for each DMA channel supported by the device should be specified.
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The last interrupt listed should be the PCS auto-negotiation interrupt.
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- clocks:
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- DMA clock for the amd-xgbe device (used for calculating the
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correct Rx interrupt watchdog timer value on a DMA channel
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for coalescing)
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- PTP clock for the amd-xgbe device
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- clock-names: Should be the names of the clocks
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- "dma_clk" for the DMA clock
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- "ptp_clk" for the PTP clock
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- phy-mode: See ethernet.txt file in the same directory
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-
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Optional properties:
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- dma-coherent: Present if dma operations are coherent
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- amd,per-channel-interrupt: Indicates that Rx and Tx complete will generate
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a unique interrupt for each DMA channel - this requires an additional
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interrupt be configured for each DMA channel
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- amd,speed-set: Speed capabilities of the device
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0 - 1GbE and 10GbE (default)
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1 - 2.5GbE and 10GbE
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The MAC address will be determined using the optional properties defined in
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ethernet.txt.
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The following optional properties are represented by an array with each
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value corresponding to a particular speed. The first array value represents
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the setting for the 1GbE speed, the second value for the 2.5GbE speed and
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the third value for the 10GbE speed. All three values are required if the
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property is used.
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- amd,serdes-blwc: Baseline wandering correction enablement
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0 - Off
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1 - On
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- amd,serdes-cdr-rate: CDR rate speed selection
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- amd,serdes-pq-skew: PQ (data sampling) skew
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- amd,serdes-tx-amp: TX amplitude boost
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- amd,serdes-dfe-tap-config: DFE taps available to run
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- amd,serdes-dfe-tap-enable: DFE taps to enable
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Example:
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xgbe@e0700000 {
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compatible = "amd,xgbe-seattle-v1a";
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reg = <0 0xe0700000 0 0x80000>,
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<0 0xe0780000 0 0x80000>,
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<0 0xe1240800 0 0x00400>,
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<0 0xe1250000 0 0x00060>,
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<0 0xe1250080 0 0x00004>;
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interrupt-parent = <&gic>;
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interrupts = <0 325 4>,
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<0 326 1>, <0 327 1>, <0 328 1>, <0 329 1>,
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<0 323 4>;
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amd,per-channel-interrupt;
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clocks = <&xgbe_dma_clk>, <&xgbe_ptp_clk>;
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clock-names = "dma_clk", "ptp_clk";
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phy-mode = "xgmii";
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mac-address = [ 02 a1 a2 a3 a4 a5 ];
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amd,speed-set = <0>;
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amd,serdes-blwc = <1>, <1>, <0>;
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amd,serdes-cdr-rate = <2>, <2>, <7>;
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amd,serdes-pq-skew = <10>, <10>, <30>;
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amd,serdes-tx-amp = <15>, <15>, <10>;
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amd,serdes-dfe-tap-config = <3>, <3>, <1>;
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amd,serdes-dfe-tap-enable = <0>, <0>, <127>;
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};