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dt-bindings: net: Convert amd,xgbe-seattle-v1a to DT schema

Convert amd,xgbe-seattle-v1a binding to DT schema format. It's a
straight-forward conversion.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20251013213049.686797-2-robh@kernel.org
Signed-off-by: Paolo Abeni <pabeni@redhat.com>

authored by

Rob Herring (Arm) and committed by
Paolo Abeni
00922eea 6608b952

+147 -76
+147
Documentation/devicetree/bindings/net/amd,xgbe-seattle-v1a.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/net/amd,xgbe-seattle-v1a.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: AMD XGBE Seattle v1a 8 + 9 + maintainers: 10 + - Shyam Sundar S K <Shyam-sundar.S-k@amd.com> 11 + 12 + allOf: 13 + - $ref: /schemas/net/ethernet-controller.yaml# 14 + 15 + properties: 16 + compatible: 17 + const: amd,xgbe-seattle-v1a 18 + 19 + reg: 20 + items: 21 + - description: MAC registers 22 + - description: PCS registers 23 + - description: SerDes Rx/Tx registers 24 + - description: SerDes integration registers (1/2) 25 + - description: SerDes integration registers (2/2) 26 + 27 + interrupts: 28 + description: Device interrupts. The first entry is the general device 29 + interrupt. If amd,per-channel-interrupt is specified, each DMA channel 30 + interrupt must be specified. The last entry is the PCS auto-negotiation 31 + interrupt. 32 + minItems: 2 33 + maxItems: 6 34 + 35 + clocks: 36 + items: 37 + - description: DMA clock for the device 38 + - description: PTP clock for the device 39 + 40 + clock-names: 41 + items: 42 + - const: dma_clk 43 + - const: ptp_clk 44 + 45 + iommus: 46 + maxItems: 1 47 + 48 + phy-mode: true 49 + 50 + dma-coherent: true 51 + 52 + amd,per-channel-interrupt: 53 + description: Indicates that Rx and Tx complete will generate a unique 54 + interrupt for each DMA channel. 55 + type: boolean 56 + 57 + amd,speed-set: 58 + description: > 59 + Speed capabilities of the device. 60 + 0 = 1GbE and 10GbE 61 + 1 = 2.5GbE and 10GbE 62 + $ref: /schemas/types.yaml#/definitions/uint32 63 + enum: [0, 1] 64 + 65 + amd,serdes-blwc: 66 + description: Baseline wandering correction enablement for each speed. 67 + $ref: /schemas/types.yaml#/definitions/uint32-array 68 + minItems: 3 69 + maxItems: 3 70 + items: 71 + enum: [0, 1] 72 + 73 + amd,serdes-cdr-rate: 74 + description: CDR rate speed selection for each speed. 75 + $ref: /schemas/types.yaml#/definitions/uint32-array 76 + items: 77 + - description: CDR rate for 1GbE 78 + - description: CDR rate for 2.5GbE 79 + - description: CDR rate for 10GbE 80 + 81 + amd,serdes-pq-skew: 82 + description: PQ data sampling skew for each speed. 83 + $ref: /schemas/types.yaml#/definitions/uint32-array 84 + items: 85 + - description: PQ skew for 1GbE 86 + - description: PQ skew for 2.5GbE 87 + - description: PQ skew for 10GbE 88 + 89 + amd,serdes-tx-amp: 90 + description: TX amplitude boost for each speed. 91 + $ref: /schemas/types.yaml#/definitions/uint32-array 92 + items: 93 + - description: TX amplitude for 1GbE 94 + - description: TX amplitude for 2.5GbE 95 + - description: TX amplitude for 10GbE 96 + 97 + amd,serdes-dfe-tap-config: 98 + description: DFE taps available to run for each speed. 99 + $ref: /schemas/types.yaml#/definitions/uint32-array 100 + items: 101 + - description: DFE taps available for 1GbE 102 + - description: DFE taps available for 2.5GbE 103 + - description: DFE taps available for 10GbE 104 + 105 + amd,serdes-dfe-tap-enable: 106 + description: DFE taps to enable for each speed. 107 + $ref: /schemas/types.yaml#/definitions/uint32-array 108 + items: 109 + - description: DFE taps to enable for 1GbE 110 + - description: DFE taps to enable for 2.5GbE 111 + - description: DFE taps to enable for 10GbE 112 + 113 + required: 114 + - compatible 115 + - reg 116 + - interrupts 117 + - clocks 118 + - clock-names 119 + - phy-mode 120 + 121 + unevaluatedProperties: false 122 + 123 + examples: 124 + - | 125 + ethernet@e0700000 { 126 + compatible = "amd,xgbe-seattle-v1a"; 127 + reg = <0xe0700000 0x80000>, 128 + <0xe0780000 0x80000>, 129 + <0xe1240800 0x00400>, 130 + <0xe1250000 0x00060>, 131 + <0xe1250080 0x00004>; 132 + interrupts = <0 325 4>, 133 + <0 326 1>, <0 327 1>, <0 328 1>, <0 329 1>, 134 + <0 323 4>; 135 + amd,per-channel-interrupt; 136 + clocks = <&xgbe_dma_clk>, <&xgbe_ptp_clk>; 137 + clock-names = "dma_clk", "ptp_clk"; 138 + phy-mode = "xgmii"; 139 + mac-address = [ 02 a1 a2 a3 a4 a5 ]; 140 + amd,speed-set = <0>; 141 + amd,serdes-blwc = <1>, <1>, <0>; 142 + amd,serdes-cdr-rate = <2>, <2>, <7>; 143 + amd,serdes-pq-skew = <10>, <10>, <30>; 144 + amd,serdes-tx-amp = <15>, <15>, <10>; 145 + amd,serdes-dfe-tap-config = <3>, <3>, <1>; 146 + amd,serdes-dfe-tap-enable = <0>, <0>, <127>; 147 + };
-76
Documentation/devicetree/bindings/net/amd-xgbe.txt
··· 1 - * AMD 10GbE driver (amd-xgbe) 2 - 3 - Required properties: 4 - - compatible: Should be "amd,xgbe-seattle-v1a" 5 - - reg: Address and length of the register sets for the device 6 - - MAC registers 7 - - PCS registers 8 - - SerDes Rx/Tx registers 9 - - SerDes integration registers (1/2) 10 - - SerDes integration registers (2/2) 11 - - interrupts: Should contain the amd-xgbe interrupt(s). The first interrupt 12 - listed is required and is the general device interrupt. If the optional 13 - amd,per-channel-interrupt property is specified, then one additional 14 - interrupt for each DMA channel supported by the device should be specified. 15 - The last interrupt listed should be the PCS auto-negotiation interrupt. 16 - - clocks: 17 - - DMA clock for the amd-xgbe device (used for calculating the 18 - correct Rx interrupt watchdog timer value on a DMA channel 19 - for coalescing) 20 - - PTP clock for the amd-xgbe device 21 - - clock-names: Should be the names of the clocks 22 - - "dma_clk" for the DMA clock 23 - - "ptp_clk" for the PTP clock 24 - - phy-mode: See ethernet.txt file in the same directory 25 - 26 - Optional properties: 27 - - dma-coherent: Present if dma operations are coherent 28 - - amd,per-channel-interrupt: Indicates that Rx and Tx complete will generate 29 - a unique interrupt for each DMA channel - this requires an additional 30 - interrupt be configured for each DMA channel 31 - - amd,speed-set: Speed capabilities of the device 32 - 0 - 1GbE and 10GbE (default) 33 - 1 - 2.5GbE and 10GbE 34 - 35 - The MAC address will be determined using the optional properties defined in 36 - ethernet.txt. 37 - 38 - The following optional properties are represented by an array with each 39 - value corresponding to a particular speed. The first array value represents 40 - the setting for the 1GbE speed, the second value for the 2.5GbE speed and 41 - the third value for the 10GbE speed. All three values are required if the 42 - property is used. 43 - - amd,serdes-blwc: Baseline wandering correction enablement 44 - 0 - Off 45 - 1 - On 46 - - amd,serdes-cdr-rate: CDR rate speed selection 47 - - amd,serdes-pq-skew: PQ (data sampling) skew 48 - - amd,serdes-tx-amp: TX amplitude boost 49 - - amd,serdes-dfe-tap-config: DFE taps available to run 50 - - amd,serdes-dfe-tap-enable: DFE taps to enable 51 - 52 - Example: 53 - xgbe@e0700000 { 54 - compatible = "amd,xgbe-seattle-v1a"; 55 - reg = <0 0xe0700000 0 0x80000>, 56 - <0 0xe0780000 0 0x80000>, 57 - <0 0xe1240800 0 0x00400>, 58 - <0 0xe1250000 0 0x00060>, 59 - <0 0xe1250080 0 0x00004>; 60 - interrupt-parent = <&gic>; 61 - interrupts = <0 325 4>, 62 - <0 326 1>, <0 327 1>, <0 328 1>, <0 329 1>, 63 - <0 323 4>; 64 - amd,per-channel-interrupt; 65 - clocks = <&xgbe_dma_clk>, <&xgbe_ptp_clk>; 66 - clock-names = "dma_clk", "ptp_clk"; 67 - phy-mode = "xgmii"; 68 - mac-address = [ 02 a1 a2 a3 a4 a5 ]; 69 - amd,speed-set = <0>; 70 - amd,serdes-blwc = <1>, <1>, <0>; 71 - amd,serdes-cdr-rate = <2>, <2>, <7>; 72 - amd,serdes-pq-skew = <10>, <10>, <30>; 73 - amd,serdes-tx-amp = <15>, <15>, <10>; 74 - amd,serdes-dfe-tap-config = <3>, <3>, <1>; 75 - amd,serdes-dfe-tap-enable = <0>, <0>, <127>; 76 - };