Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Olof Johansson:
"We didn't have any fixes sent up for -rc2, so this is a slightly
larger batch. A bit all over the place platform-wise; OMAP, at91,
marvell, renesas, sunxi, ux500, etc.
I tried to summarize highlights but there isn't a whole lot to point
out. Lots of little things fixed all over. A couple of defconfig
updates due to new/changing options."
* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (44 commits)
ARM: at91/sama5: fix incorrect PMC pcr div definition
ARM: at91/dt: fix macb pinctrl_macb_rmii_mii_alt definition
ARM: at91: at91sam9n12: move external irq declatation to DT
ARM: shmobile: marzen: Use error values in usb_power_*
ARM: tegra: defconfig fixes
ARM: nomadik: fix IRQ assignment for SMC ethernet
ARM: vt8500: Add missing NULL terminator in dt_compat
clk: tegra: add ac97 controller clock
clk: tegra: remove USB from clk init table
ARM: dts: mvebu: Fix wrong the address reg value for the L2-cache node
ARM: plat-orion: Fix num_resources and id for ge10 and ge11
ARM: OMAP2+: hwmod: Remove sysc slave idle and auto idle apis
SERIAL: OMAP: Remove the slave idle handling from the driver
ARM: OMAP2+: serial: Remove the un-used slave idle hooks
ARM: OMAP2+: hwmod-data: UART IP needs software control to manage sidle modes
ARM: OMAP2+: hwmod: Add a new flag to handle SIDLE in SWSUP only in active
ARM: OMAP2+: hwmod: Fix sidle programming in _enable_sysc()/_idle_sysc()
arm: mvebu: fix the 'ranges' property to handle PCIe
ARM: mvebu: select ARCH_REQUIRE_GPIOLIB for mvebu platform
ARM: AM33XX: Add missing .clkdm_name to clkdiv32k_ick clock
...
+185
-236
+1
-1
Documentation/devicetree/bindings/net/macb.txt
+1
-1
Documentation/devicetree/bindings/net/macb.txt
···
4
4
- compatible: Should be "cdns,[<chip>-]{macb|gem}"
5
5
Use "cdns,at91sam9260-macb" Atmel at91sam9260 and at91sam9263 SoCs.
6
6
Use "cdns,at32ap7000-macb" for other 10/100 usage or use the generic form: "cdns,macb".
7
-
Use "cnds,pc302-gem" for Picochip picoXcell pc302 and later devices based on
7
+
Use "cdns,pc302-gem" for Picochip picoXcell pc302 and later devices based on
8
8
the Cadence GEM, or the generic form: "cdns,gem".
9
9
- reg: Address and length of the register set for the device
10
10
- interrupts: Should contain macb interrupt
+3
-1
arch/arm/boot/dts/Makefile
+3
-1
arch/arm/boot/dts/Makefile
···
177
177
spear320-evb.dtb \
178
178
spear320-hmi.dtb
179
179
dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb
180
-
dtb-$(CONFIG_ARCH_SUNXI) += sun4i-a10-cubieboard.dtb \
180
+
dtb-$(CONFIG_ARCH_SUNXI) += \
181
+
sun4i-a10-cubieboard.dtb \
182
+
sun4i-a10-mini-xplus.dtb \
181
183
sun4i-a10-hackberry.dtb \
182
184
sun5i-a13-olinuxino.dtb
183
185
dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
+2
-1
arch/arm/boot/dts/armada-370-xp.dtsi
+2
-1
arch/arm/boot/dts/armada-370-xp.dtsi
···
33
33
#size-cells = <1>;
34
34
compatible = "simple-bus";
35
35
interrupt-parent = <&mpic>;
36
-
ranges = <0 0 0xd0000000 0x100000>;
36
+
ranges = <0 0 0xd0000000 0x0100000 /* internal registers */
37
+
0xe0000000 0 0xe0000000 0x8100000 /* PCIe */>;
37
38
38
39
internal-regs {
39
40
compatible = "simple-bus";
+4
-3
arch/arm/boot/dts/armada-370.dtsi
+4
-3
arch/arm/boot/dts/armada-370.dtsi
···
29
29
};
30
30
31
31
soc {
32
-
ranges = <0 0xd0000000 0x100000>;
32
+
ranges = <0 0xd0000000 0x0100000 /* internal registers */
33
+
0xe0000000 0xe0000000 0x8100000 /* PCIe */>;
33
34
internal-regs {
34
35
system-controller@18200 {
35
36
compatible = "marvell,armada-370-xp-system-controller";
···
39
38
40
39
L2: l2-cache {
41
40
compatible = "marvell,aurora-outer-cache";
42
-
reg = <0xd0008000 0x1000>;
41
+
reg = <0x08000 0x1000>;
43
42
cache-id-part = <0x100>;
44
43
wt-override;
45
44
};
46
45
47
-
mpic: interrupt-controller@20000 {
46
+
interrupt-controller@20000 {
48
47
reg = <0x20a00 0x1d0>, <0x21870 0x58>;
49
48
};
50
49
+3
arch/arm/boot/dts/armada-xp-gp.dts
+3
arch/arm/boot/dts/armada-xp-gp.dts
+3
arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
+3
arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
+1
-1
arch/arm/boot/dts/armada-xp.dtsi
+1
-1
arch/arm/boot/dts/armada-xp.dtsi
+1
-1
arch/arm/boot/dts/at91sam9260.dtsi
+1
-1
arch/arm/boot/dts/at91sam9260.dtsi
···
264
264
atmel,pins =
265
265
<0 10 0x2 0x0 /* PA10 periph B */
266
266
0 11 0x2 0x0 /* PA11 periph B */
267
-
0 24 0x2 0x0 /* PA24 periph B */
267
+
0 22 0x2 0x0 /* PA22 periph B */
268
268
0 25 0x2 0x0 /* PA25 periph B */
269
269
0 26 0x2 0x0 /* PA26 periph B */
270
270
0 27 0x2 0x0 /* PA27 periph B */
+1
arch/arm/boot/dts/at91sam9n12.dtsi
+1
arch/arm/boot/dts/at91sam9n12.dtsi
+1
-1
arch/arm/boot/dts/at91sam9x25ek.dts
+1
-1
arch/arm/boot/dts/at91sam9x25ek.dts
+1
-1
arch/arm/boot/dts/omap3.dtsi
+1
-1
arch/arm/boot/dts/omap3.dtsi
+1
-11
arch/arm/boot/dts/sama5d3.dtsi
+1
-11
arch/arm/boot/dts/sama5d3.dtsi
···
75
75
compatible = "atmel,at91sam9x5-spi";
76
76
reg = <0xf0004000 0x100>;
77
77
interrupts = <24 4 3>;
78
-
cs-gpios = <&pioD 13 0
79
-
&pioD 14 0 /* conflicts with SCK0 and CANRX0 */
80
-
&pioD 15 0 /* conflicts with CTS0 and CANTX0 */
81
-
&pioD 16 0 /* conflicts with RTS0 and PWMFI3 */
82
-
>;
83
78
pinctrl-names = "default";
84
79
pinctrl-0 = <&pinctrl_spi0>;
85
80
status = "disabled";
···
151
156
};
152
157
153
158
macb0: ethernet@f0028000 {
154
-
compatible = "cnds,pc302-gem", "cdns,gem";
159
+
compatible = "cdns,pc302-gem", "cdns,gem";
155
160
reg = <0xf0028000 0x100>;
156
161
interrupts = <34 4 3>;
157
162
pinctrl-names = "default";
···
198
203
compatible = "atmel,at91sam9x5-spi";
199
204
reg = <0xf8008000 0x100>;
200
205
interrupts = <25 4 3>;
201
-
cs-gpios = <&pioC 25 0
202
-
&pioC 26 0 /* conflitcs with TWD1 and ISI_D11 */
203
-
&pioC 27 0 /* conflitcs with TWCK1 and ISI_D10 */
204
-
&pioC 28 0 /* conflitcs with PWMFI0 and ISI_D9 */
205
-
>;
206
206
pinctrl-names = "default";
207
207
pinctrl-0 = <&pinctrl_spi1>;
208
208
status = "disabled";
+4
arch/arm/boot/dts/sama5d3xcm.dtsi
+4
arch/arm/boot/dts/sama5d3xcm.dtsi
+9
-3
arch/arm/boot/dts/ste-nomadik-s8815.dts
+9
-3
arch/arm/boot/dts/ste-nomadik-s8815.dts
···
14
14
bootargs = "root=/dev/ram0 console=ttyAMA1,115200n8 earlyprintk";
15
15
};
16
16
17
+
/* This is where the interrupt is routed on the S8815 board */
18
+
external-bus@34000000 {
19
+
ethernet@300 {
20
+
interrupt-parent = <&gpio3>;
21
+
interrupts = <8 0x1>;
22
+
};
23
+
};
24
+
17
25
/* Custom board node with GPIO pins to active etc */
18
26
usb-s8815 {
19
27
/* The S8815 is using this very GPIO pin for the SMSC91x IRQs */
20
28
ethernet-gpio {
21
-
gpios = <&gpio3 19 0x1>;
22
-
interrupts = <19 0x1>;
23
-
interrupt-parent = <&gpio3>;
29
+
gpios = <&gpio3 8 0x1>;
24
30
};
25
31
/* This will bias the MMC/SD card detect line */
26
32
mmcsd-gpio {
+2
-2
arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
+2
-2
arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
+1
arch/arm/configs/omap2plus_defconfig
+1
arch/arm/configs/omap2plus_defconfig
+2
-1
arch/arm/configs/tegra_defconfig
+2
-1
arch/arm/configs/tegra_defconfig
···
153
153
CONFIG_MEDIA_USB_SUPPORT=y
154
154
CONFIG_USB_VIDEO_CLASS=m
155
155
CONFIG_DRM=y
156
+
CONFIG_TEGRA_HOST1X=y
156
157
CONFIG_DRM_TEGRA=y
157
158
CONFIG_BACKLIGHT_LCD_SUPPORT=y
158
159
# CONFIG_LCD_CLASS_DEVICE is not set
···
203
202
CONFIG_STAGING=y
204
203
CONFIG_SENSORS_ISL29018=y
205
204
CONFIG_SENSORS_ISL29028=y
206
-
CONFIG_SENSORS_AK8975=y
205
+
CONFIG_AK8975=y
207
206
CONFIG_MFD_NVEC=y
208
207
CONFIG_KEYBOARD_NVEC=y
209
208
CONFIG_SERIO_NVEC_PS2=y
+3
-3
arch/arm/include/debug/ux500.S
+3
-3
arch/arm/include/debug/ux500.S
···
24
24
#define U8500_UART0_PHYS_BASE (0x80120000)
25
25
#define U8500_UART1_PHYS_BASE (0x80121000)
26
26
#define U8500_UART2_PHYS_BASE (0x80007000)
27
-
#define U8500_UART0_VIRT_BASE (0xa8120000)
28
-
#define U8500_UART1_VIRT_BASE (0xa8121000)
29
-
#define U8500_UART2_VIRT_BASE (0xa8007000)
27
+
#define U8500_UART0_VIRT_BASE (0xf8120000)
28
+
#define U8500_UART1_VIRT_BASE (0xf8121000)
29
+
#define U8500_UART2_VIRT_BASE (0xf8007000)
30
30
#define __UX500_PHYS_UART(n) U8500_UART##n##_PHYS_BASE
31
31
#define __UX500_VIRT_UART(n) U8500_UART##n##_VIRT_BASE
32
32
#endif
+5
-2
arch/arm/mach-at91/at91rm9200_time.c
+5
-2
arch/arm/mach-at91/at91rm9200_time.c
···
174
174
static struct clock_event_device clkevt = {
175
175
.name = "at91_tick",
176
176
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
177
+
.shift = 32,
177
178
.rating = 150,
178
179
.set_next_event = clkevt32k_next_event,
179
180
.set_mode = clkevt32k_mode,
···
265
264
at91_st_write(AT91_ST_RTMR, 1);
266
265
267
266
/* Setup timer clockevent, with minimum of two ticks (important!!) */
267
+
clkevt.mult = div_sc(AT91_SLOW_CLOCK, NSEC_PER_SEC, clkevt.shift);
268
+
clkevt.max_delta_ns = clockevent_delta2ns(AT91_ST_ALMV, &clkevt);
269
+
clkevt.min_delta_ns = clockevent_delta2ns(2, &clkevt) + 1;
268
270
clkevt.cpumask = cpumask_of(0);
269
-
clockevents_config_and_register(&clkevt, AT91_SLOW_CLOCK,
270
-
2, AT91_ST_ALMV);
271
+
clockevents_register_device(&clkevt);
271
272
272
273
/* register clocksource */
273
274
clocksource_register_hz(&clk32k, AT91_SLOW_CLOCK);
-6
arch/arm/mach-at91/at91sam9n12.c
-6
arch/arm/mach-at91/at91sam9n12.c
···
223
223
at91_init_sram(0, AT91SAM9N12_SRAM_BASE, AT91SAM9N12_SRAM_SIZE);
224
224
}
225
225
226
-
void __init at91sam9n12_initialize(void)
227
-
{
228
-
at91_extern_irq = (1 << AT91SAM9N12_ID_IRQ0);
229
-
}
230
-
231
226
AT91_SOC_START(at91sam9n12)
232
227
.map_io = at91sam9n12_map_io,
233
228
.register_clocks = at91sam9n12_register_clocks,
234
-
.init = at91sam9n12_initialize,
235
229
AT91_SOC_END
+3
-3
arch/arm/mach-at91/include/mach/at91_pmc.h
+3
-3
arch/arm/mach-at91/include/mach/at91_pmc.h
···
179
179
#define AT91_PMC_PCR_CMD (0x1 << 12) /* Command (read=0, write=1) */
180
180
#define AT91_PMC_PCR_DIV(n) ((n) << 16) /* Divisor Value */
181
181
#define AT91_PMC_PCR_DIV0 0x0 /* Peripheral clock is MCK */
182
-
#define AT91_PMC_PCR_DIV2 0x2 /* Peripheral clock is MCK/2 */
183
-
#define AT91_PMC_PCR_DIV4 0x4 /* Peripheral clock is MCK/4 */
184
-
#define AT91_PMC_PCR_DIV8 0x8 /* Peripheral clock is MCK/8 */
182
+
#define AT91_PMC_PCR_DIV2 0x1 /* Peripheral clock is MCK/2 */
183
+
#define AT91_PMC_PCR_DIV4 0x2 /* Peripheral clock is MCK/4 */
184
+
#define AT91_PMC_PCR_DIV8 0x3 /* Peripheral clock is MCK/8 */
185
185
#define AT91_PMC_PCR_EN (0x1 << 28) /* Enable */
186
186
187
187
#endif
+6
-5
arch/arm/mach-imx/clk-imx6q.c
+6
-5
arch/arm/mach-imx/clk-imx6q.c
···
177
177
static const char *step_sels[] = { "osc", "pll2_pfd2_396m", };
178
178
static const char *pll1_sw_sels[] = { "pll1_sys", "step", };
179
179
static const char *periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", };
180
-
static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", };
180
+
static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", "dummy", };
181
+
static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "pll2_bus", };
181
182
static const char *periph_sels[] = { "periph_pre", "periph_clk2", };
182
183
static const char *periph2_sels[] = { "periph2_pre", "periph2_clk2", };
183
184
static const char *axi_sels[] = { "periph", "pll2_pfd2_396m", "pll3_pfd1_540m", };
···
186
185
static const char *gpu_axi_sels[] = { "axi", "ahb", };
187
186
static const char *gpu2d_core_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", };
188
187
static const char *gpu3d_core_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd2_396m", };
189
-
static const char *gpu3d_shader_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd9_720m", };
188
+
static const char *gpu3d_shader_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll3_pfd0_720m", };
190
189
static const char *ipu_sels[] = { "mmdc_ch0_axi", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", };
191
190
static const char *ldb_di_sels[] = { "pll5_video", "pll2_pfd0_352m", "pll2_pfd2_396m", "mmdc_ch1_axi", "pll3_usb_otg", };
192
191
static const char *ipu_di_pre_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd1_540m", };
···
370
369
clk[pll1_sw] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels));
371
370
clk[periph_pre] = imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
372
371
clk[periph2_pre] = imx_clk_mux("periph2_pre", base + 0x18, 21, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
373
-
clk[periph_clk2_sel] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 1, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
374
-
clk[periph2_clk2_sel] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
372
+
clk[periph_clk2_sel] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
373
+
clk[periph2_clk2_sel] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels));
375
374
clk[axi_sel] = imx_clk_mux("axi_sel", base + 0x14, 6, 2, axi_sels, ARRAY_SIZE(axi_sels));
376
375
clk[esai_sel] = imx_clk_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels));
377
376
clk[asrc_sel] = imx_clk_mux("asrc_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels));
···
499
498
clk[ldb_di1] = imx_clk_gate2("ldb_di1", "ldb_di1_podf", base + 0x74, 14);
500
499
clk[ipu2_di1] = imx_clk_gate2("ipu2_di1", "ipu2_di1_sel", base + 0x74, 10);
501
500
clk[hsi_tx] = imx_clk_gate2("hsi_tx", "hsi_tx_podf", base + 0x74, 16);
502
-
clk[mlb] = imx_clk_gate2("mlb", "pll8_mlb", base + 0x74, 18);
501
+
clk[mlb] = imx_clk_gate2("mlb", "axi", base + 0x74, 18);
503
502
clk[mmdc_ch0_axi] = imx_clk_gate2("mmdc_ch0_axi", "mmdc_ch0_axi_podf", base + 0x74, 20);
504
503
clk[mmdc_ch1_axi] = imx_clk_gate2("mmdc_ch1_axi", "mmdc_ch1_axi_podf", base + 0x74, 22);
505
504
clk[ocram] = imx_clk_gate2("ocram", "ahb", base + 0x74, 28);
+12
arch/arm/mach-imx/headsmp.S
+12
arch/arm/mach-imx/headsmp.S
···
18
18
.section ".text.head", "ax"
19
19
20
20
#ifdef CONFIG_SMP
21
+
diag_reg_offset:
22
+
.word g_diag_reg - .
23
+
24
+
.macro set_diag_reg
25
+
adr r0, diag_reg_offset
26
+
ldr r1, [r0]
27
+
add r1, r1, r0 @ r1 = physical &g_diag_reg
28
+
ldr r0, [r1]
29
+
mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
30
+
.endm
31
+
21
32
ENTRY(v7_secondary_startup)
22
33
bl v7_invalidate_l1
34
+
set_diag_reg
23
35
b secondary_startup
24
36
ENDPROC(v7_secondary_startup)
25
37
#endif
+14
arch/arm/mach-imx/platsmp.c
+14
arch/arm/mach-imx/platsmp.c
···
12
12
13
13
#include <linux/init.h>
14
14
#include <linux/smp.h>
15
+
#include <asm/cacheflush.h>
15
16
#include <asm/page.h>
16
17
#include <asm/smp_scu.h>
17
18
#include <asm/mach/map.h>
···
22
21
23
22
#define SCU_STANDBY_ENABLE (1 << 5)
24
23
24
+
u32 g_diag_reg;
25
25
static void __iomem *scu_base;
26
26
27
27
static struct map_desc scu_io_desc __initdata = {
···
82
80
static void __init imx_smp_prepare_cpus(unsigned int max_cpus)
83
81
{
84
82
imx_smp_prepare();
83
+
84
+
/*
85
+
* The diagnostic register holds the errata bits. Mostly bootloader
86
+
* does not bring up secondary cores, so that when errata bits are set
87
+
* in bootloader, they are set only for boot cpu. But on a SMP
88
+
* configuration, it should be equally done on every single core.
89
+
* Read the register from boot cpu here, and will replicate it into
90
+
* secondary cores when booting them.
91
+
*/
92
+
asm("mrc p15, 0, %0, c15, c0, 1" : "=r" (g_diag_reg) : : "cc");
93
+
__cpuc_flush_dcache_area(&g_diag_reg, sizeof(g_diag_reg));
94
+
outer_clean_range(__pa(&g_diag_reg), __pa(&g_diag_reg + 1));
85
95
}
86
96
87
97
struct smp_operations imx_smp_ops __initdata = {
-6
arch/arm/mach-kirkwood/common.c
-6
arch/arm/mach-kirkwood/common.c
···
528
528
{
529
529
orion_time_set_base(TIMER_VIRT_BASE);
530
530
531
-
/*
532
-
* Some Kirkwood devices allocate their coherent buffers from atomic
533
-
* context. Increase size of atomic coherent pool to make sure such
534
-
* the allocations won't fail.
535
-
*/
536
-
init_dma_coherent_pool_size(SZ_1M);
537
531
mvebu_mbus_init("marvell,kirkwood-mbus",
538
532
BRIDGE_WINS_BASE, BRIDGE_WINS_SZ,
539
533
DDR_WINDOW_CPU_BASE, DDR_WINDOW_CPU_SZ);
+1
-1
arch/arm/mach-kirkwood/ts219-setup.c
+1
-1
arch/arm/mach-kirkwood/ts219-setup.c
+1
arch/arm/mach-mvebu/Kconfig
+1
arch/arm/mach-mvebu/Kconfig
-7
arch/arm/mach-mvebu/armada-370-xp.c
-7
arch/arm/mach-mvebu/armada-370-xp.c
···
54
54
char *mbus_soc_name;
55
55
56
56
/*
57
-
* Some Armada 370/XP devices allocate their coherent buffers
58
-
* from atomic context. Increase size of atomic coherent pool
59
-
* to make sure such the allocations won't fail.
60
-
*/
61
-
init_dma_coherent_pool_size(SZ_1M);
62
-
63
-
/*
64
57
* This initialization will be replaced by a DT-based
65
58
* initialization once the mvebu-mbus driver gains DT support.
66
59
*/
+1
arch/arm/mach-omap1/dma.c
+1
arch/arm/mach-omap1/dma.c
+23
-3
arch/arm/mach-omap2/cclock33xx_data.c
+23
-3
arch/arm/mach-omap2/cclock33xx_data.c
···
454
454
*/
455
455
DEFINE_CLK_FIXED_FACTOR(clkdiv32k_ck, "clk_24mhz", &clk_24mhz, 0x0, 1, 732);
456
456
457
-
DEFINE_CLK_GATE(clkdiv32k_ick, "clkdiv32k_ck", &clkdiv32k_ck, 0x0,
458
-
AM33XX_CM_PER_CLKDIV32K_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT,
459
-
0x0, NULL);
457
+
static struct clk clkdiv32k_ick;
458
+
459
+
static const char *clkdiv32k_ick_parent_names[] = {
460
+
"clkdiv32k_ck",
461
+
};
462
+
463
+
static const struct clk_ops clkdiv32k_ick_ops = {
464
+
.enable = &omap2_dflt_clk_enable,
465
+
.disable = &omap2_dflt_clk_disable,
466
+
.is_enabled = &omap2_dflt_clk_is_enabled,
467
+
.init = &omap2_init_clk_clkdm,
468
+
};
469
+
470
+
static struct clk_hw_omap clkdiv32k_ick_hw = {
471
+
.hw = {
472
+
.clk = &clkdiv32k_ick,
473
+
},
474
+
.enable_reg = AM33XX_CM_PER_CLKDIV32K_CLKCTRL,
475
+
.enable_bit = AM33XX_MODULEMODE_SWCTRL_SHIFT,
476
+
.clkdm_name = "clk_24mhz_clkdm",
477
+
};
478
+
479
+
DEFINE_STRUCT_CLK(clkdiv32k_ick, clkdiv32k_ick_parent_names, clkdiv32k_ick_ops);
460
480
461
481
/* "usbotg_fck" is an additional clock and not really a modulemode */
462
482
DEFINE_CLK_GATE(usbotg_fck, "dpll_per_ck", &dpll_per_ck, 0x0,
+27
-86
arch/arm/mach-omap2/omap_hwmod.c
+27
-86
arch/arm/mach-omap2/omap_hwmod.c
···
1356
1356
1357
1357
clkdm = _get_clkdm(oh);
1358
1358
if (sf & SYSC_HAS_SIDLEMODE) {
1359
+
if (oh->flags & HWMOD_SWSUP_SIDLE ||
1360
+
oh->flags & HWMOD_SWSUP_SIDLE_ACT) {
1361
+
idlemode = HWMOD_IDLEMODE_NO;
1362
+
} else {
1363
+
if (sf & SYSC_HAS_ENAWAKEUP)
1364
+
_enable_wakeup(oh, &v);
1365
+
if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)
1366
+
idlemode = HWMOD_IDLEMODE_SMART_WKUP;
1367
+
else
1368
+
idlemode = HWMOD_IDLEMODE_SMART;
1369
+
}
1370
+
1371
+
/*
1372
+
* This is special handling for some IPs like
1373
+
* 32k sync timer. Force them to idle!
1374
+
*/
1359
1375
clkdm_act = (clkdm && clkdm->flags & CLKDM_ACTIVE_WITH_MPU);
1360
1376
if (clkdm_act && !(oh->class->sysc->idlemodes &
1361
1377
(SIDLE_SMART | SIDLE_SMART_WKUP)))
1362
1378
idlemode = HWMOD_IDLEMODE_FORCE;
1363
-
else
1364
-
idlemode = (oh->flags & HWMOD_SWSUP_SIDLE) ?
1365
-
HWMOD_IDLEMODE_NO : HWMOD_IDLEMODE_SMART;
1379
+
1366
1380
_set_slave_idlemode(oh, idlemode, &v);
1367
1381
}
1368
1382
···
1404
1390
if ((oh->flags & HWMOD_SET_DEFAULT_CLOCKACT) &&
1405
1391
(sf & SYSC_HAS_CLOCKACTIVITY))
1406
1392
_set_clockactivity(oh, oh->class->sysc->clockact, &v);
1407
-
1408
-
/* If slave is in SMARTIDLE, also enable wakeup */
1409
-
if ((sf & SYSC_HAS_SIDLEMODE) && !(oh->flags & HWMOD_SWSUP_SIDLE))
1410
-
_enable_wakeup(oh, &v);
1411
1393
1412
1394
_write_sysconfig(v, oh);
1413
1395
···
1440
1430
sf = oh->class->sysc->sysc_flags;
1441
1431
1442
1432
if (sf & SYSC_HAS_SIDLEMODE) {
1443
-
/* XXX What about HWMOD_IDLEMODE_SMART_WKUP? */
1444
-
if (oh->flags & HWMOD_SWSUP_SIDLE ||
1445
-
!(oh->class->sysc->idlemodes &
1446
-
(SIDLE_SMART | SIDLE_SMART_WKUP)))
1433
+
if (oh->flags & HWMOD_SWSUP_SIDLE) {
1447
1434
idlemode = HWMOD_IDLEMODE_FORCE;
1448
-
else
1449
-
idlemode = HWMOD_IDLEMODE_SMART;
1435
+
} else {
1436
+
if (sf & SYSC_HAS_ENAWAKEUP)
1437
+
_enable_wakeup(oh, &v);
1438
+
if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)
1439
+
idlemode = HWMOD_IDLEMODE_SMART_WKUP;
1440
+
else
1441
+
idlemode = HWMOD_IDLEMODE_SMART;
1442
+
}
1450
1443
_set_slave_idlemode(oh, idlemode, &v);
1451
1444
}
1452
1445
···
1467
1454
}
1468
1455
_set_master_standbymode(oh, idlemode, &v);
1469
1456
}
1470
-
1471
-
/* If slave is in SMARTIDLE, also enable wakeup */
1472
-
if ((sf & SYSC_HAS_SIDLEMODE) && !(oh->flags & HWMOD_SWSUP_SIDLE))
1473
-
_enable_wakeup(oh, &v);
1474
1457
1475
1458
_write_sysconfig(v, oh);
1476
1459
}
···
2074
2065
* do so is present in the hwmod data, then call it and pass along the
2075
2066
* return value; otherwise, return 0.
2076
2067
*/
2077
-
static int __init _enable_preprogram(struct omap_hwmod *oh)
2068
+
static int _enable_preprogram(struct omap_hwmod *oh)
2078
2069
{
2079
2070
if (!oh->class->enable_preprogram)
2080
2071
return 0;
···
2252
2243
oh->_state = _HWMOD_STATE_IDLE;
2253
2244
2254
2245
return 0;
2255
-
}
2256
-
2257
-
/**
2258
-
* omap_hwmod_set_ocp_autoidle - set the hwmod's OCP autoidle bit
2259
-
* @oh: struct omap_hwmod *
2260
-
* @autoidle: desired AUTOIDLE bitfield value (0 or 1)
2261
-
*
2262
-
* Sets the IP block's OCP autoidle bit in hardware, and updates our
2263
-
* local copy. Intended to be used by drivers that require
2264
-
* direct manipulation of the AUTOIDLE bits.
2265
-
* Returns -EINVAL if @oh is null or is not in the ENABLED state, or passes
2266
-
* along the return value from _set_module_autoidle().
2267
-
*
2268
-
* Any users of this function should be scrutinized carefully.
2269
-
*/
2270
-
int omap_hwmod_set_ocp_autoidle(struct omap_hwmod *oh, u8 autoidle)
2271
-
{
2272
-
u32 v;
2273
-
int retval = 0;
2274
-
unsigned long flags;
2275
-
2276
-
if (!oh || oh->_state != _HWMOD_STATE_ENABLED)
2277
-
return -EINVAL;
2278
-
2279
-
spin_lock_irqsave(&oh->_lock, flags);
2280
-
2281
-
v = oh->_sysc_cache;
2282
-
2283
-
retval = _set_module_autoidle(oh, autoidle, &v);
2284
-
2285
-
if (!retval)
2286
-
_write_sysconfig(v, oh);
2287
-
2288
-
spin_unlock_irqrestore(&oh->_lock, flags);
2289
-
2290
-
return retval;
2291
2246
}
2292
2247
2293
2248
/**
···
3150
3177
3151
3178
error:
3152
3179
return ret;
3153
-
}
3154
-
3155
-
/**
3156
-
* omap_hwmod_set_slave_idlemode - set the hwmod's OCP slave idlemode
3157
-
* @oh: struct omap_hwmod *
3158
-
* @idlemode: SIDLEMODE field bits (shifted to bit 0)
3159
-
*
3160
-
* Sets the IP block's OCP slave idlemode in hardware, and updates our
3161
-
* local copy. Intended to be used by drivers that have some erratum
3162
-
* that requires direct manipulation of the SIDLEMODE bits. Returns
3163
-
* -EINVAL if @oh is null, or passes along the return value from
3164
-
* _set_slave_idlemode().
3165
-
*
3166
-
* XXX Does this function have any current users? If not, we should
3167
-
* remove it; it is better to let the rest of the hwmod code handle this.
3168
-
* Any users of this function should be scrutinized carefully.
3169
-
*/
3170
-
int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode)
3171
-
{
3172
-
u32 v;
3173
-
int retval = 0;
3174
-
3175
-
if (!oh)
3176
-
return -EINVAL;
3177
-
3178
-
v = oh->_sysc_cache;
3179
-
3180
-
retval = _set_slave_idlemode(oh, idlemode, &v);
3181
-
if (!retval)
3182
-
_write_sysconfig(v, oh);
3183
-
3184
-
return retval;
3185
3180
}
3186
3181
3187
3182
/**
+4
-3
arch/arm/mach-omap2/omap_hwmod.h
+4
-3
arch/arm/mach-omap2/omap_hwmod.h
···
463
463
* is kept in force-standby mode. Failing to do so causes PM problems
464
464
* with musb on OMAP3630 at least. Note that musb has a dedicated register
465
465
* to control MSTANDBY signal when MIDLEMODE is set to force-standby.
466
+
* HWMOD_SWSUP_SIDLE_ACT: omap_hwmod code should manually bring the module
467
+
* out of idle, but rely on smart-idle to the put it back in idle,
468
+
* so the wakeups are still functional (Only known case for now is UART)
466
469
*/
467
470
#define HWMOD_SWSUP_SIDLE (1 << 0)
468
471
#define HWMOD_SWSUP_MSTANDBY (1 << 1)
···
479
476
#define HWMOD_EXT_OPT_MAIN_CLK (1 << 9)
480
477
#define HWMOD_BLOCK_WFI (1 << 10)
481
478
#define HWMOD_FORCE_MSTANDBY (1 << 11)
479
+
#define HWMOD_SWSUP_SIDLE_ACT (1 << 12)
482
480
483
481
/*
484
482
* omap_hwmod._int_flags definitions
···
644
640
645
641
int omap_hwmod_enable_clocks(struct omap_hwmod *oh);
646
642
int omap_hwmod_disable_clocks(struct omap_hwmod *oh);
647
-
648
-
int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode);
649
-
int omap_hwmod_set_ocp_autoidle(struct omap_hwmod *oh, u8 autoidle);
650
643
651
644
int omap_hwmod_reset(struct omap_hwmod *oh);
652
645
void omap_hwmod_ocp_barrier(struct omap_hwmod *oh);
+3
arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+3
arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
···
512
512
.mpu_irqs = omap2_uart1_mpu_irqs,
513
513
.sdma_reqs = omap2_uart1_sdma_reqs,
514
514
.main_clk = "uart1_fck",
515
+
.flags = HWMOD_SWSUP_SIDLE_ACT,
515
516
.prcm = {
516
517
.omap2 = {
517
518
.module_offs = CORE_MOD,
···
532
531
.mpu_irqs = omap2_uart2_mpu_irqs,
533
532
.sdma_reqs = omap2_uart2_sdma_reqs,
534
533
.main_clk = "uart2_fck",
534
+
.flags = HWMOD_SWSUP_SIDLE_ACT,
535
535
.prcm = {
536
536
.omap2 = {
537
537
.module_offs = CORE_MOD,
···
552
550
.mpu_irqs = omap2_uart3_mpu_irqs,
553
551
.sdma_reqs = omap2_uart3_sdma_reqs,
554
552
.main_clk = "uart3_fck",
553
+
.flags = HWMOD_SWSUP_SIDLE_ACT,
555
554
.prcm = {
556
555
.omap2 = {
557
556
.module_offs = CORE_MOD,
+6
arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+6
arch/arm/mach-omap2/omap_hwmod_33xx_data.c
···
1995
1995
.name = "uart1",
1996
1996
.class = &uart_class,
1997
1997
.clkdm_name = "l4_wkup_clkdm",
1998
+
.flags = HWMOD_SWSUP_SIDLE_ACT,
1998
1999
.mpu_irqs = am33xx_uart1_irqs,
1999
2000
.sdma_reqs = uart1_edma_reqs,
2000
2001
.main_clk = "dpll_per_m2_div4_wkupdm_ck",
···
2016
2015
.name = "uart2",
2017
2016
.class = &uart_class,
2018
2017
.clkdm_name = "l4ls_clkdm",
2018
+
.flags = HWMOD_SWSUP_SIDLE_ACT,
2019
2019
.mpu_irqs = am33xx_uart2_irqs,
2020
2020
.sdma_reqs = uart1_edma_reqs,
2021
2021
.main_clk = "dpll_per_m2_div4_ck",
···
2044
2042
.name = "uart3",
2045
2043
.class = &uart_class,
2046
2044
.clkdm_name = "l4ls_clkdm",
2045
+
.flags = HWMOD_SWSUP_SIDLE_ACT,
2047
2046
.mpu_irqs = am33xx_uart3_irqs,
2048
2047
.sdma_reqs = uart3_edma_reqs,
2049
2048
.main_clk = "dpll_per_m2_div4_ck",
···
2065
2062
.name = "uart4",
2066
2063
.class = &uart_class,
2067
2064
.clkdm_name = "l4ls_clkdm",
2065
+
.flags = HWMOD_SWSUP_SIDLE_ACT,
2068
2066
.mpu_irqs = am33xx_uart4_irqs,
2069
2067
.sdma_reqs = uart1_edma_reqs,
2070
2068
.main_clk = "dpll_per_m2_div4_ck",
···
2086
2082
.name = "uart5",
2087
2083
.class = &uart_class,
2088
2084
.clkdm_name = "l4ls_clkdm",
2085
+
.flags = HWMOD_SWSUP_SIDLE_ACT,
2089
2086
.mpu_irqs = am33xx_uart5_irqs,
2090
2087
.sdma_reqs = uart1_edma_reqs,
2091
2088
.main_clk = "dpll_per_m2_div4_ck",
···
2107
2102
.name = "uart6",
2108
2103
.class = &uart_class,
2109
2104
.clkdm_name = "l4ls_clkdm",
2105
+
.flags = HWMOD_SWSUP_SIDLE_ACT,
2110
2106
.mpu_irqs = am33xx_uart6_irqs,
2111
2107
.sdma_reqs = uart1_edma_reqs,
2112
2108
.main_clk = "dpll_per_m2_div4_ck",
+4
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+4
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
···
490
490
.mpu_irqs = omap2_uart1_mpu_irqs,
491
491
.sdma_reqs = omap2_uart1_sdma_reqs,
492
492
.main_clk = "uart1_fck",
493
+
.flags = HWMOD_SWSUP_SIDLE_ACT,
493
494
.prcm = {
494
495
.omap2 = {
495
496
.module_offs = CORE_MOD,
···
509
508
.mpu_irqs = omap2_uart2_mpu_irqs,
510
509
.sdma_reqs = omap2_uart2_sdma_reqs,
511
510
.main_clk = "uart2_fck",
511
+
.flags = HWMOD_SWSUP_SIDLE_ACT,
512
512
.prcm = {
513
513
.omap2 = {
514
514
.module_offs = CORE_MOD,
···
528
526
.mpu_irqs = omap2_uart3_mpu_irqs,
529
527
.sdma_reqs = omap2_uart3_sdma_reqs,
530
528
.main_clk = "uart3_fck",
529
+
.flags = HWMOD_SWSUP_SIDLE_ACT,
531
530
.prcm = {
532
531
.omap2 = {
533
532
.module_offs = OMAP3430_PER_MOD,
···
558
555
.mpu_irqs = uart4_mpu_irqs,
559
556
.sdma_reqs = uart4_sdma_reqs,
560
557
.main_clk = "uart4_fck",
558
+
.flags = HWMOD_SWSUP_SIDLE_ACT,
561
559
.prcm = {
562
560
.omap2 = {
563
561
.module_offs = OMAP3430_PER_MOD,
+5
-1
arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+5
-1
arch/arm/mach-omap2/omap_hwmod_44xx_data.c
···
3434
3434
.name = "uart1",
3435
3435
.class = &omap44xx_uart_hwmod_class,
3436
3436
.clkdm_name = "l4_per_clkdm",
3437
+
.flags = HWMOD_SWSUP_SIDLE_ACT,
3437
3438
.mpu_irqs = omap44xx_uart1_irqs,
3438
3439
.sdma_reqs = omap44xx_uart1_sdma_reqs,
3439
3440
.main_clk = "func_48m_fclk",
···
3463
3462
.name = "uart2",
3464
3463
.class = &omap44xx_uart_hwmod_class,
3465
3464
.clkdm_name = "l4_per_clkdm",
3465
+
.flags = HWMOD_SWSUP_SIDLE_ACT,
3466
3466
.mpu_irqs = omap44xx_uart2_irqs,
3467
3467
.sdma_reqs = omap44xx_uart2_sdma_reqs,
3468
3468
.main_clk = "func_48m_fclk",
···
3492
3490
.name = "uart3",
3493
3491
.class = &omap44xx_uart_hwmod_class,
3494
3492
.clkdm_name = "l4_per_clkdm",
3495
-
.flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3493
+
.flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET |
3494
+
HWMOD_SWSUP_SIDLE_ACT,
3496
3495
.mpu_irqs = omap44xx_uart3_irqs,
3497
3496
.sdma_reqs = omap44xx_uart3_sdma_reqs,
3498
3497
.main_clk = "func_48m_fclk",
···
3522
3519
.name = "uart4",
3523
3520
.class = &omap44xx_uart_hwmod_class,
3524
3521
.clkdm_name = "l4_per_clkdm",
3522
+
.flags = HWMOD_SWSUP_SIDLE_ACT,
3525
3523
.mpu_irqs = omap44xx_uart4_irqs,
3526
3524
.sdma_reqs = omap44xx_uart4_sdma_reqs,
3527
3525
.main_clk = "func_48m_fclk",
-31
arch/arm/mach-omap2/serial.c
-31
arch/arm/mach-omap2/serial.c
···
95
95
omap_hwmod_disable_wakeup(od->hwmods[0]);
96
96
}
97
97
98
-
/*
99
-
* Errata i291: [UART]:Cannot Acknowledge Idle Requests
100
-
* in Smartidle Mode When Configured for DMA Operations.
101
-
* WA: configure uart in force idle mode.
102
-
*/
103
-
static void omap_uart_set_noidle(struct device *dev)
104
-
{
105
-
struct platform_device *pdev = to_platform_device(dev);
106
-
struct omap_device *od = to_omap_device(pdev);
107
-
108
-
omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_NO);
109
-
}
110
-
111
-
static void omap_uart_set_smartidle(struct device *dev)
112
-
{
113
-
struct platform_device *pdev = to_platform_device(dev);
114
-
struct omap_device *od = to_omap_device(pdev);
115
-
u8 idlemode;
116
-
117
-
if (od->hwmods[0]->class->sysc->idlemodes & SIDLE_SMART_WKUP)
118
-
idlemode = HWMOD_IDLEMODE_SMART_WKUP;
119
-
else
120
-
idlemode = HWMOD_IDLEMODE_SMART;
121
-
122
-
omap_hwmod_set_slave_idlemode(od->hwmods[0], idlemode);
123
-
}
124
-
125
98
#else
126
99
static void omap_uart_enable_wakeup(struct device *dev, bool enable)
127
100
{}
128
-
static void omap_uart_set_noidle(struct device *dev) {}
129
-
static void omap_uart_set_smartidle(struct device *dev) {}
130
101
#endif /* CONFIG_PM */
131
102
132
103
#ifdef CONFIG_OMAP_MUX
···
270
299
omap_up.uartclk = OMAP24XX_BASE_BAUD * 16;
271
300
omap_up.flags = UPF_BOOT_AUTOCONF;
272
301
omap_up.get_context_loss_count = omap_pm_get_dev_context_loss_count;
273
-
omap_up.set_forceidle = omap_uart_set_smartidle;
274
-
omap_up.set_noidle = omap_uart_set_noidle;
275
302
omap_up.enable_wakeup = omap_uart_enable_wakeup;
276
303
omap_up.dma_rx_buf_size = info->dma_rx_buf_size;
277
304
omap_up.dma_rx_timeout = info->dma_rx_timeout;
-7
arch/arm/mach-orion5x/common.c
-7
arch/arm/mach-orion5x/common.c
···
199
199
200
200
orion_time_set_base(TIMER_VIRT_BASE);
201
201
202
-
/*
203
-
* Some Orion5x devices allocate their coherent buffers from atomic
204
-
* context. Increase size of atomic coherent pool to make sure such
205
-
* the allocations won't fail.
206
-
*/
207
-
init_dma_coherent_pool_size(SZ_1M);
208
-
209
202
/* Initialize the MBUS driver */
210
203
orion5x_pcie_id(&dev, &rev);
211
204
if (dev == MV88F5281_DEV_ID)
+3
-3
arch/arm/mach-shmobile/board-marzen.c
+3
-3
arch/arm/mach-shmobile/board-marzen.c
···
212
212
static struct usb_phy *phy;
213
213
static int usb_power_on(struct platform_device *pdev)
214
214
{
215
-
if (!phy)
216
-
return -EIO;
215
+
if (IS_ERR(phy))
216
+
return PTR_ERR(phy);
217
217
218
218
pm_runtime_enable(&pdev->dev);
219
219
pm_runtime_get_sync(&pdev->dev);
···
225
225
226
226
static void usb_power_off(struct platform_device *pdev)
227
227
{
228
-
if (!phy)
228
+
if (IS_ERR(phy))
229
229
return;
230
230
231
231
usb_phy_shutdown(phy);
+1
arch/arm/mach-sunxi/Kconfig
+1
arch/arm/mach-sunxi/Kconfig
+1
arch/arm/mach-ux500/Kconfig
+1
arch/arm/mach-ux500/Kconfig
+3
-3
arch/arm/mach-ux500/board-mop500.c
+3
-3
arch/arm/mach-ux500/board-mop500.c
···
623
623
sdi0_reg_info.gpios[0].gpio = GPIO_SDMMC_1V8_3V_SEL;
624
624
625
625
mop500_pinmaps_init();
626
-
parent = u8500_init_devices(&ab8500_platdata);
626
+
parent = u8500_init_devices();
627
627
628
628
for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++)
629
629
mop500_platform_devs[i]->dev.parent = parent;
···
660
660
sdi0_reg_info.gpios[0].gpio = SNOWBALL_SDMMC_1V8_3V_GPIO;
661
661
662
662
snowball_pinmaps_init();
663
-
parent = u8500_init_devices(&ab8500_platdata);
663
+
parent = u8500_init_devices();
664
664
665
665
for (i = 0; i < ARRAY_SIZE(snowball_platform_devs); i++)
666
666
snowball_platform_devs[i]->dev.parent = parent;
···
698
698
sdi0_reg_info.gpios[0].gpio = HREFV60_SDMMC_1V8_3V_GPIO;
699
699
700
700
hrefv60_pinmaps_init();
701
-
parent = u8500_init_devices(&ab8500_platdata);
701
+
parent = u8500_init_devices();
702
702
703
703
for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++)
704
704
mop500_platform_devs[i]->dev.parent = parent;
+2
-4
arch/arm/mach-ux500/cpu-db8500.c
+2
-4
arch/arm/mach-ux500/cpu-db8500.c
···
206
206
/*
207
207
* This function is called from the board init
208
208
*/
209
-
struct device * __init u8500_init_devices(struct ab8500_platform_data *ab8500)
209
+
struct device * __init u8500_init_devices(void)
210
210
{
211
211
struct device *parent;
212
212
int i;
···
219
219
220
220
for (i = 0; i < ARRAY_SIZE(platform_devs); i++)
221
221
platform_devs[i]->dev.parent = parent;
222
-
223
-
db8500_prcmu_device.dev.platform_data = ab8500;
224
222
225
223
platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
226
224
···
276
278
OF_DEV_AUXDATA("st,nomadik-i2c", 0x8012a000, "nmk-i2c.4", NULL),
277
279
OF_DEV_AUXDATA("stericsson,db8500-prcmu", 0x80157000, "db8500-prcmu",
278
280
&db8500_prcmu_pdata),
279
-
OF_DEV_AUXDATA("smsc,lan9115", 0x50000000, "smsc911x", NULL),
281
+
OF_DEV_AUXDATA("smsc,lan9115", 0x50000000, "smsc911x.0", NULL),
280
282
/* Requires device name bindings. */
281
283
OF_DEV_AUXDATA("stericsson,nmk-pinctrl", U8500_PRCMU_BASE,
282
284
"pinctrl-db8500", NULL),
+1
-1
arch/arm/mach-ux500/setup.h
+1
-1
arch/arm/mach-ux500/setup.h
···
18
18
void __init ux500_map_io(void);
19
19
extern void __init u8500_map_io(void);
20
20
21
-
extern struct device * __init u8500_init_devices(struct ab8500_platform_data *ab8500);
21
+
extern struct device * __init u8500_init_devices(void);
22
22
23
23
extern void __init ux500_init_irq(void);
24
24
extern void __init ux500_init_late(void);
+1
arch/arm/mach-vt8500/vt8500.c
+1
arch/arm/mach-vt8500/vt8500.c
+6
-6
arch/arm/plat-orion/common.c
+6
-6
arch/arm/plat-orion/common.c
···
383
383
384
384
static struct platform_device orion_ge10_shared = {
385
385
.name = MV643XX_ETH_SHARED_NAME,
386
-
.id = 1,
386
+
.id = 2,
387
387
.dev = {
388
388
.platform_data = &orion_ge10_shared_data,
389
389
},
···
398
398
399
399
static struct platform_device orion_ge10 = {
400
400
.name = MV643XX_ETH_NAME,
401
-
.id = 1,
402
-
.num_resources = 2,
401
+
.id = 2,
402
+
.num_resources = 1,
403
403
.resource = orion_ge10_resources,
404
404
.dev = {
405
405
.coherent_dma_mask = DMA_BIT_MASK(32),
···
432
432
433
433
static struct platform_device orion_ge11_shared = {
434
434
.name = MV643XX_ETH_SHARED_NAME,
435
-
.id = 1,
435
+
.id = 3,
436
436
.dev = {
437
437
.platform_data = &orion_ge11_shared_data,
438
438
},
···
447
447
448
448
static struct platform_device orion_ge11 = {
449
449
.name = MV643XX_ETH_NAME,
450
-
.id = 1,
451
-
.num_resources = 2,
450
+
.id = 3,
451
+
.num_resources = 1,
452
452
.resource = orion_ge11_resources,
453
453
.dev = {
454
454
.coherent_dma_mask = DMA_BIT_MASK(32),
+1
arch/arm/plat-orion/include/plat/common.h
+1
arch/arm/plat-orion/include/plat/common.h
+8
-3
drivers/clk/tegra/clk-tegra20.c
+8
-3
drivers/clk/tegra/clk-tegra20.c
···
872
872
struct clk *clk;
873
873
int i;
874
874
875
+
/* ac97 */
876
+
clk = tegra_clk_register_periph_gate("ac97", "pll_a_out0",
877
+
TEGRA_PERIPH_ON_APB,
878
+
clk_base, 0, 3, &periph_l_regs,
879
+
periph_clk_enb_refcnt);
880
+
clk_register_clkdev(clk, NULL, "tegra20-ac97");
881
+
clks[ac97] = clk;
882
+
875
883
/* apbdma */
876
884
clk = tegra_clk_register_periph_gate("apbdma", "pclk", 0, clk_base,
877
885
0, 34, &periph_h_regs,
···
1242
1234
{uartc, pll_p, 0, 0},
1243
1235
{uartd, pll_p, 0, 0},
1244
1236
{uarte, pll_p, 0, 0},
1245
-
{usbd, clk_max, 12000000, 0},
1246
-
{usb2, clk_max, 12000000, 0},
1247
-
{usb3, clk_max, 12000000, 0},
1248
1237
{pll_a, clk_max, 56448000, 1},
1249
1238
{pll_a_out0, clk_max, 11289600, 1},
1250
1239
{cdev1, clk_max, 0, 1},
-23
drivers/tty/serial/omap-serial.c
-23
drivers/tty/serial/omap-serial.c
···
202
202
return pdata->get_context_loss_count(up->dev);
203
203
}
204
204
205
-
static void serial_omap_set_forceidle(struct uart_omap_port *up)
206
-
{
207
-
struct omap_uart_port_info *pdata = up->dev->platform_data;
208
-
209
-
if (!pdata || !pdata->set_forceidle)
210
-
return;
211
-
212
-
pdata->set_forceidle(up->dev);
213
-
}
214
-
215
-
static void serial_omap_set_noidle(struct uart_omap_port *up)
216
-
{
217
-
struct omap_uart_port_info *pdata = up->dev->platform_data;
218
-
219
-
if (!pdata || !pdata->set_noidle)
220
-
return;
221
-
222
-
pdata->set_noidle(up->dev);
223
-
}
224
-
225
205
static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable)
226
206
{
227
207
struct omap_uart_port_info *pdata = up->dev->platform_data;
···
278
298
serial_out(up, UART_IER, up->ier);
279
299
}
280
300
281
-
serial_omap_set_forceidle(up);
282
-
283
301
pm_runtime_mark_last_busy(up->dev);
284
302
pm_runtime_put_autosuspend(up->dev);
285
303
}
···
342
364
343
365
pm_runtime_get_sync(up->dev);
344
366
serial_omap_enable_ier_thri(up);
345
-
serial_omap_set_noidle(up);
346
367
pm_runtime_mark_last_busy(up->dev);
347
368
pm_runtime_put_autosuspend(up->dev);
348
369
}