drm/i915/dp_mst: Add support for fractional compressed link bpps on MST

Add support for a fractional compressed link bpp on an MST link. Leave
the actual enabling of fractional bpps to a follow-up change.

While at it add an assert before the bpp loop, that the min and max bpps
are aligned to the bpp step. This should hold regardless of the non-DSC/DSC
or MST/UHBR-SST modes.

This keeps the mode validation and DSC->DPT BW specific maximum link
bpps as rounded-down integer values still, changing those to a
fractional value is left for later, add here TODO comments for them.

v2:
- Align the min/max bpp value to the bpp step.
- Assert that the min/max bpp values are aligned to the bpp step.

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://lore.kernel.org/r/20250509180340.554867-9-imre.deak@intel.com

Imre Deak 1 year ago 00f00859 7acc7a6f

+24 -9

2 changed files

expand all

drivers

gpu

drm

i915

display

intel_dp.c

intel_dp_mst.c

drivers/gpu/drm/i915/display/intel_dp.c

··· 958 958 return max_bpp; 959 959 } 960 960 961 + /* TODO: return a bpp_x16 value */ 961 962 u16 intel_dp_dsc_get_max_compressed_bpp(struct intel_display *display, 962 963 u32 link_clock, u32 lane_count, 963 964 u32 mode_clock, u32 mode_hdisplay,

+23 -9

drivers/gpu/drm/i915/display/intel_dp_mst.c

··· 23 23 * 24 24 */ 25 25 26 + #include <linux/log2.h> 27 + #include <linux/math.h> 28 + 26 29 #include <drm/drm_atomic.h> 27 30 #include <drm/drm_atomic_helper.h> 28 31 #include <drm/drm_edid.h> ··· 138 135 return intel_dp->mst.active_streams++ == 0; 139 136 } 140 137 138 + /* TODO: return a bpp_x16 value */ 141 139 static int intel_dp_mst_max_dpt_bpp(const struct intel_crtc_state *crtc_state, 142 140 bool dsc) 143 141 { ··· 319 315 } 320 316 } 321 317 318 + drm_WARN_ON(display->drm, min_bpp_x16 % bpp_step_x16 || max_bpp_x16 % bpp_step_x16); 319 + 322 320 for (bpp_x16 = max_bpp_x16; bpp_x16 >= min_bpp_x16; bpp_x16 -= bpp_step_x16) { 323 321 int local_bw_overhead; 324 322 int link_bpp_x16; ··· 466 460 int num_bpc; 467 461 u8 dsc_bpc[3] = {}; 468 462 int min_bpp, max_bpp, sink_min_bpp, sink_max_bpp; 469 - int min_compressed_bpp, max_compressed_bpp; 463 + int min_compressed_bpp_x16, max_compressed_bpp_x16; 464 + int bpp_step_x16; 470 465 471 466 max_bpp = limits->pipe.max_bpp; 472 467 min_bpp = limits->pipe.min_bpp; ··· 492 485 493 486 crtc_state->pipe_bpp = max_bpp; 494 487 495 - max_compressed_bpp = fxp_q4_to_int(limits->link.max_bpp_x16); 496 - min_compressed_bpp = fxp_q4_to_int_roundup(limits->link.min_bpp_x16); 488 + min_compressed_bpp_x16 = limits->link.min_bpp_x16; 489 + max_compressed_bpp_x16 = limits->link.max_bpp_x16; 497 490 498 - drm_dbg_kms(display->drm, "DSC Sink supported compressed min bpp %d compressed max bpp %d\n", 499 - min_compressed_bpp, max_compressed_bpp); 491 + drm_dbg_kms(display->drm, 492 + "DSC Sink supported compressed min bpp " FXP_Q4_FMT " compressed max bpp " FXP_Q4_FMT "\n", 493 + FXP_Q4_ARGS(min_compressed_bpp_x16), FXP_Q4_ARGS(max_compressed_bpp_x16)); 500 494 501 - max_compressed_bpp = min(max_compressed_bpp, crtc_state->pipe_bpp - 1); 495 + bpp_step_x16 = fxp_q4_from_int(1); 496 + 497 + max_compressed_bpp_x16 = min(max_compressed_bpp_x16, fxp_q4_from_int(crtc_state->pipe_bpp) - bpp_step_x16); 498 + 499 + drm_WARN_ON(display->drm, !is_power_of_2(bpp_step_x16)); 500 + min_compressed_bpp_x16 = round_up(min_compressed_bpp_x16, bpp_step_x16); 501 + max_compressed_bpp_x16 = round_down(max_compressed_bpp_x16, bpp_step_x16); 502 502 503 503 crtc_state->lane_count = limits->max_lane_count; 504 504 crtc_state->port_clock = limits->max_rate; 505 505 506 506 return intel_dp_mtp_tu_compute_config(intel_dp, crtc_state, conn_state, 507 - fxp_q4_from_int(min_compressed_bpp), 508 - fxp_q4_from_int(max_compressed_bpp), 509 - fxp_q4_from_int(1), true); 507 + min_compressed_bpp_x16, 508 + max_compressed_bpp_x16, 509 + bpp_step_x16, true); 510 510 } 511 511 512 512 static int mode_hblank_period_ns(const struct drm_display_mode *mode)

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