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Merge tag 'soc-fixes-6.15-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull SoC fixes from Arnd Bergmann:
"These all address issues in devicetree files:

- The Rockchip rk3588j are now limited the same way as the vendor
kernel, to allow room for the industrial-grade temperature ranges.

- Seven more Rockchip fixes address minor issues with specific boards

- Invalid clk controller references in multiple amlogic chips, plus
one accidentally disabled audio on clock

- Two devicetree fixes for i.MX8MP boards, both for incorrect
regulator settings

- A power domain change for apple laptop touchbar, fixing
suspend/resume problems

- An incorrect DMA controller setting for sophgo cv18xx chips"

* tag 'soc-fixes-6.15-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
arm64: dts: amazon: Fix simple-bus node name schema warnings
MAINTAINERS: delete email for Shiraz Hashim
arm64: dts: imx8mp-var-som: Fix LDO5 shutdown causing SD card timeout
arm64: dts: imx8mp: use 800MHz NoC OPP for nominal drive mode
arm64: dts: amlogic: dreambox: fix missing clkc_audio node
riscv: dts: sophgo: fix DMA data-width configuration for CV18xx
arm64: dts: rockchip: fix Sige5 RTC interrupt pin
arm64: dts: rockchip: Assign RT5616 MCLK rate on rk3588-friendlyelec-cm3588
arm64: dts: rockchip: Align wifi node name with bindings in CB2
arm64: dts: amlogic: g12: fix reference to unknown/untested PWM clock
arm64: dts: amlogic: gx: fix reference to unknown/untested PWM clock
ARM: dts: amlogic: meson8b: fix reference to unknown/untested PWM clock
ARM: dts: amlogic: meson8: fix reference to unknown/untested PWM clock
arm64: dts: apple: touchbar: Mark ps_dispdfr_be as always-on
mailmap: Update email for Asahi Lina
arm64: dts: rockchip: Fix mmc-pwrseq clock name on rock-pi-4
arm64: dts: rockchip: Use "regulator-fixed" for btreg on px30-engicam for vcc3v3-btreg
arm64: dts: rockchip: Add pinmuxing for eMMC on QNAP TS433
arm64: dts: rockchip: Remove overdrive-mode OPPs from RK3588J SoC dtsi
arm64: dts: rockchip: Allow Turing RK1 cooling fan to spin down

Linus Torvalds 00f281fd 9f35e331

+93 -63
+1
.mailmap
··· 102 102 Arnaud Patard <arnaud.patard@rtp-net.org> 103 103 Arnd Bergmann <arnd@arndb.de> 104 104 Arun Kumar Neelakantam <quic_aneela@quicinc.com> <aneela@codeaurora.org> 105 + Asahi Lina <lina+kernel@asahilina.net> <lina@asahilina.net> 105 106 Ashok Raj Nagarajan <quic_arnagara@quicinc.com> <arnagara@codeaurora.org> 106 107 Ashwin Chaugule <quic_ashwinc@quicinc.com> <ashwinc@codeaurora.org> 107 108 Asutosh Das <quic_asutoshd@quicinc.com> <asutoshd@codeaurora.org>
-1
MAINTAINERS
··· 22916 22916 22917 22917 SPEAR PLATFORM/CLOCK/PINCTRL SUPPORT 22918 22918 M: Viresh Kumar <vireshk@kernel.org> 22919 - M: Shiraz Hashim <shiraz.linux.kernel@gmail.com> 22920 22919 L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) 22921 22920 L: soc@lists.linux.dev 22922 22921 S: Maintained
+3 -3
arch/arm/boot/dts/amlogic/meson8.dtsi
··· 451 451 pwm_ef: pwm@86c0 { 452 452 compatible = "amlogic,meson8-pwm-v2"; 453 453 clocks = <&xtal>, 454 - <>, /* unknown/untested, the datasheet calls it "Video PLL" */ 454 + <0>, /* unknown/untested, the datasheet calls it "Video PLL" */ 455 455 <&clkc CLKID_FCLK_DIV4>, 456 456 <&clkc CLKID_FCLK_DIV3>; 457 457 reg = <0x86c0 0x10>; ··· 705 705 &pwm_ab { 706 706 compatible = "amlogic,meson8-pwm-v2"; 707 707 clocks = <&xtal>, 708 - <>, /* unknown/untested, the datasheet calls it "Video PLL" */ 708 + <0>, /* unknown/untested, the datasheet calls it "Video PLL" */ 709 709 <&clkc CLKID_FCLK_DIV4>, 710 710 <&clkc CLKID_FCLK_DIV3>; 711 711 }; ··· 713 713 &pwm_cd { 714 714 compatible = "amlogic,meson8-pwm-v2"; 715 715 clocks = <&xtal>, 716 - <>, /* unknown/untested, the datasheet calls it "Video PLL" */ 716 + <0>, /* unknown/untested, the datasheet calls it "Video PLL" */ 717 717 <&clkc CLKID_FCLK_DIV4>, 718 718 <&clkc CLKID_FCLK_DIV3>; 719 719 };
+3 -3
arch/arm/boot/dts/amlogic/meson8b.dtsi
··· 406 406 compatible = "amlogic,meson8b-pwm-v2", "amlogic,meson8-pwm-v2"; 407 407 reg = <0x86c0 0x10>; 408 408 clocks = <&xtal>, 409 - <>, /* unknown/untested, the datasheet calls it "Video PLL" */ 409 + <0>, /* unknown/untested, the datasheet calls it "Video PLL" */ 410 410 <&clkc CLKID_FCLK_DIV4>, 411 411 <&clkc CLKID_FCLK_DIV3>; 412 412 #pwm-cells = <3>; ··· 680 680 &pwm_ab { 681 681 compatible = "amlogic,meson8b-pwm-v2", "amlogic,meson8-pwm-v2"; 682 682 clocks = <&xtal>, 683 - <>, /* unknown/untested, the datasheet calls it "Video PLL" */ 683 + <0>, /* unknown/untested, the datasheet calls it "Video PLL" */ 684 684 <&clkc CLKID_FCLK_DIV4>, 685 685 <&clkc CLKID_FCLK_DIV3>; 686 686 }; ··· 688 688 &pwm_cd { 689 689 compatible = "amlogic,meson8b-pwm-v2", "amlogic,meson8-pwm-v2"; 690 690 clocks = <&xtal>, 691 - <>, /* unknown/untested, the datasheet calls it "Video PLL" */ 691 + <0>, /* unknown/untested, the datasheet calls it "Video PLL" */ 692 692 <&clkc CLKID_FCLK_DIV4>, 693 693 <&clkc CLKID_FCLK_DIV3>; 694 694 };
+1 -1
arch/arm64/boot/dts/amazon/alpine-v2.dtsi
··· 151 151 al,msi-num-spis = <160>; 152 152 }; 153 153 154 - io-fabric@fc000000 { 154 + io-bus@fc000000 { 155 155 compatible = "simple-bus"; 156 156 #address-cells = <1>; 157 157 #size-cells = <1>;
+1 -1
arch/arm64/boot/dts/amazon/alpine-v3.dtsi
··· 361 361 interrupt-parent = <&gic>; 362 362 }; 363 363 364 - io-fabric@fc000000 { 364 + io-bus@fc000000 { 365 365 compatible = "simple-bus"; 366 366 #address-cells = <1>; 367 367 #size-cells = <1>;
+3 -3
arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
··· 2313 2313 "amlogic,meson8-pwm-v2"; 2314 2314 reg = <0x0 0x19000 0x0 0x20>; 2315 2315 clocks = <&xtal>, 2316 - <>, /* unknown/untested, the datasheet calls it "vid_pll" */ 2316 + <0>, /* unknown/untested, the datasheet calls it "vid_pll" */ 2317 2317 <&clkc CLKID_FCLK_DIV4>, 2318 2318 <&clkc CLKID_FCLK_DIV3>; 2319 2319 #pwm-cells = <3>; ··· 2325 2325 "amlogic,meson8-pwm-v2"; 2326 2326 reg = <0x0 0x1a000 0x0 0x20>; 2327 2327 clocks = <&xtal>, 2328 - <>, /* unknown/untested, the datasheet calls it "vid_pll" */ 2328 + <0>, /* unknown/untested, the datasheet calls it "vid_pll" */ 2329 2329 <&clkc CLKID_FCLK_DIV4>, 2330 2330 <&clkc CLKID_FCLK_DIV3>; 2331 2331 #pwm-cells = <3>; ··· 2337 2337 "amlogic,meson8-pwm-v2"; 2338 2338 reg = <0x0 0x1b000 0x0 0x20>; 2339 2339 clocks = <&xtal>, 2340 - <>, /* unknown/untested, the datasheet calls it "vid_pll" */ 2340 + <0>, /* unknown/untested, the datasheet calls it "vid_pll" */ 2341 2341 <&clkc CLKID_FCLK_DIV4>, 2342 2342 <&clkc CLKID_FCLK_DIV3>; 2343 2343 #pwm-cells = <3>;
+4
arch/arm64/boot/dts/amlogic/meson-g12b-dreambox.dtsi
··· 116 116 status = "okay"; 117 117 }; 118 118 119 + &clkc_audio { 120 + status = "okay"; 121 + }; 122 + 119 123 &frddr_a { 120 124 status = "okay"; 121 125 };
+3 -3
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
··· 741 741 742 742 &pwm_ab { 743 743 clocks = <&xtal>, 744 - <>, /* unknown/untested, the datasheet calls it "vid_pll" */ 744 + <0>, /* unknown/untested, the datasheet calls it "vid_pll" */ 745 745 <&clkc CLKID_FCLK_DIV4>, 746 746 <&clkc CLKID_FCLK_DIV3>; 747 747 }; ··· 752 752 753 753 &pwm_cd { 754 754 clocks = <&xtal>, 755 - <>, /* unknown/untested, the datasheet calls it "vid_pll" */ 755 + <0>, /* unknown/untested, the datasheet calls it "vid_pll" */ 756 756 <&clkc CLKID_FCLK_DIV4>, 757 757 <&clkc CLKID_FCLK_DIV3>; 758 758 }; 759 759 760 760 &pwm_ef { 761 761 clocks = <&xtal>, 762 - <>, /* unknown/untested, the datasheet calls it "vid_pll" */ 762 + <0>, /* unknown/untested, the datasheet calls it "vid_pll" */ 763 763 <&clkc CLKID_FCLK_DIV4>, 764 764 <&clkc CLKID_FCLK_DIV3>; 765 765 };
+3 -3
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
··· 811 811 812 812 &pwm_ab { 813 813 clocks = <&xtal>, 814 - <>, /* unknown/untested, the datasheet calls it "vid_pll" */ 814 + <0>, /* unknown/untested, the datasheet calls it "vid_pll" */ 815 815 <&clkc CLKID_FCLK_DIV4>, 816 816 <&clkc CLKID_FCLK_DIV3>; 817 817 }; ··· 822 822 823 823 &pwm_cd { 824 824 clocks = <&xtal>, 825 - <>, /* unknown/untested, the datasheet calls it "vid_pll" */ 825 + <0>, /* unknown/untested, the datasheet calls it "vid_pll" */ 826 826 <&clkc CLKID_FCLK_DIV4>, 827 827 <&clkc CLKID_FCLK_DIV3>; 828 828 }; 829 829 830 830 &pwm_ef { 831 831 clocks = <&xtal>, 832 - <>, /* unknown/untested, the datasheet calls it "vid_pll" */ 832 + <0>, /* unknown/untested, the datasheet calls it "vid_pll" */ 833 833 <&clkc CLKID_FCLK_DIV4>, 834 834 <&clkc CLKID_FCLK_DIV3>; 835 835 };
+10
arch/arm64/boot/dts/apple/t8103-j293.dts
··· 77 77 }; 78 78 }; 79 79 80 + /* 81 + * The driver depends on boot loader initialized state which resets when this 82 + * power-domain is powered off. This happens on suspend or when the driver is 83 + * missing during boot. Mark the domain as always on until the driver can 84 + * handle this. 85 + */ 86 + &ps_dispdfr_be { 87 + apple,always-on; 88 + }; 89 + 80 90 &display_dfr { 81 91 status = "okay"; 82 92 };
+10
arch/arm64/boot/dts/apple/t8112-j493.dts
··· 40 40 }; 41 41 }; 42 42 43 + /* 44 + * The driver depends on boot loader initialized state which resets when this 45 + * power-domain is powered off. This happens on suspend or when the driver is 46 + * missing during boot. Mark the domain as always on until the driver can 47 + * handle this. 48 + */ 49 + &ps_dispdfr_be { 50 + apple,always-on; 51 + }; 52 + 43 53 &display_dfr { 44 54 status = "okay"; 45 55 };
+2
arch/arm64/boot/dts/freescale/imx8mp-nominal.dtsi
··· 88 88 <0>, <0>, <400000000>, 89 89 <1039500000>; 90 90 }; 91 + 92 + /delete-node/ &{noc_opp_table/opp-1000000000};
+11 -1
arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi
··· 35 35 <0x1 0x00000000 0 0xc0000000>; 36 36 }; 37 37 38 - 39 38 reg_usdhc2_vmmc: regulator-usdhc2-vmmc { 40 39 compatible = "regulator-fixed"; 41 40 regulator-name = "VSD_3V3"; ··· 44 45 enable-active-high; 45 46 startup-delay-us = <100>; 46 47 off-on-delay-us = <12000>; 48 + }; 49 + 50 + reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc { 51 + compatible = "regulator-gpio"; 52 + regulator-name = "VSD_VSEL"; 53 + regulator-min-microvolt = <1800000>; 54 + regulator-max-microvolt = <3300000>; 55 + gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; 56 + states = <3300000 0x0 1800000 0x1>; 57 + vin-supply = <&ldo5>; 47 58 }; 48 59 }; 49 60 ··· 214 205 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 215 206 cd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; 216 207 vmmc-supply = <&reg_usdhc2_vmmc>; 208 + vqmmc-supply = <&reg_usdhc2_vqmmc>; 217 209 bus-width = <4>; 218 210 status = "okay"; 219 211 };
+6
arch/arm64/boot/dts/freescale/imx8mp.dtsi
··· 1645 1645 opp-hz = /bits/ 64 <200000000>; 1646 1646 }; 1647 1647 1648 + /* Nominal drive mode maximum */ 1649 + opp-800000000 { 1650 + opp-hz = /bits/ 64 <800000000>; 1651 + }; 1652 + 1653 + /* Overdrive mode maximum */ 1648 1654 opp-1000000000 { 1649 1655 opp-hz = /bits/ 64 <1000000000>; 1650 1656 };
+1 -2
arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi
··· 31 31 }; 32 32 33 33 vcc3v3_btreg: vcc3v3-btreg { 34 - compatible = "regulator-gpio"; 34 + compatible = "regulator-fixed"; 35 35 enable-active-high; 36 36 pinctrl-names = "default"; 37 37 pinctrl-0 = <&bt_enable_h>; ··· 39 39 regulator-min-microvolt = <3300000>; 40 40 regulator-max-microvolt = <3300000>; 41 41 regulator-always-on; 42 - states = <3300000 0x0>; 43 42 }; 44 43 45 44 vcc3v3_rf_aux_mod: regulator-vcc3v3-rf-aux-mod {
+1 -1
arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi
··· 26 26 }; 27 27 28 28 &vcc3v3_btreg { 29 - enable-gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>; 29 + gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>; 30 30 };
+1 -1
arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts
··· 39 39 }; 40 40 41 41 &vcc3v3_btreg { 42 - enable-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; 42 + gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; 43 43 };
+1 -1
arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi
··· 43 43 sdio_pwrseq: sdio-pwrseq { 44 44 compatible = "mmc-pwrseq-simple"; 45 45 clocks = <&rk808 1>; 46 - clock-names = "lpo"; 46 + clock-names = "ext_clock"; 47 47 pinctrl-names = "default"; 48 48 pinctrl-0 = <&wifi_enable_h>; 49 49 reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
+1 -1
arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-cb2.dtsi
··· 775 775 rockchip,default-sample-phase = <90>; 776 776 status = "okay"; 777 777 778 - sdio-wifi@1 { 778 + wifi@1 { 779 779 compatible = "brcm,bcm4329-fmac"; 780 780 reg = <1>; 781 781 interrupt-parent = <&gpio2>;
+2
arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts
··· 619 619 bus-width = <8>; 620 620 max-frequency = <200000000>; 621 621 non-removable; 622 + pinctrl-names = "default"; 623 + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; 622 624 status = "okay"; 623 625 }; 624 626
+1 -1
arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts
··· 610 610 reg = <0x51>; 611 611 clock-output-names = "hym8563"; 612 612 interrupt-parent = <&gpio0>; 613 - interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>; 613 + interrupts = <RK_PA0 IRQ_TYPE_LEVEL_LOW>; 614 614 pinctrl-names = "default"; 615 615 pinctrl-0 = <&hym8563_int>; 616 616 wakeup-source;
+4
arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588.dtsi
··· 222 222 compatible = "realtek,rt5616"; 223 223 reg = <0x1b>; 224 224 #sound-dai-cells = <0>; 225 + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; 226 + assigned-clock-rates = <12288000>; 227 + clocks = <&cru I2S0_8CH_MCLKOUT>; 228 + clock-names = "mclk"; 225 229 }; 226 230 }; 227 231
+2
arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi
··· 214 214 }; 215 215 216 216 &package_thermal { 217 + polling-delay = <1000>; 218 + 217 219 trips { 218 220 package_active1: trip-active1 { 219 221 temperature = <45000>;
+17 -36
arch/arm64/boot/dts/rockchip/rk3588j.dtsi
··· 11 11 compatible = "operating-points-v2"; 12 12 opp-shared; 13 13 14 - opp-1416000000 { 15 - opp-hz = /bits/ 64 <1416000000>; 14 + opp-1200000000 { 15 + opp-hz = /bits/ 64 <1200000000>; 16 16 opp-microvolt = <750000 750000 950000>; 17 17 clock-latency-ns = <40000>; 18 18 opp-suspend; 19 19 }; 20 - opp-1608000000 { 21 - opp-hz = /bits/ 64 <1608000000>; 22 - opp-microvolt = <887500 887500 950000>; 23 - clock-latency-ns = <40000>; 24 - }; 25 - opp-1704000000 { 26 - opp-hz = /bits/ 64 <1704000000>; 27 - opp-microvolt = <937500 937500 950000>; 20 + opp-1296000000 { 21 + opp-hz = /bits/ 64 <1296000000>; 22 + opp-microvolt = <775000 775000 950000>; 28 23 clock-latency-ns = <40000>; 29 24 }; 30 25 }; ··· 28 33 compatible = "operating-points-v2"; 29 34 opp-shared; 30 35 36 + opp-1200000000{ 37 + opp-hz = /bits/ 64 <1200000000>; 38 + opp-microvolt = <750000 750000 950000>; 39 + clock-latency-ns = <40000>; 40 + }; 31 41 opp-1416000000 { 32 42 opp-hz = /bits/ 64 <1416000000>; 33 - opp-microvolt = <750000 750000 950000>; 43 + opp-microvolt = <762500 762500 950000>; 34 44 clock-latency-ns = <40000>; 35 45 }; 36 46 opp-1608000000 { 37 47 opp-hz = /bits/ 64 <1608000000>; 38 48 opp-microvolt = <787500 787500 950000>; 39 - clock-latency-ns = <40000>; 40 - }; 41 - opp-1800000000 { 42 - opp-hz = /bits/ 64 <1800000000>; 43 - opp-microvolt = <875000 875000 950000>; 44 - clock-latency-ns = <40000>; 45 - }; 46 - opp-2016000000 { 47 - opp-hz = /bits/ 64 <2016000000>; 48 - opp-microvolt = <950000 950000 950000>; 49 49 clock-latency-ns = <40000>; 50 50 }; 51 51 }; ··· 49 59 compatible = "operating-points-v2"; 50 60 opp-shared; 51 61 62 + opp-1200000000{ 63 + opp-hz = /bits/ 64 <1200000000>; 64 + opp-microvolt = <750000 750000 950000>; 65 + clock-latency-ns = <40000>; 66 + }; 52 67 opp-1416000000 { 53 68 opp-hz = /bits/ 64 <1416000000>; 54 - opp-microvolt = <750000 750000 950000>; 69 + opp-microvolt = <762500 762500 950000>; 55 70 clock-latency-ns = <40000>; 56 71 }; 57 72 opp-1608000000 { 58 73 opp-hz = /bits/ 64 <1608000000>; 59 74 opp-microvolt = <787500 787500 950000>; 60 - clock-latency-ns = <40000>; 61 - }; 62 - opp-1800000000 { 63 - opp-hz = /bits/ 64 <1800000000>; 64 - opp-microvolt = <875000 875000 950000>; 65 - clock-latency-ns = <40000>; 66 - }; 67 - opp-2016000000 { 68 - opp-hz = /bits/ 64 <2016000000>; 69 - opp-microvolt = <950000 950000 950000>; 70 75 clock-latency-ns = <40000>; 71 76 }; 72 77 }; ··· 88 103 opp-700000000 { 89 104 opp-hz = /bits/ 64 <700000000>; 90 105 opp-microvolt = <750000 750000 850000>; 91 - }; 92 - opp-850000000 { 93 - opp-hz = /bits/ 64 <800000000>; 94 - opp-microvolt = <787500 787500 850000>; 95 106 }; 96 107 }; 97 108 };
+1 -1
arch/riscv/boot/dts/sophgo/cv18xx.dtsi
··· 341 341 1024 1024 1024 1024>; 342 342 snps,priority = <0 1 2 3 4 5 6 7>; 343 343 snps,dma-masters = <2>; 344 - snps,data-width = <4>; 344 + snps,data-width = <2>; 345 345 status = "disabled"; 346 346 }; 347 347