+3 -3

Documentation/devicetree/bindings/hwmon/moortec,mr75203.yaml

reviewed

··· 105 105 G coefficient for temperature equation. 106 106 Default for series 5 = 60000 107 107 Default for series 6 = 57400 108 108 - multipleOf: 1000 108 108 + multipleOf: 100 109 109 minimum: 1000 110 110 $ref: /schemas/types.yaml#/definitions/uint32 111 111 ··· 114 114 H coefficient for temperature equation. 115 115 Default for series 5 = 200000 116 116 Default for series 6 = 249400 117 117 - multipleOf: 1000 117 117 + multipleOf: 100 118 118 minimum: 1000 119 119 $ref: /schemas/types.yaml#/definitions/uint32 120 120 ··· 131 131 J coefficient for temperature equation. 132 132 Default for series 5 = -100 133 133 Default for series 6 = 0 134 134 - multipleOf: 1000 134 134 + multipleOf: 100 135 135 maximum: 0 136 136 $ref: /schemas/types.yaml#/definitions/int32 137 137

-19

Documentation/devicetree/bindings/serial/cavium-uart.txt

reviewed

··· 1 1 - * Universal Asynchronous Receiver/Transmitter (UART) 2 2 - 3 3 - - compatible: "cavium,octeon-3860-uart" 4 4 - 5 5 - Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. 6 6 - 7 7 - - reg: The base address of the UART register bank. 8 8 - 9 9 - - interrupts: A single interrupt specifier. 10 10 - 11 11 - - current-speed: Optional, the current bit rate in bits per second. 12 12 - 13 13 - Example: 14 14 - uart1: serial@1180000000c00 { 15 15 - compatible = "cavium,octeon-3860-uart","ns16550"; 16 16 - reg = <0x11800 0x00000c00 0x0 0x400>; 17 17 - current-speed = <115200>; 18 18 - interrupts = <0 35>; 19 19 - };

-28

Documentation/devicetree/bindings/serial/nxp,lpc1850-uart.txt

reviewed

··· 1 1 - * NXP LPC1850 UART 2 2 - 3 3 - Required properties: 4 4 - - compatible : "nxp,lpc1850-uart", "ns16550a". 5 5 - - reg : offset and length of the register set for the device. 6 6 - - interrupts : should contain uart interrupt. 7 7 - - clocks : phandle to the input clocks. 8 8 - - clock-names : required elements: "uartclk", "reg". 9 9 - 10 10 - Optional properties: 11 11 - - dmas : Two or more DMA channel specifiers following the 12 12 - convention outlined in bindings/dma/dma.txt 13 13 - - dma-names : Names for the dma channels, if present. There must 14 14 - be at least one channel named "tx" for transmit 15 15 - and named "rx" for receive. 16 16 - 17 17 - Since it's also possible to also use the of_serial.c driver all 18 18 - parameters from 8250.txt also apply but are optional. 19 19 - 20 20 - Example: 21 21 - uart0: serial@40081000 { 22 22 - compatible = "nxp,lpc1850-uart", "ns16550a"; 23 23 - reg = <0x40081000 0x1000>; 24 24 - reg-shift = <2>; 25 25 - interrupts = <24>; 26 26 - clocks = <&ccu2 CLK_APB0_UART0>, <&ccu1 CLK_CPU_UART0>; 27 27 - clock-names = "uartclk", "reg"; 28 28 - };

+1 -19

Documentation/devicetree/bindings/sound/audio-graph-card2.yaml

reviewed

··· 39 39 40 40 additionalProperties: false 41 41 42 42 - examples: 43 43 - - | 44 44 - sound { 45 45 - compatible = "audio-graph-card2"; 46 46 - 47 47 - links = <&cpu_port>; 48 48 - }; 49 49 - 50 50 - cpu { 51 51 - compatible = "cpu-driver"; 52 52 - 53 53 - cpu_port: port { cpu_ep: endpoint { remote-endpoint = <&codec_ep>; }; }; 54 54 - }; 55 55 - 56 56 - codec { 57 57 - compatible = "codec-driver"; 58 58 - 59 59 - port { codec_ep: endpoint { remote-endpoint = <&cpu_ep>; }; }; 60 60 - }; 42 42 + ...

+1 -1

Documentation/devicetree/bindings/sound/google,sc7180-trogdor.yaml

reviewed

··· 7 7 title: Google SC7180-Trogdor ASoC sound card driver 8 8 9 9 maintainers: 10 10 - - Rohit kumar <rohitkr@codeaurora.org> 10 10 + - Rohit kumar <quic_rohkumar@quicinc.com> 11 11 - Cheng-Yi Chiang <cychiang@chromium.org> 12 12 13 13 description:

+1 -1

Documentation/devicetree/bindings/sound/qcom,lpass-cpu.yaml

reviewed

··· 8 8 9 9 maintainers: 10 10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org> 11 11 - - Rohit kumar <rohitkr@codeaurora.org> 11 11 + - Rohit kumar <quic_rohkumar@quicinc.com> 12 12 13 13 description: | 14 14 Qualcomm Technologies Inc. SOC Low-Power Audio SubSystem (LPASS) that consist

+7 -6

Documentation/networking/napi.rst

reviewed

··· 65 65 packets but should only process up to ``budget`` number of 66 66 Rx packets. Rx processing is usually much more expensive. 67 67 68 68 - In other words, it is recommended to ignore the budget argument when 69 69 - performing TX buffer reclamation to ensure that the reclamation is not 70 70 - arbitrarily bounded; however, it is required to honor the budget argument 71 71 - for RX processing. 68 68 + In other words for Rx processing the ``budget`` argument limits how many 69 69 + packets driver can process in a single poll. Rx specific APIs like page 70 70 + pool or XDP cannot be used at all when ``budget`` is 0. 71 71 + skb Tx processing should happen regardless of the ``budget``, but if 72 72 + the argument is 0 driver cannot call any XDP (or page pool) APIs. 72 73 73 74 .. warning:: 74 75 75 75 - The ``budget`` argument may be 0 if core tries to only process Tx completions 76 76 - and no Rx packets. 76 76 + The ``budget`` argument may be 0 if core tries to only process 77 77 + skb Tx completions and no Rx or XDP packets. 77 78 78 79 The poll method returns the amount of work done. If the driver still 79 80 has outstanding work to do (e.g. ``budget`` was exhausted)

+2

MAINTAINERS

reviewed

··· 1865 1865 L: asahi@lists.linux.dev 1866 1866 L: alsa-devel@alsa-project.org (moderated for non-subscribers) 1867 1867 S: Maintained 1868 1868 + F: Documentation/devicetree/bindings/sound/adi,ssm3515.yaml 1868 1869 F: Documentation/devicetree/bindings/sound/apple,* 1869 1870 F: sound/soc/apple/* 1870 1871 F: sound/soc/codecs/cs42l83-i2c.c 1872 1872 + F: sound/soc/codecs/ssm3515.c 1871 1873 1872 1874 ARM/APPLE MACHINE SUPPORT 1873 1875 M: Hector Martin <marcan@marcan.st>

+18 -6

Makefile

reviewed

··· 2 2 VERSION = 6 3 3 PATCHLEVEL = 5 4 4 SUBLEVEL = 0 5 5 - EXTRAVERSION = -rc2 5 5 + EXTRAVERSION = -rc3 6 6 NAME = Hurr durr I'ma ninja sloth 7 7 8 8 # *DOCUMENTATION* ··· 555 555 $(USERINCLUDE) 556 556 557 557 KBUILD_AFLAGS := -D__ASSEMBLY__ -fno-PIE 558 558 - KBUILD_CFLAGS := -Wall -Wundef -Werror=strict-prototypes -Wno-trigraphs \ 559 559 - -fno-strict-aliasing -fno-common -fshort-wchar -fno-PIE \ 560 560 - -Werror=implicit-function-declaration -Werror=implicit-int \ 561 561 - -Werror=return-type -Wno-format-security -funsigned-char \ 562 562 - -std=gnu11 558 558 + 559 559 + KBUILD_CFLAGS := 560 560 + KBUILD_CFLAGS += -std=gnu11 561 561 + KBUILD_CFLAGS += -fshort-wchar 562 562 + KBUILD_CFLAGS += -funsigned-char 563 563 + KBUILD_CFLAGS += -fno-common 564 564 + KBUILD_CFLAGS += -fno-PIE 565 565 + KBUILD_CFLAGS += -fno-strict-aliasing 566 566 + KBUILD_CFLAGS += -Wall 567 567 + KBUILD_CFLAGS += -Wundef 568 568 + KBUILD_CFLAGS += -Werror=implicit-function-declaration 569 569 + KBUILD_CFLAGS += -Werror=implicit-int 570 570 + KBUILD_CFLAGS += -Werror=return-type 571 571 + KBUILD_CFLAGS += -Werror=strict-prototypes 572 572 + KBUILD_CFLAGS += -Wno-format-security 573 573 + KBUILD_CFLAGS += -Wno-trigraphs 574 574 + 563 575 KBUILD_CPPFLAGS := -D__KERNEL__ 564 576 KBUILD_RUSTFLAGS := $(rust_common_flags) \ 565 577 --target=$(objtree)/scripts/target.json \

+2

arch/arm64/include/asm/kvm_host.h

reviewed

··· 727 727 #define DBG_SS_ACTIVE_PENDING __vcpu_single_flag(sflags, BIT(5)) 728 728 /* PMUSERENR for the guest EL0 is on physical CPU */ 729 729 #define PMUSERENR_ON_CPU __vcpu_single_flag(sflags, BIT(6)) 730 730 + /* WFI instruction trapped */ 731 731 + #define IN_WFI __vcpu_single_flag(sflags, BIT(7)) 730 732 731 733 732 734 /* Pointer to the vcpu's SVE FFR for sve_{save,load}_state() */

+9 -17

arch/arm64/include/asm/kvm_pgtable.h

reviewed

··· 608 608 kvm_pte_t kvm_pgtable_stage2_mkyoung(struct kvm_pgtable *pgt, u64 addr); 609 609 610 610 /** 611 611 - * kvm_pgtable_stage2_mkold() - Clear the access flag in a page-table entry. 611 611 + * kvm_pgtable_stage2_test_clear_young() - Test and optionally clear the access 612 612 + * flag in a page-table entry. 612 613 * @pgt: Page-table structure initialised by kvm_pgtable_stage2_init*(). 613 614 * @addr: Intermediate physical address to identify the page-table entry. 615 615 + * @size: Size of the address range to visit. 616 616 + * @mkold: True if the access flag should be cleared. 614 617 * 615 618 * The offset of @addr within a page is ignored. 616 619 * 617 617 - * If there is a valid, leaf page-table entry used to translate @addr, then 618 618 - * clear the access flag in that entry. 620 620 + * Tests and conditionally clears the access flag for every valid, leaf 621 621 + * page-table entry used to translate the range [@addr, @addr + @size). 619 622 * 620 623 * Note that it is the caller's responsibility to invalidate the TLB after 621 624 * calling this function to ensure that the updated permissions are visible 622 625 * to the CPUs. 623 626 * 624 624 - * Return: The old page-table entry prior to clearing the flag, 0 on failure. 627 627 + * Return: True if any of the visited PTEs had the access flag set. 625 628 */ 626 626 - kvm_pte_t kvm_pgtable_stage2_mkold(struct kvm_pgtable *pgt, u64 addr); 629 629 + bool kvm_pgtable_stage2_test_clear_young(struct kvm_pgtable *pgt, u64 addr, 630 630 + u64 size, bool mkold); 627 631 628 632 /** 629 633 * kvm_pgtable_stage2_relax_perms() - Relax the permissions enforced by a ··· 648 644 */ 649 645 int kvm_pgtable_stage2_relax_perms(struct kvm_pgtable *pgt, u64 addr, 650 646 enum kvm_pgtable_prot prot); 651 651 - 652 652 - /** 653 653 - * kvm_pgtable_stage2_is_young() - Test whether a page-table entry has the 654 654 - * access flag set. 655 655 - * @pgt: Page-table structure initialised by kvm_pgtable_stage2_init*(). 656 656 - * @addr: Intermediate physical address to identify the page-table entry. 657 657 - * 658 658 - * The offset of @addr within a page is ignored. 659 659 - * 660 660 - * Return: True if the page-table entry has the access flag set, false otherwise. 661 661 - */ 662 662 - bool kvm_pgtable_stage2_is_young(struct kvm_pgtable *pgt, u64 addr); 663 647 664 648 /** 665 649 * kvm_pgtable_stage2_flush_range() - Clean and invalidate data cache to Point

+1

arch/arm64/include/asm/virt.h

reviewed

··· 78 78 79 79 void __hyp_set_vectors(phys_addr_t phys_vector_base); 80 80 void __hyp_reset_vectors(void); 81 81 + bool is_kvm_arm_initialised(void); 81 82 82 83 DECLARE_STATIC_KEY_FALSE(kvm_protected_mode_initialized); 83 84

+25 -8

arch/arm64/kernel/fpsimd.c

reviewed

··· 847 847 int vec_set_vector_length(struct task_struct *task, enum vec_type type, 848 848 unsigned long vl, unsigned long flags) 849 849 { 850 850 + bool free_sme = false; 851 851 + 850 852 if (flags & ~(unsigned long)(PR_SVE_VL_INHERIT | 851 853 PR_SVE_SET_VL_ONEXEC)) 852 854 return -EINVAL; ··· 899 897 task->thread.fp_type = FP_STATE_FPSIMD; 900 898 } 901 899 902 902 - if (system_supports_sme() && type == ARM64_VEC_SME) { 903 903 - task->thread.svcr &= ~(SVCR_SM_MASK | 904 904 - SVCR_ZA_MASK); 905 905 - clear_thread_flag(TIF_SME); 900 900 + if (system_supports_sme()) { 901 901 + if (type == ARM64_VEC_SME || 902 902 + !(task->thread.svcr & (SVCR_SM_MASK | SVCR_ZA_MASK))) { 903 903 + /* 904 904 + * We are changing the SME VL or weren't using 905 905 + * SME anyway, discard the state and force a 906 906 + * reallocation. 907 907 + */ 908 908 + task->thread.svcr &= ~(SVCR_SM_MASK | 909 909 + SVCR_ZA_MASK); 910 910 + clear_thread_flag(TIF_SME); 911 911 + free_sme = true; 912 912 + } 906 913 } 907 914 908 915 if (task == current) 909 916 put_cpu_fpsimd_context(); 910 917 911 918 /* 912 912 - * Force reallocation of task SVE and SME state to the correct 913 913 - * size on next use: 919 919 + * Free the changed states if they are not in use, SME will be 920 920 + * reallocated to the correct size on next use and we just 921 921 + * allocate SVE now in case it is needed for use in streaming 922 922 + * mode. 914 923 */ 915 915 - sve_free(task); 916 916 - if (system_supports_sme() && type == ARM64_VEC_SME) 924 924 + if (system_supports_sve()) { 925 925 + sve_free(task); 926 926 + sve_alloc(task, true); 927 927 + } 928 928 + 929 929 + if (free_sme) 917 930 sme_free(task); 918 931 919 932 task_set_vl(task, type, vl);

+4

arch/arm64/kernel/vdso/vgettimeofday.c

reviewed

··· 6 6 * 7 7 */ 8 8 9 9 + int __kernel_clock_gettime(clockid_t clock, struct __kernel_timespec *ts); 10 10 + int __kernel_gettimeofday(struct __kernel_old_timeval *tv, struct timezone *tz); 11 11 + int __kernel_clock_getres(clockid_t clock_id, struct __kernel_timespec *res); 12 12 + 9 13 int __kernel_clock_gettime(clockid_t clock, 10 14 struct __kernel_timespec *ts) 11 15 {

+3 -3

arch/arm64/kvm/arch_timer.c

reviewed

··· 827 827 assign_clear_set_bit(tpt, CNTHCTL_EL1PCEN << 10, set, clr); 828 828 assign_clear_set_bit(tpc, CNTHCTL_EL1PCTEN << 10, set, clr); 829 829 830 830 - /* This only happens on VHE, so use the CNTKCTL_EL1 accessor */ 831 831 - sysreg_clear_set(cntkctl_el1, clr, set); 830 830 + /* This only happens on VHE, so use the CNTHCTL_EL2 accessor. */ 831 831 + sysreg_clear_set(cnthctl_el2, clr, set); 832 832 } 833 833 834 834 void kvm_timer_vcpu_load(struct kvm_vcpu *vcpu) ··· 1563 1563 void kvm_timer_init_vhe(void) 1564 1564 { 1565 1565 if (cpus_have_final_cap(ARM64_HAS_ECV_CNTPOFF)) 1566 1566 - sysreg_clear_set(cntkctl_el1, 0, CNTHCTL_ECV); 1566 1566 + sysreg_clear_set(cnthctl_el2, 0, CNTHCTL_ECV); 1567 1567 } 1568 1568 1569 1569 int kvm_arm_timer_set_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *attr)

+24 -4

arch/arm64/kvm/arm.c

reviewed

··· 53 53 54 54 DECLARE_KVM_NVHE_PER_CPU(struct kvm_cpu_context, kvm_hyp_ctxt); 55 55 56 56 - static bool vgic_present; 56 56 + static bool vgic_present, kvm_arm_initialised; 57 57 58 58 static DEFINE_PER_CPU(unsigned char, kvm_arm_hardware_enabled); 59 59 DEFINE_STATIC_KEY_FALSE(userspace_irqchip_in_use); 60 60 + 61 61 + bool is_kvm_arm_initialised(void) 62 62 + { 63 63 + return kvm_arm_initialised; 64 64 + } 60 65 61 66 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) 62 67 { ··· 718 713 */ 719 714 preempt_disable(); 720 715 kvm_vgic_vmcr_sync(vcpu); 721 721 - vgic_v4_put(vcpu, true); 716 716 + vcpu_set_flag(vcpu, IN_WFI); 717 717 + vgic_v4_put(vcpu); 722 718 preempt_enable(); 723 719 724 720 kvm_vcpu_halt(vcpu); 725 721 vcpu_clear_flag(vcpu, IN_WFIT); 726 722 727 723 preempt_disable(); 724 724 + vcpu_clear_flag(vcpu, IN_WFI); 728 725 vgic_v4_load(vcpu); 729 726 preempt_enable(); 730 727 } ··· 794 787 if (kvm_check_request(KVM_REQ_RELOAD_GICv4, vcpu)) { 795 788 /* The distributor enable bits were changed */ 796 789 preempt_disable(); 797 797 - vgic_v4_put(vcpu, false); 790 790 + vgic_v4_put(vcpu); 798 791 vgic_v4_load(vcpu); 799 792 preempt_enable(); 800 793 } ··· 1874 1867 1875 1868 int kvm_arch_hardware_enable(void) 1876 1869 { 1877 1877 - int was_enabled = __this_cpu_read(kvm_arm_hardware_enabled); 1870 1870 + int was_enabled; 1878 1871 1872 1872 + /* 1873 1873 + * Most calls to this function are made with migration 1874 1874 + * disabled, but not with preemption disabled. The former is 1875 1875 + * enough to ensure correctness, but most of the helpers 1876 1876 + * expect the later and will throw a tantrum otherwise. 1877 1877 + */ 1878 1878 + preempt_disable(); 1879 1879 + 1880 1880 + was_enabled = __this_cpu_read(kvm_arm_hardware_enabled); 1879 1881 _kvm_arch_hardware_enable(NULL); 1880 1882 1881 1883 if (!was_enabled) { 1882 1884 kvm_vgic_cpu_up(); 1883 1885 kvm_timer_cpu_up(); 1884 1886 } 1887 1887 + 1888 1888 + preempt_enable(); 1885 1889 1886 1890 return 0; 1887 1891 } ··· 2499 2481 err = kvm_init(sizeof(struct kvm_vcpu), 0, THIS_MODULE); 2500 2482 if (err) 2501 2483 goto out_subs; 2484 2484 + 2485 2485 + kvm_arm_initialised = true; 2502 2486 2503 2487 return 0; 2504 2488

+8

arch/arm64/kvm/hyp/hyp-entry.S

reviewed

··· 154 154 esb 155 155 stp x0, x1, [sp, #-16]! 156 156 662: 157 157 + /* 158 158 + * spectre vectors __bp_harden_hyp_vecs generate br instructions at runtime 159 159 + * that jump at offset 8 at __kvm_hyp_vector. 160 160 + * As hyp .text is guarded section, it needs bti j. 161 161 + */ 162 162 + bti j 157 163 b \target 158 164 159 165 check_preamble_length 661b, 662b ··· 171 165 nop 172 166 stp x0, x1, [sp, #-16]! 173 167 662: 168 168 + /* Check valid_vect */ 169 169 + bti j 174 170 b \target 175 171 176 172 check_preamble_length 661b, 662b

+10

arch/arm64/kvm/hyp/nvhe/host.S

reviewed

··· 297 297 298 298 ret 299 299 SYM_CODE_END(__kvm_hyp_host_forward_smc) 300 300 + 301 301 + /* 302 302 + * kvm_host_psci_cpu_entry is called through br instruction, which requires 303 303 + * bti j instruction as compilers (gcc and llvm) doesn't insert bti j for external 304 304 + * functions, but bti c instead. 305 305 + */ 306 306 + SYM_CODE_START(kvm_host_psci_cpu_entry) 307 307 + bti j 308 308 + b __kvm_host_psci_cpu_entry 309 309 + SYM_CODE_END(kvm_host_psci_cpu_entry)

+1 -1

arch/arm64/kvm/hyp/nvhe/psci-relay.c

reviewed

··· 200 200 __hyp_pa(init_params), 0); 201 201 } 202 202 203 203 - asmlinkage void __noreturn kvm_host_psci_cpu_entry(bool is_cpu_on) 203 203 + asmlinkage void __noreturn __kvm_host_psci_cpu_entry(bool is_cpu_on) 204 204 { 205 205 struct psci_boot_args *boot_args; 206 206 struct kvm_cpu_context *host_ctxt;

+38 -9

arch/arm64/kvm/hyp/pgtable.c

reviewed

··· 1195 1195 return pte; 1196 1196 } 1197 1197 1198 1198 - kvm_pte_t kvm_pgtable_stage2_mkold(struct kvm_pgtable *pgt, u64 addr) 1198 1198 + struct stage2_age_data { 1199 1199 + bool mkold; 1200 1200 + bool young; 1201 1201 + }; 1202 1202 + 1203 1203 + static int stage2_age_walker(const struct kvm_pgtable_visit_ctx *ctx, 1204 1204 + enum kvm_pgtable_walk_flags visit) 1199 1205 { 1200 1200 - kvm_pte_t pte = 0; 1201 1201 - stage2_update_leaf_attrs(pgt, addr, 1, 0, KVM_PTE_LEAF_ATTR_LO_S2_AF, 1202 1202 - &pte, NULL, 0); 1206 1206 + kvm_pte_t new = ctx->old & ~KVM_PTE_LEAF_ATTR_LO_S2_AF; 1207 1207 + struct stage2_age_data *data = ctx->arg; 1208 1208 + 1209 1209 + if (!kvm_pte_valid(ctx->old) || new == ctx->old) 1210 1210 + return 0; 1211 1211 + 1212 1212 + data->young = true; 1213 1213 + 1214 1214 + /* 1215 1215 + * stage2_age_walker() is always called while holding the MMU lock for 1216 1216 + * write, so this will always succeed. Nonetheless, this deliberately 1217 1217 + * follows the race detection pattern of the other stage-2 walkers in 1218 1218 + * case the locking mechanics of the MMU notifiers is ever changed. 1219 1219 + */ 1220 1220 + if (data->mkold && !stage2_try_set_pte(ctx, new)) 1221 1221 + return -EAGAIN; 1222 1222 + 1203 1223 /* 1204 1224 * "But where's the TLBI?!", you scream. 1205 1225 * "Over in the core code", I sigh. 1206 1226 * 1207 1227 * See the '->clear_flush_young()' callback on the KVM mmu notifier. 1208 1228 */ 1209 1209 - return pte; 1229 1229 + return 0; 1210 1230 } 1211 1231 1212 1212 - bool kvm_pgtable_stage2_is_young(struct kvm_pgtable *pgt, u64 addr) 1232 1232 + bool kvm_pgtable_stage2_test_clear_young(struct kvm_pgtable *pgt, u64 addr, 1233 1233 + u64 size, bool mkold) 1213 1234 { 1214 1214 - kvm_pte_t pte = 0; 1215 1215 - stage2_update_leaf_attrs(pgt, addr, 1, 0, 0, &pte, NULL, 0); 1216 1216 - return pte & KVM_PTE_LEAF_ATTR_LO_S2_AF; 1235 1235 + struct stage2_age_data data = { 1236 1236 + .mkold = mkold, 1237 1237 + }; 1238 1238 + struct kvm_pgtable_walker walker = { 1239 1239 + .cb = stage2_age_walker, 1240 1240 + .arg = &data, 1241 1241 + .flags = KVM_PGTABLE_WALK_LEAF, 1242 1242 + }; 1243 1243 + 1244 1244 + WARN_ON(kvm_pgtable_walk(pgt, addr, size, &walker)); 1245 1245 + return data.young; 1217 1246 } 1218 1247 1219 1248 int kvm_pgtable_stage2_relax_perms(struct kvm_pgtable *pgt, u64 addr,

+8 -10

arch/arm64/kvm/mmu.c

reviewed

··· 1756 1756 bool kvm_age_gfn(struct kvm *kvm, struct kvm_gfn_range *range) 1757 1757 { 1758 1758 u64 size = (range->end - range->start) << PAGE_SHIFT; 1759 1759 - kvm_pte_t kpte; 1760 1760 - pte_t pte; 1761 1759 1762 1760 if (!kvm->arch.mmu.pgt) 1763 1761 return false; 1764 1762 1765 1765 - WARN_ON(size != PAGE_SIZE && size != PMD_SIZE && size != PUD_SIZE); 1766 1766 - 1767 1767 - kpte = kvm_pgtable_stage2_mkold(kvm->arch.mmu.pgt, 1768 1768 - range->start << PAGE_SHIFT); 1769 1769 - pte = __pte(kpte); 1770 1770 - return pte_valid(pte) && pte_young(pte); 1763 1763 + return kvm_pgtable_stage2_test_clear_young(kvm->arch.mmu.pgt, 1764 1764 + range->start << PAGE_SHIFT, 1765 1765 + size, true); 1771 1766 } 1772 1767 1773 1768 bool kvm_test_age_gfn(struct kvm *kvm, struct kvm_gfn_range *range) 1774 1769 { 1770 1770 + u64 size = (range->end - range->start) << PAGE_SHIFT; 1771 1771 + 1775 1772 if (!kvm->arch.mmu.pgt) 1776 1773 return false; 1777 1774 1778 1778 - return kvm_pgtable_stage2_is_young(kvm->arch.mmu.pgt, 1779 1779 - range->start << PAGE_SHIFT); 1775 1775 + return kvm_pgtable_stage2_test_clear_young(kvm->arch.mmu.pgt, 1776 1776 + range->start << PAGE_SHIFT, 1777 1777 + size, false); 1780 1778 } 1781 1779 1782 1780 phys_addr_t kvm_mmu_get_httbr(void)

+1 -1

arch/arm64/kvm/pkvm.c

reviewed

··· 244 244 { 245 245 int ret; 246 246 247 247 - if (!is_protected_kvm_enabled()) 247 247 + if (!is_protected_kvm_enabled() || !is_kvm_arm_initialised()) 248 248 return 0; 249 249 250 250 /*

+21 -21

arch/arm64/kvm/sys_regs.c

reviewed

··· 986 986 987 987 if (p->is_write) { 988 988 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx); 989 989 - __vcpu_sys_reg(vcpu, reg) = p->regval & ARMV8_PMU_EVTYPE_MASK; 990 989 kvm_vcpu_pmu_restore_guest(vcpu); 991 990 } else { 992 991 p->regval = __vcpu_sys_reg(vcpu, reg) & ARMV8_PMU_EVTYPE_MASK; ··· 1114 1115 { SYS_DESC(SYS_DBGWCRn_EL1(n)), \ 1115 1116 trap_wcr, reset_wcr, 0, 0, get_wcr, set_wcr } 1116 1117 1117 1117 - #define PMU_SYS_REG(r) \ 1118 1118 - SYS_DESC(r), .reset = reset_pmu_reg, .visibility = pmu_visibility 1118 1118 + #define PMU_SYS_REG(name) \ 1119 1119 + SYS_DESC(SYS_##name), .reset = reset_pmu_reg, \ 1120 1120 + .visibility = pmu_visibility 1119 1121 1120 1122 /* Macro to expand the PMEVCNTRn_EL0 register */ 1121 1123 #define PMU_PMEVCNTR_EL0(n) \ 1122 1122 - { PMU_SYS_REG(SYS_PMEVCNTRn_EL0(n)), \ 1124 1124 + { PMU_SYS_REG(PMEVCNTRn_EL0(n)), \ 1123 1125 .reset = reset_pmevcntr, .get_user = get_pmu_evcntr, \ 1124 1126 .access = access_pmu_evcntr, .reg = (PMEVCNTR0_EL0 + n), } 1125 1127 1126 1128 /* Macro to expand the PMEVTYPERn_EL0 register */ 1127 1129 #define PMU_PMEVTYPER_EL0(n) \ 1128 1128 - { PMU_SYS_REG(SYS_PMEVTYPERn_EL0(n)), \ 1130 1130 + { PMU_SYS_REG(PMEVTYPERn_EL0(n)), \ 1129 1131 .reset = reset_pmevtyper, \ 1130 1132 .access = access_pmu_evtyper, .reg = (PMEVTYPER0_EL0 + n), } 1131 1133 ··· 2115 2115 { SYS_DESC(SYS_PMBSR_EL1), undef_access }, 2116 2116 /* PMBIDR_EL1 is not trapped */ 2117 2117 2118 2118 - { PMU_SYS_REG(SYS_PMINTENSET_EL1), 2118 2118 + { PMU_SYS_REG(PMINTENSET_EL1), 2119 2119 .access = access_pminten, .reg = PMINTENSET_EL1 }, 2120 2120 - { PMU_SYS_REG(SYS_PMINTENCLR_EL1), 2120 2120 + { PMU_SYS_REG(PMINTENCLR_EL1), 2121 2121 .access = access_pminten, .reg = PMINTENSET_EL1 }, 2122 2122 { SYS_DESC(SYS_PMMIR_EL1), trap_raz_wi }, 2123 2123 ··· 2164 2164 { SYS_DESC(SYS_CTR_EL0), access_ctr }, 2165 2165 { SYS_DESC(SYS_SVCR), undef_access }, 2166 2166 2167 2167 - { PMU_SYS_REG(SYS_PMCR_EL0), .access = access_pmcr, 2167 2167 + { PMU_SYS_REG(PMCR_EL0), .access = access_pmcr, 2168 2168 .reset = reset_pmcr, .reg = PMCR_EL0 }, 2169 2169 - { PMU_SYS_REG(SYS_PMCNTENSET_EL0), 2169 2169 + { PMU_SYS_REG(PMCNTENSET_EL0), 2170 2170 .access = access_pmcnten, .reg = PMCNTENSET_EL0 }, 2171 2171 - { PMU_SYS_REG(SYS_PMCNTENCLR_EL0), 2171 2171 + { PMU_SYS_REG(PMCNTENCLR_EL0), 2172 2172 .access = access_pmcnten, .reg = PMCNTENSET_EL0 }, 2173 2173 - { PMU_SYS_REG(SYS_PMOVSCLR_EL0), 2173 2173 + { PMU_SYS_REG(PMOVSCLR_EL0), 2174 2174 .access = access_pmovs, .reg = PMOVSSET_EL0 }, 2175 2175 /* 2176 2176 * PM_SWINC_EL0 is exposed to userspace as RAZ/WI, as it was 2177 2177 * previously (and pointlessly) advertised in the past... 2178 2178 */ 2179 2179 - { PMU_SYS_REG(SYS_PMSWINC_EL0), 2179 2179 + { PMU_SYS_REG(PMSWINC_EL0), 2180 2180 .get_user = get_raz_reg, .set_user = set_wi_reg, 2181 2181 .access = access_pmswinc, .reset = NULL }, 2182 2182 - { PMU_SYS_REG(SYS_PMSELR_EL0), 2182 2182 + { PMU_SYS_REG(PMSELR_EL0), 2183 2183 .access = access_pmselr, .reset = reset_pmselr, .reg = PMSELR_EL0 }, 2184 2184 - { PMU_SYS_REG(SYS_PMCEID0_EL0), 2184 2184 + { PMU_SYS_REG(PMCEID0_EL0), 2185 2185 .access = access_pmceid, .reset = NULL }, 2186 2186 - { PMU_SYS_REG(SYS_PMCEID1_EL0), 2186 2186 + { PMU_SYS_REG(PMCEID1_EL0), 2187 2187 .access = access_pmceid, .reset = NULL }, 2188 2188 - { PMU_SYS_REG(SYS_PMCCNTR_EL0), 2188 2188 + { PMU_SYS_REG(PMCCNTR_EL0), 2189 2189 .access = access_pmu_evcntr, .reset = reset_unknown, 2190 2190 .reg = PMCCNTR_EL0, .get_user = get_pmu_evcntr}, 2191 2191 - { PMU_SYS_REG(SYS_PMXEVTYPER_EL0), 2191 2191 + { PMU_SYS_REG(PMXEVTYPER_EL0), 2192 2192 .access = access_pmu_evtyper, .reset = NULL }, 2193 2193 - { PMU_SYS_REG(SYS_PMXEVCNTR_EL0), 2193 2193 + { PMU_SYS_REG(PMXEVCNTR_EL0), 2194 2194 .access = access_pmu_evcntr, .reset = NULL }, 2195 2195 /* 2196 2196 * PMUSERENR_EL0 resets as unknown in 64bit mode while it resets as zero 2197 2197 * in 32bit mode. Here we choose to reset it as zero for consistency. 2198 2198 */ 2199 2199 - { PMU_SYS_REG(SYS_PMUSERENR_EL0), .access = access_pmuserenr, 2199 2199 + { PMU_SYS_REG(PMUSERENR_EL0), .access = access_pmuserenr, 2200 2200 .reset = reset_val, .reg = PMUSERENR_EL0, .val = 0 }, 2201 2201 - { PMU_SYS_REG(SYS_PMOVSSET_EL0), 2201 2201 + { PMU_SYS_REG(PMOVSSET_EL0), 2202 2202 .access = access_pmovs, .reg = PMOVSSET_EL0 }, 2203 2203 2204 2204 { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 }, ··· 2354 2354 * PMCCFILTR_EL0 resets as unknown in 64bit mode while it resets as zero 2355 2355 * in 32bit mode. Here we choose to reset it as zero for consistency. 2356 2356 */ 2357 2357 - { PMU_SYS_REG(SYS_PMCCFILTR_EL0), .access = access_pmu_evtyper, 2357 2357 + { PMU_SYS_REG(PMCCFILTR_EL0), .access = access_pmu_evtyper, 2358 2358 .reset = reset_val, .reg = PMCCFILTR_EL0, .val = 0 }, 2359 2359 2360 2360 EL2_REG(VPIDR_EL2, access_rw, reset_unknown, 0),

+1 -1

arch/arm64/kvm/vgic/vgic-v3.c

reviewed

··· 749 749 { 750 750 struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3; 751 751 752 752 - WARN_ON(vgic_v4_put(vcpu, false)); 752 752 + WARN_ON(vgic_v4_put(vcpu)); 753 753 754 754 vgic_v3_vmcr_sync(vcpu); 755 755

+5 -2

arch/arm64/kvm/vgic/vgic-v4.c

reviewed

··· 336 336 its_vm->vpes = NULL; 337 337 } 338 338 339 339 - int vgic_v4_put(struct kvm_vcpu *vcpu, bool need_db) 339 339 + int vgic_v4_put(struct kvm_vcpu *vcpu) 340 340 { 341 341 struct its_vpe *vpe = &vcpu->arch.vgic_cpu.vgic_v3.its_vpe; 342 342 343 343 if (!vgic_supports_direct_msis(vcpu->kvm) || !vpe->resident) 344 344 return 0; 345 345 346 346 - return its_make_vpe_non_resident(vpe, need_db); 346 346 + return its_make_vpe_non_resident(vpe, !!vcpu_get_flag(vcpu, IN_WFI)); 347 347 } 348 348 349 349 int vgic_v4_load(struct kvm_vcpu *vcpu) ··· 352 352 int err; 353 353 354 354 if (!vgic_supports_direct_msis(vcpu->kvm) || vpe->resident) 355 355 + return 0; 356 356 + 357 357 + if (vcpu_get_flag(vcpu, IN_WFI)) 355 358 return 0; 356 359 357 360 /*

+3 -1

arch/arm64/mm/trans_pgd.c

reviewed

··· 24 24 #include <linux/bug.h> 25 25 #include <linux/mm.h> 26 26 #include <linux/mmzone.h> 27 27 + #include <linux/kfence.h> 27 28 28 29 static void *trans_alloc(struct trans_pgd_info *info) 29 30 { ··· 42 41 * the temporary mappings we use during restore. 43 42 */ 44 43 set_pte(dst_ptep, pte_mkwrite(pte)); 45 45 - } else if (debug_pagealloc_enabled() && !pte_none(pte)) { 44 44 + } else if ((debug_pagealloc_enabled() || 45 45 + is_kfence_address((void *)addr)) && !pte_none(pte)) { 46 46 /* 47 47 * debug_pagealloc will removed the PTE_VALID bit if 48 48 * the page isn't in use by the resume kernel. It may have

+6 -6

arch/arm64/tools/sysreg

reviewed

··· 2017 2017 EndSysreg 2018 2018 2019 2019 SysregFields HFGxTR_EL2 2020 2020 - Field 63 nAMIAIR2_EL1 2020 2020 + Field 63 nAMAIR2_EL1 2021 2021 Field 62 nMAIR2_EL1 2022 2022 Field 61 nS2POR_EL1 2023 2023 Field 60 nPOR_EL1 ··· 2032 2032 Res0 51 2033 2033 Field 50 nACCDATA_EL1 2034 2034 Field 49 ERXADDR_EL1 2035 2035 - Field 48 EXRPFGCDN_EL1 2036 2036 - Field 47 EXPFGCTL_EL1 2037 2037 - Field 46 EXPFGF_EL1 2035 2035 + Field 48 ERXPFGCDN_EL1 2036 2036 + Field 47 ERXPFGCTL_EL1 2037 2037 + Field 46 ERXPFGF_EL1 2038 2038 Field 45 ERXMISCn_EL1 2039 2039 Field 44 ERXSTATUS_EL1 2040 2040 Field 43 ERXCTLR_EL1 ··· 2049 2049 Field 34 TPIDRRO_EL0 2050 2050 Field 33 TPIDR_EL1 2051 2051 Field 32 TCR_EL1 2052 2052 - Field 31 SCTXNUM_EL0 2053 2053 - Field 30 SCTXNUM_EL1 2052 2052 + Field 31 SCXTNUM_EL0 2053 2053 + Field 30 SCXTNUM_EL1 2054 2054 Field 29 SCTLR_EL1 2055 2055 Field 28 REVIDR_EL1 2056 2056 Field 27 PAR_EL1

+1 -1

arch/ia64/kernel/sys_ia64.c

reviewed

··· 63 63 info.low_limit = addr; 64 64 info.high_limit = TASK_SIZE; 65 65 info.align_mask = align_mask; 66 66 - info.align_offset = 0; 66 66 + info.align_offset = pgoff << PAGE_SHIFT; 67 67 return vm_unmapped_area(&info); 68 68 } 69 69

+2 -2

arch/m68k/fpsp040/skeleton.S

reviewed

··· 499 499 dbf %d0,morein 500 500 rts 501 501 502 502 - .section .fixup,#alloc,#execinstr 502 502 + .section .fixup,"ax" 503 503 .even 504 504 1: 505 505 jbsr fpsp040_die 506 506 jbra .Lnotkern 507 507 508 508 - .section __ex_table,#alloc 508 508 + .section __ex_table,"a" 509 509 .align 4 510 510 511 511 .long in_ea,1b

+2 -2

arch/m68k/ifpsp060/os.S

reviewed

··· 379 379 380 380 381 381 | Execption handling for movs access to illegal memory 382 382 - .section .fixup,#alloc,#execinstr 382 382 + .section .fixup,"ax" 383 383 .even 384 384 1: moveq #-1,%d1 385 385 rts 386 386 - .section __ex_table,#alloc 386 386 + .section __ex_table,"a" 387 387 .align 4 388 388 .long dmrbuae,1b 389 389 .long dmrwuae,1b

+2 -2

arch/m68k/kernel/relocate_kernel.S

reviewed

··· 26 26 lea %pc@(.Lcopy),%a4 27 27 2: addl #0x00000000,%a4 /* virt_to_phys() */ 28 28 29 29 - .section ".m68k_fixup","aw" 29 29 + .section .m68k_fixup,"aw" 30 30 .long M68K_FIXUP_MEMOFFSET, 2b+2 31 31 .previous 32 32 ··· 49 49 lea %pc@(.Lcont040),%a4 50 50 5: addl #0x00000000,%a4 /* virt_to_phys() */ 51 51 52 52 - .section ".m68k_fixup","aw" 52 52 + .section .m68k_fixup,"aw" 53 53 .long M68K_FIXUP_MEMOFFSET, 5b+2 54 54 .previous 55 55

+10 -5

arch/parisc/kernel/sys_parisc.c

reviewed

··· 27 27 #include <linux/elf-randomize.h> 28 28 29 29 /* 30 30 - * Construct an artificial page offset for the mapping based on the physical 30 30 + * Construct an artificial page offset for the mapping based on the virtual 31 31 * address of the kernel file mapping variable. 32 32 + * If filp is zero the calculated pgoff value aliases the memory of the given 33 33 + * address. This is useful for io_uring where the mapping shall alias a kernel 34 34 + * address and a userspace adress where both the kernel and the userspace 35 35 + * access the same memory region. 32 36 */ 33 33 - #define GET_FILP_PGOFF(filp) \ 34 34 - (filp ? (((unsigned long) filp->f_mapping) >> 8) \ 35 35 - & ((SHM_COLOUR-1) >> PAGE_SHIFT) : 0UL) 37 37 + #define GET_FILP_PGOFF(filp, addr) \ 38 38 + ((filp ? (((unsigned long) filp->f_mapping) >> 8) \ 39 39 + & ((SHM_COLOUR-1) >> PAGE_SHIFT) : 0UL) \ 40 40 + + (addr >> PAGE_SHIFT)) 36 41 37 42 static unsigned long shared_align_offset(unsigned long filp_pgoff, 38 43 unsigned long pgoff) ··· 117 112 do_color_align = 0; 118 113 if (filp || (flags & MAP_SHARED)) 119 114 do_color_align = 1; 120 120 - filp_pgoff = GET_FILP_PGOFF(filp); 115 115 + filp_pgoff = GET_FILP_PGOFF(filp, addr); 121 116 122 117 if (flags & MAP_FIXED) { 123 118 /* Even MAP_FIXED mappings must reside within TASK_SIZE */

+3

arch/powerpc/crypto/.gitignore

reviewed

··· 1 1 + # SPDX-License-Identifier: GPL-2.0-only 2 2 + aesp10-ppc.S 3 3 + ghashp10-ppc.S

+13 -56

arch/powerpc/include/asm/bug.h

reviewed

··· 4 4 #ifdef __KERNEL__ 5 5 6 6 #include <asm/asm-compat.h> 7 7 - #include <asm/extable.h> 8 7 9 8 #ifdef CONFIG_BUG 10 9 11 10 #ifdef __ASSEMBLY__ 12 11 #include <asm/asm-offsets.h> 13 12 #ifdef CONFIG_DEBUG_BUGVERBOSE 14 14 - .macro __EMIT_BUG_ENTRY addr,file,line,flags 13 13 + .macro EMIT_BUG_ENTRY addr,file,line,flags 15 14 .section __bug_table,"aw" 16 15 5001: .4byte \addr - . 17 16 .4byte 5002f - . ··· 22 23 .previous 23 24 .endm 24 25 #else 25 25 - .macro __EMIT_BUG_ENTRY addr,file,line,flags 26 26 + .macro EMIT_BUG_ENTRY addr,file,line,flags 26 27 .section __bug_table,"aw" 27 28 5001: .4byte \addr - . 28 29 .short \flags ··· 30 31 .previous 31 32 .endm 32 33 #endif /* verbose */ 33 33 - 34 34 - .macro EMIT_WARN_ENTRY addr,file,line,flags 35 35 - EX_TABLE(\addr,\addr+4) 36 36 - __EMIT_BUG_ENTRY \addr,\file,\line,\flags 37 37 - .endm 38 38 - 39 39 - .macro EMIT_BUG_ENTRY addr,file,line,flags 40 40 - .if \flags & 1 /* BUGFLAG_WARNING */ 41 41 - .err /* Use EMIT_WARN_ENTRY for warnings */ 42 42 - .endif 43 43 - __EMIT_BUG_ENTRY \addr,\file,\line,\flags 44 44 - .endm 45 34 46 35 #else /* !__ASSEMBLY__ */ 47 36 /* _EMIT_BUG_ENTRY expects args %0,%1,%2,%3 to be FILE, LINE, flags and ··· 60 73 "i" (sizeof(struct bug_entry)), \ 61 74 ##__VA_ARGS__) 62 75 63 63 - #define WARN_ENTRY(insn, flags, label, ...) \ 64 64 - asm_volatile_goto( \ 65 65 - "1: " insn "\n" \ 66 66 - EX_TABLE(1b, %l[label]) \ 67 67 - _EMIT_BUG_ENTRY \ 68 68 - : : "i" (__FILE__), "i" (__LINE__), \ 69 69 - "i" (flags), \ 70 70 - "i" (sizeof(struct bug_entry)), \ 71 71 - ##__VA_ARGS__ : : label) 72 72 - 73 76 /* 74 77 * BUG_ON() and WARN_ON() do their best to cooperate with compile-time 75 78 * optimisations. However depending on the complexity of the condition ··· 72 95 } while (0) 73 96 #define HAVE_ARCH_BUG 74 97 75 75 - #define __WARN_FLAGS(flags) do { \ 76 76 - __label__ __label_warn_on; \ 77 77 - \ 78 78 - WARN_ENTRY("twi 31, 0, 0", BUGFLAG_WARNING | (flags), __label_warn_on); \ 79 79 - barrier_before_unreachable(); \ 80 80 - __builtin_unreachable(); \ 81 81 - \ 82 82 - __label_warn_on: \ 83 83 - break; \ 84 84 - } while (0) 98 98 + #define __WARN_FLAGS(flags) BUG_ENTRY("twi 31, 0, 0", BUGFLAG_WARNING | (flags)) 85 99 86 100 #ifdef CONFIG_PPC64 87 101 #define BUG_ON(x) do { \ ··· 85 117 } while (0) 86 118 87 119 #define WARN_ON(x) ({ \ 88 88 - bool __ret_warn_on = false; \ 89 89 - do { \ 90 90 - if (__builtin_constant_p((x))) { \ 91 91 - if (!(x)) \ 92 92 - break; \ 120 120 + int __ret_warn_on = !!(x); \ 121 121 + if (__builtin_constant_p(__ret_warn_on)) { \ 122 122 + if (__ret_warn_on) \ 93 123 __WARN(); \ 94 94 - __ret_warn_on = true; \ 95 95 - } else { \ 96 96 - __label__ __label_warn_on; \ 97 97 - \ 98 98 - WARN_ENTRY(PPC_TLNEI " %4, 0", \ 99 99 - BUGFLAG_WARNING | BUGFLAG_TAINT(TAINT_WARN), \ 100 100 - __label_warn_on, \ 101 101 - "r" ((__force long)(x))); \ 102 102 - break; \ 103 103 - __label_warn_on: \ 104 104 - __ret_warn_on = true; \ 105 105 - } \ 106 106 - } while (0); \ 124 124 + } else { \ 125 125 + BUG_ENTRY(PPC_TLNEI " %4, 0", \ 126 126 + BUGFLAG_WARNING | BUGFLAG_TAINT(TAINT_WARN), \ 127 127 + "r" (__ret_warn_on)); \ 128 128 + } \ 107 129 unlikely(__ret_warn_on); \ 108 130 }) 109 131 ··· 106 148 #ifdef __ASSEMBLY__ 107 149 .macro EMIT_BUG_ENTRY addr,file,line,flags 108 150 .endm 109 109 - .macro EMIT_WARN_ENTRY addr,file,line,flags 110 110 - .endm 111 151 #else /* !__ASSEMBLY__ */ 112 152 #define _EMIT_BUG_ENTRY 113 113 - #define _EMIT_WARN_ENTRY 114 153 #endif 115 154 #endif /* CONFIG_BUG */ 155 155 + 156 156 + #define EMIT_WARN_ENTRY EMIT_BUG_ENTRY 116 157 117 158 #include <asm-generic/bug.h> 118 159

-6

arch/powerpc/include/asm/elf.h

reviewed

··· 12 12 13 13 /* 14 14 * This is used to ensure we don't load something for the wrong architecture. 15 15 - * 64le only supports ELFv2 64-bit binaries (64be supports v1 and v2). 16 15 */ 17 17 - #if defined(CONFIG_PPC64) && defined(CONFIG_CPU_LITTLE_ENDIAN) 18 18 - #define elf_check_arch(x) (((x)->e_machine == ELF_ARCH) && \ 19 19 - (((x)->e_flags & 0x3) == 0x2)) 20 20 - #else 21 16 #define elf_check_arch(x) ((x)->e_machine == ELF_ARCH) 22 22 - #endif 23 17 #define compat_elf_check_arch(x) ((x)->e_machine == EM_PPC) 24 18 25 19 #define CORE_DUMP_USE_REGSET

+1 -5

arch/powerpc/include/asm/thread_info.h

reviewed

··· 183 183 #define clear_tsk_compat_task(tsk) do { } while (0) 184 184 #endif 185 185 186 186 - #ifdef CONFIG_PPC64 187 187 - #ifdef CONFIG_CPU_BIG_ENDIAN 186 186 + #if defined(CONFIG_PPC64) 188 187 #define is_elf2_task() (test_thread_flag(TIF_ELF2ABI)) 189 189 - #else 190 190 - #define is_elf2_task() (1) 191 191 - #endif 192 188 #else 193 189 #define is_elf2_task() (0) 194 190 #endif

+2 -7

arch/powerpc/kernel/traps.c

reviewed

··· 1508 1508 1509 1509 if (!(regs->msr & MSR_PR) && /* not user-mode */ 1510 1510 report_bug(bugaddr, regs) == BUG_TRAP_TYPE_WARN) { 1511 1511 - const struct exception_table_entry *entry; 1512 1512 - 1513 1513 - entry = search_exception_tables(bugaddr); 1514 1514 - if (entry) { 1515 1515 - regs_set_return_ip(regs, extable_fixup(entry) + regs->nip - bugaddr); 1516 1516 - return; 1517 1517 - } 1511 1511 + regs_add_return_ip(regs, 4); 1512 1512 + return; 1518 1513 } 1519 1514 1520 1515 if (cpu_has_feature(CPU_FTR_DEXCR_NPHIE) && user_mode(regs)) {

+1

arch/powerpc/mm/kasan/Makefile

reviewed

··· 1 1 # SPDX-License-Identifier: GPL-2.0 2 2 3 3 KASAN_SANITIZE := n 4 4 + KCOV_INSTRUMENT := n 4 5 5 6 obj-$(CONFIG_PPC32) += init_32.o 6 7 obj-$(CONFIG_PPC_8xx) += 8xx.o

+2 -4

arch/powerpc/platforms/512x/mpc512x_lpbfifo.c

reviewed

··· 477 477 return ret; 478 478 } 479 479 480 480 - static int mpc512x_lpbfifo_remove(struct platform_device *pdev) 480 480 + static void mpc512x_lpbfifo_remove(struct platform_device *pdev) 481 481 { 482 482 unsigned long flags; 483 483 struct dma_device *dma_dev = lpbfifo.chan->device; ··· 494 494 free_irq(lpbfifo.irq, &pdev->dev); 495 495 irq_dispose_mapping(lpbfifo.irq); 496 496 dma_release_channel(lpbfifo.chan); 497 497 - 498 498 - return 0; 499 497 } 500 498 501 499 static const struct of_device_id mpc512x_lpbfifo_match[] = { ··· 504 506 505 507 static struct platform_driver mpc512x_lpbfifo_driver = { 506 508 .probe = mpc512x_lpbfifo_probe, 507 507 - .remove = mpc512x_lpbfifo_remove, 509 509 + .remove_new = mpc512x_lpbfifo_remove, 508 510 .driver = { 509 511 .name = DRV_NAME, 510 512 .of_match_table = mpc512x_lpbfifo_match,

+7 -2

arch/powerpc/platforms/pseries/vas.c

reviewed

··· 744 744 } 745 745 746 746 task_ref = &win->vas_win.task_ref; 747 747 + /* 748 748 + * VAS mmap (coproc_mmap()) and its fault handler 749 749 + * (vas_mmap_fault()) are called after holding mmap lock. 750 750 + * So hold mmap mutex after mmap_lock to avoid deadlock. 751 751 + */ 752 752 + mmap_write_lock(task_ref->mm); 747 753 mutex_lock(&task_ref->mmap_mutex); 748 754 vma = task_ref->vma; 749 755 /* ··· 758 752 */ 759 753 win->vas_win.status |= flag; 760 754 761 761 - mmap_write_lock(task_ref->mm); 762 755 /* 763 756 * vma is set in the original mapping. But this mapping 764 757 * is done with mmap() after the window is opened with ioctl. ··· 767 762 if (vma) 768 763 zap_vma_pages(vma); 769 764 770 770 - mmap_write_unlock(task_ref->mm); 771 765 mutex_unlock(&task_ref->mmap_mutex); 766 766 + mmap_write_unlock(task_ref->mm); 772 767 /* 773 768 * Close VAS window in the hypervisor, but do not 774 769 * free vas_window struct since it may be reused

+1 -1

arch/s390/crypto/paes_s390.c

reviewed

··· 103 103 { 104 104 if (kb->key && kb->key != kb->keybuf 105 105 && kb->keylen > sizeof(kb->keybuf)) { 106 106 - kfree(kb->key); 106 106 + kfree_sensitive(kb->key); 107 107 kb->key = NULL; 108 108 } 109 109 }

+6 -2

arch/s390/kvm/pv.c

reviewed

··· 411 411 u16 _rc, _rrc; 412 412 int cc = 0; 413 413 414 414 - /* Make sure the counter does not reach 0 before calling s390_uv_destroy_range */ 415 415 - atomic_inc(&kvm->mm->context.protected_count); 414 414 + /* 415 415 + * Nothing to do if the counter was already 0. Otherwise make sure 416 416 + * the counter does not reach 0 before calling s390_uv_destroy_range. 417 417 + */ 418 418 + if (!atomic_inc_not_zero(&kvm->mm->context.protected_count)) 419 419 + return 0; 416 420 417 421 *rc = 1; 418 422 /* If the current VM is protected, destroy it */

+2

arch/s390/mm/fault.c

reviewed

··· 421 421 vma_end_read(vma); 422 422 if (!(fault & VM_FAULT_RETRY)) { 423 423 count_vm_vma_lock_event(VMA_LOCK_SUCCESS); 424 424 + if (likely(!(fault & VM_FAULT_ERROR))) 425 425 + fault = 0; 424 426 goto out; 425 427 } 426 428 count_vm_vma_lock_event(VMA_LOCK_RETRY);

+1

arch/s390/mm/gmap.c

reviewed

··· 2853 2853 page = alloc_pages(GFP_KERNEL_ACCOUNT, CRST_ALLOC_ORDER); 2854 2854 if (!page) 2855 2855 return -ENOMEM; 2856 2856 + page->index = 0; 2856 2857 table = page_to_virt(page); 2857 2858 memcpy(table, gmap->table, 1UL << (CRST_ALLOC_ORDER + PAGE_SHIFT)); 2858 2859

+1

arch/x86/include/asm/microcode.h

reviewed

··· 5 5 #include <asm/cpu.h> 6 6 #include <linux/earlycpio.h> 7 7 #include <linux/initrd.h> 8 8 + #include <asm/microcode_amd.h> 8 9 9 10 struct ucode_patch { 10 11 struct list_head plist;

+2

arch/x86/include/asm/microcode_amd.h

reviewed

··· 48 48 extern void load_ucode_amd_ap(unsigned int family); 49 49 extern int __init save_microcode_in_initrd_amd(unsigned int family); 50 50 void reload_ucode_amd(unsigned int cpu); 51 51 + extern void amd_check_microcode(void); 51 52 #else 52 53 static inline void __init load_ucode_amd_bsp(unsigned int family) {} 53 54 static inline void load_ucode_amd_ap(unsigned int family) {} 54 55 static inline int __init 55 56 save_microcode_in_initrd_amd(unsigned int family) { return -EINVAL; } 56 57 static inline void reload_ucode_amd(unsigned int cpu) {} 58 58 + static inline void amd_check_microcode(void) {} 57 59 #endif 58 60 #endif /* _ASM_X86_MICROCODE_AMD_H */

+1

arch/x86/include/asm/msr-index.h

reviewed

··· 545 545 #define MSR_AMD64_DE_CFG 0xc0011029 546 546 #define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT 1 547 547 #define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE BIT_ULL(MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT) 548 548 + #define MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT 9 548 549 549 550 #define MSR_AMD64_BU_CFG2 0xc001102a 550 551 #define MSR_AMD64_IBSFETCHCTL 0xc0011030

+127 -72

arch/x86/kernel/cpu/amd.c

reviewed

··· 27 27 28 28 #include "cpu.h" 29 29 30 30 - static const int amd_erratum_383[]; 31 31 - static const int amd_erratum_400[]; 32 32 - static const int amd_erratum_1054[]; 33 33 - static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum); 34 34 - 35 30 /* 36 31 * nodes_per_socket: Stores the number of nodes per socket. 37 32 * Refer to Fam15h Models 00-0fh BKDG - CPUID Fn8000_001E_ECX 38 33 * Node Identifiers[10:8] 39 34 */ 40 35 static u32 nodes_per_socket = 1; 36 36 + 37 37 + /* 38 38 + * AMD errata checking 39 39 + * 40 40 + * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or 41 41 + * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that 42 42 + * have an OSVW id assigned, which it takes as first argument. Both take a 43 43 + * variable number of family-specific model-stepping ranges created by 44 44 + * AMD_MODEL_RANGE(). 45 45 + * 46 46 + * Example: 47 47 + * 48 48 + * const int amd_erratum_319[] = 49 49 + * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2), 50 50 + * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0), 51 51 + * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0)); 52 52 + */ 53 53 + 54 54 + #define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 } 55 55 + #define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 } 56 56 + #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \ 57 57 + ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end)) 58 58 + #define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff) 59 59 + #define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff) 60 60 + #define AMD_MODEL_RANGE_END(range) ((range) & 0xfff) 61 61 + 62 62 + static const int amd_erratum_400[] = 63 63 + AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf), 64 64 + AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf)); 65 65 + 66 66 + static const int amd_erratum_383[] = 67 67 + AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf)); 68 68 + 69 69 + /* #1054: Instructions Retired Performance Counter May Be Inaccurate */ 70 70 + static const int amd_erratum_1054[] = 71 71 + AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0, 0, 0x2f, 0xf)); 72 72 + 73 73 + static const int amd_zenbleed[] = 74 74 + AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0x30, 0x0, 0x4f, 0xf), 75 75 + AMD_MODEL_RANGE(0x17, 0x60, 0x0, 0x7f, 0xf), 76 76 + AMD_MODEL_RANGE(0x17, 0xa0, 0x0, 0xaf, 0xf)); 77 77 + 78 78 + static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum) 79 79 + { 80 80 + int osvw_id = *erratum++; 81 81 + u32 range; 82 82 + u32 ms; 83 83 + 84 84 + if (osvw_id >= 0 && osvw_id < 65536 && 85 85 + cpu_has(cpu, X86_FEATURE_OSVW)) { 86 86 + u64 osvw_len; 87 87 + 88 88 + rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len); 89 89 + if (osvw_id < osvw_len) { 90 90 + u64 osvw_bits; 91 91 + 92 92 + rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6), 93 93 + osvw_bits); 94 94 + return osvw_bits & (1ULL << (osvw_id & 0x3f)); 95 95 + } 96 96 + } 97 97 + 98 98 + /* OSVW unavailable or ID unknown, match family-model-stepping range */ 99 99 + ms = (cpu->x86_model << 4) | cpu->x86_stepping; 100 100 + while ((range = *erratum++)) 101 101 + if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) && 102 102 + (ms >= AMD_MODEL_RANGE_START(range)) && 103 103 + (ms <= AMD_MODEL_RANGE_END(range))) 104 104 + return true; 105 105 + 106 106 + return false; 107 107 + } 41 108 42 109 static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p) 43 110 { ··· 983 916 } 984 917 } 985 918 919 919 + static bool cpu_has_zenbleed_microcode(void) 920 920 + { 921 921 + u32 good_rev = 0; 922 922 + 923 923 + switch (boot_cpu_data.x86_model) { 924 924 + case 0x30 ... 0x3f: good_rev = 0x0830107a; break; 925 925 + case 0x60 ... 0x67: good_rev = 0x0860010b; break; 926 926 + case 0x68 ... 0x6f: good_rev = 0x08608105; break; 927 927 + case 0x70 ... 0x7f: good_rev = 0x08701032; break; 928 928 + case 0xa0 ... 0xaf: good_rev = 0x08a00008; break; 929 929 + 930 930 + default: 931 931 + return false; 932 932 + break; 933 933 + } 934 934 + 935 935 + if (boot_cpu_data.microcode < good_rev) 936 936 + return false; 937 937 + 938 938 + return true; 939 939 + } 940 940 + 941 941 + static void zenbleed_check(struct cpuinfo_x86 *c) 942 942 + { 943 943 + if (!cpu_has_amd_erratum(c, amd_zenbleed)) 944 944 + return; 945 945 + 946 946 + if (cpu_has(c, X86_FEATURE_HYPERVISOR)) 947 947 + return; 948 948 + 949 949 + if (!cpu_has(c, X86_FEATURE_AVX)) 950 950 + return; 951 951 + 952 952 + if (!cpu_has_zenbleed_microcode()) { 953 953 + pr_notice_once("Zenbleed: please update your microcode for the most optimal fix\n"); 954 954 + msr_set_bit(MSR_AMD64_DE_CFG, MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT); 955 955 + } else { 956 956 + msr_clear_bit(MSR_AMD64_DE_CFG, MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT); 957 957 + } 958 958 + } 959 959 + 986 960 static void init_amd(struct cpuinfo_x86 *c) 987 961 { 988 962 early_init_amd(c); ··· 1128 1020 if (spectre_v2_in_eibrs_mode(spectre_v2_enabled) && 1129 1021 cpu_has(c, X86_FEATURE_AUTOIBRS)) 1130 1022 WARN_ON_ONCE(msr_set_bit(MSR_EFER, _EFER_AUTOIBRS)); 1023 1023 + 1024 1024 + zenbleed_check(c); 1131 1025 } 1132 1026 1133 1027 #ifdef CONFIG_X86_32 ··· 1225 1115 1226 1116 cpu_dev_register(amd_cpu_dev); 1227 1117 1228 1228 - /* 1229 1229 - * AMD errata checking 1230 1230 - * 1231 1231 - * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or 1232 1232 - * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that 1233 1233 - * have an OSVW id assigned, which it takes as first argument. Both take a 1234 1234 - * variable number of family-specific model-stepping ranges created by 1235 1235 - * AMD_MODEL_RANGE(). 1236 1236 - * 1237 1237 - * Example: 1238 1238 - * 1239 1239 - * const int amd_erratum_319[] = 1240 1240 - * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2), 1241 1241 - * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0), 1242 1242 - * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0)); 1243 1243 - */ 1244 1244 - 1245 1245 - #define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 } 1246 1246 - #define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 } 1247 1247 - #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \ 1248 1248 - ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end)) 1249 1249 - #define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff) 1250 1250 - #define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff) 1251 1251 - #define AMD_MODEL_RANGE_END(range) ((range) & 0xfff) 1252 1252 - 1253 1253 - static const int amd_erratum_400[] = 1254 1254 - AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf), 1255 1255 - AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf)); 1256 1256 - 1257 1257 - static const int amd_erratum_383[] = 1258 1258 - AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf)); 1259 1259 - 1260 1260 - /* #1054: Instructions Retired Performance Counter May Be Inaccurate */ 1261 1261 - static const int amd_erratum_1054[] = 1262 1262 - AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0, 0, 0x2f, 0xf)); 1263 1263 - 1264 1264 - static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum) 1265 1265 - { 1266 1266 - int osvw_id = *erratum++; 1267 1267 - u32 range; 1268 1268 - u32 ms; 1269 1269 - 1270 1270 - if (osvw_id >= 0 && osvw_id < 65536 && 1271 1271 - cpu_has(cpu, X86_FEATURE_OSVW)) { 1272 1272 - u64 osvw_len; 1273 1273 - 1274 1274 - rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len); 1275 1275 - if (osvw_id < osvw_len) { 1276 1276 - u64 osvw_bits; 1277 1277 - 1278 1278 - rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6), 1279 1279 - osvw_bits); 1280 1280 - return osvw_bits & (1ULL << (osvw_id & 0x3f)); 1281 1281 - } 1282 1282 - } 1283 1283 - 1284 1284 - /* OSVW unavailable or ID unknown, match family-model-stepping range */ 1285 1285 - ms = (cpu->x86_model << 4) | cpu->x86_stepping; 1286 1286 - while ((range = *erratum++)) 1287 1287 - if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) && 1288 1288 - (ms >= AMD_MODEL_RANGE_START(range)) && 1289 1289 - (ms <= AMD_MODEL_RANGE_END(range))) 1290 1290 - return true; 1291 1291 - 1292 1292 - return false; 1293 1293 - } 1294 1294 - 1295 1118 static DEFINE_PER_CPU_READ_MOSTLY(unsigned long[4], amd_dr_addr_mask); 1296 1119 1297 1120 static unsigned int amd_msr_dr_addr_masks[] = { ··· 1278 1235 return 255; 1279 1236 } 1280 1237 EXPORT_SYMBOL_GPL(amd_get_highest_perf); 1238 1238 + 1239 1239 + static void zenbleed_check_cpu(void *unused) 1240 1240 + { 1241 1241 + struct cpuinfo_x86 *c = &cpu_data(smp_processor_id()); 1242 1242 + 1243 1243 + zenbleed_check(c); 1244 1244 + } 1245 1245 + 1246 1246 + void amd_check_microcode(void) 1247 1247 + { 1248 1248 + on_each_cpu(zenbleed_check_cpu, NULL, 1); 1249 1249 + }

+2

arch/x86/kernel/cpu/common.c

reviewed

··· 2287 2287 2288 2288 perf_check_microcode(); 2289 2289 2290 2290 + amd_check_microcode(); 2291 2291 + 2290 2292 store_cpu_caps(&curr_info); 2291 2293 2292 2294 if (!memcmp(&prev_info->x86_capability, &curr_info.x86_capability,

+11 -7

arch/x86/kernel/traps.c

reviewed

··· 697 697 } 698 698 699 699 static bool gp_try_fixup_and_notify(struct pt_regs *regs, int trapnr, 700 700 - unsigned long error_code, const char *str) 700 700 + unsigned long error_code, const char *str, 701 701 + unsigned long address) 701 702 { 702 702 - if (fixup_exception(regs, trapnr, error_code, 0)) 703 703 + if (fixup_exception(regs, trapnr, error_code, address)) 703 704 return true; 704 705 705 706 current->thread.error_code = error_code; ··· 760 759 goto exit; 761 760 } 762 761 763 763 - if (gp_try_fixup_and_notify(regs, X86_TRAP_GP, error_code, desc)) 762 762 + if (gp_try_fixup_and_notify(regs, X86_TRAP_GP, error_code, desc, 0)) 764 763 goto exit; 765 764 766 765 if (error_code) ··· 1358 1357 1359 1358 #define VE_FAULT_STR "VE fault" 1360 1359 1361 1361 - static void ve_raise_fault(struct pt_regs *regs, long error_code) 1360 1360 + static void ve_raise_fault(struct pt_regs *regs, long error_code, 1361 1361 + unsigned long address) 1362 1362 { 1363 1363 if (user_mode(regs)) { 1364 1364 gp_user_force_sig_segv(regs, X86_TRAP_VE, error_code, VE_FAULT_STR); 1365 1365 return; 1366 1366 } 1367 1367 1368 1368 - if (gp_try_fixup_and_notify(regs, X86_TRAP_VE, error_code, VE_FAULT_STR)) 1368 1368 + if (gp_try_fixup_and_notify(regs, X86_TRAP_VE, error_code, 1369 1369 + VE_FAULT_STR, address)) { 1369 1370 return; 1371 1371 + } 1370 1372 1371 1371 - die_addr(VE_FAULT_STR, regs, error_code, 0); 1373 1373 + die_addr(VE_FAULT_STR, regs, error_code, address); 1372 1374 } 1373 1375 1374 1376 /* ··· 1435 1431 * it successfully, treat it as #GP(0) and handle it. 1436 1432 */ 1437 1433 if (!tdx_handle_virt_exception(regs, &ve)) 1438 1438 - ve_raise_fault(regs, 0); 1434 1434 + ve_raise_fault(regs, 0, ve.gla); 1439 1435 1440 1436 cond_local_irq_disable(regs); 1441 1437 }

+1 -2

block/blk-core.c

reviewed

··· 1144 1144 { 1145 1145 if (!list_empty(&plug->cb_list)) 1146 1146 flush_plug_callbacks(plug, from_schedule); 1147 1147 - if (!rq_list_empty(plug->mq_list)) 1148 1148 - blk_mq_flush_plug_list(plug, from_schedule); 1147 1147 + blk_mq_flush_plug_list(plug, from_schedule); 1149 1148 /* 1150 1149 * Unconditionally flush out cached requests, even if the unplug 1151 1150 * event came from schedule. Since we know hold references to the

+4

block/blk-iocost.c

reviewed

··· 2516 2516 u64 seek_pages = 0; 2517 2517 u64 cost = 0; 2518 2518 2519 2519 + /* Can't calculate cost for empty bio */ 2520 2520 + if (!bio->bi_iter.bi_size) 2521 2521 + goto out; 2522 2522 + 2519 2523 switch (bio_op(bio)) { 2520 2524 case REQ_OP_READ: 2521 2525 coef_seqio = ioc->params.lcoefs[LCOEF_RSEQIO];

+8 -1

block/blk-mq.c

reviewed

··· 2754 2754 { 2755 2755 struct request *rq; 2756 2756 2757 2757 - if (rq_list_empty(plug->mq_list)) 2757 2757 + /* 2758 2758 + * We may have been called recursively midway through handling 2759 2759 + * plug->mq_list via a schedule() in the driver's queue_rq() callback. 2760 2760 + * To avoid mq_list changing under our feet, clear rq_count early and 2761 2761 + * bail out specifically if rq_count is 0 rather than checking 2762 2762 + * whether the mq_list is empty. 2763 2763 + */ 2764 2764 + if (plug->rq_count == 0) 2758 2765 return; 2759 2766 plug->rq_count = 0; 2760 2767

+9

drivers/accel/habanalabs/common/habanalabs.h

reviewed

··· 3980 3980 { 3981 3981 } 3982 3982 3983 3983 + static inline int hl_debugfs_device_init(struct hl_device *hdev) 3984 3984 + { 3985 3985 + return 0; 3986 3986 + } 3987 3987 + 3988 3988 + static inline void hl_debugfs_device_fini(struct hl_device *hdev) 3989 3989 + { 3990 3990 + } 3991 3991 + 3983 3992 static inline void hl_debugfs_add_device(struct hl_device *hdev) 3984 3993 { 3985 3994 }

+25 -14

drivers/accel/qaic/qaic_control.c

reviewed

··· 14 14 #include <linux/mm.h> 15 15 #include <linux/moduleparam.h> 16 16 #include <linux/mutex.h> 17 17 + #include <linux/overflow.h> 17 18 #include <linux/pci.h> 18 19 #include <linux/scatterlist.h> 19 20 #include <linux/types.h> ··· 367 366 if (in_trans->hdr.len % 8 != 0) 368 367 return -EINVAL; 369 368 370 370 - if (msg_hdr_len + in_trans->hdr.len > QAIC_MANAGE_EXT_MSG_LENGTH) 369 369 + if (size_add(msg_hdr_len, in_trans->hdr.len) > QAIC_MANAGE_EXT_MSG_LENGTH) 371 370 return -ENOSPC; 372 371 373 372 trans_wrapper = add_wrapper(wrappers, ··· 419 418 } 420 419 421 420 ret = get_user_pages_fast(xfer_start_addr, nr_pages, 0, page_list); 422 422 - if (ret < 0 || ret != nr_pages) { 423 423 - ret = -EFAULT; 421 421 + if (ret < 0) 424 422 goto free_page_list; 423 423 + if (ret != nr_pages) { 424 424 + nr_pages = ret; 425 425 + ret = -EFAULT; 426 426 + goto put_pages; 425 427 } 426 428 427 429 sgt = kmalloc(sizeof(*sgt), GFP_KERNEL); ··· 561 557 msg = &wrapper->msg; 562 558 msg_hdr_len = le32_to_cpu(msg->hdr.len); 563 559 564 564 - if (msg_hdr_len > (UINT_MAX - QAIC_MANAGE_EXT_MSG_LENGTH)) 565 565 - return -EINVAL; 566 566 - 567 560 /* There should be enough space to hold at least one ASP entry. */ 568 568 - if (msg_hdr_len + sizeof(*out_trans) + sizeof(struct wire_addr_size_pair) > 561 561 + if (size_add(msg_hdr_len, sizeof(*out_trans) + sizeof(struct wire_addr_size_pair)) > 569 562 QAIC_MANAGE_EXT_MSG_LENGTH) 570 563 return -ENOMEM; 571 564 ··· 635 634 msg = &wrapper->msg; 636 635 msg_hdr_len = le32_to_cpu(msg->hdr.len); 637 636 638 638 - if (msg_hdr_len + sizeof(*out_trans) > QAIC_MANAGE_MAX_MSG_LENGTH) 637 637 + if (size_add(msg_hdr_len, sizeof(*out_trans)) > QAIC_MANAGE_MAX_MSG_LENGTH) 639 638 return -ENOSPC; 640 639 641 640 if (!in_trans->queue_size) ··· 719 718 msg = &wrapper->msg; 720 719 msg_hdr_len = le32_to_cpu(msg->hdr.len); 721 720 722 722 - if (msg_hdr_len + in_trans->hdr.len > QAIC_MANAGE_MAX_MSG_LENGTH) 721 721 + if (size_add(msg_hdr_len, in_trans->hdr.len) > QAIC_MANAGE_MAX_MSG_LENGTH) 723 722 return -ENOSPC; 724 723 725 724 trans_wrapper = add_wrapper(wrappers, sizeof(*trans_wrapper)); ··· 749 748 int ret; 750 749 int i; 751 750 752 752 - if (!user_msg->count) { 751 751 + if (!user_msg->count || 752 752 + user_msg->len < sizeof(*trans_hdr)) { 753 753 ret = -EINVAL; 754 754 goto out; 755 755 } ··· 767 765 } 768 766 769 767 for (i = 0; i < user_msg->count; ++i) { 770 770 - if (user_len >= user_msg->len) { 768 768 + if (user_len > user_msg->len - sizeof(*trans_hdr)) { 771 769 ret = -EINVAL; 772 770 break; 773 771 } 774 772 trans_hdr = (struct qaic_manage_trans_hdr *)(user_msg->data + user_len); 775 775 - if (user_len + trans_hdr->len > user_msg->len) { 773 773 + if (trans_hdr->len < sizeof(trans_hdr) || 774 774 + size_add(user_len, trans_hdr->len) > user_msg->len) { 776 775 ret = -EINVAL; 777 776 break; 778 777 } ··· 956 953 int ret; 957 954 int i; 958 955 959 959 - if (msg_hdr_len > QAIC_MANAGE_MAX_MSG_LENGTH) 956 956 + if (msg_hdr_len < sizeof(*trans_hdr) || 957 957 + msg_hdr_len > QAIC_MANAGE_MAX_MSG_LENGTH) 960 958 return -EINVAL; 961 959 962 960 user_msg->len = 0; 963 961 user_msg->count = le32_to_cpu(msg->hdr.count); 964 962 965 963 for (i = 0; i < user_msg->count; ++i) { 964 964 + u32 hdr_len; 965 965 + 966 966 + if (msg_len > msg_hdr_len - sizeof(*trans_hdr)) 967 967 + return -EINVAL; 968 968 + 966 969 trans_hdr = (struct wire_trans_hdr *)(msg->data + msg_len); 967 967 - if (msg_len + le32_to_cpu(trans_hdr->len) > msg_hdr_len) 970 970 + hdr_len = le32_to_cpu(trans_hdr->len); 971 971 + if (hdr_len < sizeof(*trans_hdr) || 972 972 + size_add(msg_len, hdr_len) > msg_hdr_len) 968 973 return -EINVAL; 969 974 970 975 switch (le32_to_cpu(trans_hdr->type)) {

+2

drivers/ata/pata_parport/aten.c

reviewed

··· 139 139 }; 140 140 141 141 MODULE_LICENSE("GPL"); 142 142 + MODULE_AUTHOR("Grant R. Guenther <grant@torque.net>"); 143 143 + MODULE_DESCRIPTION("ATEN EH-100 parallel port IDE adapter protocol driver"); 142 144 module_pata_parport_driver(aten);

+2

drivers/ata/pata_parport/bpck.c

reviewed

··· 502 502 }; 503 503 504 504 MODULE_LICENSE("GPL"); 505 505 + MODULE_AUTHOR("Grant R. Guenther <grant@torque.net>"); 506 506 + MODULE_DESCRIPTION("MicroSolutions BACKPACK parallel port IDE adapter protocol driver"); 505 507 module_pata_parport_driver(bpck);

+2 -1

drivers/ata/pata_parport/bpck6.c

reviewed

··· 459 459 460 460 MODULE_LICENSE("GPL"); 461 461 MODULE_AUTHOR("Micro Solutions Inc."); 462 462 - MODULE_DESCRIPTION("BACKPACK Protocol module, compatible with PARIDE"); 462 462 + MODULE_DESCRIPTION("Micro Solutions BACKPACK parallel port IDE adapter " 463 463 + "(version 6 drives) protocol driver"); 463 464 module_pata_parport_driver(bpck6);

+2

drivers/ata/pata_parport/comm.c

reviewed

··· 201 201 }; 202 202 203 203 MODULE_LICENSE("GPL"); 204 204 + MODULE_AUTHOR("Grant R. Guenther <grant@torque.net>"); 205 205 + MODULE_DESCRIPTION("DataStor Commuter parallel port IDE adapter protocol driver"); 204 206 module_pata_parport_driver(comm);

+2

drivers/ata/pata_parport/dstr.c

reviewed

··· 230 230 }; 231 231 232 232 MODULE_LICENSE("GPL"); 233 233 + MODULE_AUTHOR("Grant R. Guenther <grant@torque.net>"); 234 234 + MODULE_DESCRIPTION("DataStor EP2000 parallel port IDE adapter protocol driver"); 233 235 module_pata_parport_driver(dstr);

+3

drivers/ata/pata_parport/epat.c

reviewed

··· 358 358 } 359 359 360 360 MODULE_LICENSE("GPL"); 361 361 + MODULE_AUTHOR("Grant R. Guenther <grant@torque.net>"); 362 362 + MODULE_DESCRIPTION("Shuttle Technologies EPAT parallel port IDE adapter " 363 363 + "protocol driver"); 361 364 module_init(epat_init) 362 365 module_exit(epat_exit)

+3

drivers/ata/pata_parport/epia.c

reviewed

··· 306 306 }; 307 307 308 308 MODULE_LICENSE("GPL"); 309 309 + MODULE_AUTHOR("Grant R. Guenther <grant@torque.net>"); 310 310 + MODULE_DESCRIPTION("Shuttle Technologies EPIA parallel port IDE adapter " 311 311 + "protocol driver"); 309 312 module_pata_parport_driver(epia);

+3

drivers/ata/pata_parport/fit2.c

reviewed

··· 132 132 }; 133 133 134 134 MODULE_LICENSE("GPL"); 135 135 + MODULE_AUTHOR("Grant R. Guenther <grant@torque.net>"); 136 136 + MODULE_DESCRIPTION("Fidelity International Technology parallel port IDE adapter" 137 137 + "(older models) protocol driver"); 135 138 module_pata_parport_driver(fit2);

+3

drivers/ata/pata_parport/fit3.c

reviewed

··· 193 193 }; 194 194 195 195 MODULE_LICENSE("GPL"); 196 196 + MODULE_AUTHOR("Grant R. Guenther <grant@torque.net>"); 197 197 + MODULE_DESCRIPTION("Fidelity International Technology parallel port IDE adapter" 198 198 + "(newer models) protocol driver"); 196 199 module_pata_parport_driver(fit3);

+2

drivers/ata/pata_parport/friq.c

reviewed

··· 259 259 }; 260 260 261 261 MODULE_LICENSE("GPL"); 262 262 + MODULE_AUTHOR("Grant R. Guenther <grant@torque.net>"); 263 263 + MODULE_DESCRIPTION("Freecom IQ parallel port IDE adapter protocol driver"); 262 264 module_pata_parport_driver(friq);

+2

drivers/ata/pata_parport/frpw.c

reviewed

··· 293 293 }; 294 294 295 295 MODULE_LICENSE("GPL"); 296 296 + MODULE_AUTHOR("Grant R. Guenther <grant@torque.net>"); 297 297 + MODULE_DESCRIPTION("Freecom Power parallel port IDE adapter protocol driver"); 296 298 module_pata_parport_driver(frpw);

+3

drivers/ata/pata_parport/kbic.c

reviewed

··· 301 301 } 302 302 303 303 MODULE_LICENSE("GPL"); 304 304 + MODULE_AUTHOR("Grant R. Guenther <grant@torque.net>"); 305 305 + MODULE_DESCRIPTION("KingByte Information Systems KBIC-951A and KBIC-971A " 306 306 + "parallel port IDE adapter protocol driver"); 304 307 module_init(kbic_init) 305 308 module_exit(kbic_exit)

+2

drivers/ata/pata_parport/ktti.c

reviewed

··· 106 106 }; 107 107 108 108 MODULE_LICENSE("GPL"); 109 109 + MODULE_AUTHOR("Grant R. Guenther <grant@torque.net>"); 110 110 + MODULE_DESCRIPTION("KT Technology parallel port IDE adapter protocol driver"); 109 111 module_pata_parport_driver(ktti);

+2

drivers/ata/pata_parport/on20.c

reviewed

··· 142 142 }; 143 143 144 144 MODULE_LICENSE("GPL"); 145 145 + MODULE_AUTHOR("Grant R. Guenther <grant@torque.net>"); 146 146 + MODULE_DESCRIPTION("Onspec 90c20 parallel port IDE adapter protocol driver"); 145 147 module_pata_parport_driver(on20);

+2

drivers/ata/pata_parport/on26.c

reviewed

··· 310 310 }; 311 311 312 312 MODULE_LICENSE("GPL"); 313 313 + MODULE_AUTHOR("Grant R. Guenther <grant@torque.net>"); 314 314 + MODULE_DESCRIPTION("Onspec 90c26 parallel port IDE adapter protocol driver"); 313 315 module_pata_parport_driver(on26);

+4

drivers/base/regmap/regcache-rbtree.c

reviewed

··· 471 471 unsigned int start, end; 472 472 int ret; 473 473 474 474 + map->async = true; 475 475 + 474 476 rbtree_ctx = map->cache; 475 477 for (node = rb_first(&rbtree_ctx->root); node; node = rb_next(node)) { 476 478 rbnode = rb_entry(node, struct regcache_rbtree_node, node); ··· 500 498 if (ret != 0) 501 499 return ret; 502 500 } 501 501 + 502 502 + map->async = false; 503 503 504 504 return regmap_async_complete(map); 505 505 }

-3

drivers/base/regmap/regcache.c

reviewed

··· 368 368 if (!map->cache_dirty) 369 369 goto out; 370 370 371 371 - map->async = true; 372 372 - 373 371 /* Apply any patch first */ 374 372 map->cache_bypass = true; 375 373 for (i = 0; i < map->patch_regs; i++) { ··· 390 392 391 393 out: 392 394 /* Restore the bypass state */ 393 393 - map->async = false; 394 395 map->cache_bypass = bypass; 395 396 map->no_sync_defaults = false; 396 397 map->unlock(map->lock_arg);

+4 -4

drivers/base/regmap/regmap-i2c.c

reviewed

··· 242 242 static const struct regmap_bus regmap_i2c_smbus_i2c_block = { 243 243 .write = regmap_i2c_smbus_i2c_write, 244 244 .read = regmap_i2c_smbus_i2c_read, 245 245 - .max_raw_read = I2C_SMBUS_BLOCK_MAX, 246 246 - .max_raw_write = I2C_SMBUS_BLOCK_MAX, 245 245 + .max_raw_read = I2C_SMBUS_BLOCK_MAX - 1, 246 246 + .max_raw_write = I2C_SMBUS_BLOCK_MAX - 1, 247 247 }; 248 248 249 249 static int regmap_i2c_smbus_i2c_write_reg16(void *context, const void *data, ··· 299 299 static const struct regmap_bus regmap_i2c_smbus_i2c_block_reg16 = { 300 300 .write = regmap_i2c_smbus_i2c_write_reg16, 301 301 .read = regmap_i2c_smbus_i2c_read_reg16, 302 302 - .max_raw_read = I2C_SMBUS_BLOCK_MAX, 303 303 - .max_raw_write = I2C_SMBUS_BLOCK_MAX, 302 302 + .max_raw_read = I2C_SMBUS_BLOCK_MAX - 2, 303 303 + .max_raw_write = I2C_SMBUS_BLOCK_MAX - 2, 304 304 }; 305 305 306 306 static const struct regmap_bus *regmap_get_i2c_bus(struct i2c_client *i2c,

+5

drivers/base/regmap/regmap-kunit.c

reviewed

··· 58 58 int i; 59 59 struct reg_default *defaults; 60 60 61 61 + config->disable_locking = config->cache_type == REGCACHE_RBTREE || 62 62 + config->cache_type == REGCACHE_MAPLE; 63 63 + 61 64 buf = kmalloc(size, GFP_KERNEL); 62 65 if (!buf) 63 66 return ERR_PTR(-ENOMEM); ··· 892 889 893 890 config->cache_type = test_type->cache_type; 894 891 config->val_format_endian = test_type->val_endian; 892 892 + config->disable_locking = config->cache_type == REGCACHE_RBTREE || 893 893 + config->cache_type == REGCACHE_MAPLE; 895 894 896 895 buf = kmalloc(size, GFP_KERNEL); 897 896 if (!buf)

+1 -1

drivers/base/regmap/regmap-spi-avmm.c

reviewed

··· 660 660 .reg_format_endian_default = REGMAP_ENDIAN_NATIVE, 661 661 .val_format_endian_default = REGMAP_ENDIAN_NATIVE, 662 662 .max_raw_read = SPI_AVMM_VAL_SIZE * MAX_READ_CNT, 663 663 - .max_raw_write = SPI_AVMM_REG_SIZE + SPI_AVMM_VAL_SIZE * MAX_WRITE_CNT, 663 663 + .max_raw_write = SPI_AVMM_VAL_SIZE * MAX_WRITE_CNT, 664 664 .free_context = spi_avmm_bridge_ctx_free, 665 665 }; 666 666

+2 -4

drivers/base/regmap/regmap.c

reviewed

··· 2082 2082 size_t val_count = val_len / val_bytes; 2083 2083 size_t chunk_count, chunk_bytes; 2084 2084 size_t chunk_regs = val_count; 2085 2085 - size_t max_data = map->max_raw_write - map->format.reg_bytes - 2086 2086 - map->format.pad_bytes; 2087 2085 int ret, i; 2088 2086 2089 2087 if (!val_count) ··· 2089 2091 2090 2092 if (map->use_single_write) 2091 2093 chunk_regs = 1; 2092 2092 - else if (map->max_raw_write && val_len > max_data) 2093 2093 - chunk_regs = max_data / val_bytes; 2094 2094 + else if (map->max_raw_write && val_len > map->max_raw_write) 2095 2095 + chunk_regs = map->max_raw_write / val_bytes; 2094 2096 2095 2097 chunk_count = val_count / chunk_regs; 2096 2098 chunk_bytes = chunk_regs * val_bytes;

+38 -2

drivers/block/loop.c

reviewed

··· 1775 1775 /* 1776 1776 * If max_loop is specified, create that many devices upfront. 1777 1777 * This also becomes a hard limit. If max_loop is not specified, 1778 1778 + * the default isn't a hard limit (as before commit 85c50197716c 1779 1779 + * changed the default value from 0 for max_loop=0 reasons), just 1778 1780 * create CONFIG_BLK_DEV_LOOP_MIN_COUNT loop devices at module 1779 1781 * init time. Loop devices can be requested on-demand with the 1780 1782 * /dev/loop-control interface, or be instantiated by accessing 1781 1783 * a 'dead' device node. 1782 1784 */ 1783 1785 static int max_loop = CONFIG_BLK_DEV_LOOP_MIN_COUNT; 1784 1784 - module_param(max_loop, int, 0444); 1786 1786 + 1787 1787 + #ifdef CONFIG_BLOCK_LEGACY_AUTOLOAD 1788 1788 + static bool max_loop_specified; 1789 1789 + 1790 1790 + static int max_loop_param_set_int(const char *val, 1791 1791 + const struct kernel_param *kp) 1792 1792 + { 1793 1793 + int ret; 1794 1794 + 1795 1795 + ret = param_set_int(val, kp); 1796 1796 + if (ret < 0) 1797 1797 + return ret; 1798 1798 + 1799 1799 + max_loop_specified = true; 1800 1800 + return 0; 1801 1801 + } 1802 1802 + 1803 1803 + static const struct kernel_param_ops max_loop_param_ops = { 1804 1804 + .set = max_loop_param_set_int, 1805 1805 + .get = param_get_int, 1806 1806 + }; 1807 1807 + 1808 1808 + module_param_cb(max_loop, &max_loop_param_ops, &max_loop, 0444); 1785 1809 MODULE_PARM_DESC(max_loop, "Maximum number of loop devices"); 1810 1810 + #else 1811 1811 + module_param(max_loop, int, 0444); 1812 1812 + MODULE_PARM_DESC(max_loop, "Initial number of loop devices"); 1813 1813 + #endif 1814 1814 + 1786 1815 module_param(max_part, int, 0444); 1787 1816 MODULE_PARM_DESC(max_part, "Maximum number of partitions per loop device"); 1788 1817 ··· 2122 2093 put_disk(lo->lo_disk); 2123 2094 } 2124 2095 2096 2096 + #ifdef CONFIG_BLOCK_LEGACY_AUTOLOAD 2125 2097 static void loop_probe(dev_t dev) 2126 2098 { 2127 2099 int idx = MINOR(dev) >> part_shift; 2128 2100 2129 2129 - if (max_loop && idx >= max_loop) 2101 2101 + if (max_loop_specified && max_loop && idx >= max_loop) 2130 2102 return; 2131 2103 loop_add(idx); 2132 2104 } 2105 2105 + #else 2106 2106 + #define loop_probe NULL 2107 2107 + #endif /* !CONFIG_BLOCK_LEGACY_AUTOLOAD */ 2133 2108 2134 2109 static int loop_control_remove(int idx) 2135 2110 { ··· 2314 2281 static int __init max_loop_setup(char *str) 2315 2282 { 2316 2283 max_loop = simple_strtol(str, NULL, 0); 2284 2284 + #ifdef CONFIG_BLOCK_LEGACY_AUTOLOAD 2285 2285 + max_loop_specified = true; 2286 2286 + #endif 2317 2287 return 1; 2318 2288 } 2319 2289

+9 -4

drivers/dma-buf/dma-resv.c

reviewed

··· 571 571 dma_resv_for_each_fence_unlocked(&cursor, fence) { 572 572 573 573 if (dma_resv_iter_is_restarted(&cursor)) { 574 574 + struct dma_fence **new_fences; 574 575 unsigned int count; 575 576 576 577 while (*num_fences) ··· 580 579 count = cursor.num_fences + 1; 581 580 582 581 /* Eventually re-allocate the array */ 583 583 - *fences = krealloc_array(*fences, count, 584 584 - sizeof(void *), 585 585 - GFP_KERNEL); 586 586 - if (count && !*fences) { 582 582 + new_fences = krealloc_array(*fences, count, 583 583 + sizeof(void *), 584 584 + GFP_KERNEL); 585 585 + if (count && !new_fences) { 586 586 + kfree(*fences); 587 587 + *fences = NULL; 588 588 + *num_fences = 0; 587 589 dma_resv_iter_end(&cursor); 588 590 return -ENOMEM; 589 591 } 592 592 + *fences = new_fences; 590 593 } 591 594 592 595 (*fences)[(*num_fences)++] = dma_fence_get(fence);

+15 -11

drivers/gpio/gpio-mvebu.c

reviewed

··· 874 874 875 875 spin_lock_init(&mvpwm->lock); 876 876 877 877 - return pwmchip_add(&mvpwm->chip); 877 877 + return devm_pwmchip_add(dev, &mvpwm->chip); 878 878 } 879 879 880 880 #ifdef CONFIG_DEBUG_FS ··· 1112 1112 return 0; 1113 1113 } 1114 1114 1115 1115 + static void mvebu_gpio_remove_irq_domain(void *data) 1116 1116 + { 1117 1117 + struct irq_domain *domain = data; 1118 1118 + 1119 1119 + irq_domain_remove(domain); 1120 1120 + } 1121 1121 + 1115 1122 static int mvebu_gpio_probe(struct platform_device *pdev) 1116 1123 { 1117 1124 struct mvebu_gpio_chip *mvchip; ··· 1250 1243 if (!mvchip->domain) { 1251 1244 dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n", 1252 1245 mvchip->chip.label); 1253 1253 - err = -ENODEV; 1254 1254 - goto err_pwm; 1246 1246 + return -ENODEV; 1255 1247 } 1248 1248 + 1249 1249 + err = devm_add_action_or_reset(&pdev->dev, mvebu_gpio_remove_irq_domain, 1250 1250 + mvchip->domain); 1251 1251 + if (err) 1252 1252 + return err; 1256 1253 1257 1254 err = irq_alloc_domain_generic_chips( 1258 1255 mvchip->domain, ngpios, 2, np->name, handle_level_irq, ··· 1264 1253 if (err) { 1265 1254 dev_err(&pdev->dev, "couldn't allocate irq chips %s (DT).\n", 1266 1255 mvchip->chip.label); 1267 1267 - goto err_domain; 1256 1256 + return err; 1268 1257 } 1269 1258 1270 1259 /* ··· 1304 1293 } 1305 1294 1306 1295 return 0; 1307 1307 - 1308 1308 - err_domain: 1309 1309 - irq_domain_remove(mvchip->domain); 1310 1310 - err_pwm: 1311 1311 - pwmchip_remove(&mvchip->mvpwm->chip); 1312 1312 - 1313 1313 - return err; 1314 1296 } 1315 1297 1316 1298 static struct platform_driver mvebu_gpio_driver = {

+3 -3

drivers/gpio/gpio-tps68470.c

reviewed

··· 91 91 struct tps68470_gpio_data *tps68470_gpio = gpiochip_get_data(gc); 92 92 struct regmap *regmap = tps68470_gpio->tps68470_regmap; 93 93 94 94 + /* Set the initial value */ 95 95 + tps68470_gpio_set(gc, offset, value); 96 96 + 94 97 /* rest are always outputs */ 95 98 if (offset >= TPS68470_N_REGULAR_GPIO) 96 99 return 0; 97 97 - 98 98 - /* Set the initial value */ 99 99 - tps68470_gpio_set(gc, offset, value); 100 100 101 101 return regmap_update_bits(regmap, TPS68470_GPIO_CTL_REG_A(offset), 102 102 TPS68470_GPIO_MODE_MASK,

+2 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

reviewed

··· 1709 1709 alloc_flags |= (flags & KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC) ? 1710 1710 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED : 0; 1711 1711 } 1712 1712 - xcp_id = fpriv->xcp_id == ~0 ? 0 : fpriv->xcp_id; 1712 1712 + xcp_id = fpriv->xcp_id == AMDGPU_XCP_NO_PARTITION ? 1713 1713 + 0 : fpriv->xcp_id; 1713 1714 } else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_GTT) { 1714 1715 domain = alloc_domain = AMDGPU_GEM_DOMAIN_GTT; 1715 1716 alloc_flags = 0;

+3 -3

drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

reviewed

··· 1229 1229 pasid = 0; 1230 1230 } 1231 1231 1232 1232 - r = amdgpu_vm_init(adev, &fpriv->vm); 1232 1232 + r = amdgpu_xcp_open_device(adev, fpriv, file_priv); 1233 1233 if (r) 1234 1234 goto error_pasid; 1235 1235 1236 1236 - r = amdgpu_xcp_open_device(adev, fpriv, file_priv); 1236 1236 + r = amdgpu_vm_init(adev, &fpriv->vm, fpriv->xcp_id); 1237 1237 if (r) 1238 1238 - goto error_vm; 1238 1238 + goto error_pasid; 1239 1239 1240 1240 r = amdgpu_vm_set_pasid(adev, &fpriv->vm, pasid); 1241 1241 if (r)

+1 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c

reviewed

··· 1382 1382 goto error_pasid; 1383 1383 } 1384 1384 1385 1385 - r = amdgpu_vm_init(adev, vm); 1385 1385 + r = amdgpu_vm_init(adev, vm, -1); 1386 1386 if (r) { 1387 1387 DRM_ERROR("failed to initialize vm\n"); 1388 1388 goto error_pasid;

+3 -2

drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c

reviewed

··· 55 55 DRM_WARN("%s: vblank timer overrun\n", __func__); 56 56 57 57 ret = drm_crtc_handle_vblank(crtc); 58 58 + /* Don't queue timer again when vblank is disabled. */ 58 59 if (!ret) 59 59 - DRM_ERROR("amdgpu_vkms failure on handling vblank"); 60 60 + return HRTIMER_NORESTART; 60 61 61 62 return HRTIMER_RESTART; 62 63 } ··· 82 81 { 83 82 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 84 83 85 85 - hrtimer_cancel(&amdgpu_crtc->vblank_timer); 84 84 + hrtimer_try_to_cancel(&amdgpu_crtc->vblank_timer); 86 85 } 87 86 88 87 static bool amdgpu_vkms_get_vblank_timestamp(struct drm_crtc *crtc,

+3 -2

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c

reviewed

··· 2121 2121 * 2122 2122 * @adev: amdgpu_device pointer 2123 2123 * @vm: requested vm 2124 2124 + * @xcp_id: GPU partition selection id 2124 2125 * 2125 2126 * Init @vm fields. 2126 2127 * 2127 2128 * Returns: 2128 2129 * 0 for success, error for failure. 2129 2130 */ 2130 2130 - int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm) 2131 2131 + int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, int32_t xcp_id) 2131 2132 { 2132 2133 struct amdgpu_bo *root_bo; 2133 2134 struct amdgpu_bo_vm *root; ··· 2178 2177 vm->evicting = false; 2179 2178 2180 2179 r = amdgpu_vm_pt_create(adev, vm, adev->vm_manager.root_level, 2181 2181 - false, &root); 2180 2180 + false, &root, xcp_id); 2182 2181 if (r) 2183 2182 goto error_free_delayed; 2184 2183 root_bo = &root->bo;

+3 -2

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h

reviewed

··· 392 392 u32 pasid); 393 393 394 394 long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout); 395 395 - int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm); 395 395 + int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, int32_t xcp_id); 396 396 int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm); 397 397 void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm); 398 398 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm); ··· 475 475 int amdgpu_vm_pt_clear(struct amdgpu_device *adev, struct amdgpu_vm *vm, 476 476 struct amdgpu_bo_vm *vmbo, bool immediate); 477 477 int amdgpu_vm_pt_create(struct amdgpu_device *adev, struct amdgpu_vm *vm, 478 478 - int level, bool immediate, struct amdgpu_bo_vm **vmbo); 478 478 + int level, bool immediate, struct amdgpu_bo_vm **vmbo, 479 479 + int32_t xcp_id); 479 480 void amdgpu_vm_pt_free_root(struct amdgpu_device *adev, struct amdgpu_vm *vm); 480 481 bool amdgpu_vm_pt_is_root_clean(struct amdgpu_device *adev, 481 482 struct amdgpu_vm *vm);

+7 -5

drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c

reviewed

··· 498 498 * @level: the page table level 499 499 * @immediate: use a immediate update 500 500 * @vmbo: pointer to the buffer object pointer 501 501 + * @xcp_id: GPU partition id 501 502 */ 502 503 int amdgpu_vm_pt_create(struct amdgpu_device *adev, struct amdgpu_vm *vm, 503 503 - int level, bool immediate, struct amdgpu_bo_vm **vmbo) 504 504 + int level, bool immediate, struct amdgpu_bo_vm **vmbo, 505 505 + int32_t xcp_id) 504 506 { 505 505 - struct amdgpu_fpriv *fpriv = container_of(vm, struct amdgpu_fpriv, vm); 506 507 struct amdgpu_bo_param bp; 507 508 struct amdgpu_bo *bo; 508 509 struct dma_resv *resv; ··· 536 535 537 536 bp.type = ttm_bo_type_kernel; 538 537 bp.no_wait_gpu = immediate; 539 539 - bp.xcp_id_plus1 = fpriv->xcp_id == ~0 ? 0 : fpriv->xcp_id + 1; 538 538 + bp.xcp_id_plus1 = xcp_id + 1; 540 539 541 540 if (vm->root.bo) 542 541 bp.resv = vm->root.bo->tbo.base.resv; ··· 562 561 bp.type = ttm_bo_type_kernel; 563 562 bp.resv = bo->tbo.base.resv; 564 563 bp.bo_ptr_size = sizeof(struct amdgpu_bo); 565 565 - bp.xcp_id_plus1 = fpriv->xcp_id == ~0 ? 0 : fpriv->xcp_id + 1; 564 564 + bp.xcp_id_plus1 = xcp_id + 1; 566 565 567 566 r = amdgpu_bo_create(adev, &bp, &(*vmbo)->shadow); 568 567 ··· 607 606 return 0; 608 607 609 608 amdgpu_vm_eviction_unlock(vm); 610 610 - r = amdgpu_vm_pt_create(adev, vm, cursor->level, immediate, &pt); 609 609 + r = amdgpu_vm_pt_create(adev, vm, cursor->level, immediate, &pt, 610 610 + vm->root.bo->xcp_id); 611 611 amdgpu_vm_eviction_lock(vm); 612 612 if (r) 613 613 return r;

+2 -2

drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c

reviewed

··· 363 363 if (!adev->xcp_mgr) 364 364 return 0; 365 365 366 366 - fpriv->xcp_id = ~0; 366 366 + fpriv->xcp_id = AMDGPU_XCP_NO_PARTITION; 367 367 for (i = 0; i < MAX_XCP; ++i) { 368 368 if (!adev->xcp_mgr->xcp[i].ddev) 369 369 break; ··· 381 381 } 382 382 } 383 383 384 384 - fpriv->vm.mem_id = fpriv->xcp_id == ~0 ? -1 : 384 384 + fpriv->vm.mem_id = fpriv->xcp_id == AMDGPU_XCP_NO_PARTITION ? -1 : 385 385 adev->xcp_mgr->xcp[fpriv->xcp_id].mem_id; 386 386 return 0; 387 387 }

+2

drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h

reviewed

··· 37 37 #define AMDGPU_XCP_FL_NONE 0 38 38 #define AMDGPU_XCP_FL_LOCKED (1 << 0) 39 39 40 40 + #define AMDGPU_XCP_NO_PARTITION (~0) 41 41 + 40 42 struct amdgpu_fpriv; 41 43 42 44 enum AMDGPU_XCP_IP_BLOCK {

+2 -2

drivers/gpu/drm/amd/amdgpu/aqua_vanjaram_reg_init.c

reviewed

··· 68 68 enum AMDGPU_XCP_IP_BLOCK ip_blk; 69 69 uint32_t inst_mask; 70 70 71 71 - ring->xcp_id = ~0; 71 71 + ring->xcp_id = AMDGPU_XCP_NO_PARTITION; 72 72 if (adev->xcp_mgr->mode == AMDGPU_XCP_MODE_NONE) 73 73 return; 74 74 ··· 177 177 u32 sel_xcp_id; 178 178 int i; 179 179 180 180 - if (fpriv->xcp_id == ~0) { 180 180 + if (fpriv->xcp_id == AMDGPU_XCP_NO_PARTITION) { 181 181 u32 least_ref_cnt = ~0; 182 182 183 183 fpriv->xcp_id = 0;

+1

drivers/gpu/drm/amd/amdgpu/psp_v13_0.c

reviewed

··· 49 49 MODULE_FIRMWARE("amdgpu/psp_13_0_11_toc.bin"); 50 50 MODULE_FIRMWARE("amdgpu/psp_13_0_11_ta.bin"); 51 51 MODULE_FIRMWARE("amdgpu/psp_13_0_6_sos.bin"); 52 52 + MODULE_FIRMWARE("amdgpu/psp_13_0_6_ta.bin"); 52 53 53 54 /* For large FW files the time to complete can be very long */ 54 55 #define USBC_PD_POLLING_LIMIT_S 240

+103 -153

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

reviewed

··· 424 424 425 425 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 426 426 427 427 - if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){ 428 428 - DC_LOG_PFLIP("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n", 429 429 - amdgpu_crtc->pflip_status, 430 430 - AMDGPU_FLIP_SUBMITTED, 431 431 - amdgpu_crtc->crtc_id, 432 432 - amdgpu_crtc); 427 427 + if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) { 428 428 + DC_LOG_PFLIP("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p]\n", 429 429 + amdgpu_crtc->pflip_status, 430 430 + AMDGPU_FLIP_SUBMITTED, 431 431 + amdgpu_crtc->crtc_id, 432 432 + amdgpu_crtc); 433 433 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 434 434 return; 435 435 } ··· 883 883 } 884 884 885 885 /* Prototypes of private functions */ 886 886 - static int dm_early_init(void* handle); 886 886 + static int dm_early_init(void *handle); 887 887 888 888 /* Allocate memory for FBC compressed data */ 889 889 static void amdgpu_dm_fbc_init(struct drm_connector *connector) ··· 1282 1282 pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18; 1283 1283 pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18; 1284 1284 1285 1285 - pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24 ; 1285 1285 + pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24; 1286 1286 pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24; 1287 1287 pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24; 1288 1288 ··· 1347 1347 if (amdgpu_in_reset(adev)) 1348 1348 goto skip; 1349 1349 1350 1350 + if (offload_work->data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY || 1351 1351 + offload_work->data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) { 1352 1352 + dm_handle_mst_sideband_msg_ready_event(&aconnector->mst_mgr, DOWN_OR_UP_MSG_RDY_EVENT); 1353 1353 + spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags); 1354 1354 + offload_work->offload_wq->is_handling_mst_msg_rdy_event = false; 1355 1355 + spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags); 1356 1356 + goto skip; 1357 1357 + } 1358 1358 + 1350 1359 mutex_lock(&adev->dm.dc_lock); 1351 1360 if (offload_work->data.bytes.device_service_irq.bits.AUTOMATED_TEST) { 1352 1361 dc_link_dp_handle_automated_test(dc_link); ··· 1374 1365 DP_TEST_RESPONSE, 1375 1366 &test_response.raw, 1376 1367 sizeof(test_response)); 1377 1377 - } 1378 1378 - else if ((dc_link->connector_signal != SIGNAL_TYPE_EDP) && 1368 1368 + } else if ((dc_link->connector_signal != SIGNAL_TYPE_EDP) && 1379 1369 dc_link_check_link_loss_status(dc_link, &offload_work->data) && 1380 1370 dc_link_dp_allow_hpd_rx_irq(dc_link)) { 1381 1371 /* offload_work->data is from handle_hpd_rx_irq-> ··· 1562 1554 mutex_init(&adev->dm.dc_lock); 1563 1555 mutex_init(&adev->dm.audio_lock); 1564 1556 1565 1565 - if(amdgpu_dm_irq_init(adev)) { 1557 1557 + if (amdgpu_dm_irq_init(adev)) { 1566 1558 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n"); 1567 1559 goto error; 1568 1560 } ··· 1704 1696 if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER) 1705 1697 adev->dm.dc->debug.disable_stutter = true; 1706 1698 1707 1707 - if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) { 1699 1699 + if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) 1708 1700 adev->dm.dc->debug.disable_dsc = true; 1709 1709 - } 1710 1701 1711 1702 if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING) 1712 1703 adev->dm.dc->debug.disable_clock_gate = true; ··· 1949 1942 mutex_destroy(&adev->dm.audio_lock); 1950 1943 mutex_destroy(&adev->dm.dc_lock); 1951 1944 mutex_destroy(&adev->dm.dpia_aux_lock); 1952 1952 - 1953 1953 - return; 1954 1945 } 1955 1946 1956 1947 static int load_dmcu_fw(struct amdgpu_device *adev) ··· 1957 1952 int r; 1958 1953 const struct dmcu_firmware_header_v1_0 *hdr; 1959 1954 1960 1960 - switch(adev->asic_type) { 1955 1955 + switch (adev->asic_type) { 1961 1956 #if defined(CONFIG_DRM_AMD_DC_SI) 1962 1957 case CHIP_TAHITI: 1963 1958 case CHIP_PITCAIRN: ··· 2714 2709 struct dc_scaling_info scaling_infos[MAX_SURFACES]; 2715 2710 struct dc_flip_addrs flip_addrs[MAX_SURFACES]; 2716 2711 struct dc_stream_update stream_update; 2717 2717 - } * bundle; 2712 2712 + } *bundle; 2718 2713 int k, m; 2719 2714 2720 2715 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL); ··· 2744 2739 2745 2740 cleanup: 2746 2741 kfree(bundle); 2747 2747 - 2748 2748 - return; 2749 2742 } 2750 2743 2751 2744 static int dm_resume(void *handle) ··· 2957 2954 .set_powergating_state = dm_set_powergating_state, 2958 2955 }; 2959 2956 2960 2960 - const struct amdgpu_ip_block_version dm_ip_block = 2961 2961 - { 2957 2957 + const struct amdgpu_ip_block_version dm_ip_block = { 2962 2958 .type = AMD_IP_BLOCK_TYPE_DCE, 2963 2959 .major = 1, 2964 2960 .minor = 0, ··· 3002 3000 caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps; 3003 3001 caps->aux_support = false; 3004 3002 3005 3005 - if (caps->ext_caps->bits.oled == 1 /*|| 3006 3006 - caps->ext_caps->bits.sdr_aux_backlight_control == 1 || 3007 3007 - caps->ext_caps->bits.hdr_aux_backlight_control == 1*/) 3003 3003 + if (caps->ext_caps->bits.oled == 1 3004 3004 + /* 3005 3005 + * || 3006 3006 + * caps->ext_caps->bits.sdr_aux_backlight_control == 1 || 3007 3007 + * caps->ext_caps->bits.hdr_aux_backlight_control == 1 3008 3008 + */) 3008 3009 caps->aux_support = true; 3009 3010 3010 3011 if (amdgpu_backlight == 0) ··· 3241 3236 3242 3237 } 3243 3238 3244 3244 - static void dm_handle_mst_sideband_msg(struct amdgpu_dm_connector *aconnector) 3245 3245 - { 3246 3246 - u8 esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 }; 3247 3247 - u8 dret; 3248 3248 - bool new_irq_handled = false; 3249 3249 - int dpcd_addr; 3250 3250 - int dpcd_bytes_to_read; 3251 3251 - 3252 3252 - const int max_process_count = 30; 3253 3253 - int process_count = 0; 3254 3254 - 3255 3255 - const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link); 3256 3256 - 3257 3257 - if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) { 3258 3258 - dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT; 3259 3259 - /* DPCD 0x200 - 0x201 for downstream IRQ */ 3260 3260 - dpcd_addr = DP_SINK_COUNT; 3261 3261 - } else { 3262 3262 - dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI; 3263 3263 - /* DPCD 0x2002 - 0x2005 for downstream IRQ */ 3264 3264 - dpcd_addr = DP_SINK_COUNT_ESI; 3265 3265 - } 3266 3266 - 3267 3267 - dret = drm_dp_dpcd_read( 3268 3268 - &aconnector->dm_dp_aux.aux, 3269 3269 - dpcd_addr, 3270 3270 - esi, 3271 3271 - dpcd_bytes_to_read); 3272 3272 - 3273 3273 - while (dret == dpcd_bytes_to_read && 3274 3274 - process_count < max_process_count) { 3275 3275 - u8 ack[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = {}; 3276 3276 - u8 retry; 3277 3277 - dret = 0; 3278 3278 - 3279 3279 - process_count++; 3280 3280 - 3281 3281 - DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]); 3282 3282 - /* handle HPD short pulse irq */ 3283 3283 - if (aconnector->mst_mgr.mst_state) 3284 3284 - drm_dp_mst_hpd_irq_handle_event(&aconnector->mst_mgr, 3285 3285 - esi, 3286 3286 - ack, 3287 3287 - &new_irq_handled); 3288 3288 - 3289 3289 - if (new_irq_handled) { 3290 3290 - /* ACK at DPCD to notify down stream */ 3291 3291 - for (retry = 0; retry < 3; retry++) { 3292 3292 - ssize_t wret; 3293 3293 - 3294 3294 - wret = drm_dp_dpcd_writeb(&aconnector->dm_dp_aux.aux, 3295 3295 - dpcd_addr + 1, 3296 3296 - ack[1]); 3297 3297 - if (wret == 1) 3298 3298 - break; 3299 3299 - } 3300 3300 - 3301 3301 - if (retry == 3) { 3302 3302 - DRM_ERROR("Failed to ack MST event.\n"); 3303 3303 - return; 3304 3304 - } 3305 3305 - 3306 3306 - drm_dp_mst_hpd_irq_send_new_request(&aconnector->mst_mgr); 3307 3307 - /* check if there is new irq to be handled */ 3308 3308 - dret = drm_dp_dpcd_read( 3309 3309 - &aconnector->dm_dp_aux.aux, 3310 3310 - dpcd_addr, 3311 3311 - esi, 3312 3312 - dpcd_bytes_to_read); 3313 3313 - 3314 3314 - new_irq_handled = false; 3315 3315 - } else { 3316 3316 - break; 3317 3317 - } 3318 3318 - } 3319 3319 - 3320 3320 - if (process_count == max_process_count) 3321 3321 - DRM_DEBUG_DRIVER("Loop exceeded max iterations\n"); 3322 3322 - } 3323 3323 - 3324 3239 static void schedule_hpd_rx_offload_work(struct hpd_rx_irq_offload_work_queue *offload_wq, 3325 3240 union hpd_irq_data hpd_irq_data) 3326 3241 { ··· 3302 3377 if (dc_link_dp_allow_hpd_rx_irq(dc_link)) { 3303 3378 if (hpd_irq_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY || 3304 3379 hpd_irq_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) { 3305 3305 - dm_handle_mst_sideband_msg(aconnector); 3380 3380 + bool skip = false; 3381 3381 + 3382 3382 + /* 3383 3383 + * DOWN_REP_MSG_RDY is also handled by polling method 3384 3384 + * mgr->cbs->poll_hpd_irq() 3385 3385 + */ 3386 3386 + spin_lock(&offload_wq->offload_lock); 3387 3387 + skip = offload_wq->is_handling_mst_msg_rdy_event; 3388 3388 + 3389 3389 + if (!skip) 3390 3390 + offload_wq->is_handling_mst_msg_rdy_event = true; 3391 3391 + 3392 3392 + spin_unlock(&offload_wq->offload_lock); 3393 3393 + 3394 3394 + if (!skip) 3395 3395 + schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data); 3396 3396 + 3306 3397 goto out; 3307 3398 } 3308 3399 ··· 3409 3468 aconnector = to_amdgpu_dm_connector(connector); 3410 3469 dc_link = aconnector->dc_link; 3411 3470 3412 3412 - if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) { 3471 3471 + if (dc_link->irq_source_hpd != DC_IRQ_SOURCE_INVALID) { 3413 3472 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; 3414 3473 int_params.irq_source = dc_link->irq_source_hpd; 3415 3474 ··· 3418 3477 (void *) aconnector); 3419 3478 } 3420 3479 3421 3421 - if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) { 3480 3480 + if (dc_link->irq_source_hpd_rx != DC_IRQ_SOURCE_INVALID) { 3422 3481 3423 3482 /* Also register for DP short pulse (hpd_rx). */ 3424 3483 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; ··· 3427 3486 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3428 3487 handle_hpd_rx_irq, 3429 3488 (void *) aconnector); 3430 3430 - 3431 3431 - if (adev->dm.hpd_rx_offload_wq) 3432 3432 - adev->dm.hpd_rx_offload_wq[dc_link->link_index].aconnector = 3433 3433 - aconnector; 3434 3489 } 3490 3490 + 3491 3491 + if (adev->dm.hpd_rx_offload_wq) 3492 3492 + adev->dm.hpd_rx_offload_wq[connector->index].aconnector = 3493 3493 + aconnector; 3435 3494 } 3436 3495 } 3437 3496 ··· 3444 3503 struct dc_interrupt_params int_params = {0}; 3445 3504 int r; 3446 3505 int i; 3447 3447 - unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY; 3506 3506 + unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY; 3448 3507 3449 3508 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 3450 3509 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; ··· 3458 3517 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts 3459 3518 * coming from DC hardware. 3460 3519 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC 3461 3461 - * for acknowledging and handling. */ 3520 3520 + * for acknowledging and handling. 3521 3521 + */ 3462 3522 3463 3523 /* Use VBLANK interrupt */ 3464 3524 for (i = 0; i < adev->mode_info.num_crtc; i++) { 3465 3465 - r = amdgpu_irq_add_id(adev, client_id, i+1 , &adev->crtc_irq); 3525 3525 + r = amdgpu_irq_add_id(adev, client_id, i + 1, &adev->crtc_irq); 3466 3526 if (r) { 3467 3527 DRM_ERROR("Failed to add crtc irq id!\n"); 3468 3528 return r; ··· 3471 3529 3472 3530 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3473 3531 int_params.irq_source = 3474 3474 - dc_interrupt_to_irq_source(dc, i+1 , 0); 3532 3532 + dc_interrupt_to_irq_source(dc, i + 1, 0); 3475 3533 3476 3534 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; 3477 3535 ··· 3527 3585 struct dc_interrupt_params int_params = {0}; 3528 3586 int r; 3529 3587 int i; 3530 3530 - unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY; 3588 3588 + unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY; 3531 3589 3532 3590 if (adev->family >= AMDGPU_FAMILY_AI) 3533 3591 client_id = SOC15_IH_CLIENTID_DCE; ··· 3544 3602 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts 3545 3603 * coming from DC hardware. 3546 3604 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC 3547 3547 - * for acknowledging and handling. */ 3605 3605 + * for acknowledging and handling. 3606 3606 + */ 3548 3607 3549 3608 /* Use VBLANK interrupt */ 3550 3609 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) { ··· 3992 4049 } 3993 4050 3994 4051 static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps, 3995 3995 - unsigned *min, unsigned *max) 4052 4052 + unsigned int *min, unsigned int *max) 3996 4053 { 3997 4054 if (!caps) 3998 4055 return 0; ··· 4012 4069 static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps, 4013 4070 uint32_t brightness) 4014 4071 { 4015 4015 - unsigned min, max; 4072 4072 + unsigned int min, max; 4016 4073 4017 4074 if (!get_brightness_range(caps, &min, &max)) 4018 4075 return brightness; ··· 4025 4082 static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps, 4026 4083 uint32_t brightness) 4027 4084 { 4028 4028 - unsigned min, max; 4085 4085 + unsigned int min, max; 4029 4086 4030 4087 if (!get_brightness_range(caps, &min, &max)) 4031 4088 return brightness; ··· 4505 4562 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm) 4506 4563 { 4507 4564 drm_atomic_private_obj_fini(&dm->atomic_obj); 4508 4508 - return; 4509 4565 } 4510 4566 4511 4567 /****************************************************************************** ··· 5336 5394 { 5337 5395 enum dc_color_depth depth = timing_out->display_color_depth; 5338 5396 int normalized_clk; 5397 5397 + 5339 5398 do { 5340 5399 normalized_clk = timing_out->pix_clk_100hz / 10; 5341 5400 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */ ··· 5552 5609 { 5553 5610 struct dc_sink_init_data sink_init_data = { 0 }; 5554 5611 struct dc_sink *sink = NULL; 5612 5612 + 5555 5613 sink_init_data.link = aconnector->dc_link; 5556 5614 sink_init_data.sink_signal = aconnector->dc_link->connector_signal; 5557 5615 ··· 5676 5732 return &aconnector->freesync_vid_base; 5677 5733 5678 5734 /* Find the preferred mode */ 5679 5679 - list_for_each_entry (m, list_head, head) { 5735 5735 + list_for_each_entry(m, list_head, head) { 5680 5736 if (m->type & DRM_MODE_TYPE_PREFERRED) { 5681 5737 m_pref = m; 5682 5738 break; ··· 5700 5756 * For some monitors, preferred mode is not the mode with highest 5701 5757 * supported refresh rate. 5702 5758 */ 5703 5703 - list_for_each_entry (m, list_head, head) { 5759 5759 + list_for_each_entry(m, list_head, head) { 5704 5760 current_refresh = drm_mode_vrefresh(m); 5705 5761 5706 5762 if (m->hdisplay == m_pref->hdisplay && ··· 5972 6028 * This may not be an error, the use case is when we have no 5973 6029 * usermode calls to reset and set mode upon hotplug. In this 5974 6030 * case, we call set mode ourselves to restore the previous mode 5975 5975 - * and the modelist may not be filled in in time. 6031 6031 + * and the modelist may not be filled in time. 5976 6032 */ 5977 6033 DRM_DEBUG_DRIVER("No preferred mode found\n"); 5978 6034 } else { ··· 5995 6051 drm_mode_set_crtcinfo(&mode, 0); 5996 6052 5997 6053 /* 5998 5998 - * If scaling is enabled and refresh rate didn't change 5999 5999 - * we copy the vic and polarities of the old timings 6000 6000 - */ 6054 6054 + * If scaling is enabled and refresh rate didn't change 6055 6055 + * we copy the vic and polarities of the old timings 6056 6056 + */ 6001 6057 if (!scale || mode_refresh != preferred_refresh) 6002 6058 fill_stream_properties_from_drm_display_mode( 6003 6059 stream, &mode, &aconnector->base, con_state, NULL, ··· 6761 6817 6762 6818 if (!state->duplicated) { 6763 6819 int max_bpc = conn_state->max_requested_bpc; 6820 6820 + 6764 6821 is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) && 6765 6822 aconnector->force_yuv420_output; 6766 6823 color_depth = convert_color_depth_from_display_info(connector, ··· 7080 7135 { 7081 7136 struct drm_display_mode *m; 7082 7137 7083 7083 - list_for_each_entry (m, &aconnector->base.probed_modes, head) { 7138 7138 + list_for_each_entry(m, &aconnector->base.probed_modes, head) { 7084 7139 if (drm_mode_equal(m, mode)) 7085 7140 return true; 7086 7141 } ··· 7240 7295 aconnector->as_type = ADAPTIVE_SYNC_TYPE_NONE; 7241 7296 memset(&aconnector->vsdb_info, 0, sizeof(aconnector->vsdb_info)); 7242 7297 mutex_init(&aconnector->hpd_lock); 7298 7298 + mutex_init(&aconnector->handle_mst_msg_ready); 7243 7299 7244 7300 /* 7245 7301 * configure support HPD hot plug connector_>polled default value is 0 ··· 7400 7454 7401 7455 link->priv = aconnector; 7402 7456 7403 7403 - DRM_DEBUG_DRIVER("%s()\n", __func__); 7404 7457 7405 7458 i2c = create_i2c(link->ddc, link->link_index, &res); 7406 7459 if (!i2c) { ··· 8070 8125 * Only allow immediate flips for fast updates that don't 8071 8126 * change memory domain, FB pitch, DCC state, rotation or 8072 8127 * mirroring. 8128 8128 + * 8129 8129 + * dm_crtc_helper_atomic_check() only accepts async flips with 8130 8130 + * fast updates. 8073 8131 */ 8132 8132 + if (crtc->state->async_flip && 8133 8133 + acrtc_state->update_type != UPDATE_TYPE_FAST) 8134 8134 + drm_warn_once(state->dev, 8135 8135 + "[PLANE:%d:%s] async flip with non-fast update\n", 8136 8136 + plane->base.id, plane->name); 8074 8137 bundle->flip_addrs[planes_count].flip_immediate = 8075 8138 crtc->state->async_flip && 8076 8139 acrtc_state->update_type == UPDATE_TYPE_FAST && ··· 8121 8168 * DRI3/Present extension with defined target_msc. 8122 8169 */ 8123 8170 last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc); 8124 8124 - } 8125 8125 - else { 8171 8171 + } else { 8126 8172 /* For variable refresh rate mode only: 8127 8173 * Get vblank of last completed flip to avoid > 1 vrr 8128 8174 * flips per video frame by use of throttling, but allow ··· 8454 8502 dc_resource_state_copy_construct_current(dm->dc, dc_state); 8455 8503 } 8456 8504 8457 8457 - for_each_oldnew_crtc_in_state (state, crtc, old_crtc_state, 8458 8458 - new_crtc_state, i) { 8505 8505 + for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, 8506 8506 + new_crtc_state, i) { 8459 8507 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 8460 8508 8461 8509 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); ··· 8478 8526 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 8479 8527 8480 8528 drm_dbg_state(state->dev, 8481 8481 - "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, " 8482 8482 - "planes_changed:%d, mode_changed:%d,active_changed:%d," 8483 8483 - "connectors_changed:%d\n", 8529 8529 + "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n", 8484 8530 acrtc->crtc_id, 8485 8531 new_crtc_state->enable, 8486 8532 new_crtc_state->active, ··· 9054 9104 &commit->flip_done, 10*HZ); 9055 9105 9056 9106 if (ret == 0) 9057 9057 - DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done " 9058 9058 - "timed out\n", crtc->base.id, crtc->name); 9107 9107 + DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done timed out\n", 9108 9108 + crtc->base.id, crtc->name); 9059 9109 9060 9110 drm_crtc_commit_put(commit); 9061 9111 } ··· 9140 9190 return false; 9141 9191 } 9142 9192 9143 9143 - static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state) { 9193 9193 + static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state) 9194 9194 + { 9144 9195 u64 num, den, res; 9145 9196 struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base; 9146 9197 ··· 9263 9312 goto skip_modeset; 9264 9313 9265 9314 drm_dbg_state(state->dev, 9266 9266 - "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, " 9267 9267 - "planes_changed:%d, mode_changed:%d,active_changed:%d," 9268 9268 - "connectors_changed:%d\n", 9315 9315 + "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n", 9269 9316 acrtc->crtc_id, 9270 9317 new_crtc_state->enable, 9271 9318 new_crtc_state->active, ··· 9292 9343 old_crtc_state)) { 9293 9344 new_crtc_state->mode_changed = false; 9294 9345 DRM_DEBUG_DRIVER( 9295 9295 - "Mode change not required for front porch change, " 9296 9296 - "setting mode_changed to %d", 9346 9346 + "Mode change not required for front porch change, setting mode_changed to %d", 9297 9347 new_crtc_state->mode_changed); 9298 9348 9299 9349 set_freesync_fixed_config(dm_new_crtc_state); ··· 9304 9356 struct drm_display_mode *high_mode; 9305 9357 9306 9358 high_mode = get_highest_refresh_rate_mode(aconnector, false); 9307 9307 - if (!drm_mode_equal(&new_crtc_state->mode, high_mode)) { 9359 9359 + if (!drm_mode_equal(&new_crtc_state->mode, high_mode)) 9308 9360 set_freesync_fixed_config(dm_new_crtc_state); 9309 9309 - } 9310 9361 } 9311 9362 9312 9363 ret = dm_atomic_get_state(state, &dm_state); ··· 9473 9526 */ 9474 9527 for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) { 9475 9528 struct amdgpu_framebuffer *old_afb, *new_afb; 9529 9529 + 9476 9530 if (other->type == DRM_PLANE_TYPE_CURSOR) 9477 9531 continue; 9478 9532 ··· 9572 9624 } 9573 9625 9574 9626 /* Core DRM takes care of checking FB modifiers, so we only need to 9575 9575 - * check tiling flags when the FB doesn't have a modifier. */ 9627 9627 + * check tiling flags when the FB doesn't have a modifier. 9628 9628 + */ 9576 9629 if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) { 9577 9630 if (adev->family < AMDGPU_FAMILY_AI) { 9578 9631 linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 && 9579 9579 - AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 && 9632 9632 + AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 && 9580 9633 AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0; 9581 9634 } else { 9582 9635 linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0; ··· 9799 9850 /* On DCE and DCN there is no dedicated hardware cursor plane. We get a 9800 9851 * cursor per pipe but it's going to inherit the scaling and 9801 9852 * positioning from the underlying pipe. Check the cursor plane's 9802 9802 - * blending properties match the underlying planes'. */ 9853 9853 + * blending properties match the underlying planes'. 9854 9854 + */ 9803 9855 9804 9856 new_cursor_state = drm_atomic_get_new_plane_state(state, cursor); 9805 9805 - if (!new_cursor_state || !new_cursor_state->fb) { 9857 9857 + if (!new_cursor_state || !new_cursor_state->fb) 9806 9858 return 0; 9807 9807 - } 9808 9859 9809 9860 dm_get_oriented_plane_size(new_cursor_state, &cursor_src_w, &cursor_src_h); 9810 9861 cursor_scale_w = new_cursor_state->crtc_w * 1000 / cursor_src_w; ··· 9849 9900 struct drm_connector_state *conn_state, *old_conn_state; 9850 9901 struct amdgpu_dm_connector *aconnector = NULL; 9851 9902 int i; 9903 9903 + 9852 9904 for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) { 9853 9905 if (!conn_state->crtc) 9854 9906 conn_state = old_conn_state; ··· 10284 10334 } 10285 10335 10286 10336 /* Store the overall update type for use later in atomic check. */ 10287 10287 - for_each_new_crtc_in_state (state, crtc, new_crtc_state, i) { 10337 10337 + for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 10288 10338 struct dm_crtc_state *dm_new_crtc_state = 10289 10339 to_dm_crtc_state(new_crtc_state); 10290 10340 ··· 10306 10356 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS) 10307 10357 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n"); 10308 10358 else 10309 10309 - DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret); 10359 10359 + DRM_DEBUG_DRIVER("Atomic check failed with err: %d\n", ret); 10310 10360 10311 10361 trace_amdgpu_dm_atomic_check_finish(state, ret); 10312 10362

+7

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h

reviewed

··· 195 195 */ 196 196 bool is_handling_link_loss; 197 197 /** 198 198 + * @is_handling_mst_msg_rdy_event: Used to prevent inserting mst message 199 199 + * ready event when we're already handling mst message ready event 200 200 + */ 201 201 + bool is_handling_mst_msg_rdy_event; 202 202 + /** 198 203 * @aconnector: The aconnector that this work queue is attached to 199 204 */ 200 205 struct amdgpu_dm_connector *aconnector; ··· 643 638 struct drm_dp_mst_port *mst_output_port; 644 639 struct amdgpu_dm_connector *mst_root; 645 640 struct drm_dp_aux *dsc_aux; 641 641 + struct mutex handle_mst_msg_ready; 642 642 + 646 643 /* TODO see if we can merge with ddc_bus or make a dm_connector */ 647 644 struct amdgpu_i2c_adapter *i2c; 648 645

+12

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

reviewed

··· 398 398 return -EINVAL; 399 399 } 400 400 401 401 + /* 402 402 + * Only allow async flips for fast updates that don't change the FB 403 403 + * pitch, the DCC state, rotation, etc. 404 404 + */ 405 405 + if (crtc_state->async_flip && 406 406 + dm_crtc_state->update_type != UPDATE_TYPE_FAST) { 407 407 + drm_dbg_atomic(crtc->dev, 408 408 + "[CRTC:%d:%s] async flips are only supported for fast updates\n", 409 409 + crtc->base.id, crtc->name); 410 410 + return -EINVAL; 411 411 + } 412 412 + 401 413 /* In some use cases, like reset, no stream is attached */ 402 414 if (!dm_crtc_state->stream) 403 415 return 0;

+110

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

reviewed

··· 619 619 return connector; 620 620 } 621 621 622 622 + void dm_handle_mst_sideband_msg_ready_event( 623 623 + struct drm_dp_mst_topology_mgr *mgr, 624 624 + enum mst_msg_ready_type msg_rdy_type) 625 625 + { 626 626 + uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 }; 627 627 + uint8_t dret; 628 628 + bool new_irq_handled = false; 629 629 + int dpcd_addr; 630 630 + uint8_t dpcd_bytes_to_read; 631 631 + const uint8_t max_process_count = 30; 632 632 + uint8_t process_count = 0; 633 633 + u8 retry; 634 634 + struct amdgpu_dm_connector *aconnector = 635 635 + container_of(mgr, struct amdgpu_dm_connector, mst_mgr); 636 636 + 637 637 + 638 638 + const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link); 639 639 + 640 640 + if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) { 641 641 + dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT; 642 642 + /* DPCD 0x200 - 0x201 for downstream IRQ */ 643 643 + dpcd_addr = DP_SINK_COUNT; 644 644 + } else { 645 645 + dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI; 646 646 + /* DPCD 0x2002 - 0x2005 for downstream IRQ */ 647 647 + dpcd_addr = DP_SINK_COUNT_ESI; 648 648 + } 649 649 + 650 650 + mutex_lock(&aconnector->handle_mst_msg_ready); 651 651 + 652 652 + while (process_count < max_process_count) { 653 653 + u8 ack[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = {}; 654 654 + 655 655 + process_count++; 656 656 + 657 657 + dret = drm_dp_dpcd_read( 658 658 + &aconnector->dm_dp_aux.aux, 659 659 + dpcd_addr, 660 660 + esi, 661 661 + dpcd_bytes_to_read); 662 662 + 663 663 + if (dret != dpcd_bytes_to_read) { 664 664 + DRM_DEBUG_KMS("DPCD read and acked number is not as expected!"); 665 665 + break; 666 666 + } 667 667 + 668 668 + DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]); 669 669 + 670 670 + switch (msg_rdy_type) { 671 671 + case DOWN_REP_MSG_RDY_EVENT: 672 672 + /* Only handle DOWN_REP_MSG_RDY case*/ 673 673 + esi[1] &= DP_DOWN_REP_MSG_RDY; 674 674 + break; 675 675 + case UP_REQ_MSG_RDY_EVENT: 676 676 + /* Only handle UP_REQ_MSG_RDY case*/ 677 677 + esi[1] &= DP_UP_REQ_MSG_RDY; 678 678 + break; 679 679 + default: 680 680 + /* Handle both cases*/ 681 681 + esi[1] &= (DP_DOWN_REP_MSG_RDY | DP_UP_REQ_MSG_RDY); 682 682 + break; 683 683 + } 684 684 + 685 685 + if (!esi[1]) 686 686 + break; 687 687 + 688 688 + /* handle MST irq */ 689 689 + if (aconnector->mst_mgr.mst_state) 690 690 + drm_dp_mst_hpd_irq_handle_event(&aconnector->mst_mgr, 691 691 + esi, 692 692 + ack, 693 693 + &new_irq_handled); 694 694 + 695 695 + if (new_irq_handled) { 696 696 + /* ACK at DPCD to notify down stream */ 697 697 + for (retry = 0; retry < 3; retry++) { 698 698 + ssize_t wret; 699 699 + 700 700 + wret = drm_dp_dpcd_writeb(&aconnector->dm_dp_aux.aux, 701 701 + dpcd_addr + 1, 702 702 + ack[1]); 703 703 + if (wret == 1) 704 704 + break; 705 705 + } 706 706 + 707 707 + if (retry == 3) { 708 708 + DRM_ERROR("Failed to ack MST event.\n"); 709 709 + return; 710 710 + } 711 711 + 712 712 + drm_dp_mst_hpd_irq_send_new_request(&aconnector->mst_mgr); 713 713 + 714 714 + new_irq_handled = false; 715 715 + } else { 716 716 + break; 717 717 + } 718 718 + } 719 719 + 720 720 + mutex_unlock(&aconnector->handle_mst_msg_ready); 721 721 + 722 722 + if (process_count == max_process_count) 723 723 + DRM_DEBUG_DRIVER("Loop exceeded max iterations\n"); 724 724 + } 725 725 + 726 726 + static void dm_handle_mst_down_rep_msg_ready(struct drm_dp_mst_topology_mgr *mgr) 727 727 + { 728 728 + dm_handle_mst_sideband_msg_ready_event(mgr, DOWN_REP_MSG_RDY_EVENT); 729 729 + } 730 730 + 622 731 static const struct drm_dp_mst_topology_cbs dm_mst_cbs = { 623 732 .add_connector = dm_dp_add_mst_connector, 733 733 + .poll_hpd_irq = dm_handle_mst_down_rep_msg_ready, 624 734 }; 625 735 626 736 void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,

+11

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h

reviewed

··· 49 49 #define PBN_FEC_OVERHEAD_MULTIPLIER_8B_10B 1031 50 50 #define PBN_FEC_OVERHEAD_MULTIPLIER_128B_132B 1000 51 51 52 52 + enum mst_msg_ready_type { 53 53 + NONE_MSG_RDY_EVENT = 0, 54 54 + DOWN_REP_MSG_RDY_EVENT = 1, 55 55 + UP_REQ_MSG_RDY_EVENT = 2, 56 56 + DOWN_OR_UP_MSG_RDY_EVENT = 3 57 57 + }; 58 58 + 52 59 struct amdgpu_display_manager; 53 60 struct amdgpu_dm_connector; 54 61 ··· 67 60 68 61 void 69 62 dm_dp_create_fake_mst_encoders(struct amdgpu_device *adev); 63 63 + 64 64 + void dm_handle_mst_sideband_msg_ready_event( 65 65 + struct drm_dp_mst_topology_mgr *mgr, 66 66 + enum mst_msg_ready_type msg_rdy_type); 70 67 71 68 struct dsc_mst_fairness_vars { 72 69 int pbn;

+5

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

reviewed

··· 87 87 stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK || 88 88 stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) 89 89 tmds_present = true; 90 90 + 91 91 + /* Checking stream / link detection ensuring that PHY is active*/ 92 92 + if (dc_is_dp_signal(stream->signal) && !stream->dpms_off) 93 93 + display_count++; 94 94 + 90 95 } 91 96 92 97 for (i = 0; i < dc->link_count; i++) {

+2 -1

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

reviewed

··· 3278 3278 if (pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst]) { 3279 3279 struct hubp *hubp = get_hubp_by_inst(res_pool, mpcc_inst); 3280 3280 3281 3281 - if (pipe_ctx->stream_res.tg->funcs->is_tg_enabled(pipe_ctx->stream_res.tg)) 3281 3281 + if (pipe_ctx->stream_res.tg && 3282 3282 + pipe_ctx->stream_res.tg->funcs->is_tg_enabled(pipe_ctx->stream_res.tg)) 3282 3283 res_pool->mpc->funcs->wait_for_idle(res_pool->mpc, mpcc_inst); 3283 3284 pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst] = false; 3284 3285 hubp->funcs->set_blank(hubp, true);

+2 -2

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c

reviewed

··· 215 215 optc1->opp_count = 1; 216 216 } 217 217 218 218 - static void optc3_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, 218 218 + void optc3_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, 219 219 struct dc_crtc_timing *timing) 220 220 { 221 221 struct optc *optc1 = DCN10TG_FROM_TG(optc); ··· 293 293 OTG_DRR_TIMING_DBUF_UPDATE_MODE, mode); 294 294 } 295 295 296 296 - static void optc3_wait_drr_doublebuffer_pending_clear(struct timing_generator *optc) 296 296 + void optc3_wait_drr_doublebuffer_pending_clear(struct timing_generator *optc) 297 297 { 298 298 struct optc *optc1 = DCN10TG_FROM_TG(optc); 299 299

+3

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h

reviewed

··· 351 351 352 352 void optc3_set_odm_bypass(struct timing_generator *optc, 353 353 const struct dc_crtc_timing *dc_crtc_timing); 354 354 + void optc3_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, 355 355 + struct dc_crtc_timing *timing); 356 356 + void optc3_wait_drr_doublebuffer_pending_clear(struct timing_generator *optc); 354 357 void optc3_tg_init(struct timing_generator *optc); 355 358 void optc3_set_vtotal_min_max(struct timing_generator *optc, int vtotal_min, int vtotal_max); 356 359 #endif /* __DC_OPTC_DCN30_H__ */

+2 -1

drivers/gpu/drm/amd/display/dc/dcn301/Makefile

reviewed

··· 11 11 # Makefile for dcn30. 12 12 13 13 DCN301 = dcn301_init.o dcn301_resource.o dcn301_dccg.o \ 14 14 - dcn301_dio_link_encoder.o dcn301_hwseq.o dcn301_panel_cntl.o dcn301_hubbub.o 14 14 + dcn301_dio_link_encoder.o dcn301_hwseq.o dcn301_panel_cntl.o dcn301_hubbub.o \ 15 15 + dcn301_optc.o 15 16 16 17 AMD_DAL_DCN301 = $(addprefix $(AMDDALPATH)/dc/dcn301/,$(DCN301)) 17 18

+185

drivers/gpu/drm/amd/display/dc/dcn301/dcn301_optc.c

reviewed

··· 1 1 + /* 2 2 + * Copyright 2020 Advanced Micro Devices, Inc. 3 3 + * 4 4 + * Permission is hereby granted, free of charge, to any person obtaining a 5 5 + * copy of this software and associated documentation files (the "Software"), 6 6 + * to deal in the Software without restriction, including without limitation 7 7 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 8 + * and/or sell copies of the Software, and to permit persons to whom the 9 9 + * Software is furnished to do so, subject to the following conditions: 10 10 + * 11 11 + * The above copyright notice and this permission notice shall be included in 12 12 + * all copies or substantial portions of the Software. 13 13 + * 14 14 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 15 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 16 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 17 + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 18 + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 19 + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 20 + * OTHER DEALINGS IN THE SOFTWARE. 21 21 + * 22 22 + * Authors: AMD 23 23 + * 24 24 + */ 25 25 + 26 26 + #include "reg_helper.h" 27 27 + #include "dcn301_optc.h" 28 28 + #include "dc.h" 29 29 + #include "dcn_calc_math.h" 30 30 + #include "dc_dmub_srv.h" 31 31 + 32 32 + #include "dml/dcn30/dcn30_fpu.h" 33 33 + #include "dc_trace.h" 34 34 + 35 35 + #define REG(reg)\ 36 36 + optc1->tg_regs->reg 37 37 + 38 38 + #define CTX \ 39 39 + optc1->base.ctx 40 40 + 41 41 + #undef FN 42 42 + #define FN(reg_name, field_name) \ 43 43 + optc1->tg_shift->field_name, optc1->tg_mask->field_name 44 44 + 45 45 + 46 46 + /** 47 47 + * optc301_set_drr() - Program dynamic refresh rate registers m_OTGx_OTG_V_TOTAL_*. 48 48 + * 49 49 + * @optc: timing_generator instance. 50 50 + * @params: parameters used for Dynamic Refresh Rate. 51 51 + */ 52 52 + void optc301_set_drr( 53 53 + struct timing_generator *optc, 54 54 + const struct drr_params *params) 55 55 + { 56 56 + struct optc *optc1 = DCN10TG_FROM_TG(optc); 57 57 + 58 58 + if (params != NULL && 59 59 + params->vertical_total_max > 0 && 60 60 + params->vertical_total_min > 0) { 61 61 + 62 62 + if (params->vertical_total_mid != 0) { 63 63 + 64 64 + REG_SET(OTG_V_TOTAL_MID, 0, 65 65 + OTG_V_TOTAL_MID, params->vertical_total_mid - 1); 66 66 + 67 67 + REG_UPDATE_2(OTG_V_TOTAL_CONTROL, 68 68 + OTG_VTOTAL_MID_REPLACING_MAX_EN, 1, 69 69 + OTG_VTOTAL_MID_FRAME_NUM, 70 70 + (uint8_t)params->vertical_total_mid_frame_num); 71 71 + 72 72 + } 73 73 + 74 74 + optc->funcs->set_vtotal_min_max(optc, params->vertical_total_min - 1, params->vertical_total_max - 1); 75 75 + 76 76 + REG_UPDATE_5(OTG_V_TOTAL_CONTROL, 77 77 + OTG_V_TOTAL_MIN_SEL, 1, 78 78 + OTG_V_TOTAL_MAX_SEL, 1, 79 79 + OTG_FORCE_LOCK_ON_EVENT, 0, 80 80 + OTG_SET_V_TOTAL_MIN_MASK_EN, 0, 81 81 + OTG_SET_V_TOTAL_MIN_MASK, 0); 82 82 + // Setup manual flow control for EOF via TRIG_A 83 83 + optc->funcs->setup_manual_trigger(optc); 84 84 + 85 85 + } else { 86 86 + REG_UPDATE_4(OTG_V_TOTAL_CONTROL, 87 87 + OTG_SET_V_TOTAL_MIN_MASK, 0, 88 88 + OTG_V_TOTAL_MIN_SEL, 0, 89 89 + OTG_V_TOTAL_MAX_SEL, 0, 90 90 + OTG_FORCE_LOCK_ON_EVENT, 0); 91 91 + 92 92 + optc->funcs->set_vtotal_min_max(optc, 0, 0); 93 93 + } 94 94 + } 95 95 + 96 96 + 97 97 + void optc301_setup_manual_trigger(struct timing_generator *optc) 98 98 + { 99 99 + struct optc *optc1 = DCN10TG_FROM_TG(optc); 100 100 + 101 101 + REG_SET_8(OTG_TRIGA_CNTL, 0, 102 102 + OTG_TRIGA_SOURCE_SELECT, 21, 103 103 + OTG_TRIGA_SOURCE_PIPE_SELECT, optc->inst, 104 104 + OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1, 105 105 + OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 0, 106 106 + OTG_TRIGA_POLARITY_SELECT, 0, 107 107 + OTG_TRIGA_FREQUENCY_SELECT, 0, 108 108 + OTG_TRIGA_DELAY, 0, 109 109 + OTG_TRIGA_CLEAR, 1); 110 110 + } 111 111 + 112 112 + static struct timing_generator_funcs dcn30_tg_funcs = { 113 113 + .validate_timing = optc1_validate_timing, 114 114 + .program_timing = optc1_program_timing, 115 115 + .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0, 116 116 + .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1, 117 117 + .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2, 118 118 + .program_global_sync = optc1_program_global_sync, 119 119 + .enable_crtc = optc2_enable_crtc, 120 120 + .disable_crtc = optc1_disable_crtc, 121 121 + /* used by enable_timing_synchronization. Not need for FPGA */ 122 122 + .is_counter_moving = optc1_is_counter_moving, 123 123 + .get_position = optc1_get_position, 124 124 + .get_frame_count = optc1_get_vblank_counter, 125 125 + .get_scanoutpos = optc1_get_crtc_scanoutpos, 126 126 + .get_otg_active_size = optc1_get_otg_active_size, 127 127 + .set_early_control = optc1_set_early_control, 128 128 + /* used by enable_timing_synchronization. Not need for FPGA */ 129 129 + .wait_for_state = optc1_wait_for_state, 130 130 + .set_blank_color = optc3_program_blank_color, 131 131 + .did_triggered_reset_occur = optc1_did_triggered_reset_occur, 132 132 + .triplebuffer_lock = optc3_triplebuffer_lock, 133 133 + .triplebuffer_unlock = optc2_triplebuffer_unlock, 134 134 + .enable_reset_trigger = optc1_enable_reset_trigger, 135 135 + .enable_crtc_reset = optc1_enable_crtc_reset, 136 136 + .disable_reset_trigger = optc1_disable_reset_trigger, 137 137 + .lock = optc3_lock, 138 138 + .unlock = optc1_unlock, 139 139 + .lock_doublebuffer_enable = optc3_lock_doublebuffer_enable, 140 140 + .lock_doublebuffer_disable = optc3_lock_doublebuffer_disable, 141 141 + .enable_optc_clock = optc1_enable_optc_clock, 142 142 + .set_drr = optc301_set_drr, 143 143 + .get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal, 144 144 + .set_vtotal_min_max = optc3_set_vtotal_min_max, 145 145 + .set_static_screen_control = optc1_set_static_screen_control, 146 146 + .program_stereo = optc1_program_stereo, 147 147 + .is_stereo_left_eye = optc1_is_stereo_left_eye, 148 148 + .tg_init = optc3_tg_init, 149 149 + .is_tg_enabled = optc1_is_tg_enabled, 150 150 + .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred, 151 151 + .clear_optc_underflow = optc1_clear_optc_underflow, 152 152 + .setup_global_swap_lock = NULL, 153 153 + .get_crc = optc1_get_crc, 154 154 + .configure_crc = optc2_configure_crc, 155 155 + .set_dsc_config = optc3_set_dsc_config, 156 156 + .get_dsc_status = optc2_get_dsc_status, 157 157 + .set_dwb_source = NULL, 158 158 + .set_odm_bypass = optc3_set_odm_bypass, 159 159 + .set_odm_combine = optc3_set_odm_combine, 160 160 + .get_optc_source = optc2_get_optc_source, 161 161 + .set_out_mux = optc3_set_out_mux, 162 162 + .set_drr_trigger_window = optc3_set_drr_trigger_window, 163 163 + .set_vtotal_change_limit = optc3_set_vtotal_change_limit, 164 164 + .set_gsl = optc2_set_gsl, 165 165 + .set_gsl_source_select = optc2_set_gsl_source_select, 166 166 + .set_vtg_params = optc1_set_vtg_params, 167 167 + .program_manual_trigger = optc2_program_manual_trigger, 168 168 + .setup_manual_trigger = optc301_setup_manual_trigger, 169 169 + .get_hw_timing = optc1_get_hw_timing, 170 170 + .wait_drr_doublebuffer_pending_clear = optc3_wait_drr_doublebuffer_pending_clear, 171 171 + }; 172 172 + 173 173 + void dcn301_timing_generator_init(struct optc *optc1) 174 174 + { 175 175 + optc1->base.funcs = &dcn30_tg_funcs; 176 176 + 177 177 + optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; 178 178 + optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; 179 179 + 180 180 + optc1->min_h_blank = 32; 181 181 + optc1->min_v_blank = 3; 182 182 + optc1->min_v_blank_interlace = 5; 183 183 + optc1->min_h_sync_width = 4; 184 184 + optc1->min_v_sync_width = 1; 185 185 + }

+36

drivers/gpu/drm/amd/display/dc/dcn301/dcn301_optc.h

reviewed

··· 1 1 + /* 2 2 + * Copyright 2020 Advanced Micro Devices, Inc. 3 3 + * 4 4 + * Permission is hereby granted, free of charge, to any person obtaining a 5 5 + * copy of this software and associated documentation files (the "Software"), 6 6 + * to deal in the Software without restriction, including without limitation 7 7 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 8 + * and/or sell copies of the Software, and to permit persons to whom the 9 9 + * Software is furnished to do so, subject to the following conditions: 10 10 + * 11 11 + * The above copyright notice and this permission notice shall be included in 12 12 + * all copies or substantial portions of the Software. 13 13 + * 14 14 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 15 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 16 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 17 + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 18 + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 19 + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 20 + * OTHER DEALINGS IN THE SOFTWARE. 21 21 + * 22 22 + * Authors: AMD 23 23 + * 24 24 + */ 25 25 + 26 26 + #ifndef __DC_OPTC_DCN301_H__ 27 27 + #define __DC_OPTC_DCN301_H__ 28 28 + 29 29 + #include "dcn20/dcn20_optc.h" 30 30 + #include "dcn30/dcn30_optc.h" 31 31 + 32 32 + void dcn301_timing_generator_init(struct optc *optc1); 33 33 + void optc301_setup_manual_trigger(struct timing_generator *optc); 34 34 + void optc301_set_drr(struct timing_generator *optc, const struct drr_params *params); 35 35 + 36 36 + #endif /* __DC_OPTC_DCN301_H__ */

+2 -2

drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c

reviewed

··· 42 42 #include "dcn30/dcn30_hubp.h" 43 43 #include "irq/dcn30/irq_service_dcn30.h" 44 44 #include "dcn30/dcn30_dpp.h" 45 45 - #include "dcn30/dcn30_optc.h" 45 45 + #include "dcn301/dcn301_optc.h" 46 46 #include "dcn20/dcn20_hwseq.h" 47 47 #include "dcn30/dcn30_hwseq.h" 48 48 #include "dce110/dce110_hw_sequencer.h" ··· 855 855 tgn10->tg_shift = &optc_shift; 856 856 tgn10->tg_mask = &optc_mask; 857 857 858 858 - dcn30_timing_generator_init(tgn10); 858 858 + dcn301_timing_generator_init(tgn10); 859 859 860 860 return &tgn10->base; 861 861 }

+1 -1

drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c

reviewed

··· 65 65 .timing_trace = false, 66 66 .clock_trace = true, 67 67 .disable_pplib_clock_request = true, 68 68 - .pipe_split_policy = MPC_SPLIT_DYNAMIC, 68 68 + .pipe_split_policy = MPC_SPLIT_AVOID, 69 69 .force_single_disp_pipe_split = false, 70 70 .disable_dcc = DCC_ENABLE, 71 71 .vsr_support = true,

+5 -1

drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

reviewed

··· 295 295 pipe = &res_ctx->pipe_ctx[i]; 296 296 timing = &pipe->stream->timing; 297 297 298 298 - pipes[pipe_cnt].pipe.dest.vtotal = pipe->stream->adjust.v_total_min; 298 298 + if (pipe->stream->adjust.v_total_min != 0) 299 299 + pipes[pipe_cnt].pipe.dest.vtotal = pipe->stream->adjust.v_total_min; 300 300 + else 301 301 + pipes[pipe_cnt].pipe.dest.vtotal = timing->v_total; 302 302 + 299 303 pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - pipes[pipe_cnt].pipe.dest.vactive; 300 304 pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, dcn3_14_ip.VBlankNomDefaultUS); 301 305 pipes[pipe_cnt].pipe.dest.vblank_nom = max(pipes[pipe_cnt].pipe.dest.vblank_nom, timing->v_sync_width);

+2 -12

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

reviewed

··· 1798 1798 return result; 1799 1799 } 1800 1800 1801 1801 - static bool intel_core_rkl_chk(void) 1802 1802 - { 1803 1803 - #if IS_ENABLED(CONFIG_X86_64) 1804 1804 - struct cpuinfo_x86 *c = &cpu_data(0); 1805 1805 - 1806 1806 - return (c->x86 == 6 && c->x86_model == INTEL_FAM6_ROCKETLAKE); 1807 1807 - #else 1808 1808 - return false; 1809 1809 - #endif 1810 1810 - } 1811 1811 - 1812 1801 static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr) 1813 1802 { 1814 1803 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); ··· 1824 1835 data->mclk_dpm_key_disabled = hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true; 1825 1836 data->sclk_dpm_key_disabled = hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true; 1826 1837 data->pcie_dpm_key_disabled = 1827 1827 - intel_core_rkl_chk() || !(hwmgr->feature_mask & PP_PCIE_DPM_MASK); 1838 1838 + !amdgpu_device_pcie_dynamic_switching_supported() || 1839 1839 + !(hwmgr->feature_mask & PP_PCIE_DPM_MASK); 1828 1840 /* need to set voltage control types before EVV patching */ 1829 1841 data->voltage_control = SMU7_VOLTAGE_CONTROL_NONE; 1830 1842 data->vddci_control = SMU7_VOLTAGE_CONTROL_NONE;

+6 -2

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

reviewed

··· 1927 1927 *size = 4; 1928 1928 break; 1929 1929 case AMDGPU_PP_SENSOR_GFX_MCLK: 1930 1930 - ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data); 1930 1930 + ret = sienna_cichlid_get_smu_metrics_data(smu, 1931 1931 + METRICS_CURR_UCLK, 1932 1932 + (uint32_t *)data); 1931 1933 *(uint32_t *)data *= 100; 1932 1934 *size = 4; 1933 1935 break; 1934 1936 case AMDGPU_PP_SENSOR_GFX_SCLK: 1935 1935 - ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data); 1937 1937 + ret = sienna_cichlid_get_smu_metrics_data(smu, 1938 1938 + METRICS_AVERAGE_GFXCLK, 1939 1939 + (uint32_t *)data); 1936 1940 *(uint32_t *)data *= 100; 1937 1941 *size = 4; 1938 1942 break;

+1 -1

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

reviewed

··· 949 949 break; 950 950 case AMDGPU_PP_SENSOR_GFX_MCLK: 951 951 ret = smu_v13_0_7_get_smu_metrics_data(smu, 952 952 - METRICS_AVERAGE_UCLK, 952 952 + METRICS_CURR_UCLK, 953 953 (uint32_t *)data); 954 954 *(uint32_t *)data *= 100; 955 955 *size = 4;

+10 -1

drivers/gpu/drm/drm_atomic.c

reviewed

··· 140 140 if (!state->planes) 141 141 goto fail; 142 142 143 143 + /* 144 144 + * Because drm_atomic_state can be committed asynchronously we need our 145 145 + * own reference and cannot rely on the on implied by drm_file in the 146 146 + * ioctl call. 147 147 + */ 148 148 + drm_dev_get(dev); 143 149 state->dev = dev; 144 150 145 151 drm_dbg_atomic(dev, "Allocated atomic state %p\n", state); ··· 305 299 void __drm_atomic_state_free(struct kref *ref) 306 300 { 307 301 struct drm_atomic_state *state = container_of(ref, typeof(*state), ref); 308 308 - struct drm_mode_config *config = &state->dev->mode_config; 302 302 + struct drm_device *dev = state->dev; 303 303 + struct drm_mode_config *config = &dev->mode_config; 309 304 310 305 drm_atomic_state_clear(state); 311 306 ··· 318 311 drm_atomic_state_default_release(state); 319 312 kfree(state); 320 313 } 314 314 + 315 315 + drm_dev_put(dev); 321 316 } 322 317 EXPORT_SYMBOL(__drm_atomic_state_free); 323 318

+6

drivers/gpu/drm/drm_client_modeset.c

reviewed

··· 311 311 can_clone = true; 312 312 dmt_mode = drm_mode_find_dmt(dev, 1024, 768, 60, false); 313 313 314 314 + if (!dmt_mode) 315 315 + goto fail; 316 316 + 314 317 for (i = 0; i < connector_count; i++) { 315 318 if (!enabled[i]) 316 319 continue; ··· 329 326 if (!modes[i]) 330 327 can_clone = false; 331 328 } 329 329 + kfree(dmt_mode); 332 330 333 331 if (can_clone) { 334 332 DRM_DEBUG_KMS("can clone using 1024x768\n"); 335 333 return true; 336 334 } 335 335 + fail: 337 336 DRM_INFO("kms: can't enable cloning when we probably wanted to.\n"); 338 337 return false; 339 338 } ··· 867 862 break; 868 863 } 869 864 865 865 + kfree(modeset->mode); 870 866 modeset->mode = drm_mode_duplicate(dev, mode); 871 867 drm_connector_get(connector); 872 868 modeset->connectors[modeset->num_connectors++] = connector;

+5

drivers/gpu/drm/i915/Makefile

reviewed

··· 23 23 subdir-ccflags-y += $(call cc-disable-warning, frame-address) 24 24 subdir-ccflags-$(CONFIG_DRM_I915_WERROR) += -Werror 25 25 26 26 + # Fine grained warnings disable 27 27 + CFLAGS_i915_pci.o = $(call cc-disable-warning, override-init) 28 28 + CFLAGS_display/intel_display_device.o = $(call cc-disable-warning, override-init) 29 29 + CFLAGS_display/intel_fbdev.o = $(call cc-disable-warning, override-init) 30 30 + 26 31 subdir-ccflags-y += -I$(srctree)/$(src) 27 32 28 33 # Please keep these build lists sorted!

-5

drivers/gpu/drm/i915/display/intel_display_device.c

reviewed

··· 16 16 #include "intel_display_reg_defs.h" 17 17 #include "intel_fbc.h" 18 18 19 19 - __diag_push(); 20 20 - __diag_ignore_all("-Woverride-init", "Allow overriding inherited members"); 21 21 - 22 19 static const struct intel_display_device_info no_display = {}; 23 20 24 21 #define PIPE_A_OFFSET 0x70000 ··· 661 664 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 662 665 BIT(TRANSCODER_C) | BIT(TRANSCODER_D), 663 666 }; 664 664 - 665 665 - __diag_pop(); 666 667 667 668 #undef INTEL_VGA_DEVICE 668 669 #undef INTEL_QUANTA_VGA_DEVICE

-5

drivers/gpu/drm/i915/display/intel_fbdev.c

reviewed

··· 135 135 return i915_gem_fb_mmap(obj, vma); 136 136 } 137 137 138 138 - __diag_push(); 139 139 - __diag_ignore_all("-Woverride-init", "Allow overriding the default ops"); 140 140 - 141 138 static const struct fb_ops intelfb_ops = { 142 139 .owner = THIS_MODULE, 143 140 __FB_DEFAULT_DEFERRED_OPS_RDWR(intel_fbdev), ··· 145 148 __FB_DEFAULT_DEFERRED_OPS_DRAW(intel_fbdev), 146 149 .fb_mmap = intel_fbdev_mmap, 147 150 }; 148 148 - 149 149 - __diag_pop(); 150 151 151 152 static int intelfb_alloc(struct drm_fb_helper *helper, 152 153 struct drm_fb_helper_surface_size *sizes)

-5

drivers/gpu/drm/i915/i915_pci.c

reviewed

··· 38 38 #include "i915_reg.h" 39 39 #include "intel_pci_config.h" 40 40 41 41 - __diag_push(); 42 42 - __diag_ignore_all("-Woverride-init", "Allow overriding inherited members"); 43 43 - 44 41 #define PLATFORM(x) .platform = (x) 45 42 #define GEN(x) \ 46 43 .__runtime.graphics.ip.ver = (x), \ ··· 842 845 }; 843 846 844 847 #undef PLATFORM 845 845 - 846 846 - __diag_pop(); 847 848 848 849 /* 849 850 * Make sure any device matches here are from most specific to most

+1

drivers/gpu/drm/i915/i915_perf.c

reviewed

··· 4431 4431 static const struct i915_range xehp_oa_b_counters[] = { 4432 4432 { .start = 0xdc48, .end = 0xdc48 }, /* OAA_ENABLE_REG */ 4433 4433 { .start = 0xdd00, .end = 0xdd48 }, /* OAG_LCE0_0 - OAA_LENABLE_REG */ 4434 4434 + {} 4434 4435 }; 4435 4436 4436 4437 static const struct i915_range gen7_oa_mux_regs[] = {

+4

drivers/gpu/drm/nouveau/dispnv50/disp.c

reviewed

··· 1877 1877 nvif_outp_dtor(&nv_encoder->outp); 1878 1878 1879 1879 drm_encoder_cleanup(encoder); 1880 1880 + 1881 1881 + mutex_destroy(&nv_encoder->dp.hpd_irq_lock); 1880 1882 kfree(encoder); 1881 1883 } 1882 1884 ··· 1922 1920 nv_encoder->dcb = dcbe; 1923 1921 nv_encoder->i2c = ddc; 1924 1922 nv_encoder->aux = aux; 1923 1923 + 1924 1924 + mutex_init(&nv_encoder->dp.hpd_irq_lock); 1925 1925 1926 1926 encoder = to_drm_encoder(nv_encoder); 1927 1927 encoder->possible_crtcs = dcbe->heads;

+2 -2

drivers/gpu/drm/nouveau/include/nvkm/subdev/i2c.h

reviewed

··· 16 16 const struct nvkm_i2c_bus_func *func; 17 17 struct nvkm_i2c_pad *pad; 18 18 #define NVKM_I2C_BUS_CCB(n) /* 'n' is ccb index */ (n) 19 19 - #define NVKM_I2C_BUS_EXT(n) /* 'n' is dcb external encoder type */ ((n) + 0x100) 19 19 + #define NVKM_I2C_BUS_EXT(n) /* 'n' is dcb external encoder type */ ((n) + 0x10) 20 20 #define NVKM_I2C_BUS_PRI /* ccb primary comm. port */ -1 21 21 #define NVKM_I2C_BUS_SEC /* ccb secondary comm. port */ -2 22 22 int id; ··· 38 38 const struct nvkm_i2c_aux_func *func; 39 39 struct nvkm_i2c_pad *pad; 40 40 #define NVKM_I2C_AUX_CCB(n) /* 'n' is ccb index */ (n) 41 41 - #define NVKM_I2C_AUX_EXT(n) /* 'n' is dcb external encoder type */ ((n) + 0x100) 41 41 + #define NVKM_I2C_AUX_EXT(n) /* 'n' is dcb external encoder type */ ((n) + 0x10) 42 42 int id; 43 43 44 44 struct mutex mutex;

+18 -9

drivers/gpu/drm/nouveau/nvkm/engine/disp/uconn.c

reviewed

··· 81 81 return -ENOSYS; 82 82 83 83 list_for_each_entry(outp, &conn->disp->outps, head) { 84 84 - if (outp->info.connector == conn->index && outp->dp.aux) { 85 85 - if (args->v0.types & NVIF_CONN_EVENT_V0_PLUG ) bits |= NVKM_I2C_PLUG; 86 86 - if (args->v0.types & NVIF_CONN_EVENT_V0_UNPLUG) bits |= NVKM_I2C_UNPLUG; 87 87 - if (args->v0.types & NVIF_CONN_EVENT_V0_IRQ ) bits |= NVKM_I2C_IRQ; 84 84 + if (outp->info.connector == conn->index) 85 85 + break; 86 86 + } 88 87 89 89 - return nvkm_uevent_add(uevent, &device->i2c->event, outp->dp.aux->id, bits, 90 90 - nvkm_uconn_uevent_aux); 91 91 - } 88 88 + if (&outp->head == &conn->disp->outps) 89 89 + return -EINVAL; 90 90 + 91 91 + if (outp->dp.aux && !outp->info.location) { 92 92 + if (args->v0.types & NVIF_CONN_EVENT_V0_PLUG ) bits |= NVKM_I2C_PLUG; 93 93 + if (args->v0.types & NVIF_CONN_EVENT_V0_UNPLUG) bits |= NVKM_I2C_UNPLUG; 94 94 + if (args->v0.types & NVIF_CONN_EVENT_V0_IRQ ) bits |= NVKM_I2C_IRQ; 95 95 + 96 96 + return nvkm_uevent_add(uevent, &device->i2c->event, outp->dp.aux->id, bits, 97 97 + nvkm_uconn_uevent_aux); 92 98 } 93 99 94 100 if (args->v0.types & NVIF_CONN_EVENT_V0_PLUG ) bits |= NVKM_GPIO_HI; 95 101 if (args->v0.types & NVIF_CONN_EVENT_V0_UNPLUG) bits |= NVKM_GPIO_LO; 96 96 - if (args->v0.types & NVIF_CONN_EVENT_V0_IRQ) 97 97 - return -EINVAL; 102 102 + if (args->v0.types & NVIF_CONN_EVENT_V0_IRQ) { 103 103 + /* TODO: support DP IRQ on ANX9805 and remove this hack. */ 104 104 + if (!outp->info.location) 105 105 + return -EINVAL; 106 106 + } 98 107 99 108 return nvkm_uevent_add(uevent, &device->gpio->event, conn->info.hpd, bits, 100 109 nvkm_uconn_uevent_gpio);

+9 -2

drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.c

reviewed

··· 260 260 { 261 261 struct nvkm_bios *bios = device->bios; 262 262 struct nvkm_i2c *i2c; 263 263 + struct nvkm_i2c_aux *aux; 263 264 struct dcb_i2c_entry ccbE; 264 265 struct dcb_output dcbE; 265 266 u8 ver, hdr; 266 266 - int ret, i; 267 267 + int ret, i, ids; 267 268 268 269 if (!(i2c = *pi2c = kzalloc(sizeof(*i2c), GFP_KERNEL))) 269 270 return -ENOMEM; ··· 407 406 } 408 407 } 409 408 410 410 - return nvkm_event_init(&nvkm_i2c_intr_func, &i2c->subdev, 4, i, &i2c->event); 409 409 + ids = 0; 410 410 + list_for_each_entry(aux, &i2c->aux, head) 411 411 + ids = max(ids, aux->id + 1); 412 412 + if (!ids) 413 413 + return 0; 414 414 + 415 415 + return nvkm_event_init(&nvkm_i2c_intr_func, &i2c->subdev, 4, ids, &i2c->event); 411 416 }

+1 -171

drivers/idle/intel_idle.c

reviewed

··· 199 199 return __intel_idle(dev, drv, index); 200 200 } 201 201 202 202 - static __always_inline int __intel_idle_hlt(struct cpuidle_device *dev, 203 203 - struct cpuidle_driver *drv, int index) 204 204 - { 205 205 - raw_safe_halt(); 206 206 - raw_local_irq_disable(); 207 207 - return index; 208 208 - } 209 209 - 210 210 - /** 211 211 - * intel_idle_hlt - Ask the processor to enter the given idle state using hlt. 212 212 - * @dev: cpuidle device of the target CPU. 213 213 - * @drv: cpuidle driver (assumed to point to intel_idle_driver). 214 214 - * @index: Target idle state index. 215 215 - * 216 216 - * Use the HLT instruction to notify the processor that the CPU represented by 217 217 - * @dev is idle and it can try to enter the idle state corresponding to @index. 218 218 - * 219 219 - * Must be called under local_irq_disable(). 220 220 - */ 221 221 - static __cpuidle int intel_idle_hlt(struct cpuidle_device *dev, 222 222 - struct cpuidle_driver *drv, int index) 223 223 - { 224 224 - return __intel_idle_hlt(dev, drv, index); 225 225 - } 226 226 - 227 227 - static __cpuidle int intel_idle_hlt_irq_on(struct cpuidle_device *dev, 228 228 - struct cpuidle_driver *drv, int index) 229 229 - { 230 230 - int ret; 231 231 - 232 232 - raw_local_irq_enable(); 233 233 - ret = __intel_idle_hlt(dev, drv, index); 234 234 - raw_local_irq_disable(); 235 235 - 236 236 - return ret; 237 237 - } 238 238 - 239 202 /** 240 203 * intel_idle_s2idle - Ask the processor to enter the given idle state. 241 204 * @dev: cpuidle device of the target CPU. ··· 1242 1279 .enter = NULL } 1243 1280 }; 1244 1281 1245 1245 - static struct cpuidle_state vmguest_cstates[] __initdata = { 1246 1246 - { 1247 1247 - .name = "C1", 1248 1248 - .desc = "HLT", 1249 1249 - .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_IRQ_ENABLE, 1250 1250 - .exit_latency = 5, 1251 1251 - .target_residency = 10, 1252 1252 - .enter = &intel_idle_hlt, }, 1253 1253 - { 1254 1254 - .name = "C1L", 1255 1255 - .desc = "Long HLT", 1256 1256 - .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TLB_FLUSHED, 1257 1257 - .exit_latency = 5, 1258 1258 - .target_residency = 200, 1259 1259 - .enter = &intel_idle_hlt, }, 1260 1260 - { 1261 1261 - .enter = NULL } 1262 1262 - }; 1263 1263 - 1264 1282 static const struct idle_cpu idle_cpu_nehalem __initconst = { 1265 1283 .state_table = nehalem_cstates, 1266 1284 .auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE, ··· 1841 1897 1842 1898 static void state_update_enter_method(struct cpuidle_state *state, int cstate) 1843 1899 { 1844 1844 - if (state->enter == intel_idle_hlt) { 1845 1845 - if (force_irq_on) { 1846 1846 - pr_info("forced intel_idle_irq for state %d\n", cstate); 1847 1847 - state->enter = intel_idle_hlt_irq_on; 1848 1848 - } 1849 1849 - return; 1850 1850 - } 1851 1851 - if (state->enter == intel_idle_hlt_irq_on) 1852 1852 - return; /* no update scenarios */ 1853 1853 - 1854 1900 if (state->flags & CPUIDLE_FLAG_INIT_XSTATE) { 1855 1901 /* 1856 1902 * Combining with XSTATE with IBRS or IRQ_ENABLE flags ··· 1872 1938 pr_info("forced intel_idle_irq for state %d\n", cstate); 1873 1939 state->enter = intel_idle_irq; 1874 1940 } 1875 1875 - } 1876 1876 - 1877 1877 - /* 1878 1878 - * For mwait based states, we want to verify the cpuid data to see if the state 1879 1879 - * is actually supported by this specific CPU. 1880 1880 - * For non-mwait based states, this check should be skipped. 1881 1881 - */ 1882 1882 - static bool should_verify_mwait(struct cpuidle_state *state) 1883 1883 - { 1884 1884 - if (state->enter == intel_idle_hlt) 1885 1885 - return false; 1886 1886 - if (state->enter == intel_idle_hlt_irq_on) 1887 1887 - return false; 1888 1888 - 1889 1889 - return true; 1890 1941 } 1891 1942 1892 1943 static void __init intel_idle_init_cstates_icpu(struct cpuidle_driver *drv) ··· 1922 2003 } 1923 2004 1924 2005 mwait_hint = flg2MWAIT(cpuidle_state_table[cstate].flags); 1925 1925 - if (should_verify_mwait(&cpuidle_state_table[cstate]) && !intel_idle_verify_cstate(mwait_hint)) 2006 2006 + if (!intel_idle_verify_cstate(mwait_hint)) 1926 2007 continue; 1927 2008 1928 2009 /* Structure copy. */ ··· 2056 2137 cpuidle_unregister_device(per_cpu_ptr(intel_idle_cpuidle_devices, i)); 2057 2138 } 2058 2139 2059 2059 - /* 2060 2060 - * Match up the latency and break even point of the bare metal (cpu based) 2061 2061 - * states with the deepest VM available state. 2062 2062 - * 2063 2063 - * We only want to do this for the deepest state, the ones that has 2064 2064 - * the TLB_FLUSHED flag set on the . 2065 2065 - * 2066 2066 - * All our short idle states are dominated by vmexit/vmenter latencies, 2067 2067 - * not the underlying hardware latencies so we keep our values for these. 2068 2068 - */ 2069 2069 - static void __init matchup_vm_state_with_baremetal(void) 2070 2070 - { 2071 2071 - int cstate; 2072 2072 - 2073 2073 - for (cstate = 0; cstate < CPUIDLE_STATE_MAX; ++cstate) { 2074 2074 - int matching_cstate; 2075 2075 - 2076 2076 - if (intel_idle_max_cstate_reached(cstate)) 2077 2077 - break; 2078 2078 - 2079 2079 - if (!cpuidle_state_table[cstate].enter) 2080 2080 - break; 2081 2081 - 2082 2082 - if (!(cpuidle_state_table[cstate].flags & CPUIDLE_FLAG_TLB_FLUSHED)) 2083 2083 - continue; 2084 2084 - 2085 2085 - for (matching_cstate = 0; matching_cstate < CPUIDLE_STATE_MAX; ++matching_cstate) { 2086 2086 - if (!icpu->state_table[matching_cstate].enter) 2087 2087 - break; 2088 2088 - if (icpu->state_table[matching_cstate].exit_latency > cpuidle_state_table[cstate].exit_latency) { 2089 2089 - cpuidle_state_table[cstate].exit_latency = icpu->state_table[matching_cstate].exit_latency; 2090 2090 - cpuidle_state_table[cstate].target_residency = icpu->state_table[matching_cstate].target_residency; 2091 2091 - } 2092 2092 - } 2093 2093 - 2094 2094 - } 2095 2095 - } 2096 2096 - 2097 2097 - 2098 2098 - static int __init intel_idle_vminit(const struct x86_cpu_id *id) 2099 2099 - { 2100 2100 - int retval; 2101 2101 - 2102 2102 - cpuidle_state_table = vmguest_cstates; 2103 2103 - 2104 2104 - icpu = (const struct idle_cpu *)id->driver_data; 2105 2105 - 2106 2106 - pr_debug("v" INTEL_IDLE_VERSION " model 0x%X\n", 2107 2107 - boot_cpu_data.x86_model); 2108 2108 - 2109 2109 - intel_idle_cpuidle_devices = alloc_percpu(struct cpuidle_device); 2110 2110 - if (!intel_idle_cpuidle_devices) 2111 2111 - return -ENOMEM; 2112 2112 - 2113 2113 - /* 2114 2114 - * We don't know exactly what the host will do when we go idle, but as a worst estimate 2115 2115 - * we can assume that the exit latency of the deepest host state will be hit for our 2116 2116 - * deep (long duration) guest idle state. 2117 2117 - * The same logic applies to the break even point for the long duration guest idle state. 2118 2118 - * So lets copy these two properties from the table we found for the host CPU type. 2119 2119 - */ 2120 2120 - matchup_vm_state_with_baremetal(); 2121 2121 - 2122 2122 - intel_idle_cpuidle_driver_init(&intel_idle_driver); 2123 2123 - 2124 2124 - retval = cpuidle_register_driver(&intel_idle_driver); 2125 2125 - if (retval) { 2126 2126 - struct cpuidle_driver *drv = cpuidle_get_driver(); 2127 2127 - printk(KERN_DEBUG pr_fmt("intel_idle yielding to %s\n"), 2128 2128 - drv ? drv->name : "none"); 2129 2129 - goto init_driver_fail; 2130 2130 - } 2131 2131 - 2132 2132 - retval = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "idle/intel:online", 2133 2133 - intel_idle_cpu_online, NULL); 2134 2134 - if (retval < 0) 2135 2135 - goto hp_setup_fail; 2136 2136 - 2137 2137 - return 0; 2138 2138 - hp_setup_fail: 2139 2139 - intel_idle_cpuidle_devices_uninit(); 2140 2140 - cpuidle_unregister_driver(&intel_idle_driver); 2141 2141 - init_driver_fail: 2142 2142 - free_percpu(intel_idle_cpuidle_devices); 2143 2143 - return retval; 2144 2144 - } 2145 2145 - 2146 2140 static int __init intel_idle_init(void) 2147 2141 { 2148 2142 const struct x86_cpu_id *id; ··· 2074 2242 id = x86_match_cpu(intel_idle_ids); 2075 2243 if (id) { 2076 2244 if (!boot_cpu_has(X86_FEATURE_MWAIT)) { 2077 2077 - if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) 2078 2078 - return intel_idle_vminit(id); 2079 2245 pr_debug("Please enable MWAIT in BIOS SETUP\n"); 2080 2246 return -ENODEV; 2081 2247 }

+5 -2

drivers/media/cec/usb/pulse8/pulse8-cec.c

reviewed

··· 809 809 810 810 mutex_lock(&pulse8->lock); 811 811 cmd = MSGCODE_PING; 812 812 - pulse8_send_and_wait(pulse8, &cmd, 1, 813 813 - MSGCODE_COMMAND_ACCEPTED, 0); 812 812 + if (pulse8_send_and_wait(pulse8, &cmd, 1, 813 813 + MSGCODE_COMMAND_ACCEPTED, 0)) { 814 814 + dev_warn(pulse8->dev, "failed to ping EEPROM\n"); 815 815 + goto unlock; 816 816 + } 814 817 815 818 if (pulse8->vers < 2) 816 819 goto unlock;

+2 -2

drivers/media/i2c/tc358746.c

reviewed

··· 813 813 u32 min_delta = 0xffffffff; 814 814 u16 prediv_max = 17; 815 815 u16 prediv_min = 1; 816 816 - u16 m_best, mul; 817 817 - u16 p_best, p; 816 816 + u16 m_best = 0, mul; 817 817 + u16 p_best = 1, p; 818 818 u8 postdiv; 819 819 820 820 if (fout > 1000 * HZ_PER_MHZ) {

-12

drivers/media/pci/cx23885/cx23885-dvb.c

reviewed

··· 2459 2459 request_module("%s", info.type); 2460 2460 client_tuner = i2c_new_client_device(&dev->i2c_bus[1].i2c_adap, &info); 2461 2461 if (!i2c_client_has_driver(client_tuner)) { 2462 2462 - module_put(client_demod->dev.driver->owner); 2463 2463 - i2c_unregister_device(client_demod); 2464 2464 - port->i2c_client_demod = NULL; 2465 2462 goto frontend_detach; 2466 2463 } 2467 2464 if (!try_module_get(client_tuner->dev.driver->owner)) { 2468 2465 i2c_unregister_device(client_tuner); 2469 2469 - module_put(client_demod->dev.driver->owner); 2470 2470 - i2c_unregister_device(client_demod); 2471 2471 - port->i2c_client_demod = NULL; 2472 2466 goto frontend_detach; 2473 2467 } 2474 2468 port->i2c_client_tuner = client_tuner; ··· 2499 2505 request_module("%s", info.type); 2500 2506 client_tuner = i2c_new_client_device(&dev->i2c_bus[1].i2c_adap, &info); 2501 2507 if (!i2c_client_has_driver(client_tuner)) { 2502 2502 - module_put(client_demod->dev.driver->owner); 2503 2503 - i2c_unregister_device(client_demod); 2504 2504 - port->i2c_client_demod = NULL; 2505 2508 goto frontend_detach; 2506 2509 } 2507 2510 if (!try_module_get(client_tuner->dev.driver->owner)) { 2508 2511 i2c_unregister_device(client_tuner); 2509 2509 - module_put(client_demod->dev.driver->owner); 2510 2510 - i2c_unregister_device(client_demod); 2511 2511 - port->i2c_client_demod = NULL; 2512 2512 goto frontend_detach; 2513 2513 } 2514 2514 port->i2c_client_tuner = client_tuner;

+2 -2

drivers/media/platform/amphion/vpu_core.c

reviewed

··· 826 826 827 827 static struct vpu_core_resources imx8q_enc = { 828 828 .type = VPU_CORE_TYPE_ENC, 829 829 - .fwname = "vpu/vpu_fw_imx8_enc.bin", 829 829 + .fwname = "amphion/vpu/vpu_fw_imx8_enc.bin", 830 830 .stride = 16, 831 831 .max_width = 1920, 832 832 .max_height = 1920, ··· 841 841 842 842 static struct vpu_core_resources imx8q_dec = { 843 843 .type = VPU_CORE_TYPE_DEC, 844 844 - .fwname = "vpu/vpu_fw_imx8_dec.bin", 844 844 + .fwname = "amphion/vpu/vpu_fw_imx8_dec.bin", 845 845 .stride = 256, 846 846 .max_width = 8188, 847 847 .max_height = 8188,

+4 -5

drivers/media/platform/amphion/vpu_mbox.c

reviewed

··· 46 46 cl->rx_callback = vpu_mbox_rx_callback; 47 47 48 48 ch = mbox_request_channel_byname(cl, mbox->name); 49 49 - if (IS_ERR(ch)) { 50 50 - dev_err(dev, "Failed to request mbox chan %s, ret : %ld\n", 51 51 - mbox->name, PTR_ERR(ch)); 52 52 - return PTR_ERR(ch); 53 53 - } 49 49 + if (IS_ERR(ch)) 50 50 + return dev_err_probe(dev, PTR_ERR(ch), 51 51 + "Failed to request mbox chan %s\n", 52 52 + mbox->name); 54 53 55 54 mbox->ch = ch; 56 55 return 0;

+1 -5

drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c

reviewed

··· 28 28 #include "mtk_jpeg_core.h" 29 29 #include "mtk_jpeg_dec_parse.h" 30 30 31 31 - #if defined(CONFIG_OF) 32 31 static struct mtk_jpeg_fmt mtk_jpeg_enc_formats[] = { 33 32 { 34 33 .fourcc = V4L2_PIX_FMT_JPEG, ··· 101 102 .flags = MTK_JPEG_FMT_FLAG_CAPTURE, 102 103 }, 103 104 }; 104 104 - #endif 105 105 106 106 #define MTK_JPEG_ENC_NUM_FORMATS ARRAY_SIZE(mtk_jpeg_enc_formats) 107 107 #define MTK_JPEG_DEC_NUM_FORMATS ARRAY_SIZE(mtk_jpeg_dec_formats) ··· 1453 1455 SET_RUNTIME_PM_OPS(mtk_jpeg_pm_suspend, mtk_jpeg_pm_resume, NULL) 1454 1456 }; 1455 1457 1456 1456 - #if defined(CONFIG_OF) 1457 1458 static int mtk_jpegenc_get_hw(struct mtk_jpeg_ctx *ctx) 1458 1459 { 1459 1460 struct mtk_jpegenc_comp_dev *comp_jpeg; ··· 1948 1951 }; 1949 1952 1950 1953 MODULE_DEVICE_TABLE(of, mtk_jpeg_match); 1951 1951 - #endif 1952 1954 1953 1955 static struct platform_driver mtk_jpeg_driver = { 1954 1956 .probe = mtk_jpeg_probe, 1955 1957 .remove_new = mtk_jpeg_remove, 1956 1958 .driver = { 1957 1959 .name = MTK_JPEG_NAME, 1958 1958 - .of_match_table = of_match_ptr(mtk_jpeg_match), 1960 1960 + .of_match_table = mtk_jpeg_match, 1959 1961 .pm = &mtk_jpeg_pm_ops, 1960 1962 }, 1961 1963 };

+1 -3

drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c

reviewed

··· 39 39 MTK_JPEG_COLOR_400 = 0x00110000 40 40 }; 41 41 42 42 - #if defined(CONFIG_OF) 43 42 static const struct of_device_id mtk_jpegdec_hw_ids[] = { 44 43 { 45 44 .compatible = "mediatek,mt8195-jpgdec-hw", ··· 46 47 {}, 47 48 }; 48 49 MODULE_DEVICE_TABLE(of, mtk_jpegdec_hw_ids); 49 49 - #endif 50 50 51 51 static inline int mtk_jpeg_verify_align(u32 val, int align, u32 reg) 52 52 { ··· 651 653 .probe = mtk_jpegdec_hw_probe, 652 654 .driver = { 653 655 .name = "mtk-jpegdec-hw", 654 654 - .of_match_table = of_match_ptr(mtk_jpegdec_hw_ids), 656 656 + .of_match_table = mtk_jpegdec_hw_ids, 655 657 }, 656 658 }; 657 659

+1 -3

drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c

reviewed

··· 46 46 {.quality_param = 97, .hardware_value = JPEG_ENC_QUALITY_Q97}, 47 47 }; 48 48 49 49 - #if defined(CONFIG_OF) 50 49 static const struct of_device_id mtk_jpegenc_drv_ids[] = { 51 50 { 52 51 .compatible = "mediatek,mt8195-jpgenc-hw", ··· 53 54 {}, 54 55 }; 55 56 MODULE_DEVICE_TABLE(of, mtk_jpegenc_drv_ids); 56 56 - #endif 57 57 58 58 void mtk_jpeg_enc_reset(void __iomem *base) 59 59 { ··· 375 377 .probe = mtk_jpegenc_hw_probe, 376 378 .driver = { 377 379 .name = "mtk-jpegenc-hw", 378 378 - .of_match_table = of_match_ptr(mtk_jpegenc_drv_ids), 380 380 + .of_match_table = mtk_jpegenc_drv_ids, 379 381 }, 380 382 }; 381 383

+2 -1

drivers/media/platform/mediatek/vcodec/vdec_msg_queue.c

reviewed

··· 233 233 kfree(lat_buf->private_data); 234 234 } 235 235 236 236 - cancel_work_sync(&msg_queue->core_work); 236 236 + if (msg_queue->wdma_addr.size) 237 237 + cancel_work_sync(&msg_queue->core_work); 237 238 } 238 239 239 240 static void vdec_msg_queue_core_work(struct work_struct *work)

-1

drivers/media/platform/nxp/imx-jpeg/mxc-jpeg-hw.h

reviewed

··· 58 58 #define CAST_OFBSIZE_LO CAST_STATUS18 59 59 #define CAST_OFBSIZE_HI CAST_STATUS19 60 60 61 61 - #define MXC_MAX_SLOTS 1 /* TODO use all 4 slots*/ 62 61 /* JPEG-Decoder Wrapper Slot Registers 0..3 */ 63 62 #define SLOT_BASE 0x10000 64 63 #define SLOT_STATUS 0x0

+65 -70

drivers/media/platform/nxp/imx-jpeg/mxc-jpeg.c

reviewed

··· 745 745 v4l2_event_queue_fh(&ctx->fh, &ev); 746 746 } 747 747 748 748 - static int mxc_get_free_slot(struct mxc_jpeg_slot_data slot_data[], int n) 748 748 + static int mxc_get_free_slot(struct mxc_jpeg_slot_data *slot_data) 749 749 { 750 750 - int free_slot = 0; 751 751 - 752 752 - while (slot_data[free_slot].used && free_slot < n) 753 753 - free_slot++; 754 754 - 755 755 - return free_slot; /* >=n when there are no more free slots */ 750 750 + if (!slot_data->used) 751 751 + return slot_data->slot; 752 752 + return -1; 756 753 } 757 754 758 758 - static bool mxc_jpeg_alloc_slot_data(struct mxc_jpeg_dev *jpeg, 759 759 - unsigned int slot) 755 755 + static bool mxc_jpeg_alloc_slot_data(struct mxc_jpeg_dev *jpeg) 760 756 { 761 757 struct mxc_jpeg_desc *desc; 762 758 struct mxc_jpeg_desc *cfg_desc; 763 759 void *cfg_stm; 764 760 765 765 - if (jpeg->slot_data[slot].desc) 761 761 + if (jpeg->slot_data.desc) 766 762 goto skip_alloc; /* already allocated, reuse it */ 767 763 768 764 /* allocate descriptor for decoding/encoding phase */ 769 765 desc = dma_alloc_coherent(jpeg->dev, 770 766 sizeof(struct mxc_jpeg_desc), 771 771 - &jpeg->slot_data[slot].desc_handle, 767 767 + &jpeg->slot_data.desc_handle, 772 768 GFP_ATOMIC); 773 769 if (!desc) 774 770 goto err; 775 775 - jpeg->slot_data[slot].desc = desc; 771 771 + jpeg->slot_data.desc = desc; 776 772 777 773 /* allocate descriptor for configuration phase (encoder only) */ 778 774 cfg_desc = dma_alloc_coherent(jpeg->dev, 779 775 sizeof(struct mxc_jpeg_desc), 780 780 - &jpeg->slot_data[slot].cfg_desc_handle, 776 776 + &jpeg->slot_data.cfg_desc_handle, 781 777 GFP_ATOMIC); 782 778 if (!cfg_desc) 783 779 goto err; 784 784 - jpeg->slot_data[slot].cfg_desc = cfg_desc; 780 780 + jpeg->slot_data.cfg_desc = cfg_desc; 785 781 786 782 /* allocate configuration stream */ 787 783 cfg_stm = dma_alloc_coherent(jpeg->dev, 788 784 MXC_JPEG_MAX_CFG_STREAM, 789 789 - &jpeg->slot_data[slot].cfg_stream_handle, 785 785 + &jpeg->slot_data.cfg_stream_handle, 790 786 GFP_ATOMIC); 791 787 if (!cfg_stm) 792 788 goto err; 793 793 - jpeg->slot_data[slot].cfg_stream_vaddr = cfg_stm; 789 789 + jpeg->slot_data.cfg_stream_vaddr = cfg_stm; 794 790 795 791 skip_alloc: 796 796 - jpeg->slot_data[slot].used = true; 792 792 + jpeg->slot_data.used = true; 797 793 798 794 return true; 799 795 err: 800 800 - dev_err(jpeg->dev, "Could not allocate descriptors for slot %d", slot); 796 796 + dev_err(jpeg->dev, "Could not allocate descriptors for slot %d", jpeg->slot_data.slot); 801 797 802 798 return false; 803 799 } 804 800 805 805 - static void mxc_jpeg_free_slot_data(struct mxc_jpeg_dev *jpeg, 806 806 - unsigned int slot) 801 801 + static void mxc_jpeg_free_slot_data(struct mxc_jpeg_dev *jpeg) 807 802 { 808 808 - if (slot >= MXC_MAX_SLOTS) { 809 809 - dev_err(jpeg->dev, "Invalid slot %d, nothing to free.", slot); 810 810 - return; 811 811 - } 812 812 - 813 803 /* free descriptor for decoding/encoding phase */ 814 804 dma_free_coherent(jpeg->dev, sizeof(struct mxc_jpeg_desc), 815 815 - jpeg->slot_data[slot].desc, 816 816 - jpeg->slot_data[slot].desc_handle); 805 805 + jpeg->slot_data.desc, 806 806 + jpeg->slot_data.desc_handle); 817 807 818 808 /* free descriptor for encoder configuration phase / decoder DHT */ 819 809 dma_free_coherent(jpeg->dev, sizeof(struct mxc_jpeg_desc), 820 820 - jpeg->slot_data[slot].cfg_desc, 821 821 - jpeg->slot_data[slot].cfg_desc_handle); 810 810 + jpeg->slot_data.cfg_desc, 811 811 + jpeg->slot_data.cfg_desc_handle); 822 812 823 813 /* free configuration stream */ 824 814 dma_free_coherent(jpeg->dev, MXC_JPEG_MAX_CFG_STREAM, 825 825 - jpeg->slot_data[slot].cfg_stream_vaddr, 826 826 - jpeg->slot_data[slot].cfg_stream_handle); 815 815 + jpeg->slot_data.cfg_stream_vaddr, 816 816 + jpeg->slot_data.cfg_stream_handle); 827 817 828 828 - jpeg->slot_data[slot].used = false; 818 818 + jpeg->slot_data.used = false; 829 819 } 830 820 831 821 static void mxc_jpeg_check_and_set_last_buffer(struct mxc_jpeg_ctx *ctx, ··· 845 855 v4l2_m2m_buf_done(dst_buf, state); 846 856 847 857 mxc_jpeg_disable_irq(reg, ctx->slot); 848 848 - ctx->mxc_jpeg->slot_data[ctx->slot].used = false; 858 858 + jpeg->slot_data.used = false; 849 859 if (reset) 850 860 mxc_jpeg_sw_reset(reg); 851 861 } ··· 909 919 goto job_unlock; 910 920 } 911 921 912 912 - if (!jpeg->slot_data[slot].used) 922 922 + if (!jpeg->slot_data.used) 913 923 goto job_unlock; 914 924 915 925 dec_ret = readl(reg + MXC_SLOT_OFFSET(slot, SLOT_STATUS)); ··· 1169 1179 struct mxc_jpeg_dev *jpeg = ctx->mxc_jpeg; 1170 1180 void __iomem *reg = jpeg->base_reg; 1171 1181 unsigned int slot = ctx->slot; 1172 1172 - struct mxc_jpeg_desc *desc = jpeg->slot_data[slot].desc; 1173 1173 - struct mxc_jpeg_desc *cfg_desc = jpeg->slot_data[slot].cfg_desc; 1174 1174 - dma_addr_t desc_handle = jpeg->slot_data[slot].desc_handle; 1175 1175 - dma_addr_t cfg_desc_handle = jpeg->slot_data[slot].cfg_desc_handle; 1176 1176 - dma_addr_t cfg_stream_handle = jpeg->slot_data[slot].cfg_stream_handle; 1177 1177 - unsigned int *cfg_size = &jpeg->slot_data[slot].cfg_stream_size; 1178 1178 - void *cfg_stream_vaddr = jpeg->slot_data[slot].cfg_stream_vaddr; 1182 1182 + struct mxc_jpeg_desc *desc = jpeg->slot_data.desc; 1183 1183 + struct mxc_jpeg_desc *cfg_desc = jpeg->slot_data.cfg_desc; 1184 1184 + dma_addr_t desc_handle = jpeg->slot_data.desc_handle; 1185 1185 + dma_addr_t cfg_desc_handle = jpeg->slot_data.cfg_desc_handle; 1186 1186 + dma_addr_t cfg_stream_handle = jpeg->slot_data.cfg_stream_handle; 1187 1187 + unsigned int *cfg_size = &jpeg->slot_data.cfg_stream_size; 1188 1188 + void *cfg_stream_vaddr = jpeg->slot_data.cfg_stream_vaddr; 1179 1189 struct mxc_jpeg_src_buf *jpeg_src_buf; 1180 1190 1181 1191 jpeg_src_buf = vb2_to_mxc_buf(src_buf); ··· 1235 1245 struct mxc_jpeg_dev *jpeg = ctx->mxc_jpeg; 1236 1246 void __iomem *reg = jpeg->base_reg; 1237 1247 unsigned int slot = ctx->slot; 1238 1238 - struct mxc_jpeg_desc *desc = jpeg->slot_data[slot].desc; 1239 1239 - struct mxc_jpeg_desc *cfg_desc = jpeg->slot_data[slot].cfg_desc; 1240 1240 - dma_addr_t desc_handle = jpeg->slot_data[slot].desc_handle; 1241 1241 - dma_addr_t cfg_desc_handle = jpeg->slot_data[slot].cfg_desc_handle; 1242 1242 - void *cfg_stream_vaddr = jpeg->slot_data[slot].cfg_stream_vaddr; 1248 1248 + struct mxc_jpeg_desc *desc = jpeg->slot_data.desc; 1249 1249 + struct mxc_jpeg_desc *cfg_desc = jpeg->slot_data.cfg_desc; 1250 1250 + dma_addr_t desc_handle = jpeg->slot_data.desc_handle; 1251 1251 + dma_addr_t cfg_desc_handle = jpeg->slot_data.cfg_desc_handle; 1252 1252 + void *cfg_stream_vaddr = jpeg->slot_data.cfg_stream_vaddr; 1243 1253 struct mxc_jpeg_q_data *q_data; 1244 1254 enum mxc_jpeg_image_format img_fmt; 1245 1255 int w, h; 1246 1256 1247 1257 q_data = mxc_jpeg_get_q_data(ctx, src_buf->vb2_queue->type); 1248 1258 1249 1249 - jpeg->slot_data[slot].cfg_stream_size = 1259 1259 + jpeg->slot_data.cfg_stream_size = 1250 1260 mxc_jpeg_setup_cfg_stream(cfg_stream_vaddr, 1251 1261 q_data->fmt->fourcc, 1252 1262 q_data->crop.width, ··· 1255 1265 /* chain the config descriptor with the encoding descriptor */ 1256 1266 cfg_desc->next_descpt_ptr = desc_handle | MXC_NXT_DESCPT_EN; 1257 1267 1258 1258 - cfg_desc->buf_base0 = jpeg->slot_data[slot].cfg_stream_handle; 1268 1268 + cfg_desc->buf_base0 = jpeg->slot_data.cfg_stream_handle; 1259 1269 cfg_desc->buf_base1 = 0; 1260 1270 cfg_desc->line_pitch = 0; 1261 1271 cfg_desc->stm_bufbase = 0; /* no output expected */ ··· 1398 1408 unsigned long flags; 1399 1409 1400 1410 spin_lock_irqsave(&ctx->mxc_jpeg->hw_lock, flags); 1401 1401 - if (ctx->slot < MXC_MAX_SLOTS && ctx->mxc_jpeg->slot_data[ctx->slot].used) { 1411 1411 + if (ctx->mxc_jpeg->slot_data.used) { 1402 1412 dev_warn(jpeg->dev, "%s timeout, cancel it\n", 1403 1413 ctx->mxc_jpeg->mode == MXC_JPEG_DECODE ? "decode" : "encode"); 1404 1414 mxc_jpeg_job_finish(ctx, VB2_BUF_STATE_ERROR, true); ··· 1466 1476 mxc_jpeg_enable(reg); 1467 1477 mxc_jpeg_set_l_endian(reg, 1); 1468 1478 1469 1469 - ctx->slot = mxc_get_free_slot(jpeg->slot_data, MXC_MAX_SLOTS); 1470 1470 - if (ctx->slot >= MXC_MAX_SLOTS) { 1479 1479 + ctx->slot = mxc_get_free_slot(&jpeg->slot_data); 1480 1480 + if (ctx->slot < 0) { 1471 1481 dev_err(dev, "No more free slots\n"); 1472 1482 goto end; 1473 1483 } 1474 1474 - if (!mxc_jpeg_alloc_slot_data(jpeg, ctx->slot)) { 1484 1484 + if (!mxc_jpeg_alloc_slot_data(jpeg)) { 1475 1485 dev_err(dev, "Cannot allocate slot data\n"); 1476 1486 goto end; 1477 1487 } ··· 2091 2101 } 2092 2102 ctx->fh.ctrl_handler = &ctx->ctrl_handler; 2093 2103 mxc_jpeg_set_default_params(ctx); 2094 2094 - ctx->slot = MXC_MAX_SLOTS; /* slot not allocated yet */ 2104 2104 + ctx->slot = -1; /* slot not allocated yet */ 2095 2105 INIT_DELAYED_WORK(&ctx->task_timer, mxc_jpeg_device_run_timeout); 2096 2106 2097 2107 if (mxc_jpeg->mode == MXC_JPEG_DECODE) ··· 2667 2677 dev_err(dev, "No power domains defined for jpeg node\n"); 2668 2678 return jpeg->num_domains; 2669 2679 } 2680 2680 + if (jpeg->num_domains == 1) { 2681 2681 + /* genpd_dev_pm_attach() attach automatically if power domains count is 1 */ 2682 2682 + jpeg->num_domains = 0; 2683 2683 + return 0; 2684 2684 + } 2670 2685 2671 2686 jpeg->pd_dev = devm_kmalloc_array(dev, jpeg->num_domains, 2672 2687 sizeof(*jpeg->pd_dev), GFP_KERNEL); ··· 2713 2718 int ret; 2714 2719 int mode; 2715 2720 const struct of_device_id *of_id; 2716 2716 - unsigned int slot; 2717 2721 2718 2722 of_id = of_match_node(mxc_jpeg_match, dev->of_node); 2719 2723 if (!of_id) ··· 2736 2742 if (IS_ERR(jpeg->base_reg)) 2737 2743 return PTR_ERR(jpeg->base_reg); 2738 2744 2739 2739 - for (slot = 0; slot < MXC_MAX_SLOTS; slot++) { 2740 2740 - dec_irq = platform_get_irq(pdev, slot); 2741 2741 - if (dec_irq < 0) { 2742 2742 - ret = dec_irq; 2743 2743 - goto err_irq; 2744 2744 - } 2745 2745 - ret = devm_request_irq(&pdev->dev, dec_irq, mxc_jpeg_dec_irq, 2746 2746 - 0, pdev->name, jpeg); 2747 2747 - if (ret) { 2748 2748 - dev_err(&pdev->dev, "Failed to request irq %d (%d)\n", 2749 2749 - dec_irq, ret); 2750 2750 - goto err_irq; 2751 2751 - } 2745 2745 + ret = of_property_read_u32_index(pdev->dev.of_node, "slot", 0, &jpeg->slot_data.slot); 2746 2746 + if (ret) 2747 2747 + jpeg->slot_data.slot = 0; 2748 2748 + dev_info(&pdev->dev, "choose slot %d\n", jpeg->slot_data.slot); 2749 2749 + dec_irq = platform_get_irq(pdev, 0); 2750 2750 + if (dec_irq < 0) { 2751 2751 + dev_err(&pdev->dev, "Failed to get irq %d\n", dec_irq); 2752 2752 + ret = dec_irq; 2753 2753 + goto err_irq; 2754 2754 + } 2755 2755 + ret = devm_request_irq(&pdev->dev, dec_irq, mxc_jpeg_dec_irq, 2756 2756 + 0, pdev->name, jpeg); 2757 2757 + if (ret) { 2758 2758 + dev_err(&pdev->dev, "Failed to request irq %d (%d)\n", 2759 2759 + dec_irq, ret); 2760 2760 + goto err_irq; 2752 2761 } 2753 2762 2754 2763 jpeg->pdev = pdev; ··· 2911 2914 2912 2915 static void mxc_jpeg_remove(struct platform_device *pdev) 2913 2916 { 2914 2914 - unsigned int slot; 2915 2917 struct mxc_jpeg_dev *jpeg = platform_get_drvdata(pdev); 2916 2918 2917 2917 - for (slot = 0; slot < MXC_MAX_SLOTS; slot++) 2918 2918 - mxc_jpeg_free_slot_data(jpeg, slot); 2919 2919 + mxc_jpeg_free_slot_data(jpeg); 2919 2920 2920 2921 pm_runtime_disable(&pdev->dev); 2921 2922 video_unregister_device(jpeg->dec_vdev);

+3 -2

drivers/media/platform/nxp/imx-jpeg/mxc-jpeg.h

reviewed

··· 97 97 struct mxc_jpeg_q_data cap_q; 98 98 struct v4l2_fh fh; 99 99 enum mxc_jpeg_enc_state enc_state; 100 100 - unsigned int slot; 100 100 + int slot; 101 101 unsigned int source_change; 102 102 bool header_parsed; 103 103 struct v4l2_ctrl_handler ctrl_handler; ··· 106 106 }; 107 107 108 108 struct mxc_jpeg_slot_data { 109 109 + int slot; 109 110 bool used; 110 111 struct mxc_jpeg_desc *desc; // enc/dec descriptor 111 112 struct mxc_jpeg_desc *cfg_desc; // configuration descriptor ··· 129 128 struct v4l2_device v4l2_dev; 130 129 struct v4l2_m2m_dev *m2m_dev; 131 130 struct video_device *dec_vdev; 132 132 - struct mxc_jpeg_slot_data slot_data[MXC_MAX_SLOTS]; 131 131 + struct mxc_jpeg_slot_data slot_data; 133 132 int num_domains; 134 133 struct device **pd_dev; 135 134 struct device_link **pd_link;

+25 -25

drivers/media/platform/verisilicon/hantro.h

reviewed

··· 370 370 pr_err("%s:%d: " fmt, __func__, __LINE__, ##args) 371 371 372 372 /* Structure access helpers. */ 373 373 - static inline struct hantro_ctx *fh_to_ctx(struct v4l2_fh *fh) 373 373 + static __always_inline struct hantro_ctx *fh_to_ctx(struct v4l2_fh *fh) 374 374 { 375 375 return container_of(fh, struct hantro_ctx, fh); 376 376 } 377 377 378 378 /* Register accessors. */ 379 379 - static inline void vepu_write_relaxed(struct hantro_dev *vpu, 380 380 - u32 val, u32 reg) 379 379 + static __always_inline void vepu_write_relaxed(struct hantro_dev *vpu, 380 380 + u32 val, u32 reg) 381 381 { 382 382 vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val); 383 383 writel_relaxed(val, vpu->enc_base + reg); 384 384 } 385 385 386 386 - static inline void vepu_write(struct hantro_dev *vpu, u32 val, u32 reg) 386 386 + static __always_inline void vepu_write(struct hantro_dev *vpu, u32 val, u32 reg) 387 387 { 388 388 vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val); 389 389 writel(val, vpu->enc_base + reg); 390 390 } 391 391 392 392 - static inline u32 vepu_read(struct hantro_dev *vpu, u32 reg) 392 392 + static __always_inline u32 vepu_read(struct hantro_dev *vpu, u32 reg) 393 393 { 394 394 u32 val = readl(vpu->enc_base + reg); 395 395 ··· 397 397 return val; 398 398 } 399 399 400 400 - static inline void vdpu_write_relaxed(struct hantro_dev *vpu, 401 401 - u32 val, u32 reg) 400 400 + static __always_inline void vdpu_write_relaxed(struct hantro_dev *vpu, 401 401 + u32 val, u32 reg) 402 402 { 403 403 vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val); 404 404 writel_relaxed(val, vpu->dec_base + reg); 405 405 } 406 406 407 407 - static inline void vdpu_write(struct hantro_dev *vpu, u32 val, u32 reg) 407 407 + static __always_inline void vdpu_write(struct hantro_dev *vpu, u32 val, u32 reg) 408 408 { 409 409 vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val); 410 410 writel(val, vpu->dec_base + reg); 411 411 } 412 412 413 413 - static inline void hantro_write_addr(struct hantro_dev *vpu, 414 414 - unsigned long offset, 415 415 - dma_addr_t addr) 413 413 + static __always_inline void hantro_write_addr(struct hantro_dev *vpu, 414 414 + unsigned long offset, 415 415 + dma_addr_t addr) 416 416 { 417 417 vdpu_write(vpu, addr & 0xffffffff, offset); 418 418 } 419 419 420 420 - static inline u32 vdpu_read(struct hantro_dev *vpu, u32 reg) 420 420 + static __always_inline u32 vdpu_read(struct hantro_dev *vpu, u32 reg) 421 421 { 422 422 u32 val = readl(vpu->dec_base + reg); 423 423 ··· 425 425 return val; 426 426 } 427 427 428 428 - static inline u32 vdpu_read_mask(struct hantro_dev *vpu, 429 429 - const struct hantro_reg *reg, 430 430 - u32 val) 428 428 + static __always_inline u32 vdpu_read_mask(struct hantro_dev *vpu, 429 429 + const struct hantro_reg *reg, 430 430 + u32 val) 431 431 { 432 432 u32 v; 433 433 ··· 437 437 return v; 438 438 } 439 439 440 440 - static inline void hantro_reg_write(struct hantro_dev *vpu, 441 441 - const struct hantro_reg *reg, 442 442 - u32 val) 443 443 - { 444 444 - vdpu_write_relaxed(vpu, vdpu_read_mask(vpu, reg, val), reg->base); 445 445 - } 446 446 - 447 447 - static inline void hantro_reg_write_s(struct hantro_dev *vpu, 448 448 - const struct hantro_reg *reg, 449 449 - u32 val) 440 440 + static __always_inline void hantro_reg_write(struct hantro_dev *vpu, 441 441 + const struct hantro_reg *reg, 442 442 + u32 val) 450 443 { 451 444 vdpu_write(vpu, vdpu_read_mask(vpu, reg, val), reg->base); 445 445 + } 446 446 + 447 447 + static __always_inline void hantro_reg_write_relaxed(struct hantro_dev *vpu, 448 448 + const struct hantro_reg *reg, 449 449 + u32 val) 450 450 + { 451 451 + vdpu_write_relaxed(vpu, vdpu_read_mask(vpu, reg, val), reg->base); 452 452 } 453 453 454 454 void *hantro_get_ctrl(struct hantro_ctx *ctx, u32 id);

+6 -6

drivers/media/platform/verisilicon/hantro_postproc.c

reviewed

··· 21 21 val); \ 22 22 } 23 23 24 24 - #define HANTRO_PP_REG_WRITE_S(vpu, reg_name, val) \ 24 24 + #define HANTRO_PP_REG_WRITE_RELAXED(vpu, reg_name, val) \ 25 25 { \ 26 26 - hantro_reg_write_s(vpu, \ 27 27 - &hantro_g1_postproc_regs.reg_name, \ 28 28 - val); \ 26 26 + hantro_reg_write_relaxed(vpu, \ 27 27 + &hantro_g1_postproc_regs.reg_name, \ 28 28 + val); \ 29 29 } 30 30 31 31 #define VPU_PP_IN_YUYV 0x0 ··· 72 72 dma_addr_t dst_dma; 73 73 74 74 /* Turn on pipeline mode. Must be done first. */ 75 75 - HANTRO_PP_REG_WRITE_S(vpu, pipeline_en, 0x1); 75 75 + HANTRO_PP_REG_WRITE(vpu, pipeline_en, 0x1); 76 76 77 77 src_pp_fmt = VPU_PP_IN_NV12; 78 78 ··· 242 242 { 243 243 struct hantro_dev *vpu = ctx->dev; 244 244 245 245 - HANTRO_PP_REG_WRITE_S(vpu, pipeline_en, 0x0); 245 245 + HANTRO_PP_REG_WRITE(vpu, pipeline_en, 0x0); 246 246 } 247 247 248 248 static void hantro_postproc_g2_disable(struct hantro_ctx *ctx)

+5

drivers/net/bonding/bond_main.c

reviewed

··· 1508 1508 1509 1509 memcpy(bond_dev->broadcast, slave_dev->broadcast, 1510 1510 slave_dev->addr_len); 1511 1511 + 1512 1512 + if (slave_dev->flags & IFF_POINTOPOINT) { 1513 1513 + bond_dev->flags &= ~(IFF_BROADCAST | IFF_MULTICAST); 1514 1514 + bond_dev->flags |= (IFF_POINTOPOINT | IFF_NOARP); 1515 1515 + } 1511 1516 } 1512 1517 1513 1518 /* On bonding slaves other than the currently active slave, suppress

+2

drivers/net/can/usb/gs_usb.c

reviewed

··· 1030 1030 usb_kill_anchored_urbs(&dev->tx_submitted); 1031 1031 atomic_set(&dev->active_tx_urbs, 0); 1032 1032 1033 1033 + dev->can.state = CAN_STATE_STOPPED; 1034 1034 + 1033 1035 /* reset the device */ 1034 1036 rc = gs_cmd_reset(dev); 1035 1037 if (rc < 0)

+5 -2

drivers/net/dsa/qca/qca8k-8xxx.c

reviewed

··· 576 576 .rd_table = &qca8k_readable_table, 577 577 .disable_locking = true, /* Locking is handled by qca8k read/write */ 578 578 .cache_type = REGCACHE_NONE, /* Explicitly disable CACHE */ 579 579 - .max_raw_read = 32, /* mgmt eth can read/write up to 8 registers at time */ 580 580 - .max_raw_write = 32, 579 579 + .max_raw_read = 32, /* mgmt eth can read up to 8 registers at time */ 580 580 + /* ATU regs suffer from a bug where some data are not correctly 581 581 + * written. Disable bulk write to correctly write ATU entry. 582 582 + */ 583 583 + .use_single_write = true, 581 584 }; 582 585 583 586 static int

+16 -3

drivers/net/dsa/qca/qca8k-common.c

reviewed

··· 244 244 } 245 245 246 246 static int qca8k_fdb_search_and_insert(struct qca8k_priv *priv, u8 port_mask, 247 247 - const u8 *mac, u16 vid) 247 247 + const u8 *mac, u16 vid, u8 aging) 248 248 { 249 249 struct qca8k_fdb fdb = { 0 }; 250 250 int ret; ··· 261 261 goto exit; 262 262 263 263 /* Rule exist. Delete first */ 264 264 - if (!fdb.aging) { 264 264 + if (fdb.aging) { 265 265 ret = qca8k_fdb_access(priv, QCA8K_FDB_PURGE, -1); 266 266 if (ret) 267 267 goto exit; 268 268 + } else { 269 269 + fdb.aging = aging; 268 270 } 269 271 270 272 /* Add port to fdb portmask */ ··· 290 288 291 289 qca8k_fdb_write(priv, vid, 0, mac, 0); 292 290 ret = qca8k_fdb_access(priv, QCA8K_FDB_SEARCH, -1); 291 291 + if (ret < 0) 292 292 + goto exit; 293 293 + 294 294 + ret = qca8k_fdb_read(priv, &fdb); 293 295 if (ret < 0) 294 296 goto exit; 295 297 ··· 816 810 const u8 *addr = mdb->addr; 817 811 u16 vid = mdb->vid; 818 812 819 819 - return qca8k_fdb_search_and_insert(priv, BIT(port), addr, vid); 813 813 + if (!vid) 814 814 + vid = QCA8K_PORT_VID_DEF; 815 815 + 816 816 + return qca8k_fdb_search_and_insert(priv, BIT(port), addr, vid, 817 817 + QCA8K_ATU_STATUS_STATIC); 820 818 } 821 819 822 820 int qca8k_port_mdb_del(struct dsa_switch *ds, int port, ··· 830 820 struct qca8k_priv *priv = ds->priv; 831 821 const u8 *addr = mdb->addr; 832 822 u16 vid = mdb->vid; 823 823 + 824 824 + if (!vid) 825 825 + vid = QCA8K_PORT_VID_DEF; 833 826 834 827 return qca8k_fdb_search_and_del(priv, BIT(port), addr, vid); 835 828 }

+5 -2

drivers/net/ethernet/atheros/atl1c/atl1c_main.c

reviewed

··· 2094 2094 real_len = (((unsigned char *)ip_hdr(skb) - skb->data) 2095 2095 + ntohs(ip_hdr(skb)->tot_len)); 2096 2096 2097 2097 - if (real_len < skb->len) 2098 2098 - pskb_trim(skb, real_len); 2097 2097 + if (real_len < skb->len) { 2098 2098 + err = pskb_trim(skb, real_len); 2099 2099 + if (err) 2100 2100 + return err; 2101 2101 + } 2099 2102 2100 2103 hdr_len = skb_tcp_all_headers(skb); 2101 2104 if (unlikely(skb->len == hdr_len)) {

+5 -2

drivers/net/ethernet/atheros/atl1e/atl1e_main.c

reviewed

··· 1641 1641 real_len = (((unsigned char *)ip_hdr(skb) - skb->data) 1642 1642 + ntohs(ip_hdr(skb)->tot_len)); 1643 1643 1644 1644 - if (real_len < skb->len) 1645 1645 - pskb_trim(skb, real_len); 1644 1644 + if (real_len < skb->len) { 1645 1645 + err = pskb_trim(skb, real_len); 1646 1646 + if (err) 1647 1647 + return err; 1648 1648 + } 1646 1649 1647 1650 hdr_len = skb_tcp_all_headers(skb); 1648 1651 if (unlikely(skb->len == hdr_len)) {

+5 -2

drivers/net/ethernet/atheros/atlx/atl1.c

reviewed

··· 2113 2113 2114 2114 real_len = (((unsigned char *)iph - skb->data) + 2115 2115 ntohs(iph->tot_len)); 2116 2116 - if (real_len < skb->len) 2117 2117 - pskb_trim(skb, real_len); 2116 2116 + if (real_len < skb->len) { 2117 2117 + err = pskb_trim(skb, real_len); 2118 2118 + if (err) 2119 2119 + return err; 2120 2120 + } 2118 2121 hdr_len = skb_tcp_all_headers(skb); 2119 2122 if (skb->len == hdr_len) { 2120 2123 iph->check = 0;

+2 -1

drivers/net/ethernet/emulex/benet/be_main.c

reviewed

··· 1138 1138 (lancer_chip(adapter) || BE3_chip(adapter) || 1139 1139 skb_vlan_tag_present(skb)) && is_ipv4_pkt(skb)) { 1140 1140 ip = (struct iphdr *)ip_hdr(skb); 1141 1141 - pskb_trim(skb, eth_hdr_len + ntohs(ip->tot_len)); 1141 1141 + if (unlikely(pskb_trim(skb, eth_hdr_len + ntohs(ip->tot_len)))) 1142 1142 + goto tx_drop; 1142 1143 } 1143 1144 1144 1145 /* If vlan tag is already inlined in the packet, skip HW VLAN

+14 -4

drivers/net/ethernet/freescale/fec_main.c

reviewed

··· 1370 1370 } 1371 1371 1372 1372 static void 1373 1373 - fec_enet_tx_queue(struct net_device *ndev, u16 queue_id) 1373 1373 + fec_enet_tx_queue(struct net_device *ndev, u16 queue_id, int budget) 1374 1374 { 1375 1375 struct fec_enet_private *fep; 1376 1376 struct xdp_frame *xdpf; ··· 1414 1414 if (!skb) 1415 1415 goto tx_buf_done; 1416 1416 } else { 1417 1417 + /* Tx processing cannot call any XDP (or page pool) APIs if 1418 1418 + * the "budget" is 0. Because NAPI is called with budget of 1419 1419 + * 0 (such as netpoll) indicates we may be in an IRQ context, 1420 1420 + * however, we can't use the page pool from IRQ context. 1421 1421 + */ 1422 1422 + if (unlikely(!budget)) 1423 1423 + break; 1424 1424 + 1417 1425 xdpf = txq->tx_buf[index].xdp; 1418 1426 if (bdp->cbd_bufaddr) 1419 1427 dma_unmap_single(&fep->pdev->dev, ··· 1514 1506 writel(0, txq->bd.reg_desc_active); 1515 1507 } 1516 1508 1517 1517 - static void fec_enet_tx(struct net_device *ndev) 1509 1509 + static void fec_enet_tx(struct net_device *ndev, int budget) 1518 1510 { 1519 1511 struct fec_enet_private *fep = netdev_priv(ndev); 1520 1512 int i; 1521 1513 1522 1514 /* Make sure that AVB queues are processed first. */ 1523 1515 for (i = fep->num_tx_queues - 1; i >= 0; i--) 1524 1524 - fec_enet_tx_queue(ndev, i); 1516 1516 + fec_enet_tx_queue(ndev, i, budget); 1525 1517 } 1526 1518 1527 1519 static void fec_enet_update_cbd(struct fec_enet_priv_rx_q *rxq, ··· 1864 1856 1865 1857 do { 1866 1858 done += fec_enet_rx(ndev, budget - done); 1867 1867 - fec_enet_tx(ndev); 1859 1859 + fec_enet_tx(ndev, budget); 1868 1860 } while ((done < budget) && fec_enet_collect_events(fep)); 1869 1861 1870 1862 if (done < budget) { ··· 3882 3874 3883 3875 __netif_tx_lock(nq, cpu); 3884 3876 3877 3877 + /* Avoid tx timeout as XDP shares the queue with kernel stack */ 3878 3878 + txq_trans_cond_update(nq); 3885 3879 for (i = 0; i < num_frames; i++) { 3886 3880 if (fec_enet_txq_xmit_frame(fep, txq, frames[i]) < 0) 3887 3881 break;

+6 -1

drivers/net/ethernet/hisilicon/hns3/hnae3.h

reviewed

··· 31 31 #include <linux/pci.h> 32 32 #include <linux/pkt_sched.h> 33 33 #include <linux/types.h> 34 34 + #include <linux/bitmap.h> 34 35 #include <net/pkt_cls.h> 35 36 #include <net/pkt_sched.h> 36 37 ··· 102 101 HNAE3_DEV_SUPPORT_FEC_STATS_B, 103 102 HNAE3_DEV_SUPPORT_LANE_NUM_B, 104 103 HNAE3_DEV_SUPPORT_WOL_B, 104 104 + HNAE3_DEV_SUPPORT_TM_FLUSH_B, 105 105 }; 106 106 107 107 #define hnae3_ae_dev_fd_supported(ae_dev) \ ··· 173 171 174 172 #define hnae3_ae_dev_wol_supported(ae_dev) \ 175 173 test_bit(HNAE3_DEV_SUPPORT_WOL_B, (ae_dev)->caps) 174 174 + 175 175 + #define hnae3_ae_dev_tm_flush_supported(hdev) \ 176 176 + test_bit(HNAE3_DEV_SUPPORT_TM_FLUSH_B, (hdev)->ae_dev->caps) 176 177 177 178 enum HNAE3_PF_CAP_BITS { 178 179 HNAE3_PF_SUPPORT_VLAN_FLTR_MDF_B = 0, ··· 412 407 unsigned long hw_err_reset_req; 413 408 struct hnae3_dev_specs dev_specs; 414 409 u32 dev_version; 415 415 - unsigned long caps[BITS_TO_LONGS(HNAE3_DEV_CAPS_MAX_NUM)]; 410 410 + DECLARE_BITMAP(caps, HNAE3_DEV_CAPS_MAX_NUM); 416 411 void *priv; 417 412 }; 418 413

+19 -3

drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c

reviewed

··· 156 156 {HCLGE_COMM_CAP_FEC_STATS_B, HNAE3_DEV_SUPPORT_FEC_STATS_B}, 157 157 {HCLGE_COMM_CAP_LANE_NUM_B, HNAE3_DEV_SUPPORT_LANE_NUM_B}, 158 158 {HCLGE_COMM_CAP_WOL_B, HNAE3_DEV_SUPPORT_WOL_B}, 159 159 + {HCLGE_COMM_CAP_TM_FLUSH_B, HNAE3_DEV_SUPPORT_TM_FLUSH_B}, 159 160 }; 160 161 161 162 static const struct hclge_comm_caps_bit_map hclge_vf_cmd_caps[] = { ··· 173 172 }; 174 173 175 174 static void 175 175 + hclge_comm_capability_to_bitmap(unsigned long *bitmap, __le32 *caps) 176 176 + { 177 177 + const unsigned int words = HCLGE_COMM_QUERY_CAP_LENGTH; 178 178 + u32 val[HCLGE_COMM_QUERY_CAP_LENGTH]; 179 179 + unsigned int i; 180 180 + 181 181 + for (i = 0; i < words; i++) 182 182 + val[i] = __le32_to_cpu(caps[i]); 183 183 + 184 184 + bitmap_from_arr32(bitmap, val, 185 185 + HCLGE_COMM_QUERY_CAP_LENGTH * BITS_PER_TYPE(u32)); 186 186 + } 187 187 + 188 188 + static void 176 189 hclge_comm_parse_capability(struct hnae3_ae_dev *ae_dev, bool is_pf, 177 190 struct hclge_comm_query_version_cmd *cmd) 178 191 { ··· 194 179 is_pf ? hclge_pf_cmd_caps : hclge_vf_cmd_caps; 195 180 u32 size = is_pf ? ARRAY_SIZE(hclge_pf_cmd_caps) : 196 181 ARRAY_SIZE(hclge_vf_cmd_caps); 197 197 - u32 caps, i; 182 182 + DECLARE_BITMAP(caps, HCLGE_COMM_QUERY_CAP_LENGTH * BITS_PER_TYPE(u32)); 183 183 + u32 i; 198 184 199 199 - caps = __le32_to_cpu(cmd->caps[0]); 185 185 + hclge_comm_capability_to_bitmap(caps, cmd->caps); 200 186 for (i = 0; i < size; i++) 201 201 - if (hnae3_get_bit(caps, caps_map[i].imp_bit)) 187 187 + if (test_bit(caps_map[i].imp_bit, caps)) 202 188 set_bit(caps_map[i].local_bit, ae_dev->caps); 203 189 } 204 190

+2

drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h

reviewed

··· 153 153 HCLGE_OPC_TM_INTERNAL_STS = 0x0850, 154 154 HCLGE_OPC_TM_INTERNAL_CNT = 0x0851, 155 155 HCLGE_OPC_TM_INTERNAL_STS_1 = 0x0852, 156 156 + HCLGE_OPC_TM_FLUSH = 0x0872, 156 157 157 158 /* Packet buffer allocate commands */ 158 159 HCLGE_OPC_TX_BUFF_ALLOC = 0x0901, ··· 350 349 HCLGE_COMM_CAP_FEC_STATS_B = 25, 351 350 HCLGE_COMM_CAP_LANE_NUM_B = 27, 352 351 HCLGE_COMM_CAP_WOL_B = 28, 352 352 + HCLGE_COMM_CAP_TM_FLUSH_B = 31, 353 353 }; 354 354 355 355 enum HCLGE_COMM_API_CAP_BITS {

+3

drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c

reviewed

··· 411 411 }, { 412 412 .name = "support wake on lan", 413 413 .cap_bit = HNAE3_DEV_SUPPORT_WOL_B, 414 414 + }, { 415 415 + .name = "support tm flush", 416 416 + .cap_bit = HNAE3_DEV_SUPPORT_TM_FLUSH_B, 414 417 } 415 418 }; 416 419

+43 -8

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c

reviewed

··· 52 52 53 53 for (i = 0; i < HNAE3_MAX_TC; i++) { 54 54 ets->prio_tc[i] = hdev->tm_info.prio_tc[i]; 55 55 - ets->tc_tx_bw[i] = hdev->tm_info.pg_info[0].tc_dwrr[i]; 55 55 + if (i < hdev->tm_info.num_tc) 56 56 + ets->tc_tx_bw[i] = hdev->tm_info.pg_info[0].tc_dwrr[i]; 57 57 + else 58 58 + ets->tc_tx_bw[i] = 0; 56 59 57 60 if (hdev->tm_info.tc_info[i].tc_sch_mode == 58 61 HCLGE_SCH_MODE_SP) ··· 126 123 } 127 124 128 125 static int hclge_ets_sch_mode_validate(struct hclge_dev *hdev, 129 129 - struct ieee_ets *ets, bool *changed) 126 126 + struct ieee_ets *ets, bool *changed, 127 127 + u8 tc_num) 130 128 { 131 129 bool has_ets_tc = false; 132 130 u32 total_ets_bw = 0; ··· 141 137 *changed = true; 142 138 break; 143 139 case IEEE_8021QAZ_TSA_ETS: 140 140 + if (i >= tc_num) { 141 141 + dev_err(&hdev->pdev->dev, 142 142 + "tc%u is disabled, cannot set ets bw\n", 143 143 + i); 144 144 + return -EINVAL; 145 145 + } 146 146 + 144 147 /* The hardware will switch to sp mode if bandwidth is 145 148 * 0, so limit ets bandwidth must be greater than 0. 146 149 */ ··· 187 176 if (ret) 188 177 return ret; 189 178 190 190 - ret = hclge_ets_sch_mode_validate(hdev, ets, changed); 179 179 + ret = hclge_ets_sch_mode_validate(hdev, ets, changed, tc_num); 191 180 if (ret) 192 181 return ret; 193 182 ··· 227 216 if (ret) 228 217 return ret; 229 218 219 219 + ret = hclge_tm_flush_cfg(hdev, true); 220 220 + if (ret) 221 221 + return ret; 222 222 + 230 223 return hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT); 231 224 } 232 225 ··· 239 224 int ret; 240 225 241 226 ret = hclge_notify_client(hdev, HNAE3_INIT_CLIENT); 227 227 + if (ret) 228 228 + return ret; 229 229 + 230 230 + ret = hclge_tm_flush_cfg(hdev, false); 242 231 if (ret) 243 232 return ret; 244 233 ··· 332 313 struct net_device *netdev = h->kinfo.netdev; 333 314 struct hclge_dev *hdev = vport->back; 334 315 u8 i, j, pfc_map, *prio_tc; 316 316 + int last_bad_ret = 0; 335 317 int ret; 336 318 337 319 if (!(hdev->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)) ··· 370 350 if (ret) 371 351 return ret; 372 352 373 373 - ret = hclge_buffer_alloc(hdev); 374 374 - if (ret) { 375 375 - hclge_notify_client(hdev, HNAE3_UP_CLIENT); 353 353 + ret = hclge_tm_flush_cfg(hdev, true); 354 354 + if (ret) 376 355 return ret; 377 377 - } 378 356 379 379 - return hclge_notify_client(hdev, HNAE3_UP_CLIENT); 357 357 + /* No matter whether the following operations are performed 358 358 + * successfully or not, disabling the tm flush and notify 359 359 + * the network status to up are necessary. 360 360 + * Do not return immediately. 361 361 + */ 362 362 + ret = hclge_buffer_alloc(hdev); 363 363 + if (ret) 364 364 + last_bad_ret = ret; 365 365 + 366 366 + ret = hclge_tm_flush_cfg(hdev, false); 367 367 + if (ret) 368 368 + last_bad_ret = ret; 369 369 + 370 370 + ret = hclge_notify_client(hdev, HNAE3_UP_CLIENT); 371 371 + if (ret) 372 372 + last_bad_ret = ret; 373 373 + 374 374 + return last_bad_ret; 380 375 } 381 376 382 377 static int hclge_ieee_setapp(struct hnae3_handle *h, struct dcb_app *app)

+1 -2

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c

reviewed

··· 693 693 for (i = 0; i < HNAE3_MAX_TC; i++) { 694 694 sch_mode_str = ets_weight->tc_weight[i] ? "dwrr" : "sp"; 695 695 pos += scnprintf(buf + pos, len - pos, "%u %4s %3u\n", 696 696 - i, sch_mode_str, 697 697 - hdev->tm_info.pg_info[0].tc_dwrr[i]); 696 696 + i, sch_mode_str, ets_weight->tc_weight[i]); 698 697 } 699 698 700 699 return 0;

+32 -2

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c

reviewed

··· 785 785 static void hclge_tm_pg_info_init(struct hclge_dev *hdev) 786 786 { 787 787 #define BW_PERCENT 100 788 788 + #define DEFAULT_BW_WEIGHT 1 788 789 789 790 u8 i; 790 791 ··· 807 806 for (k = 0; k < hdev->tm_info.num_tc; k++) 808 807 hdev->tm_info.pg_info[i].tc_dwrr[k] = BW_PERCENT; 809 808 for (; k < HNAE3_MAX_TC; k++) 810 810 - hdev->tm_info.pg_info[i].tc_dwrr[k] = 0; 809 809 + hdev->tm_info.pg_info[i].tc_dwrr[k] = DEFAULT_BW_WEIGHT; 811 810 } 812 811 } 813 812 ··· 1485 1484 return ret; 1486 1485 1487 1486 /* Cfg schd mode for each level schd */ 1488 1488 - return hclge_tm_schd_mode_hw(hdev); 1487 1487 + ret = hclge_tm_schd_mode_hw(hdev); 1488 1488 + if (ret) 1489 1489 + return ret; 1490 1490 + 1491 1491 + return hclge_tm_flush_cfg(hdev, false); 1489 1492 } 1490 1493 1491 1494 static int hclge_pause_param_setup_hw(struct hclge_dev *hdev) ··· 2117 2112 para->rate = le32_to_cpu(port_shap_cfg_cmd->port_rate); 2118 2113 2119 2114 return 0; 2115 2115 + } 2116 2116 + 2117 2117 + int hclge_tm_flush_cfg(struct hclge_dev *hdev, bool enable) 2118 2118 + { 2119 2119 + struct hclge_desc desc; 2120 2120 + int ret; 2121 2121 + 2122 2122 + if (!hnae3_ae_dev_tm_flush_supported(hdev)) 2123 2123 + return 0; 2124 2124 + 2125 2125 + hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_FLUSH, false); 2126 2126 + 2127 2127 + desc.data[0] = cpu_to_le32(enable ? HCLGE_TM_FLUSH_EN_MSK : 0); 2128 2128 + 2129 2129 + ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2130 2130 + if (ret) { 2131 2131 + dev_err(&hdev->pdev->dev, 2132 2132 + "failed to config tm flush, ret = %d\n", ret); 2133 2133 + return ret; 2134 2134 + } 2135 2135 + 2136 2136 + if (enable) 2137 2137 + msleep(HCLGE_TM_FLUSH_TIME_MS); 2138 2138 + 2139 2139 + return ret; 2120 2140 }

+4

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h

reviewed

··· 33 33 #define HCLGE_DSCP_MAP_TC_BD_NUM 2 34 34 #define HCLGE_DSCP_TC_SHIFT(n) (((n) & 1) * 4) 35 35 36 36 + #define HCLGE_TM_FLUSH_TIME_MS 10 37 37 + #define HCLGE_TM_FLUSH_EN_MSK BIT(0) 38 38 + 36 39 struct hclge_pg_to_pri_link_cmd { 37 40 u8 pg_id; 38 41 u8 rsvd1[3]; ··· 275 272 struct hclge_tm_shaper_para *para); 276 273 int hclge_up_to_tc_map(struct hclge_dev *hdev); 277 274 int hclge_dscp_to_tc_map(struct hclge_dev *hdev); 275 275 + int hclge_tm_flush_cfg(struct hclge_dev *hdev, bool enable); 278 276 #endif

+1 -1

drivers/net/ethernet/intel/i40e/i40e_debugfs.c

reviewed

··· 1839 1839 void i40e_dbg_init(void) 1840 1840 { 1841 1841 i40e_dbg_root = debugfs_create_dir(i40e_driver_name, NULL); 1842 1842 - if (!i40e_dbg_root) 1842 1842 + if (IS_ERR(i40e_dbg_root)) 1843 1843 pr_info("init of debugfs failed\n"); 1844 1844 } 1845 1845

+6 -5

drivers/net/ethernet/intel/iavf/iavf_main.c

reviewed

··· 3250 3250 u32 val, oldval; 3251 3251 u16 pending; 3252 3252 3253 3253 - if (adapter->flags & IAVF_FLAG_PF_COMMS_FAILED) 3254 3254 - goto out; 3255 3255 - 3256 3253 if (!mutex_trylock(&adapter->crit_lock)) { 3257 3254 if (adapter->state == __IAVF_REMOVE) 3258 3255 return; ··· 3258 3261 goto out; 3259 3262 } 3260 3263 3264 3264 + if (adapter->flags & IAVF_FLAG_PF_COMMS_FAILED) 3265 3265 + goto unlock; 3266 3266 + 3261 3267 event.buf_len = IAVF_MAX_AQ_BUF_SIZE; 3262 3268 event.msg_buf = kzalloc(event.buf_len, GFP_KERNEL); 3263 3269 if (!event.msg_buf) 3264 3264 - goto out; 3270 3270 + goto unlock; 3265 3271 3266 3272 do { 3267 3273 ret = iavf_clean_arq_element(hw, &event, &pending); ··· 3279 3279 if (pending != 0) 3280 3280 memset(event.msg_buf, 0, IAVF_MAX_AQ_BUF_SIZE); 3281 3281 } while (pending); 3282 3282 - mutex_unlock(&adapter->crit_lock); 3283 3282 3284 3283 if (iavf_is_reset_in_progress(adapter)) 3285 3284 goto freedom; ··· 3322 3323 3323 3324 freedom: 3324 3325 kfree(event.msg_buf); 3326 3326 + unlock: 3327 3327 + mutex_unlock(&adapter->crit_lock); 3325 3328 out: 3326 3329 /* re-enable Admin queue interrupt cause */ 3327 3330 iavf_misc_irq_enable(adapter);

+14 -12

drivers/net/ethernet/intel/ice/ice_ethtool_fdir.c

reviewed

··· 1281 1281 ICE_FLOW_FLD_OFF_INVAL); 1282 1282 } 1283 1283 1284 1284 - /* add filter for outer headers */ 1285 1284 fltr_idx = ice_ethtool_flow_to_fltr(fsp->flow_type & ~FLOW_EXT); 1285 1285 + 1286 1286 + assign_bit(fltr_idx, hw->fdir_perfect_fltr, perfect_filter); 1287 1287 + 1288 1288 + /* add filter for outer headers */ 1286 1289 ret = ice_fdir_set_hw_fltr_rule(pf, seg, fltr_idx, 1287 1290 ICE_FD_HW_SEG_NON_TUN); 1288 1288 - if (ret == -EEXIST) 1289 1289 - /* Rule already exists, free memory and continue */ 1290 1290 - devm_kfree(dev, seg); 1291 1291 - else if (ret) 1291 1291 + if (ret == -EEXIST) { 1292 1292 + /* Rule already exists, free memory and count as success */ 1293 1293 + ret = 0; 1294 1294 + goto err_exit; 1295 1295 + } else if (ret) { 1292 1296 /* could not write filter, free memory */ 1293 1297 goto err_exit; 1298 1298 + } 1294 1299 1295 1300 /* make tunneled filter HW entries if possible */ 1296 1301 memcpy(&tun_seg[1], seg, sizeof(*seg)); ··· 1310 1305 devm_kfree(dev, tun_seg); 1311 1306 } 1312 1307 1313 1313 - if (perfect_filter) 1314 1314 - set_bit(fltr_idx, hw->fdir_perfect_fltr); 1315 1315 - else 1316 1316 - clear_bit(fltr_idx, hw->fdir_perfect_fltr); 1317 1317 - 1318 1308 return ret; 1319 1309 1320 1310 err_exit: 1321 1311 devm_kfree(dev, tun_seg); 1322 1312 devm_kfree(dev, seg); 1323 1313 1324 1324 - return -EOPNOTSUPP; 1314 1314 + return ret; 1325 1315 } 1326 1316 1327 1317 /** ··· 1914 1914 input->comp_report = ICE_FXD_FLTR_QW0_COMP_REPORT_SW_FAIL; 1915 1915 1916 1916 /* input struct is added to the HW filter list */ 1917 1917 - ice_fdir_update_list_entry(pf, input, fsp->location); 1917 1917 + ret = ice_fdir_update_list_entry(pf, input, fsp->location); 1918 1918 + if (ret) 1919 1919 + goto release_lock; 1918 1920 1919 1921 ret = ice_fdir_write_all_fltr(pf, input, true); 1920 1922 if (ret)

+28 -12

drivers/net/ethernet/intel/igc/igc_main.c

reviewed

··· 316 316 igc_clean_tx_ring(adapter->tx_ring[i]); 317 317 } 318 318 319 319 + static void igc_disable_tx_ring_hw(struct igc_ring *ring) 320 320 + { 321 321 + struct igc_hw *hw = &ring->q_vector->adapter->hw; 322 322 + u8 idx = ring->reg_idx; 323 323 + u32 txdctl; 324 324 + 325 325 + txdctl = rd32(IGC_TXDCTL(idx)); 326 326 + txdctl &= ~IGC_TXDCTL_QUEUE_ENABLE; 327 327 + txdctl |= IGC_TXDCTL_SWFLUSH; 328 328 + wr32(IGC_TXDCTL(idx), txdctl); 329 329 + } 330 330 + 331 331 + /** 332 332 + * igc_disable_all_tx_rings_hw - Disable all transmit queue operation 333 333 + * @adapter: board private structure 334 334 + */ 335 335 + static void igc_disable_all_tx_rings_hw(struct igc_adapter *adapter) 336 336 + { 337 337 + int i; 338 338 + 339 339 + for (i = 0; i < adapter->num_tx_queues; i++) { 340 340 + struct igc_ring *tx_ring = adapter->tx_ring[i]; 341 341 + 342 342 + igc_disable_tx_ring_hw(tx_ring); 343 343 + } 344 344 + } 345 345 + 319 346 /** 320 347 * igc_setup_tx_resources - allocate Tx resources (Descriptors) 321 348 * @tx_ring: tx descriptor ring (for a specific queue) to setup ··· 5085 5058 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 5086 5059 adapter->flags &= ~IGC_FLAG_VLAN_PROMISC; 5087 5060 5061 5061 + igc_disable_all_tx_rings_hw(adapter); 5088 5062 igc_clean_all_tx_rings(adapter); 5089 5063 igc_clean_all_rx_rings(adapter); 5090 5064 } ··· 7345 7317 igc_alloc_rx_buffers_zc(ring, igc_desc_unused(ring)); 7346 7318 else 7347 7319 igc_alloc_rx_buffers(ring, igc_desc_unused(ring)); 7348 7348 - } 7349 7349 - 7350 7350 - static void igc_disable_tx_ring_hw(struct igc_ring *ring) 7351 7351 - { 7352 7352 - struct igc_hw *hw = &ring->q_vector->adapter->hw; 7353 7353 - u8 idx = ring->reg_idx; 7354 7354 - u32 txdctl; 7355 7355 - 7356 7356 - txdctl = rd32(IGC_TXDCTL(idx)); 7357 7357 - txdctl &= ~IGC_TXDCTL_QUEUE_ENABLE; 7358 7358 - txdctl |= IGC_TXDCTL_SWFLUSH; 7359 7359 - wr32(IGC_TXDCTL(idx), txdctl); 7360 7320 } 7361 7321 7362 7322 void igc_disable_tx_ring(struct igc_ring *ring)

+1 -1

drivers/net/ethernet/intel/ixgbe/ixgbe_main.c

reviewed

··· 8479 8479 struct ixgbe_adapter *adapter = q_vector->adapter; 8480 8480 8481 8481 if (unlikely(skb_tail_pointer(skb) < hdr.network + 8482 8482 - VXLAN_HEADROOM)) 8482 8482 + vxlan_headroom(0))) 8483 8483 return; 8484 8484 8485 8485 /* verify the port is recognized as VXLAN */

+42 -1

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_hash.c

reviewed

··· 218 218 219 219 void npc_program_mkex_hash(struct rvu *rvu, int blkaddr) 220 220 { 221 221 + struct npc_mcam_kex_hash *mh = rvu->kpu.mkex_hash; 221 222 struct hw_cap *hwcap = &rvu->hw->cap; 223 223 + u8 intf, ld, hdr_offset, byte_len; 222 224 struct rvu_hwinfo *hw = rvu->hw; 223 223 - u8 intf; 225 225 + u64 cfg; 224 226 227 227 + /* Check if hardware supports hash extraction */ 225 228 if (!hwcap->npc_hash_extract) 226 229 return; 227 230 231 231 + /* Check if IPv6 source/destination address 232 232 + * should be hash enabled. 233 233 + * Hashing reduces 128bit SIP/DIP fields to 32bit 234 234 + * so that 224 bit X2 key can be used for IPv6 based filters as well, 235 235 + * which in turn results in more number of MCAM entries available for 236 236 + * use. 237 237 + * 238 238 + * Hashing of IPV6 SIP/DIP is enabled in below scenarios 239 239 + * 1. If the silicon variant supports hashing feature 240 240 + * 2. If the number of bytes of IP addr being extracted is 4 bytes ie 241 241 + * 32bit. The assumption here is that if user wants 8bytes of LSB of 242 242 + * IP addr or full 16 bytes then his intention is not to use 32bit 243 243 + * hash. 244 244 + */ 245 245 + for (intf = 0; intf < hw->npc_intfs; intf++) { 246 246 + for (ld = 0; ld < NPC_MAX_LD; ld++) { 247 247 + cfg = rvu_read64(rvu, blkaddr, 248 248 + NPC_AF_INTFX_LIDX_LTX_LDX_CFG(intf, 249 249 + NPC_LID_LC, 250 250 + NPC_LT_LC_IP6, 251 251 + ld)); 252 252 + hdr_offset = FIELD_GET(NPC_HDR_OFFSET, cfg); 253 253 + byte_len = FIELD_GET(NPC_BYTESM, cfg); 254 254 + /* Hashing of IPv6 source/destination address should be 255 255 + * enabled if, 256 256 + * hdr_offset == 8 (offset of source IPv6 address) or 257 257 + * hdr_offset == 24 (offset of destination IPv6) 258 258 + * address) and the number of byte to be 259 259 + * extracted is 4. As per hardware configuration 260 260 + * byte_len should be == actual byte_len - 1. 261 261 + * Hence byte_len is checked against 3 but nor 4. 262 262 + */ 263 263 + if ((hdr_offset == 8 || hdr_offset == 24) && byte_len == 3) 264 264 + mh->lid_lt_ld_hash_en[intf][NPC_LID_LC][NPC_LT_LC_IP6][ld] = true; 265 265 + } 266 266 + } 267 267 + 268 268 + /* Update hash configuration if the field is hash enabled */ 228 269 for (intf = 0; intf < hw->npc_intfs; intf++) { 229 270 npc_program_mkex_hash_rx(rvu, blkaddr, intf); 230 271 npc_program_mkex_hash_tx(rvu, blkaddr, intf);

+4 -4

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_hash.h

reviewed

··· 70 70 [NIX_INTF_RX] = { 71 71 [NPC_LID_LC] = { 72 72 [NPC_LT_LC_IP6] = { 73 73 - true, 74 74 - true, 73 73 + false, 74 74 + false, 75 75 }, 76 76 }, 77 77 }, ··· 79 79 [NIX_INTF_TX] = { 80 80 [NPC_LID_LC] = { 81 81 [NPC_LT_LC_IP6] = { 82 82 - true, 83 83 - true, 82 82 + false, 83 83 + false, 84 84 }, 85 85 }, 86 86 },

+3 -1

drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c

reviewed

··· 243 243 void stmmac_dwmac4_set_mac(void __iomem *ioaddr, bool enable) 244 244 { 245 245 u32 value = readl(ioaddr + GMAC_CONFIG); 246 246 + u32 old_val = value; 246 247 247 248 if (enable) 248 249 value |= GMAC_CONFIG_RE | GMAC_CONFIG_TE; 249 250 else 250 251 value &= ~(GMAC_CONFIG_TE | GMAC_CONFIG_RE); 251 252 252 252 - writel(value, ioaddr + GMAC_CONFIG); 253 253 + if (value != old_val) 254 254 + writel(value, ioaddr + GMAC_CONFIG); 253 255 } 254 256 255 257 void stmmac_dwmac4_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,

+12 -10

drivers/net/ipa/ipa_table.c

reviewed

··· 273 273 if (ret) 274 274 return ret; 275 275 276 276 + ret = ipa_filter_reset_table(ipa, false, true, modem); 277 277 + if (ret || !ipa_table_hash_support(ipa)) 278 278 + return ret; 279 279 + 276 280 ret = ipa_filter_reset_table(ipa, true, false, modem); 277 281 if (ret) 278 282 return ret; 279 283 280 280 - ret = ipa_filter_reset_table(ipa, false, true, modem); 281 281 - if (ret) 282 282 - return ret; 283 283 - ret = ipa_filter_reset_table(ipa, true, true, modem); 284 284 - 285 285 - return ret; 284 284 + return ipa_filter_reset_table(ipa, true, true, modem); 286 285 } 287 286 288 287 /* The AP routes and modem routes are each contiguous within the ··· 290 291 * */ 291 292 static int ipa_route_reset(struct ipa *ipa, bool modem) 292 293 { 294 294 + bool hash_support = ipa_table_hash_support(ipa); 293 295 u32 modem_route_count = ipa->modem_route_count; 294 296 struct gsi_trans *trans; 295 297 u16 first; 296 298 u16 count; 297 299 298 298 - trans = ipa_cmd_trans_alloc(ipa, 4); 300 300 + trans = ipa_cmd_trans_alloc(ipa, hash_support ? 4 : 2); 299 301 if (!trans) { 300 302 dev_err(&ipa->pdev->dev, 301 303 "no transaction for %s route reset\n", ··· 313 313 } 314 314 315 315 ipa_table_reset_add(trans, false, false, false, first, count); 316 316 - ipa_table_reset_add(trans, false, true, false, first, count); 317 317 - 318 316 ipa_table_reset_add(trans, false, false, true, first, count); 319 319 - ipa_table_reset_add(trans, false, true, true, first, count); 317 317 + 318 318 + if (hash_support) { 319 319 + ipa_table_reset_add(trans, false, true, false, first, count); 320 320 + ipa_table_reset_add(trans, false, true, true, first, count); 321 321 + } 320 322 321 323 gsi_trans_commit_wait(trans); 322 324

+1

drivers/net/macvlan.c

reviewed

··· 1746 1746 [IFLA_MACVLAN_MACADDR_COUNT] = { .type = NLA_U32 }, 1747 1747 [IFLA_MACVLAN_BC_QUEUE_LEN] = { .type = NLA_U32 }, 1748 1748 [IFLA_MACVLAN_BC_QUEUE_LEN_USED] = { .type = NLA_REJECT }, 1749 1749 + [IFLA_MACVLAN_BC_CUTOFF] = { .type = NLA_S32 }, 1749 1750 }; 1750 1751 1751 1752 int macvlan_link_register(struct rtnl_link_ops *ops)

+7

drivers/net/phy/marvell10g.c

reviewed

··· 328 328 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, 329 329 MV_V2_PORT_CTRL_PWRDOWN); 330 330 331 331 + /* Sometimes, the power down bit doesn't clear immediately, and 332 332 + * a read of this register causes the bit not to clear. Delay 333 333 + * 100us to allow the PHY to come out of power down mode before 334 334 + * the next access. 335 335 + */ 336 336 + udelay(100); 337 337 + 331 338 if (phydev->drv->phy_id != MARVELL_PHY_ID_88X3310 || 332 339 priv->firmware_ver < 0x00030000) 333 340 return ret;

+9

drivers/net/team/team.c

reviewed

··· 2135 2135 dev->mtu = port_dev->mtu; 2136 2136 memcpy(dev->broadcast, port_dev->broadcast, port_dev->addr_len); 2137 2137 eth_hw_addr_inherit(dev, port_dev); 2138 2138 + 2139 2139 + if (port_dev->flags & IFF_POINTOPOINT) { 2140 2140 + dev->flags &= ~(IFF_BROADCAST | IFF_MULTICAST); 2141 2141 + dev->flags |= (IFF_POINTOPOINT | IFF_NOARP); 2142 2142 + } else if ((port_dev->flags & (IFF_BROADCAST | IFF_MULTICAST)) == 2143 2143 + (IFF_BROADCAST | IFF_MULTICAST)) { 2144 2144 + dev->flags |= (IFF_BROADCAST | IFF_MULTICAST); 2145 2145 + dev->flags &= ~(IFF_POINTOPOINT | IFF_NOARP); 2146 2146 + } 2138 2147 } 2139 2148 2140 2149 static int team_dev_type_check_change(struct net_device *dev,

+2 -2

drivers/net/virtio_net.c

reviewed

··· 4219 4219 if (vi->has_rss || vi->has_rss_hash_report) 4220 4220 virtnet_init_default_rss(vi); 4221 4221 4222 4222 + _virtnet_set_queues(vi, vi->curr_queue_pairs); 4223 4223 + 4222 4224 /* serialize netdev register + virtio_device_ready() with ndo_open() */ 4223 4225 rtnl_lock(); 4224 4226 ··· 4258 4256 pr_debug("virtio_net: registering cpu notifier failed\n"); 4259 4257 goto free_unregister_netdev; 4260 4258 } 4261 4261 - 4262 4262 - virtnet_set_queues(vi, vi->curr_queue_pairs); 4263 4259 4264 4260 /* Assume link up if device can't report link status, 4265 4261 otherwise get link status from config. */

+107 -58

drivers/net/vxlan/vxlan_core.c

reviewed

··· 623 623 return 1; 624 624 } 625 625 626 626 + static bool vxlan_parse_gpe_proto(struct vxlanhdr *hdr, __be16 *protocol) 627 627 + { 628 628 + struct vxlanhdr_gpe *gpe = (struct vxlanhdr_gpe *)hdr; 629 629 + 630 630 + /* Need to have Next Protocol set for interfaces in GPE mode. */ 631 631 + if (!gpe->np_applied) 632 632 + return false; 633 633 + /* "The initial version is 0. If a receiver does not support the 634 634 + * version indicated it MUST drop the packet. 635 635 + */ 636 636 + if (gpe->version != 0) 637 637 + return false; 638 638 + /* "When the O bit is set to 1, the packet is an OAM packet and OAM 639 639 + * processing MUST occur." However, we don't implement OAM 640 640 + * processing, thus drop the packet. 641 641 + */ 642 642 + if (gpe->oam_flag) 643 643 + return false; 644 644 + 645 645 + *protocol = tun_p_to_eth_p(gpe->next_protocol); 646 646 + if (!*protocol) 647 647 + return false; 648 648 + 649 649 + return true; 650 650 + } 651 651 + 626 652 static struct vxlanhdr *vxlan_gro_remcsum(struct sk_buff *skb, 627 653 unsigned int off, 628 654 struct vxlanhdr *vh, size_t hdrlen, ··· 675 649 return vh; 676 650 } 677 651 678 678 - static struct sk_buff *vxlan_gro_receive(struct sock *sk, 679 679 - struct list_head *head, 680 680 - struct sk_buff *skb) 652 652 + static struct vxlanhdr *vxlan_gro_prepare_receive(struct sock *sk, 653 653 + struct list_head *head, 654 654 + struct sk_buff *skb, 655 655 + struct gro_remcsum *grc) 681 656 { 682 682 - struct sk_buff *pp = NULL; 683 657 struct sk_buff *p; 684 658 struct vxlanhdr *vh, *vh2; 685 659 unsigned int hlen, off_vx; 686 686 - int flush = 1; 687 660 struct vxlan_sock *vs = rcu_dereference_sk_user_data(sk); 688 661 __be32 flags; 689 689 - struct gro_remcsum grc; 690 662 691 691 - skb_gro_remcsum_init(&grc); 663 663 + skb_gro_remcsum_init(grc); 692 664 693 665 off_vx = skb_gro_offset(skb); 694 666 hlen = off_vx + sizeof(*vh); 695 667 vh = skb_gro_header(skb, hlen, off_vx); 696 668 if (unlikely(!vh)) 697 697 - goto out; 669 669 + return NULL; 698 670 699 671 skb_gro_postpull_rcsum(skb, vh, sizeof(struct vxlanhdr)); 700 672 ··· 700 676 701 677 if ((flags & VXLAN_HF_RCO) && (vs->flags & VXLAN_F_REMCSUM_RX)) { 702 678 vh = vxlan_gro_remcsum(skb, off_vx, vh, sizeof(struct vxlanhdr), 703 703 - vh->vx_vni, &grc, 679 679 + vh->vx_vni, grc, 704 680 !!(vs->flags & 705 681 VXLAN_F_REMCSUM_NOPARTIAL)); 706 682 707 683 if (!vh) 708 708 - goto out; 684 684 + return NULL; 709 685 } 710 686 711 687 skb_gro_pull(skb, sizeof(struct vxlanhdr)); /* pull vxlan header */ ··· 722 698 } 723 699 } 724 700 725 725 - pp = call_gro_receive(eth_gro_receive, head, skb); 726 726 - flush = 0; 701 701 + return vh; 702 702 + } 727 703 704 704 + static struct sk_buff *vxlan_gro_receive(struct sock *sk, 705 705 + struct list_head *head, 706 706 + struct sk_buff *skb) 707 707 + { 708 708 + struct sk_buff *pp = NULL; 709 709 + struct gro_remcsum grc; 710 710 + int flush = 1; 711 711 + 712 712 + if (vxlan_gro_prepare_receive(sk, head, skb, &grc)) { 713 713 + pp = call_gro_receive(eth_gro_receive, head, skb); 714 714 + flush = 0; 715 715 + } 716 716 + skb_gro_flush_final_remcsum(skb, pp, flush, &grc); 717 717 + return pp; 718 718 + } 719 719 + 720 720 + static struct sk_buff *vxlan_gpe_gro_receive(struct sock *sk, 721 721 + struct list_head *head, 722 722 + struct sk_buff *skb) 723 723 + { 724 724 + const struct packet_offload *ptype; 725 725 + struct sk_buff *pp = NULL; 726 726 + struct gro_remcsum grc; 727 727 + struct vxlanhdr *vh; 728 728 + __be16 protocol; 729 729 + int flush = 1; 730 730 + 731 731 + vh = vxlan_gro_prepare_receive(sk, head, skb, &grc); 732 732 + if (vh) { 733 733 + if (!vxlan_parse_gpe_proto(vh, &protocol)) 734 734 + goto out; 735 735 + ptype = gro_find_receive_by_type(protocol); 736 736 + if (!ptype) 737 737 + goto out; 738 738 + pp = call_gro_receive(ptype->callbacks.gro_receive, head, skb); 739 739 + flush = 0; 740 740 + } 728 741 out: 729 742 skb_gro_flush_final_remcsum(skb, pp, flush, &grc); 730 730 - 731 743 return pp; 732 744 } 733 745 ··· 773 713 * 'skb->encapsulation' set. 774 714 */ 775 715 return eth_gro_complete(skb, nhoff + sizeof(struct vxlanhdr)); 716 716 + } 717 717 + 718 718 + static int vxlan_gpe_gro_complete(struct sock *sk, struct sk_buff *skb, int nhoff) 719 719 + { 720 720 + struct vxlanhdr *vh = (struct vxlanhdr *)(skb->data + nhoff); 721 721 + const struct packet_offload *ptype; 722 722 + int err = -ENOSYS; 723 723 + __be16 protocol; 724 724 + 725 725 + if (!vxlan_parse_gpe_proto(vh, &protocol)) 726 726 + return err; 727 727 + ptype = gro_find_complete_by_type(protocol); 728 728 + if (ptype) 729 729 + err = ptype->callbacks.gro_complete(skb, nhoff + sizeof(struct vxlanhdr)); 730 730 + return err; 776 731 } 777 732 778 733 static struct vxlan_fdb *vxlan_fdb_alloc(struct vxlan_dev *vxlan, const u8 *mac, ··· 1600 1525 unparsed->vx_flags &= ~VXLAN_GBP_USED_BITS; 1601 1526 } 1602 1527 1603 1603 - static bool vxlan_parse_gpe_hdr(struct vxlanhdr *unparsed, 1604 1604 - __be16 *protocol, 1605 1605 - struct sk_buff *skb, u32 vxflags) 1606 1606 - { 1607 1607 - struct vxlanhdr_gpe *gpe = (struct vxlanhdr_gpe *)unparsed; 1608 1608 - 1609 1609 - /* Need to have Next Protocol set for interfaces in GPE mode. */ 1610 1610 - if (!gpe->np_applied) 1611 1611 - return false; 1612 1612 - /* "The initial version is 0. If a receiver does not support the 1613 1613 - * version indicated it MUST drop the packet. 1614 1614 - */ 1615 1615 - if (gpe->version != 0) 1616 1616 - return false; 1617 1617 - /* "When the O bit is set to 1, the packet is an OAM packet and OAM 1618 1618 - * processing MUST occur." However, we don't implement OAM 1619 1619 - * processing, thus drop the packet. 1620 1620 - */ 1621 1621 - if (gpe->oam_flag) 1622 1622 - return false; 1623 1623 - 1624 1624 - *protocol = tun_p_to_eth_p(gpe->next_protocol); 1625 1625 - if (!*protocol) 1626 1626 - return false; 1627 1627 - 1628 1628 - unparsed->vx_flags &= ~VXLAN_GPE_USED_BITS; 1629 1629 - return true; 1630 1630 - } 1631 1631 - 1632 1528 static bool vxlan_set_mac(struct vxlan_dev *vxlan, 1633 1529 struct vxlan_sock *vs, 1634 1530 struct sk_buff *skb, __be32 vni) ··· 1701 1655 * used by VXLAN extensions if explicitly requested. 1702 1656 */ 1703 1657 if (vs->flags & VXLAN_F_GPE) { 1704 1704 - if (!vxlan_parse_gpe_hdr(&unparsed, &protocol, skb, vs->flags)) 1658 1658 + if (!vxlan_parse_gpe_proto(&unparsed, &protocol)) 1705 1659 goto drop; 1660 1660 + unparsed.vx_flags &= ~VXLAN_GPE_USED_BITS; 1706 1661 raw_proto = true; 1707 1662 } 1708 1663 ··· 2563 2516 } 2564 2517 2565 2518 ndst = &rt->dst; 2566 2566 - err = skb_tunnel_check_pmtu(skb, ndst, VXLAN_HEADROOM, 2519 2519 + err = skb_tunnel_check_pmtu(skb, ndst, vxlan_headroom(flags & VXLAN_F_GPE), 2567 2520 netif_is_any_bridge_port(dev)); 2568 2521 if (err < 0) { 2569 2522 goto tx_error; ··· 2624 2577 goto out_unlock; 2625 2578 } 2626 2579 2627 2627 - err = skb_tunnel_check_pmtu(skb, ndst, VXLAN6_HEADROOM, 2580 2580 + err = skb_tunnel_check_pmtu(skb, ndst, 2581 2581 + vxlan_headroom((flags & VXLAN_F_GPE) | VXLAN_F_IPV6), 2628 2582 netif_is_any_bridge_port(dev)); 2629 2583 if (err < 0) { 2630 2584 goto tx_error; ··· 3081 3033 struct vxlan_rdst *dst = &vxlan->default_dst; 3082 3034 struct net_device *lowerdev = __dev_get_by_index(vxlan->net, 3083 3035 dst->remote_ifindex); 3084 3084 - bool use_ipv6 = !!(vxlan->cfg.flags & VXLAN_F_IPV6); 3085 3036 3086 3037 /* This check is different than dev->max_mtu, because it looks at 3087 3038 * the lowerdev->mtu, rather than the static dev->max_mtu 3088 3039 */ 3089 3040 if (lowerdev) { 3090 3090 - int max_mtu = lowerdev->mtu - 3091 3091 - (use_ipv6 ? VXLAN6_HEADROOM : VXLAN_HEADROOM); 3041 3041 + int max_mtu = lowerdev->mtu - vxlan_headroom(vxlan->cfg.flags); 3092 3042 if (new_mtu > max_mtu) 3093 3043 return -EINVAL; 3094 3044 } ··· 3469 3423 tunnel_cfg.encap_rcv = vxlan_rcv; 3470 3424 tunnel_cfg.encap_err_lookup = vxlan_err_lookup; 3471 3425 tunnel_cfg.encap_destroy = NULL; 3472 3472 - tunnel_cfg.gro_receive = vxlan_gro_receive; 3473 3473 - tunnel_cfg.gro_complete = vxlan_gro_complete; 3426 3426 + if (vs->flags & VXLAN_F_GPE) { 3427 3427 + tunnel_cfg.gro_receive = vxlan_gpe_gro_receive; 3428 3428 + tunnel_cfg.gro_complete = vxlan_gpe_gro_complete; 3429 3429 + } else { 3430 3430 + tunnel_cfg.gro_receive = vxlan_gro_receive; 3431 3431 + tunnel_cfg.gro_complete = vxlan_gro_complete; 3432 3432 + } 3474 3433 3475 3434 setup_udp_tunnel_sock(net, sock, &tunnel_cfg); 3476 3435 ··· 3739 3688 struct vxlan_dev *vxlan = netdev_priv(dev); 3740 3689 struct vxlan_rdst *dst = &vxlan->default_dst; 3741 3690 unsigned short needed_headroom = ETH_HLEN; 3742 3742 - bool use_ipv6 = !!(conf->flags & VXLAN_F_IPV6); 3743 3691 int max_mtu = ETH_MAX_MTU; 3692 3692 + u32 flags = conf->flags; 3744 3693 3745 3694 if (!changelink) { 3746 3746 - if (conf->flags & VXLAN_F_GPE) 3695 3695 + if (flags & VXLAN_F_GPE) 3747 3696 vxlan_raw_setup(dev); 3748 3697 else 3749 3698 vxlan_ether_setup(dev); ··· 3768 3717 3769 3718 dev->needed_tailroom = lowerdev->needed_tailroom; 3770 3719 3771 3771 - max_mtu = lowerdev->mtu - (use_ipv6 ? VXLAN6_HEADROOM : 3772 3772 - VXLAN_HEADROOM); 3720 3720 + max_mtu = lowerdev->mtu - vxlan_headroom(flags); 3773 3721 if (max_mtu < ETH_MIN_MTU) 3774 3722 max_mtu = ETH_MIN_MTU; 3775 3723 ··· 3779 3729 if (dev->mtu > max_mtu) 3780 3730 dev->mtu = max_mtu; 3781 3731 3782 3782 - if (use_ipv6 || conf->flags & VXLAN_F_COLLECT_METADATA) 3783 3783 - needed_headroom += VXLAN6_HEADROOM; 3784 3784 - else 3785 3785 - needed_headroom += VXLAN_HEADROOM; 3732 3732 + if (flags & VXLAN_F_COLLECT_METADATA) 3733 3733 + flags |= VXLAN_F_IPV6; 3734 3734 + needed_headroom += vxlan_headroom(flags); 3786 3735 dev->needed_headroom = needed_headroom; 3787 3736 3788 3737 memcpy(&vxlan->cfg, conf, sizeof(*conf));

+1 -1

drivers/of/Kconfig

reviewed

··· 55 55 56 56 config OF_EARLY_FLATTREE 57 57 bool 58 58 - select DMA_DECLARE_COHERENT if HAS_DMA 58 58 + select DMA_DECLARE_COHERENT if HAS_DMA && HAS_IOMEM 59 59 select OF_FLATTREE 60 60 61 61 config OF_PROMTREE

+1 -1

drivers/of/platform.c

reviewed

··· 552 552 if (!of_get_property(node, "linux,opened", NULL) || 553 553 !of_get_property(node, "linux,boot-display", NULL)) 554 554 continue; 555 555 - dev = of_platform_device_create(node, "of-display.0", NULL); 555 555 + dev = of_platform_device_create(node, "of-display", NULL); 556 556 of_node_put(node); 557 557 if (WARN_ON(!dev)) 558 558 return -ENOMEM;

+1 -1

drivers/phy/hisilicon/phy-hisi-inno-usb2.c

reviewed

··· 184 184 phy_set_drvdata(phy, &priv->ports[i]); 185 185 i++; 186 186 187 187 - if (i > INNO_PHY_PORT_NUM) { 187 187 + if (i >= INNO_PHY_PORT_NUM) { 188 188 dev_warn(dev, "Support %d ports in maximum\n", i); 189 189 of_node_put(child); 190 190 break;

+1 -1

drivers/phy/mediatek/phy-mtk-dp.c

reviewed

··· 169 169 170 170 regs = *(struct regmap **)dev->platform_data; 171 171 if (!regs) 172 172 - return dev_err_probe(dev, EINVAL, 172 172 + return dev_err_probe(dev, -EINVAL, 173 173 "No data passed, requires struct regmap**\n"); 174 174 175 175 dp_phy = devm_kzalloc(dev, sizeof(*dp_phy), GFP_KERNEL);

+1 -1

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c

reviewed

··· 253 253 for (i = 0; i < ARRAY_SIZE(txpredivs); i++) { 254 254 ns_hdmipll_ck = 5 * tmds_clk * txposdiv * txpredivs[i]; 255 255 if (ns_hdmipll_ck >= 5 * GIGA && 256 256 - ns_hdmipll_ck <= 1 * GIGA) 256 256 + ns_hdmipll_ck <= 12 * GIGA) 257 257 break; 258 258 } 259 259 if (i == (ARRAY_SIZE(txpredivs) - 1) &&

+50 -28

drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c

reviewed

··· 110 110 /** 111 111 * struct qcom_snps_hsphy - snps hs phy attributes 112 112 * 113 113 + * @dev: device structure 114 114 + * 113 115 * @phy: generic phy 114 116 * @base: iomapped memory space for snps hs phy 115 117 * 116 116 - * @cfg_ahb_clk: AHB2PHY interface clock 117 117 - * @ref_clk: phy reference clock 118 118 + * @num_clks: number of clocks 119 119 + * @clks: array of clocks 118 120 * @phy_reset: phy reset control 119 121 * @vregs: regulator supplies bulk data 120 122 * @phy_initialized: if PHY has been initialized correctly ··· 124 122 * @update_seq_cfg: tuning parameters for phy init 125 123 */ 126 124 struct qcom_snps_hsphy { 125 125 + struct device *dev; 126 126 + 127 127 struct phy *phy; 128 128 void __iomem *base; 129 129 130 130 - struct clk *cfg_ahb_clk; 131 131 - struct clk *ref_clk; 130 130 + int num_clks; 131 131 + struct clk_bulk_data *clks; 132 132 struct reset_control *phy_reset; 133 133 struct regulator_bulk_data vregs[SNPS_HS_NUM_VREGS]; 134 134 ··· 138 134 enum phy_mode mode; 139 135 struct phy_override_seq update_seq_cfg[NUM_HSPHY_TUNING_PARAMS]; 140 136 }; 137 137 + 138 138 + static int qcom_snps_hsphy_clk_init(struct qcom_snps_hsphy *hsphy) 139 139 + { 140 140 + struct device *dev = hsphy->dev; 141 141 + 142 142 + hsphy->num_clks = 2; 143 143 + hsphy->clks = devm_kcalloc(dev, hsphy->num_clks, sizeof(*hsphy->clks), GFP_KERNEL); 144 144 + if (!hsphy->clks) 145 145 + return -ENOMEM; 146 146 + 147 147 + /* 148 148 + * TODO: Currently no device tree instantiation of the PHY is using the clock. 149 149 + * This needs to be fixed in order for this code to be able to use devm_clk_bulk_get(). 150 150 + */ 151 151 + hsphy->clks[0].id = "cfg_ahb"; 152 152 + hsphy->clks[0].clk = devm_clk_get_optional(dev, "cfg_ahb"); 153 153 + if (IS_ERR(hsphy->clks[0].clk)) 154 154 + return dev_err_probe(dev, PTR_ERR(hsphy->clks[0].clk), 155 155 + "failed to get cfg_ahb clk\n"); 156 156 + 157 157 + hsphy->clks[1].id = "ref"; 158 158 + hsphy->clks[1].clk = devm_clk_get(dev, "ref"); 159 159 + if (IS_ERR(hsphy->clks[1].clk)) 160 160 + return dev_err_probe(dev, PTR_ERR(hsphy->clks[1].clk), 161 161 + "failed to get ref clk\n"); 162 162 + 163 163 + return 0; 164 164 + } 141 165 142 166 static inline void qcom_snps_hsphy_write_mask(void __iomem *base, u32 offset, 143 167 u32 mask, u32 val) ··· 197 165 0, USB2_AUTO_RESUME); 198 166 } 199 167 200 200 - clk_disable_unprepare(hsphy->cfg_ahb_clk); 201 168 return 0; 202 169 } 203 170 204 171 static int qcom_snps_hsphy_resume(struct qcom_snps_hsphy *hsphy) 205 172 { 206 206 - int ret; 207 207 - 208 173 dev_dbg(&hsphy->phy->dev, "Resume QCOM SNPS PHY, mode\n"); 209 209 - 210 210 - ret = clk_prepare_enable(hsphy->cfg_ahb_clk); 211 211 - if (ret) { 212 212 - dev_err(&hsphy->phy->dev, "failed to enable cfg ahb clock\n"); 213 213 - return ret; 214 214 - } 215 174 216 175 return 0; 217 176 } ··· 214 191 if (!hsphy->phy_initialized) 215 192 return 0; 216 193 217 217 - qcom_snps_hsphy_suspend(hsphy); 218 218 - return 0; 194 194 + return qcom_snps_hsphy_suspend(hsphy); 219 195 } 220 196 221 197 static int __maybe_unused qcom_snps_hsphy_runtime_resume(struct device *dev) ··· 224 202 if (!hsphy->phy_initialized) 225 203 return 0; 226 204 227 227 - qcom_snps_hsphy_resume(hsphy); 228 228 - return 0; 205 205 + return qcom_snps_hsphy_resume(hsphy); 229 206 } 230 207 231 208 static int qcom_snps_hsphy_set_mode(struct phy *phy, enum phy_mode mode, ··· 395 374 if (ret) 396 375 return ret; 397 376 398 398 - ret = clk_prepare_enable(hsphy->cfg_ahb_clk); 377 377 + ret = clk_bulk_prepare_enable(hsphy->num_clks, hsphy->clks); 399 378 if (ret) { 400 400 - dev_err(&phy->dev, "failed to enable cfg ahb clock, %d\n", ret); 379 379 + dev_err(&phy->dev, "failed to enable clocks, %d\n", ret); 401 380 goto poweroff_phy; 402 381 } 403 382 404 383 ret = reset_control_assert(hsphy->phy_reset); 405 384 if (ret) { 406 385 dev_err(&phy->dev, "failed to assert phy_reset, %d\n", ret); 407 407 - goto disable_ahb_clk; 386 386 + goto disable_clks; 408 387 } 409 388 410 389 usleep_range(100, 150); ··· 412 391 ret = reset_control_deassert(hsphy->phy_reset); 413 392 if (ret) { 414 393 dev_err(&phy->dev, "failed to de-assert phy_reset, %d\n", ret); 415 415 - goto disable_ahb_clk; 394 394 + goto disable_clks; 416 395 } 417 396 418 397 qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_CFG0, ··· 469 448 470 449 return 0; 471 450 472 472 - disable_ahb_clk: 473 473 - clk_disable_unprepare(hsphy->cfg_ahb_clk); 451 451 + disable_clks: 452 452 + clk_bulk_disable_unprepare(hsphy->num_clks, hsphy->clks); 474 453 poweroff_phy: 475 454 regulator_bulk_disable(ARRAY_SIZE(hsphy->vregs), hsphy->vregs); 476 455 ··· 482 461 struct qcom_snps_hsphy *hsphy = phy_get_drvdata(phy); 483 462 484 463 reset_control_assert(hsphy->phy_reset); 485 485 - clk_disable_unprepare(hsphy->cfg_ahb_clk); 464 464 + clk_bulk_disable_unprepare(hsphy->num_clks, hsphy->clks); 486 465 regulator_bulk_disable(ARRAY_SIZE(hsphy->vregs), hsphy->vregs); 487 466 hsphy->phy_initialized = false; 488 467 ··· 575 554 if (!hsphy) 576 555 return -ENOMEM; 577 556 557 557 + hsphy->dev = dev; 558 558 + 578 559 hsphy->base = devm_platform_ioremap_resource(pdev, 0); 579 560 if (IS_ERR(hsphy->base)) 580 561 return PTR_ERR(hsphy->base); 581 562 582 582 - hsphy->ref_clk = devm_clk_get(dev, "ref"); 583 583 - if (IS_ERR(hsphy->ref_clk)) 584 584 - return dev_err_probe(dev, PTR_ERR(hsphy->ref_clk), 585 585 - "failed to get ref clk\n"); 563 563 + ret = qcom_snps_hsphy_clk_init(hsphy); 564 564 + if (ret) 565 565 + return dev_err_probe(dev, ret, "failed to initialize clocks\n"); 586 566 587 567 hsphy->phy_reset = devm_reset_control_get_exclusive(&pdev->dev, NULL); 588 568 if (IS_ERR(hsphy->phy_reset)) {

+2 -6

drivers/platform/x86/amd/pmc-quirks.c

reviewed

··· 11 11 #include <linux/dmi.h> 12 12 #include <linux/io.h> 13 13 #include <linux/ioport.h> 14 14 - #include <linux/slab.h> 15 14 16 15 #include "pmc.h" 17 16 ··· 134 135 */ 135 136 static void amd_pmc_skip_nvme_smi_handler(u32 s2idle_bug_mmio) 136 137 { 137 137 - struct resource *res; 138 138 void __iomem *addr; 139 139 u8 val; 140 140 141 141 - res = request_mem_region_muxed(s2idle_bug_mmio, 1, "amd_pmc_pm80"); 142 142 - if (!res) 141 141 + if (!request_mem_region_muxed(s2idle_bug_mmio, 1, "amd_pmc_pm80")) 143 142 return; 144 143 145 144 addr = ioremap(s2idle_bug_mmio, 1); ··· 149 152 150 153 iounmap(addr); 151 154 cleanup_resource: 152 152 - release_resource(res); 153 153 - kfree(res); 155 155 + release_mem_region(s2idle_bug_mmio, 1); 154 156 } 155 157 156 158 void amd_pmc_process_restore_quirks(struct amd_pmc_dev *dev)

+22 -1

drivers/platform/x86/amd/pmf/acpi.c

reviewed

··· 106 106 data, sizeof(*data)); 107 107 } 108 108 109 109 + int apmf_os_power_slider_update(struct amd_pmf_dev *pdev, u8 event) 110 110 + { 111 111 + struct os_power_slider args; 112 112 + struct acpi_buffer params; 113 113 + union acpi_object *info; 114 114 + int err = 0; 115 115 + 116 116 + args.size = sizeof(args); 117 117 + args.slider_event = event; 118 118 + 119 119 + params.length = sizeof(args); 120 120 + params.pointer = (void *)&args; 121 121 + 122 122 + info = apmf_if_call(pdev, APMF_FUNC_OS_POWER_SLIDER_UPDATE, &params); 123 123 + if (!info) 124 124 + err = -EIO; 125 125 + 126 126 + kfree(info); 127 127 + return err; 128 128 + } 129 129 + 109 130 static void apmf_sbios_heartbeat_notify(struct work_struct *work) 110 131 { 111 132 struct amd_pmf_dev *dev = container_of(work, struct amd_pmf_dev, heart_beat.work); ··· 310 289 311 290 ret = apmf_get_system_params(pmf_dev); 312 291 if (ret) { 313 313 - dev_err(pmf_dev->dev, "APMF apmf_get_system_params failed :%d\n", ret); 292 292 + dev_dbg(pmf_dev->dev, "APMF apmf_get_system_params failed :%d\n", ret); 314 293 goto out; 315 294 } 316 295

+7 -2

drivers/platform/x86/amd/pmf/core.c

reviewed

··· 72 72 return NOTIFY_DONE; 73 73 } 74 74 75 75 - amd_pmf_set_sps_power_limits(pmf); 75 75 + if (is_apmf_func_supported(pmf, APMF_FUNC_STATIC_SLIDER_GRANULAR)) 76 76 + amd_pmf_set_sps_power_limits(pmf); 77 77 + 78 78 + if (is_apmf_func_supported(pmf, APMF_FUNC_OS_POWER_SLIDER_UPDATE)) 79 79 + amd_pmf_power_slider_update_event(pmf); 76 80 77 81 return NOTIFY_OK; 78 82 } ··· 301 297 int ret; 302 298 303 299 /* Enable Static Slider */ 304 304 - if (is_apmf_func_supported(dev, APMF_FUNC_STATIC_SLIDER_GRANULAR)) { 300 300 + if (is_apmf_func_supported(dev, APMF_FUNC_STATIC_SLIDER_GRANULAR) || 301 301 + is_apmf_func_supported(dev, APMF_FUNC_OS_POWER_SLIDER_UPDATE)) { 305 302 amd_pmf_init_sps(dev); 306 303 dev->pwr_src_notifier.notifier_call = amd_pmf_pwr_src_notify_call; 307 304 power_supply_reg_notifier(&dev->pwr_src_notifier);

+16

drivers/platform/x86/amd/pmf/pmf.h

reviewed

··· 21 21 #define APMF_FUNC_SBIOS_HEARTBEAT 4 22 22 #define APMF_FUNC_AUTO_MODE 5 23 23 #define APMF_FUNC_SET_FAN_IDX 7 24 24 + #define APMF_FUNC_OS_POWER_SLIDER_UPDATE 8 24 25 #define APMF_FUNC_STATIC_SLIDER_GRANULAR 9 25 26 #define APMF_FUNC_DYN_SLIDER_AC 11 26 27 #define APMF_FUNC_DYN_SLIDER_DC 12 ··· 44 43 #define GET_STT_MIN_LIMIT 0x1F 45 44 #define GET_STT_LIMIT_APU 0x20 46 45 #define GET_STT_LIMIT_HS2 0x21 46 46 + 47 47 + /* OS slider update notification */ 48 48 + #define DC_BEST_PERF 0 49 49 + #define DC_BETTER_PERF 1 50 50 + #define DC_BATTERY_SAVER 3 51 51 + #define AC_BEST_PERF 4 52 52 + #define AC_BETTER_PERF 5 53 53 + #define AC_BETTER_BATTERY 6 47 54 48 55 /* Fan Index for Auto Mode */ 49 56 #define FAN_INDEX_AUTO 0xFFFFFFFF ··· 201 192 u16 size; 202 193 struct apmf_sps_prop_granular prop[POWER_SOURCE_MAX][POWER_MODE_MAX]; 203 194 }; 195 195 + 196 196 + struct os_power_slider { 197 197 + u16 size; 198 198 + u8 slider_event; 199 199 + } __packed; 204 200 205 201 struct fan_table_control { 206 202 bool manual; ··· 397 383 int amd_pmf_init_metrics_table(struct amd_pmf_dev *dev); 398 384 int amd_pmf_get_power_source(void); 399 385 int apmf_install_handler(struct amd_pmf_dev *pmf_dev); 386 386 + int apmf_os_power_slider_update(struct amd_pmf_dev *dev, u8 flag); 400 387 401 388 /* SPS Layer */ 402 389 int amd_pmf_get_pprof_modes(struct amd_pmf_dev *pmf); ··· 408 393 int apmf_get_static_slider_granular(struct amd_pmf_dev *pdev, 409 394 struct apmf_static_slider_granular_output *output); 410 395 bool is_pprof_balanced(struct amd_pmf_dev *pmf); 396 396 + int amd_pmf_power_slider_update_event(struct amd_pmf_dev *dev); 411 397 412 398 413 399 int apmf_update_fan_idx(struct amd_pmf_dev *pdev, bool manual, u32 idx);

+70 -4

drivers/platform/x86/amd/pmf/sps.c

reviewed

··· 174 174 return mode; 175 175 } 176 176 177 177 + int amd_pmf_power_slider_update_event(struct amd_pmf_dev *dev) 178 178 + { 179 179 + u8 mode, flag = 0; 180 180 + int src; 181 181 + 182 182 + mode = amd_pmf_get_pprof_modes(dev); 183 183 + if (mode < 0) 184 184 + return mode; 185 185 + 186 186 + src = amd_pmf_get_power_source(); 187 187 + 188 188 + if (src == POWER_SOURCE_AC) { 189 189 + switch (mode) { 190 190 + case POWER_MODE_PERFORMANCE: 191 191 + flag |= BIT(AC_BEST_PERF); 192 192 + break; 193 193 + case POWER_MODE_BALANCED_POWER: 194 194 + flag |= BIT(AC_BETTER_PERF); 195 195 + break; 196 196 + case POWER_MODE_POWER_SAVER: 197 197 + flag |= BIT(AC_BETTER_BATTERY); 198 198 + break; 199 199 + default: 200 200 + dev_err(dev->dev, "unsupported platform profile\n"); 201 201 + return -EOPNOTSUPP; 202 202 + } 203 203 + 204 204 + } else if (src == POWER_SOURCE_DC) { 205 205 + switch (mode) { 206 206 + case POWER_MODE_PERFORMANCE: 207 207 + flag |= BIT(DC_BEST_PERF); 208 208 + break; 209 209 + case POWER_MODE_BALANCED_POWER: 210 210 + flag |= BIT(DC_BETTER_PERF); 211 211 + break; 212 212 + case POWER_MODE_POWER_SAVER: 213 213 + flag |= BIT(DC_BATTERY_SAVER); 214 214 + break; 215 215 + default: 216 216 + dev_err(dev->dev, "unsupported platform profile\n"); 217 217 + return -EOPNOTSUPP; 218 218 + } 219 219 + } 220 220 + 221 221 + apmf_os_power_slider_update(dev, flag); 222 222 + 223 223 + return 0; 224 224 + } 225 225 + 177 226 static int amd_pmf_profile_set(struct platform_profile_handler *pprof, 178 227 enum platform_profile_option profile) 179 228 { 180 229 struct amd_pmf_dev *pmf = container_of(pprof, struct amd_pmf_dev, pprof); 230 230 + int ret = 0; 181 231 182 232 pmf->current_profile = profile; 183 233 184 184 - return amd_pmf_set_sps_power_limits(pmf); 234 234 + /* Notify EC about the slider position change */ 235 235 + if (is_apmf_func_supported(pmf, APMF_FUNC_OS_POWER_SLIDER_UPDATE)) { 236 236 + ret = amd_pmf_power_slider_update_event(pmf); 237 237 + if (ret) 238 238 + return ret; 239 239 + } 240 240 + 241 241 + if (is_apmf_func_supported(pmf, APMF_FUNC_STATIC_SLIDER_GRANULAR)) { 242 242 + ret = amd_pmf_set_sps_power_limits(pmf); 243 243 + if (ret) 244 244 + return ret; 245 245 + } 246 246 + 247 247 + return 0; 185 248 } 186 249 187 250 int amd_pmf_init_sps(struct amd_pmf_dev *dev) ··· 252 189 int err; 253 190 254 191 dev->current_profile = PLATFORM_PROFILE_BALANCED; 255 255 - amd_pmf_load_defaults_sps(dev); 256 192 257 257 - /* update SPS balanced power mode thermals */ 258 258 - amd_pmf_set_sps_power_limits(dev); 193 193 + if (is_apmf_func_supported(dev, APMF_FUNC_STATIC_SLIDER_GRANULAR)) { 194 194 + amd_pmf_load_defaults_sps(dev); 195 195 + 196 196 + /* update SPS balanced power mode thermals */ 197 197 + amd_pmf_set_sps_power_limits(dev); 198 198 + } 259 199 260 200 dev->pprof.profile_get = amd_pmf_profile_get; 261 201 dev->pprof.profile_set = amd_pmf_profile_set;

+12 -2

drivers/platform/x86/asus-wmi.c

reviewed

··· 738 738 struct device_attribute *attr, 739 739 const char *buf, size_t count) 740 740 { 741 741 - u32 cmd, mode, r, g, b, speed; 741 741 + u32 cmd, mode, r, g, b, speed; 742 742 int err; 743 743 744 744 if (sscanf(buf, "%d %d %d %d %d %d", &cmd, &mode, &r, &g, &b, &speed) != 6) 745 745 return -EINVAL; 746 746 747 747 - cmd = !!cmd; 747 747 + /* B3 is set and B4 is save to BIOS */ 748 748 + switch (cmd) { 749 749 + case 0: 750 750 + cmd = 0xb3; 751 751 + break; 752 752 + case 1: 753 753 + cmd = 0xb4; 754 754 + break; 755 755 + default: 756 756 + return -EINVAL; 757 757 + } 748 758 749 759 /* These are the known usable modes across all TUF/ROG */ 750 760 if (mode >= 12 || mode == 9)

+2

drivers/platform/x86/huawei-wmi.c

reviewed

··· 85 85 { KE_IGNORE, 0x293, { KEY_KBDILLUMTOGGLE } }, 86 86 { KE_IGNORE, 0x294, { KEY_KBDILLUMUP } }, 87 87 { KE_IGNORE, 0x295, { KEY_KBDILLUMUP } }, 88 88 + // Ignore Ambient Light Sensoring 89 89 + { KE_KEY, 0x2c1, { KEY_RESERVED } }, 88 90 { KE_END, 0 } 89 91 }; 90 92

+15 -12

drivers/platform/x86/intel/hid.c

reviewed

··· 150 150 DMI_MATCH(DMI_PRODUCT_NAME, "Surface Go"), 151 151 }, 152 152 }, 153 153 + { 154 154 + .matches = { 155 155 + DMI_MATCH(DMI_SYS_VENDOR, "HP"), 156 156 + DMI_MATCH(DMI_PRODUCT_NAME, "HP Elite Dragonfly G2 Notebook PC"), 157 157 + }, 158 158 + }, 153 159 { } 154 160 }; 155 161 ··· 626 620 static int intel_hid_probe(struct platform_device *device) 627 621 { 628 622 acpi_handle handle = ACPI_HANDLE(&device->dev); 629 629 - unsigned long long mode; 623 623 + unsigned long long mode, dummy; 630 624 struct intel_hid_priv *priv; 631 625 acpi_status status; 632 626 int err; ··· 698 692 if (err) 699 693 goto err_remove_notify; 700 694 701 701 - if (priv->array) { 702 702 - unsigned long long dummy; 695 695 + intel_button_array_enable(&device->dev, true); 703 696 704 704 - intel_button_array_enable(&device->dev, true); 705 705 - 706 706 - /* Call button load method to enable HID power button */ 707 707 - if (!intel_hid_evaluate_method(handle, INTEL_HID_DSM_BTNL_FN, 708 708 - &dummy)) { 709 709 - dev_warn(&device->dev, 710 710 - "failed to enable HID power button\n"); 711 711 - } 712 712 - } 697 697 + /* 698 698 + * Call button load method to enable HID power button 699 699 + * Always do this since it activates events on some devices without 700 700 + * a button array too. 701 701 + */ 702 702 + if (!intel_hid_evaluate_method(handle, INTEL_HID_DSM_BTNL_FN, &dummy)) 703 703 + dev_warn(&device->dev, "failed to enable HID power button\n"); 713 704 714 705 device_init_wakeup(&device->dev, true); 715 706 /*

+4 -4

drivers/platform/x86/msi-laptop.c

reviewed

··· 208 208 return -EINVAL; 209 209 210 210 if (quirks->ec_read_only) 211 211 - return -EOPNOTSUPP; 211 211 + return 0; 212 212 213 213 /* read current device state */ 214 214 result = ec_read(MSI_STANDARD_EC_COMMAND_ADDRESS, &rdata); ··· 838 838 static void msi_init_rfkill(struct work_struct *ignored) 839 839 { 840 840 if (rfk_wlan) { 841 841 - rfkill_set_sw_state(rfk_wlan, !wlan_s); 841 841 + msi_rfkill_set_state(rfk_wlan, !wlan_s); 842 842 rfkill_wlan_set(NULL, !wlan_s); 843 843 } 844 844 if (rfk_bluetooth) { 845 845 - rfkill_set_sw_state(rfk_bluetooth, !bluetooth_s); 845 845 + msi_rfkill_set_state(rfk_bluetooth, !bluetooth_s); 846 846 rfkill_bluetooth_set(NULL, !bluetooth_s); 847 847 } 848 848 if (rfk_threeg) { 849 849 - rfkill_set_sw_state(rfk_threeg, !threeg_s); 849 849 + msi_rfkill_set_state(rfk_threeg, !threeg_s); 850 850 rfkill_threeg_set(NULL, !threeg_s); 851 851 } 852 852 }

+17 -4

drivers/platform/x86/serial-multi-instantiate.c

reviewed

··· 21 21 #define IRQ_RESOURCE_NONE 0 22 22 #define IRQ_RESOURCE_GPIO 1 23 23 #define IRQ_RESOURCE_APIC 2 24 24 + #define IRQ_RESOURCE_AUTO 3 24 25 25 26 enum smi_bus_type { 26 27 SMI_I2C, ··· 53 52 int ret; 54 53 55 54 switch (inst->flags & IRQ_RESOURCE_TYPE) { 55 55 + case IRQ_RESOURCE_AUTO: 56 56 + ret = acpi_dev_gpio_irq_get(adev, inst->irq_idx); 57 57 + if (ret > 0) { 58 58 + dev_dbg(&pdev->dev, "Using gpio irq\n"); 59 59 + break; 60 60 + } 61 61 + ret = platform_get_irq(pdev, inst->irq_idx); 62 62 + if (ret > 0) { 63 63 + dev_dbg(&pdev->dev, "Using platform irq\n"); 64 64 + break; 65 65 + } 66 66 + break; 56 67 case IRQ_RESOURCE_GPIO: 57 68 ret = acpi_dev_gpio_irq_get(adev, inst->irq_idx); 58 69 break; ··· 320 307 321 308 static const struct smi_node cs35l41_hda = { 322 309 .instances = { 323 323 - { "cs35l41-hda", IRQ_RESOURCE_GPIO, 0 }, 324 324 - { "cs35l41-hda", IRQ_RESOURCE_GPIO, 0 }, 325 325 - { "cs35l41-hda", IRQ_RESOURCE_GPIO, 0 }, 326 326 - { "cs35l41-hda", IRQ_RESOURCE_GPIO, 0 }, 310 310 + { "cs35l41-hda", IRQ_RESOURCE_AUTO, 0 }, 311 311 + { "cs35l41-hda", IRQ_RESOURCE_AUTO, 0 }, 312 312 + { "cs35l41-hda", IRQ_RESOURCE_AUTO, 0 }, 313 313 + { "cs35l41-hda", IRQ_RESOURCE_AUTO, 0 }, 327 314 {} 328 315 }, 329 316 .bus_type = SMI_AUTO_DETECT,

+2 -2

drivers/platform/x86/think-lmi.c

reviewed

··· 719 719 /* Format: 'Password,Signature' */ 720 720 auth_str = kasprintf(GFP_KERNEL, "%s,%s", passwd, setting->signature); 721 721 if (!auth_str) { 722 722 - kfree(passwd); 722 722 + kfree_sensitive(passwd); 723 723 return -ENOMEM; 724 724 } 725 725 ret = tlmi_simple_call(LENOVO_CERT_TO_PASSWORD_GUID, auth_str); 726 726 kfree(auth_str); 727 727 - kfree(passwd); 727 727 + kfree_sensitive(passwd); 728 728 729 729 return ret ?: count; 730 730 }

+4 -3

drivers/platform/x86/touchscreen_dmi.c

reviewed

··· 27 27 /* NOTE: Please keep all entries sorted alphabetically */ 28 28 29 29 static const struct property_entry archos_101_cesium_educ_props[] = { 30 30 - PROPERTY_ENTRY_U32("touchscreen-size-x", 1280), 31 31 - PROPERTY_ENTRY_U32("touchscreen-size-y", 1850), 32 32 - PROPERTY_ENTRY_BOOL("touchscreen-inverted-x"), 30 30 + PROPERTY_ENTRY_U32("touchscreen-size-x", 1850), 31 31 + PROPERTY_ENTRY_U32("touchscreen-size-y", 1280), 32 32 + PROPERTY_ENTRY_BOOL("touchscreen-inverted-y"), 33 33 PROPERTY_ENTRY_BOOL("touchscreen-swapped-x-y"), 34 34 PROPERTY_ENTRY_U32("silead,max-fingers", 10), 35 35 + PROPERTY_ENTRY_BOOL("silead,home-button"), 35 36 PROPERTY_ENTRY_STRING("firmware-name", "gsl1680-archos-101-cesium-educ.fw"), 36 37 { } 37 38 };

+23 -10

drivers/s390/crypto/zcrypt_msgtype6.c

reviewed

··· 1101 1101 struct ica_xcRB *xcrb, 1102 1102 struct ap_message *ap_msg) 1103 1103 { 1104 1104 - int rc; 1105 1104 struct response_type *rtype = ap_msg->private; 1106 1105 struct { 1107 1106 struct type6_hdr hdr; 1108 1107 struct CPRBX cprbx; 1109 1108 /* ... more data blocks ... */ 1110 1109 } __packed * msg = ap_msg->msg; 1110 1110 + unsigned int max_payload_size; 1111 1111 + int rc, delta; 1111 1112 1112 1112 - /* 1113 1113 - * Set the queue's reply buffer length minus 128 byte padding 1114 1114 - * as reply limit for the card firmware. 1115 1115 - */ 1116 1116 - msg->hdr.fromcardlen1 = min_t(unsigned int, msg->hdr.fromcardlen1, 1117 1117 - zq->reply.bufsize - 128); 1118 1118 - if (msg->hdr.fromcardlen2) 1119 1119 - msg->hdr.fromcardlen2 = 1120 1120 - zq->reply.bufsize - msg->hdr.fromcardlen1 - 128; 1113 1113 + /* calculate maximum payload for this card and msg type */ 1114 1114 + max_payload_size = zq->reply.bufsize - sizeof(struct type86_fmt2_msg); 1115 1115 + 1116 1116 + /* limit each of the two from fields to the maximum payload size */ 1117 1117 + msg->hdr.fromcardlen1 = min(msg->hdr.fromcardlen1, max_payload_size); 1118 1118 + msg->hdr.fromcardlen2 = min(msg->hdr.fromcardlen2, max_payload_size); 1119 1119 + 1120 1120 + /* calculate delta if the sum of both exceeds max payload size */ 1121 1121 + delta = msg->hdr.fromcardlen1 + msg->hdr.fromcardlen2 1122 1122 + - max_payload_size; 1123 1123 + if (delta > 0) { 1124 1124 + /* 1125 1125 + * Sum exceeds maximum payload size, prune fromcardlen1 1126 1126 + * (always trust fromcardlen2) 1127 1127 + */ 1128 1128 + if (delta > msg->hdr.fromcardlen1) { 1129 1129 + rc = -EINVAL; 1130 1130 + goto out; 1131 1131 + } 1132 1132 + msg->hdr.fromcardlen1 -= delta; 1133 1133 + } 1121 1134 1122 1135 init_completion(&rtype->work); 1123 1136 rc = ap_queue_message(zq->queue, ap_msg);

+4 -3

drivers/scsi/sg.c

reviewed

··· 1497 1497 int error; 1498 1498 unsigned long iflags; 1499 1499 1500 1500 - error = blk_get_queue(scsidp->request_queue); 1501 1501 - if (error) 1502 1502 - return error; 1500 1500 + if (!blk_get_queue(scsidp->request_queue)) { 1501 1501 + pr_warn("%s: get scsi_device queue failed\n", __func__); 1502 1502 + return -ENODEV; 1503 1503 + } 1503 1504 1504 1505 error = -ENOMEM; 1505 1506 cdev = cdev_alloc();

+2 -2

drivers/soundwire/amd_manager.c

reviewed

··· 910 910 return -ENOMEM; 911 911 912 912 amd_manager->acp_mmio = devm_ioremap(dev, res->start, resource_size(res)); 913 913 - if (IS_ERR(amd_manager->mmio)) { 913 913 + if (!amd_manager->acp_mmio) { 914 914 dev_err(dev, "mmio not found\n"); 915 915 - return PTR_ERR(amd_manager->mmio); 915 915 + return -ENOMEM; 916 916 } 917 917 amd_manager->instance = pdata->instance; 918 918 amd_manager->mmio = amd_manager->acp_mmio +

+4 -4

drivers/soundwire/bus.c

reviewed

··· 922 922 "initializing enumeration and init completion for Slave %d\n", 923 923 slave->dev_num); 924 924 925 925 - init_completion(&slave->enumeration_complete); 926 926 - init_completion(&slave->initialization_complete); 925 925 + reinit_completion(&slave->enumeration_complete); 926 926 + reinit_completion(&slave->initialization_complete); 927 927 928 928 } else if ((status == SDW_SLAVE_ATTACHED) && 929 929 (slave->status == SDW_SLAVE_UNATTACHED)) { ··· 931 931 "signaling enumeration completion for Slave %d\n", 932 932 slave->dev_num); 933 933 934 934 - complete(&slave->enumeration_complete); 934 934 + complete_all(&slave->enumeration_complete); 935 935 } 936 936 slave->status = status; 937 937 mutex_unlock(&bus->bus_lock); ··· 1951 1951 "signaling initialization completion for Slave %d\n", 1952 1952 slave->dev_num); 1953 1953 1954 1954 - complete(&slave->initialization_complete); 1954 1954 + complete_all(&slave->initialization_complete); 1955 1955 1956 1956 /* 1957 1957 * If the manager became pm_runtime active, the peripherals will be

+1 -1

drivers/soundwire/qcom.c

reviewed

··· 540 540 status = (val >> (dev_num * SWRM_MCP_SLV_STATUS_SZ)); 541 541 542 542 if ((status & SWRM_MCP_SLV_STATUS_MASK) == SDW_SLAVE_ALERT) { 543 543 - ctrl->status[dev_num] = status; 543 543 + ctrl->status[dev_num] = status & SWRM_MCP_SLV_STATUS_MASK; 544 544 return dev_num; 545 545 } 546 546 }

+1

drivers/staging/media/atomisp/Kconfig

reviewed

··· 13 13 tristate "Intel Atom Image Signal Processor Driver" 14 14 depends on VIDEO_DEV && INTEL_ATOMISP 15 15 depends on PMIC_OPREGION 16 16 + select V4L2_FWNODE 16 17 select IOSF_MBI 17 18 select VIDEOBUF2_VMALLOC 18 19 select VIDEO_V4L2_SUBDEV_API

+6 -6

drivers/video/console/sticon.c

reviewed

··· 156 156 return false; 157 157 } 158 158 159 159 - static int sticon_set_def_font(int unit, struct console_font *op) 159 159 + static void sticon_set_def_font(int unit) 160 160 { 161 161 if (font_data[unit] != STI_DEF_FONT) { 162 162 if (--FNTREFCOUNT(font_data[unit]) == 0) { ··· 165 165 } 166 166 font_data[unit] = STI_DEF_FONT; 167 167 } 168 168 - 169 169 - return 0; 170 168 } 171 169 172 170 static int sticon_set_font(struct vc_data *vc, struct console_font *op, ··· 244 246 vc->vc_video_erase_char, font_data[vc->vc_num]); 245 247 246 248 /* delete old font in case it is a user font */ 247 247 - sticon_set_def_font(unit, NULL); 249 249 + sticon_set_def_font(unit); 248 250 249 251 FNTREFCOUNT(cooked_font)++; 250 252 font_data[unit] = cooked_font; ··· 262 264 263 265 static int sticon_font_default(struct vc_data *vc, struct console_font *op, char *name) 264 266 { 265 265 - return sticon_set_def_font(vc->vc_num, op); 267 267 + sticon_set_def_font(vc->vc_num); 268 268 + 269 269 + return 0; 266 270 } 267 271 268 272 static int sticon_font_set(struct vc_data *vc, struct console_font *font, ··· 297 297 298 298 /* free memory used by user font */ 299 299 for (i = 0; i < MAX_NR_CONSOLES; i++) 300 300 - sticon_set_def_font(i, NULL); 300 300 + sticon_set_def_font(i); 301 301 } 302 302 303 303 static void sticon_clear(struct vc_data *conp, int sy, int sx, int height,

+28 -46

drivers/video/console/vgacon.c

reviewed

··· 65 65 * Interface used by the world 66 66 */ 67 67 68 68 - static const char *vgacon_startup(void); 69 69 - static void vgacon_init(struct vc_data *c, int init); 70 70 - static void vgacon_deinit(struct vc_data *c); 71 71 - static void vgacon_cursor(struct vc_data *c, int mode); 72 72 - static int vgacon_switch(struct vc_data *c); 73 73 - static int vgacon_blank(struct vc_data *c, int blank, int mode_switch); 74 74 - static void vgacon_scrolldelta(struct vc_data *c, int lines); 75 68 static int vgacon_set_origin(struct vc_data *c); 76 76 - static void vgacon_save_screen(struct vc_data *c); 77 77 - static void vgacon_invert_region(struct vc_data *c, u16 * p, int count); 69 69 + 78 70 static struct uni_pagedict *vgacon_uni_pagedir; 79 71 static int vgacon_refcount; 80 72 ··· 134 142 write_vga(12, (c->vc_visible_origin - vga_vram_base) / 2); 135 143 } 136 144 137 137 - static void vgacon_restore_screen(struct vc_data *c) 138 138 - { 139 139 - if (c->vc_origin != c->vc_visible_origin) 140 140 - vgacon_scrolldelta(c, 0); 141 141 - } 142 142 - 143 145 static void vgacon_scrolldelta(struct vc_data *c, int lines) 144 146 { 145 147 vc_scrolldelta_helper(c, lines, vga_rolled_over, (void *)vga_vram_base, 146 148 vga_vram_size); 147 149 vga_set_mem_top(c); 150 150 + } 151 151 + 152 152 + static void vgacon_restore_screen(struct vc_data *c) 153 153 + { 154 154 + if (c->vc_origin != c->vc_visible_origin) 155 155 + vgacon_scrolldelta(c, 0); 148 156 } 149 157 150 158 static const char *vgacon_startup(void) ··· 437 445 } 438 446 } 439 447 440 440 - static void vgacon_set_cursor_size(int xpos, int from, int to) 448 448 + static void vgacon_set_cursor_size(int from, int to) 441 449 { 442 450 unsigned long flags; 443 451 int curs, cure; ··· 470 478 471 479 static void vgacon_cursor(struct vc_data *c, int mode) 472 480 { 481 481 + unsigned int c_height; 482 482 + 473 483 if (c->vc_mode != KD_TEXT) 474 484 return; 475 485 476 486 vgacon_restore_screen(c); 477 487 488 488 + c_height = c->vc_cell_height; 489 489 + 478 490 switch (mode) { 479 491 case CM_ERASE: 480 492 write_vga(14, (c->vc_pos - vga_vram_base) / 2); 481 493 if (vga_video_type >= VIDEO_TYPE_VGAC) 482 482 - vgacon_set_cursor_size(c->state.x, 31, 30); 494 494 + vgacon_set_cursor_size(31, 30); 483 495 else 484 484 - vgacon_set_cursor_size(c->state.x, 31, 31); 496 496 + vgacon_set_cursor_size(31, 31); 485 497 break; 486 498 487 499 case CM_MOVE: ··· 493 497 write_vga(14, (c->vc_pos - vga_vram_base) / 2); 494 498 switch (CUR_SIZE(c->vc_cursor_type)) { 495 499 case CUR_UNDERLINE: 496 496 - vgacon_set_cursor_size(c->state.x, 497 497 - c->vc_cell_height - 498 498 - (c->vc_cell_height < 499 499 - 10 ? 2 : 3), 500 500 - c->vc_cell_height - 501 501 - (c->vc_cell_height < 502 502 - 10 ? 1 : 2)); 500 500 + vgacon_set_cursor_size(c_height - 501 501 + (c_height < 10 ? 2 : 3), 502 502 + c_height - 503 503 + (c_height < 10 ? 1 : 2)); 503 504 break; 504 505 case CUR_TWO_THIRDS: 505 505 - vgacon_set_cursor_size(c->state.x, 506 506 - c->vc_cell_height / 3, 507 507 - c->vc_cell_height - 508 508 - (c->vc_cell_height < 509 509 - 10 ? 1 : 2)); 506 506 + vgacon_set_cursor_size(c_height / 3, c_height - 507 507 + (c_height < 10 ? 1 : 2)); 510 508 break; 511 509 case CUR_LOWER_THIRD: 512 512 - vgacon_set_cursor_size(c->state.x, 513 513 - (c->vc_cell_height * 2) / 3, 514 514 - c->vc_cell_height - 515 515 - (c->vc_cell_height < 516 516 - 10 ? 1 : 2)); 510 510 + vgacon_set_cursor_size(c_height * 2 / 3, c_height - 511 511 + (c_height < 10 ? 1 : 2)); 517 512 break; 518 513 case CUR_LOWER_HALF: 519 519 - vgacon_set_cursor_size(c->state.x, 520 520 - c->vc_cell_height / 2, 521 521 - c->vc_cell_height - 522 522 - (c->vc_cell_height < 523 523 - 10 ? 1 : 2)); 514 514 + vgacon_set_cursor_size(c_height / 2, c_height - 515 515 + (c_height < 10 ? 1 : 2)); 524 516 break; 525 517 case CUR_NONE: 526 518 if (vga_video_type >= VIDEO_TYPE_VGAC) 527 527 - vgacon_set_cursor_size(c->state.x, 31, 30); 519 519 + vgacon_set_cursor_size(31, 30); 528 520 else 529 529 - vgacon_set_cursor_size(c->state.x, 31, 31); 521 521 + vgacon_set_cursor_size(31, 31); 530 522 break; 531 523 default: 532 532 - vgacon_set_cursor_size(c->state.x, 1, 533 533 - c->vc_cell_height); 524 524 + vgacon_set_cursor_size(1, c_height); 534 525 break; 535 526 } 536 527 break; 537 528 } 538 529 } 539 530 540 540 - static int vgacon_doresize(struct vc_data *c, 531 531 + static void vgacon_doresize(struct vc_data *c, 541 532 unsigned int width, unsigned int height) 542 533 { 543 534 unsigned long flags; ··· 583 600 } 584 601 585 602 raw_spin_unlock_irqrestore(&vga_lock, flags); 586 586 - return 0; 587 603 } 588 604 589 605 static int vgacon_switch(struct vc_data *c)

+3

drivers/video/fbdev/au1200fb.c

reviewed

··· 1732 1732 1733 1733 /* Now hook interrupt too */ 1734 1734 irq = platform_get_irq(dev, 0); 1735 1735 + if (irq < 0) 1736 1736 + return irq; 1737 1737 + 1735 1738 ret = request_irq(irq, au1200fb_handle_irq, 1736 1739 IRQF_SHARED, "lcd", (void *)dev); 1737 1740 if (ret) {

+2 -1

drivers/video/fbdev/bw2.c

reviewed

··· 17 17 #include <linux/init.h> 18 18 #include <linux/fb.h> 19 19 #include <linux/mm.h> 20 20 - #include <linux/of_device.h> 20 20 + #include <linux/of.h> 21 21 + #include <linux/platform_device.h> 21 22 22 23 #include <asm/io.h> 23 24 #include <asm/fbio.h>

+2 -1

drivers/video/fbdev/cg14.c

reviewed

··· 17 17 #include <linux/fb.h> 18 18 #include <linux/mm.h> 19 19 #include <linux/uaccess.h> 20 20 - #include <linux/of_device.h> 20 20 + #include <linux/of.h> 21 21 + #include <linux/platform_device.h> 21 22 22 23 #include <asm/io.h> 23 24 #include <asm/fbio.h>

+2 -1

drivers/video/fbdev/cg3.c

reviewed

··· 17 17 #include <linux/init.h> 18 18 #include <linux/fb.h> 19 19 #include <linux/mm.h> 20 20 - #include <linux/of_device.h> 20 20 + #include <linux/of.h> 21 21 + #include <linux/platform_device.h> 21 22 22 23 #include <asm/io.h> 23 24 #include <asm/fbio.h>

+2 -1

drivers/video/fbdev/cg6.c

reviewed

··· 17 17 #include <linux/init.h> 18 18 #include <linux/fb.h> 19 19 #include <linux/mm.h> 20 20 - #include <linux/of_device.h> 20 20 + #include <linux/of.h> 21 21 + #include <linux/platform_device.h> 21 22 22 23 #include <asm/io.h> 23 24 #include <asm/fbio.h>

+3 -4

drivers/video/fbdev/core/fbcon.c

reviewed

··· 1612 1612 } 1613 1613 } 1614 1614 1615 1615 - static void fbcon_redraw(struct vc_data *vc, struct fbcon_display *p, 1616 1616 - int line, int count, int offset) 1615 1615 + static void fbcon_redraw(struct vc_data *vc, int line, int count, int offset) 1617 1616 { 1618 1617 unsigned short *d = (unsigned short *) 1619 1618 (vc->vc_origin + vc->vc_size_row * line); ··· 1826 1827 1827 1828 case SCROLL_REDRAW: 1828 1829 redraw_up: 1829 1829 - fbcon_redraw(vc, p, t, b - t - count, 1830 1830 + fbcon_redraw(vc, t, b - t - count, 1830 1831 count * vc->vc_cols); 1831 1832 fbcon_clear(vc, b - count, 0, count, vc->vc_cols); 1832 1833 scr_memsetw((unsigned short *) (vc->vc_origin + ··· 1912 1913 1913 1914 case SCROLL_REDRAW: 1914 1915 redraw_down: 1915 1915 - fbcon_redraw(vc, p, b - 1, b - t - count, 1916 1916 + fbcon_redraw(vc, b - 1, b - t - count, 1916 1917 -count * vc->vc_cols); 1917 1918 fbcon_clear(vc, t, 0, count, vc->vc_cols); 1918 1919 scr_memsetw((unsigned short *) (vc->vc_origin +

+3 -1

drivers/video/fbdev/ep93xx-fb.c

reviewed

··· 548 548 } 549 549 550 550 ep93xxfb_set_par(info); 551 551 - clk_prepare_enable(fbi->clk); 551 551 + err = clk_prepare_enable(fbi->clk); 552 552 + if (err) 553 553 + goto failed_check; 552 554 553 555 err = register_framebuffer(info); 554 556 if (err)

+2 -1

drivers/video/fbdev/ffb.c

reviewed

··· 16 16 #include <linux/fb.h> 17 17 #include <linux/mm.h> 18 18 #include <linux/timer.h> 19 19 - #include <linux/of_device.h> 19 19 + #include <linux/of.h> 20 20 + #include <linux/platform_device.h> 20 21 21 22 #include <asm/io.h> 22 23 #include <asm/upa.h>

+1 -2

drivers/video/fbdev/grvga.c

reviewed

··· 12 12 13 13 #include <linux/platform_device.h> 14 14 #include <linux/dma-mapping.h> 15 15 - #include <linux/of_platform.h> 16 16 - #include <linux/of_device.h> 15 15 + #include <linux/of.h> 17 16 #include <linux/module.h> 18 17 #include <linux/kernel.h> 19 18 #include <linux/string.h>

+18 -30

drivers/video/fbdev/imxfb.c

reviewed

··· 613 613 if (var->hsync_len < 1 || var->hsync_len > 64) 614 614 printk(KERN_ERR "%s: invalid hsync_len %d\n", 615 615 info->fix.id, var->hsync_len); 616 616 - if (var->left_margin > 255) 616 616 + if (var->left_margin < 3 || var->left_margin > 255) 617 617 printk(KERN_ERR "%s: invalid left_margin %d\n", 618 618 info->fix.id, var->left_margin); 619 619 - if (var->right_margin > 255) 619 619 + if (var->right_margin < 1 || var->right_margin > 255) 620 620 printk(KERN_ERR "%s: invalid right_margin %d\n", 621 621 info->fix.id, var->right_margin); 622 622 if (var->yres < 1 || var->yres > ymax_mask) ··· 673 673 674 674 pr_debug("%s\n",__func__); 675 675 676 676 - info->pseudo_palette = kmalloc_array(16, sizeof(u32), GFP_KERNEL); 676 676 + info->pseudo_palette = devm_kmalloc_array(&pdev->dev, 16, 677 677 + sizeof(u32), GFP_KERNEL); 677 678 if (!info->pseudo_palette) 678 679 return -ENOMEM; 679 680 ··· 869 868 struct imxfb_info *fbi; 870 869 struct lcd_device *lcd; 871 870 struct fb_info *info; 872 872 - struct resource *res; 873 871 struct imx_fb_videomode *m; 874 872 const struct of_device_id *of_id; 875 873 struct device_node *display_np; ··· 884 884 of_id = of_match_device(imxfb_of_dev_id, &pdev->dev); 885 885 if (of_id) 886 886 pdev->id_entry = of_id->data; 887 887 - 888 888 - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 889 889 - if (!res) 890 890 - return -ENODEV; 891 887 892 888 info = framebuffer_alloc(sizeof(struct imxfb_info), &pdev->dev); 893 889 if (!info) ··· 903 907 if (!display_np) { 904 908 dev_err(&pdev->dev, "No display defined in devicetree\n"); 905 909 ret = -EINVAL; 906 906 - goto failed_of_parse; 910 910 + goto failed_init; 907 911 } 908 912 909 913 /* ··· 917 921 if (!fbi->mode) { 918 922 ret = -ENOMEM; 919 923 of_node_put(display_np); 920 920 - goto failed_of_parse; 924 924 + goto failed_init; 921 925 } 922 926 923 927 ret = imxfb_of_read_mode(&pdev->dev, display_np, fbi->mode); 924 928 of_node_put(display_np); 925 929 if (ret) 926 926 - goto failed_of_parse; 930 930 + goto failed_init; 927 931 928 932 /* Calculate maximum bytes used per pixel. In most cases this should 929 933 * be the same as m->bpp/8 */ ··· 936 940 fbi->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 937 941 if (IS_ERR(fbi->clk_ipg)) { 938 942 ret = PTR_ERR(fbi->clk_ipg); 939 939 - goto failed_getclock; 943 943 + goto failed_init; 940 944 } 941 945 942 946 /* ··· 951 955 */ 952 956 ret = clk_prepare_enable(fbi->clk_ipg); 953 957 if (ret) 954 954 - goto failed_getclock; 958 958 + goto failed_init; 955 959 clk_disable_unprepare(fbi->clk_ipg); 956 960 957 961 fbi->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 958 962 if (IS_ERR(fbi->clk_ahb)) { 959 963 ret = PTR_ERR(fbi->clk_ahb); 960 960 - goto failed_getclock; 964 964 + goto failed_init; 961 965 } 962 966 963 967 fbi->clk_per = devm_clk_get(&pdev->dev, "per"); 964 968 if (IS_ERR(fbi->clk_per)) { 965 969 ret = PTR_ERR(fbi->clk_per); 966 966 - goto failed_getclock; 970 970 + goto failed_init; 967 971 } 968 972 969 969 - fbi->regs = devm_ioremap_resource(&pdev->dev, res); 973 973 + fbi->regs = devm_platform_ioremap_resource(pdev, 0); 970 974 if (IS_ERR(fbi->regs)) { 971 975 ret = PTR_ERR(fbi->regs); 972 972 - goto failed_ioremap; 976 976 + goto failed_init; 973 977 } 974 978 975 979 fbi->map_size = PAGE_ALIGN(info->fix.smem_len); ··· 978 982 if (!info->screen_buffer) { 979 983 dev_err(&pdev->dev, "Failed to allocate video RAM\n"); 980 984 ret = -ENOMEM; 981 981 - goto failed_map; 985 985 + goto failed_init; 982 986 } 983 987 984 988 info->fix.smem_start = fbi->map_dma; ··· 1030 1034 1031 1035 failed_lcd: 1032 1036 unregister_framebuffer(info); 1033 1033 - 1034 1037 failed_register: 1035 1038 fb_dealloc_cmap(&info->cmap); 1036 1039 failed_cmap: 1037 1040 dma_free_wc(&pdev->dev, fbi->map_size, info->screen_buffer, 1038 1041 fbi->map_dma); 1039 1039 - failed_map: 1040 1040 - failed_ioremap: 1041 1041 - failed_getclock: 1042 1042 - release_mem_region(res->start, resource_size(res)); 1043 1043 - failed_of_parse: 1044 1044 - kfree(info->pseudo_palette); 1045 1042 failed_init: 1046 1043 framebuffer_release(info); 1047 1044 return ret; ··· 1051 1062 fb_dealloc_cmap(&info->cmap); 1052 1063 dma_free_wc(&pdev->dev, fbi->map_size, info->screen_buffer, 1053 1064 fbi->map_dma); 1054 1054 - kfree(info->pseudo_palette); 1055 1065 framebuffer_release(info); 1056 1066 } 1057 1067 1058 1058 - static int __maybe_unused imxfb_suspend(struct device *dev) 1068 1068 + static int imxfb_suspend(struct device *dev) 1059 1069 { 1060 1070 struct fb_info *info = dev_get_drvdata(dev); 1061 1071 struct imxfb_info *fbi = info->par; ··· 1064 1076 return 0; 1065 1077 } 1066 1078 1067 1067 - static int __maybe_unused imxfb_resume(struct device *dev) 1079 1079 + static int imxfb_resume(struct device *dev) 1068 1080 { 1069 1081 struct fb_info *info = dev_get_drvdata(dev); 1070 1082 struct imxfb_info *fbi = info->par; ··· 1074 1086 return 0; 1075 1087 } 1076 1088 1077 1077 - static SIMPLE_DEV_PM_OPS(imxfb_pm_ops, imxfb_suspend, imxfb_resume); 1089 1089 + static DEFINE_SIMPLE_DEV_PM_OPS(imxfb_pm_ops, imxfb_suspend, imxfb_resume); 1078 1090 1079 1091 static struct platform_driver imxfb_driver = { 1080 1092 .driver = { 1081 1093 .name = DRIVER_NAME, 1082 1094 .of_match_table = imxfb_of_dev_id, 1083 1083 - .pm = &imxfb_pm_ops, 1095 1095 + .pm = pm_sleep_ptr(&imxfb_pm_ops), 1084 1096 }, 1085 1097 .probe = imxfb_probe, 1086 1098 .remove_new = imxfb_remove,

+5 -5

drivers/video/fbdev/kyro/STG4000InitDevice.c

reviewed

··· 83 83 static u32 InitSDRAMRegisters(volatile STG4000REG __iomem *pSTGReg, 84 84 u32 dwSubSysID, u32 dwRevID) 85 85 { 86 86 - u32 adwSDRAMArgCfg0[] = { 0xa0, 0x80, 0xa0, 0xa0, 0xa0 }; 87 87 - u32 adwSDRAMCfg1[] = { 0x8732, 0x8732, 0xa732, 0xa732, 0x8732 }; 88 88 - u32 adwSDRAMCfg2[] = { 0x87d2, 0x87d2, 0xa7d2, 0x87d2, 0xa7d2 }; 89 89 - u32 adwSDRAMRsh[] = { 36, 39, 40 }; 90 90 - u32 adwChipSpeed[] = { 110, 120, 125 }; 86 86 + static const u8 adwSDRAMArgCfg0[] = { 0xa0, 0x80, 0xa0, 0xa0, 0xa0 }; 87 87 + static const u16 adwSDRAMCfg1[] = { 0x8732, 0x8732, 0xa732, 0xa732, 0x8732 }; 88 88 + static const u16 adwSDRAMCfg2[] = { 0x87d2, 0x87d2, 0xa7d2, 0x87d2, 0xa7d2 }; 89 89 + static const u8 adwSDRAMRsh[] = { 36, 39, 40 }; 90 90 + static const u8 adwChipSpeed[] = { 110, 120, 125 }; 91 91 u32 dwMemTypeIdx; 92 92 u32 dwChipSpeedIdx; 93 93

+2 -1

drivers/video/fbdev/leo.c

reviewed

··· 16 16 #include <linux/init.h> 17 17 #include <linux/fb.h> 18 18 #include <linux/mm.h> 19 19 - #include <linux/of_device.h> 20 19 #include <linux/io.h> 20 20 + #include <linux/of.h> 21 21 + #include <linux/platform_device.h> 21 22 22 23 #include <asm/fbio.h> 23 24

+1 -3

drivers/video/fbdev/mb862xx/mb862xxfb_accel.c

reviewed

··· 15 15 #include <linux/module.h> 16 16 #include <linux/pci.h> 17 17 #include <linux/slab.h> 18 18 - #if defined(CONFIG_OF) 19 19 - #include <linux/of_platform.h> 20 20 - #endif 18 18 + 21 19 #include "mb862xxfb.h" 22 20 #include "mb862xx_reg.h" 23 21 #include "mb862xxfb_accel.h"

+3 -3

drivers/video/fbdev/mb862xx/mb862xxfbdrv.c

reviewed

··· 18 18 #include <linux/init.h> 19 19 #include <linux/interrupt.h> 20 20 #include <linux/pci.h> 21 21 - #if defined(CONFIG_OF) 21 21 + #include <linux/of.h> 22 22 #include <linux/of_address.h> 23 23 #include <linux/of_irq.h> 24 24 - #include <linux/of_platform.h> 25 25 - #endif 24 24 + #include <linux/platform_device.h> 25 25 + 26 26 #include "mb862xxfb.h" 27 27 #include "mb862xx_reg.h" 28 28

+1 -1

drivers/video/fbdev/omap2/omapfb/displays/panel-dsi-cm.c

reviewed

··· 15 15 #include <linux/gpio/consumer.h> 16 16 #include <linux/interrupt.h> 17 17 #include <linux/jiffies.h> 18 18 + #include <linux/mod_devicetable.h> 18 19 #include <linux/module.h> 19 20 #include <linux/platform_device.h> 20 21 #include <linux/sched/signal.h> 21 22 #include <linux/slab.h> 22 23 #include <linux/workqueue.h> 23 23 - #include <linux/of_device.h> 24 24 25 25 #include <video/omapfb_dss.h> 26 26 #include <video/mipi_display.h>

+2 -1

drivers/video/fbdev/p9100.c

reviewed

··· 15 15 #include <linux/init.h> 16 16 #include <linux/fb.h> 17 17 #include <linux/mm.h> 18 18 - #include <linux/of_device.h> 18 18 + #include <linux/of.h> 19 19 + #include <linux/platform_device.h> 19 20 20 21 #include <asm/io.h> 21 22 #include <asm/fbio.h>

+2 -2

drivers/video/fbdev/platinumfb.c

reviewed

··· 30 30 #include <linux/fb.h> 31 31 #include <linux/init.h> 32 32 #include <linux/nvram.h> 33 33 + #include <linux/of.h> 33 34 #include <linux/of_address.h> 34 34 - #include <linux/of_device.h> 35 35 - #include <linux/of_platform.h> 35 35 + #include <linux/platform_device.h> 36 36 37 37 #include "macmodes.h" 38 38 #include "platinumfb.h"

+1 -1

drivers/video/fbdev/sbuslib.c

reviewed

··· 11 11 #include <linux/fb.h> 12 12 #include <linux/mm.h> 13 13 #include <linux/uaccess.h> 14 14 - #include <linux/of_device.h> 14 14 + #include <linux/of.h> 15 15 16 16 #include <asm/fbio.h> 17 17

+2 -1

drivers/video/fbdev/sunxvr1000.c

reviewed

··· 8 8 #include <linux/kernel.h> 9 9 #include <linux/fb.h> 10 10 #include <linux/init.h> 11 11 - #include <linux/of_device.h> 11 11 + #include <linux/of.h> 12 12 + #include <linux/platform_device.h> 12 13 13 14 struct gfb_info { 14 15 struct fb_info *info;

+1 -1

drivers/video/fbdev/sunxvr2500.c

reviewed

··· 10 10 #include <linux/fb.h> 11 11 #include <linux/pci.h> 12 12 #include <linux/init.h> 13 13 - #include <linux/of_device.h> 13 13 + #include <linux/of.h> 14 14 15 15 #include <asm/io.h> 16 16

+1 -1

drivers/video/fbdev/sunxvr500.c

reviewed

··· 10 10 #include <linux/fb.h> 11 11 #include <linux/pci.h> 12 12 #include <linux/init.h> 13 13 - #include <linux/of_device.h> 13 13 + #include <linux/of.h> 14 14 15 15 #include <asm/io.h> 16 16

+2 -1

drivers/video/fbdev/tcx.c

reviewed

··· 17 17 #include <linux/init.h> 18 18 #include <linux/fb.h> 19 19 #include <linux/mm.h> 20 20 - #include <linux/of_device.h> 20 20 + #include <linux/of.h> 21 21 + #include <linux/platform_device.h> 21 22 22 23 #include <asm/io.h> 23 24 #include <asm/fbio.h>

+2 -3

drivers/video/fbdev/xilinxfb.c

reviewed

··· 24 24 #include <linux/module.h> 25 25 #include <linux/kernel.h> 26 26 #include <linux/errno.h> 27 27 + #include <linux/platform_device.h> 27 28 #include <linux/string.h> 28 29 #include <linux/mm.h> 29 30 #include <linux/fb.h> 30 31 #include <linux/init.h> 31 32 #include <linux/dma-mapping.h> 32 32 - #include <linux/of_device.h> 33 33 - #include <linux/of_platform.h> 34 34 - #include <linux/of_address.h> 33 33 + #include <linux/of.h> 35 34 #include <linux/io.h> 36 35 #include <linux/slab.h> 37 36

+34 -17

fs/btrfs/block-group.c

reviewed

··· 499 499 * used yet since their free space will be released as soon as the transaction 500 500 * commits. 501 501 */ 502 502 - u64 add_new_free_space(struct btrfs_block_group *block_group, u64 start, u64 end) 502 502 + int add_new_free_space(struct btrfs_block_group *block_group, u64 start, u64 end, 503 503 + u64 *total_added_ret) 503 504 { 504 505 struct btrfs_fs_info *info = block_group->fs_info; 505 505 - u64 extent_start, extent_end, size, total_added = 0; 506 506 + u64 extent_start, extent_end, size; 506 507 int ret; 508 508 + 509 509 + if (total_added_ret) 510 510 + *total_added_ret = 0; 507 511 508 512 while (start < end) { 509 513 ret = find_first_extent_bit(&info->excluded_extents, start, ··· 521 517 start = extent_end + 1; 522 518 } else if (extent_start > start && extent_start < end) { 523 519 size = extent_start - start; 524 524 - total_added += size; 525 520 ret = btrfs_add_free_space_async_trimmed(block_group, 526 521 start, size); 527 527 - BUG_ON(ret); /* -ENOMEM or logic error */ 522 522 + if (ret) 523 523 + return ret; 524 524 + if (total_added_ret) 525 525 + *total_added_ret += size; 528 526 start = extent_end + 1; 529 527 } else { 530 528 break; ··· 535 529 536 530 if (start < end) { 537 531 size = end - start; 538 538 - total_added += size; 539 532 ret = btrfs_add_free_space_async_trimmed(block_group, start, 540 533 size); 541 541 - BUG_ON(ret); /* -ENOMEM or logic error */ 534 534 + if (ret) 535 535 + return ret; 536 536 + if (total_added_ret) 537 537 + *total_added_ret += size; 542 538 } 543 539 544 544 - return total_added; 540 540 + return 0; 545 541 } 546 542 547 543 /* ··· 787 779 788 780 if (key.type == BTRFS_EXTENT_ITEM_KEY || 789 781 key.type == BTRFS_METADATA_ITEM_KEY) { 790 790 - total_found += add_new_free_space(block_group, last, 791 791 - key.objectid); 782 782 + u64 space_added; 783 783 + 784 784 + ret = add_new_free_space(block_group, last, key.objectid, 785 785 + &space_added); 786 786 + if (ret) 787 787 + goto out; 788 788 + total_found += space_added; 792 789 if (key.type == BTRFS_METADATA_ITEM_KEY) 793 790 last = key.objectid + 794 791 fs_info->nodesize; ··· 808 795 } 809 796 path->slots[0]++; 810 797 } 811 811 - ret = 0; 812 798 813 813 - total_found += add_new_free_space(block_group, last, 814 814 - block_group->start + block_group->length); 815 815 - 799 799 + ret = add_new_free_space(block_group, last, 800 800 + block_group->start + block_group->length, 801 801 + NULL); 816 802 out: 817 803 btrfs_free_path(path); 818 804 return ret; ··· 2306 2294 btrfs_free_excluded_extents(cache); 2307 2295 } else if (cache->used == 0) { 2308 2296 cache->cached = BTRFS_CACHE_FINISHED; 2309 2309 - add_new_free_space(cache, cache->start, 2310 2310 - cache->start + cache->length); 2297 2297 + ret = add_new_free_space(cache, cache->start, 2298 2298 + cache->start + cache->length, NULL); 2311 2299 btrfs_free_excluded_extents(cache); 2300 2300 + if (ret) 2301 2301 + goto error; 2312 2302 } 2313 2303 2314 2304 ret = btrfs_add_block_group_cache(info, cache); ··· 2754 2740 return ERR_PTR(ret); 2755 2741 } 2756 2742 2757 2757 - add_new_free_space(cache, chunk_offset, chunk_offset + size); 2758 2758 - 2743 2743 + ret = add_new_free_space(cache, chunk_offset, chunk_offset + size, NULL); 2759 2744 btrfs_free_excluded_extents(cache); 2745 2745 + if (ret) { 2746 2746 + btrfs_put_block_group(cache); 2747 2747 + return ERR_PTR(ret); 2748 2748 + } 2760 2749 2761 2750 /* 2762 2751 * Ensure the corresponding space_info object is created and

+2 -2

fs/btrfs/block-group.h

reviewed

··· 289 289 void btrfs_put_caching_control(struct btrfs_caching_control *ctl); 290 290 struct btrfs_caching_control *btrfs_get_caching_control( 291 291 struct btrfs_block_group *cache); 292 292 - u64 add_new_free_space(struct btrfs_block_group *block_group, 293 293 - u64 start, u64 end); 292 292 + int add_new_free_space(struct btrfs_block_group *block_group, 293 293 + u64 start, u64 end, u64 *total_added_ret); 294 294 struct btrfs_trans_handle *btrfs_start_trans_remove_block_group( 295 295 struct btrfs_fs_info *fs_info, 296 296 const u64 chunk_offset);

+5

fs/btrfs/block-rsv.c

reviewed

··· 349 349 } 350 350 read_unlock(&fs_info->global_root_lock); 351 351 352 352 + if (btrfs_fs_compat_ro(fs_info, BLOCK_GROUP_TREE)) { 353 353 + num_bytes += btrfs_root_used(&fs_info->block_group_root->root_item); 354 354 + min_items++; 355 355 + } 356 356 + 352 357 /* 353 358 * But we also want to reserve enough space so we can do the fallback 354 359 * global reserve for an unlink, which is an additional

+6 -1

fs/btrfs/disk-io.c

reviewed

··· 3438 3438 * For devices supporting discard turn on discard=async automatically, 3439 3439 * unless it's already set or disabled. This could be turned off by 3440 3440 * nodiscard for the same mount. 3441 3441 + * 3442 3442 + * The zoned mode piggy backs on the discard functionality for 3443 3443 + * resetting a zone. There is no reason to delay the zone reset as it is 3444 3444 + * fast enough. So, do not enable async discard for zoned mode. 3441 3445 */ 3442 3446 if (!(btrfs_test_opt(fs_info, DISCARD_SYNC) || 3443 3447 btrfs_test_opt(fs_info, DISCARD_ASYNC) || 3444 3448 btrfs_test_opt(fs_info, NODISCARD)) && 3445 3445 - fs_info->fs_devices->discardable) { 3449 3449 + fs_info->fs_devices->discardable && 3450 3450 + !btrfs_is_zoned(fs_info)) { 3446 3451 btrfs_set_and_info(fs_info, DISCARD_ASYNC, 3447 3452 "auto enabling async discard"); 3448 3453 }

+17 -7

fs/btrfs/free-space-tree.c

reviewed

··· 1515 1515 if (prev_bit == 0 && bit == 1) { 1516 1516 extent_start = offset; 1517 1517 } else if (prev_bit == 1 && bit == 0) { 1518 1518 - total_found += add_new_free_space(block_group, 1519 1519 - extent_start, 1520 1520 - offset); 1518 1518 + u64 space_added; 1519 1519 + 1520 1520 + ret = add_new_free_space(block_group, extent_start, 1521 1521 + offset, &space_added); 1522 1522 + if (ret) 1523 1523 + goto out; 1524 1524 + total_found += space_added; 1521 1525 if (total_found > CACHING_CTL_WAKE_UP) { 1522 1526 total_found = 0; 1523 1527 wake_up(&caching_ctl->wait); ··· 1533 1529 } 1534 1530 } 1535 1531 if (prev_bit == 1) { 1536 1536 - total_found += add_new_free_space(block_group, extent_start, 1537 1537 - end); 1532 1532 + ret = add_new_free_space(block_group, extent_start, end, NULL); 1533 1533 + if (ret) 1534 1534 + goto out; 1538 1535 extent_count++; 1539 1536 } 1540 1537 ··· 1574 1569 end = block_group->start + block_group->length; 1575 1570 1576 1571 while (1) { 1572 1572 + u64 space_added; 1573 1573 + 1577 1574 ret = btrfs_next_item(root, path); 1578 1575 if (ret < 0) 1579 1576 goto out; ··· 1590 1583 ASSERT(key.type == BTRFS_FREE_SPACE_EXTENT_KEY); 1591 1584 ASSERT(key.objectid < end && key.objectid + key.offset <= end); 1592 1585 1593 1593 - total_found += add_new_free_space(block_group, key.objectid, 1594 1594 - key.objectid + key.offset); 1586 1586 + ret = add_new_free_space(block_group, key.objectid, 1587 1587 + key.objectid + key.offset, &space_added); 1588 1588 + if (ret) 1589 1589 + goto out; 1590 1590 + total_found += space_added; 1595 1591 if (total_found > CACHING_CTL_WAKE_UP) { 1596 1592 total_found = 0; 1597 1593 wake_up(&caching_ctl->wait);

+8 -2

fs/btrfs/transaction.c

reviewed

··· 826 826 827 827 trans = start_transaction(root, 0, TRANS_ATTACH, 828 828 BTRFS_RESERVE_NO_FLUSH, true); 829 829 - if (trans == ERR_PTR(-ENOENT)) 830 830 - btrfs_wait_for_commit(root->fs_info, 0); 829 829 + if (trans == ERR_PTR(-ENOENT)) { 830 830 + int ret; 831 831 + 832 832 + ret = btrfs_wait_for_commit(root->fs_info, 0); 833 833 + if (ret) 834 834 + return ERR_PTR(ret); 835 835 + } 831 836 832 837 return trans; 833 838 } ··· 936 931 } 937 932 938 933 wait_for_commit(cur_trans, TRANS_STATE_COMPLETED); 934 934 + ret = cur_trans->aborted; 939 935 btrfs_put_transaction(cur_trans); 940 936 out: 941 937 return ret;

+3

fs/btrfs/zoned.c

reviewed

··· 805 805 return -EINVAL; 806 806 } 807 807 808 808 + btrfs_clear_and_info(info, DISCARD_ASYNC, 809 809 + "zoned: async discard ignored and disabled for zoned mode"); 810 810 + 808 811 return 0; 809 812 } 810 813

+143 -35

fs/ext4/mballoc.c

reviewed

··· 1006 1006 * fls() instead since we need to know the actual length while modifying 1007 1007 * goal length. 1008 1008 */ 1009 1009 - order = fls(ac->ac_g_ex.fe_len); 1009 1009 + order = fls(ac->ac_g_ex.fe_len) - 1; 1010 1010 min_order = order - sbi->s_mb_best_avail_max_trim_order; 1011 1011 if (min_order < 0) 1012 1012 min_order = 0; 1013 1013 - 1014 1014 - if (1 << min_order < ac->ac_o_ex.fe_len) 1015 1015 - min_order = fls(ac->ac_o_ex.fe_len) + 1; 1016 1013 1017 1014 if (sbi->s_stripe > 0) { 1018 1015 /* ··· 1018 1021 */ 1019 1022 num_stripe_clusters = EXT4_NUM_B2C(sbi, sbi->s_stripe); 1020 1023 if (1 << min_order < num_stripe_clusters) 1021 1021 - min_order = fls(num_stripe_clusters); 1024 1024 + /* 1025 1025 + * We consider 1 order less because later we round 1026 1026 + * up the goal len to num_stripe_clusters 1027 1027 + */ 1028 1028 + min_order = fls(num_stripe_clusters) - 1; 1022 1029 } 1030 1030 + 1031 1031 + if (1 << min_order < ac->ac_o_ex.fe_len) 1032 1032 + min_order = fls(ac->ac_o_ex.fe_len); 1023 1033 1024 1034 for (i = order; i >= min_order; i--) { 1025 1035 int frag_order; ··· 4765 4761 int order, i; 4766 4762 struct ext4_inode_info *ei = EXT4_I(ac->ac_inode); 4767 4763 struct ext4_locality_group *lg; 4768 4768 - struct ext4_prealloc_space *tmp_pa, *cpa = NULL; 4769 4769 - ext4_lblk_t tmp_pa_start, tmp_pa_end; 4764 4764 + struct ext4_prealloc_space *tmp_pa = NULL, *cpa = NULL; 4765 4765 + loff_t tmp_pa_end; 4770 4766 struct rb_node *iter; 4771 4767 ext4_fsblk_t goal_block; 4772 4768 ··· 4774 4770 if (!(ac->ac_flags & EXT4_MB_HINT_DATA)) 4775 4771 return false; 4776 4772 4777 4777 - /* first, try per-file preallocation */ 4773 4773 + /* 4774 4774 + * first, try per-file preallocation by searching the inode pa rbtree. 4775 4775 + * 4776 4776 + * Here, we can't do a direct traversal of the tree because 4777 4777 + * ext4_mb_discard_group_preallocation() can paralelly mark the pa 4778 4778 + * deleted and that can cause direct traversal to skip some entries. 4779 4779 + */ 4778 4780 read_lock(&ei->i_prealloc_lock); 4781 4781 + 4782 4782 + if (RB_EMPTY_ROOT(&ei->i_prealloc_node)) { 4783 4783 + goto try_group_pa; 4784 4784 + } 4785 4785 + 4786 4786 + /* 4787 4787 + * Step 1: Find a pa with logical start immediately adjacent to the 4788 4788 + * original logical start. This could be on the left or right. 4789 4789 + * 4790 4790 + * (tmp_pa->pa_lstart never changes so we can skip locking for it). 4791 4791 + */ 4779 4792 for (iter = ei->i_prealloc_node.rb_node; iter; 4780 4793 iter = ext4_mb_pa_rb_next_iter(ac->ac_o_ex.fe_logical, 4781 4781 - tmp_pa_start, iter)) { 4794 4794 + tmp_pa->pa_lstart, iter)) { 4782 4795 tmp_pa = rb_entry(iter, struct ext4_prealloc_space, 4783 4796 pa_node.inode_node); 4797 4797 + } 4784 4798 4785 4785 - /* all fields in this condition don't change, 4786 4786 - * so we can skip locking for them */ 4787 4787 - tmp_pa_start = tmp_pa->pa_lstart; 4788 4788 - tmp_pa_end = tmp_pa->pa_lstart + EXT4_C2B(sbi, tmp_pa->pa_len); 4799 4799 + /* 4800 4800 + * Step 2: The adjacent pa might be to the right of logical start, find 4801 4801 + * the left adjacent pa. After this step we'd have a valid tmp_pa whose 4802 4802 + * logical start is towards the left of original request's logical start 4803 4803 + */ 4804 4804 + if (tmp_pa->pa_lstart > ac->ac_o_ex.fe_logical) { 4805 4805 + struct rb_node *tmp; 4806 4806 + tmp = rb_prev(&tmp_pa->pa_node.inode_node); 4789 4807 4790 4790 - /* original request start doesn't lie in this PA */ 4791 4791 - if (ac->ac_o_ex.fe_logical < tmp_pa_start || 4792 4792 - ac->ac_o_ex.fe_logical >= tmp_pa_end) 4793 4793 - continue; 4794 4794 - 4795 4795 - /* non-extent files can't have physical blocks past 2^32 */ 4796 4796 - if (!(ext4_test_inode_flag(ac->ac_inode, EXT4_INODE_EXTENTS)) && 4797 4797 - (tmp_pa->pa_pstart + EXT4_C2B(sbi, tmp_pa->pa_len) > 4798 4798 - EXT4_MAX_BLOCK_FILE_PHYS)) { 4808 4808 + if (tmp) { 4809 4809 + tmp_pa = rb_entry(tmp, struct ext4_prealloc_space, 4810 4810 + pa_node.inode_node); 4811 4811 + } else { 4799 4812 /* 4800 4800 - * Since PAs don't overlap, we won't find any 4801 4801 - * other PA to satisfy this. 4813 4813 + * If there is no adjacent pa to the left then finding 4814 4814 + * an overlapping pa is not possible hence stop searching 4815 4815 + * inode pa tree 4816 4816 + */ 4817 4817 + goto try_group_pa; 4818 4818 + } 4819 4819 + } 4820 4820 + 4821 4821 + BUG_ON(!(tmp_pa && tmp_pa->pa_lstart <= ac->ac_o_ex.fe_logical)); 4822 4822 + 4823 4823 + /* 4824 4824 + * Step 3: If the left adjacent pa is deleted, keep moving left to find 4825 4825 + * the first non deleted adjacent pa. After this step we should have a 4826 4826 + * valid tmp_pa which is guaranteed to be non deleted. 4827 4827 + */ 4828 4828 + for (iter = &tmp_pa->pa_node.inode_node;; iter = rb_prev(iter)) { 4829 4829 + if (!iter) { 4830 4830 + /* 4831 4831 + * no non deleted left adjacent pa, so stop searching 4832 4832 + * inode pa tree 4833 4833 + */ 4834 4834 + goto try_group_pa; 4835 4835 + } 4836 4836 + tmp_pa = rb_entry(iter, struct ext4_prealloc_space, 4837 4837 + pa_node.inode_node); 4838 4838 + spin_lock(&tmp_pa->pa_lock); 4839 4839 + if (tmp_pa->pa_deleted == 0) { 4840 4840 + /* 4841 4841 + * We will keep holding the pa_lock from 4842 4842 + * this point on because we don't want group discard 4843 4843 + * to delete this pa underneath us. Since group 4844 4844 + * discard is anyways an ENOSPC operation it 4845 4845 + * should be okay for it to wait a few more cycles. 4802 4846 */ 4803 4847 break; 4804 4804 - } 4805 4805 - 4806 4806 - /* found preallocated blocks, use them */ 4807 4807 - spin_lock(&tmp_pa->pa_lock); 4808 4808 - if (tmp_pa->pa_deleted == 0 && tmp_pa->pa_free && 4809 4809 - likely(ext4_mb_pa_goal_check(ac, tmp_pa))) { 4810 4810 - atomic_inc(&tmp_pa->pa_count); 4811 4811 - ext4_mb_use_inode_pa(ac, tmp_pa); 4848 4848 + } else { 4812 4849 spin_unlock(&tmp_pa->pa_lock); 4813 4813 - read_unlock(&ei->i_prealloc_lock); 4814 4814 - return true; 4815 4850 } 4816 4816 - spin_unlock(&tmp_pa->pa_lock); 4817 4851 } 4852 4852 + 4853 4853 + BUG_ON(!(tmp_pa && tmp_pa->pa_lstart <= ac->ac_o_ex.fe_logical)); 4854 4854 + BUG_ON(tmp_pa->pa_deleted == 1); 4855 4855 + 4856 4856 + /* 4857 4857 + * Step 4: We now have the non deleted left adjacent pa. Only this 4858 4858 + * pa can possibly satisfy the request hence check if it overlaps 4859 4859 + * original logical start and stop searching if it doesn't. 4860 4860 + */ 4861 4861 + tmp_pa_end = (loff_t)tmp_pa->pa_lstart + EXT4_C2B(sbi, tmp_pa->pa_len); 4862 4862 + 4863 4863 + if (ac->ac_o_ex.fe_logical >= tmp_pa_end) { 4864 4864 + spin_unlock(&tmp_pa->pa_lock); 4865 4865 + goto try_group_pa; 4866 4866 + } 4867 4867 + 4868 4868 + /* non-extent files can't have physical blocks past 2^32 */ 4869 4869 + if (!(ext4_test_inode_flag(ac->ac_inode, EXT4_INODE_EXTENTS)) && 4870 4870 + (tmp_pa->pa_pstart + EXT4_C2B(sbi, tmp_pa->pa_len) > 4871 4871 + EXT4_MAX_BLOCK_FILE_PHYS)) { 4872 4872 + /* 4873 4873 + * Since PAs don't overlap, we won't find any other PA to 4874 4874 + * satisfy this. 4875 4875 + */ 4876 4876 + spin_unlock(&tmp_pa->pa_lock); 4877 4877 + goto try_group_pa; 4878 4878 + } 4879 4879 + 4880 4880 + if (tmp_pa->pa_free && likely(ext4_mb_pa_goal_check(ac, tmp_pa))) { 4881 4881 + atomic_inc(&tmp_pa->pa_count); 4882 4882 + ext4_mb_use_inode_pa(ac, tmp_pa); 4883 4883 + spin_unlock(&tmp_pa->pa_lock); 4884 4884 + read_unlock(&ei->i_prealloc_lock); 4885 4885 + return true; 4886 4886 + } else { 4887 4887 + /* 4888 4888 + * We found a valid overlapping pa but couldn't use it because 4889 4889 + * it had no free blocks. This should ideally never happen 4890 4890 + * because: 4891 4891 + * 4892 4892 + * 1. When a new inode pa is added to rbtree it must have 4893 4893 + * pa_free > 0 since otherwise we won't actually need 4894 4894 + * preallocation. 4895 4895 + * 4896 4896 + * 2. An inode pa that is in the rbtree can only have it's 4897 4897 + * pa_free become zero when another thread calls: 4898 4898 + * ext4_mb_new_blocks 4899 4899 + * ext4_mb_use_preallocated 4900 4900 + * ext4_mb_use_inode_pa 4901 4901 + * 4902 4902 + * 3. Further, after the above calls make pa_free == 0, we will 4903 4903 + * immediately remove it from the rbtree in: 4904 4904 + * ext4_mb_new_blocks 4905 4905 + * ext4_mb_release_context 4906 4906 + * ext4_mb_put_pa 4907 4907 + * 4908 4908 + * 4. Since the pa_free becoming 0 and pa_free getting removed 4909 4909 + * from tree both happen in ext4_mb_new_blocks, which is always 4910 4910 + * called with i_data_sem held for data allocations, we can be 4911 4911 + * sure that another process will never see a pa in rbtree with 4912 4912 + * pa_free == 0. 4913 4913 + */ 4914 4914 + WARN_ON_ONCE(tmp_pa->pa_free == 0); 4915 4915 + } 4916 4916 + spin_unlock(&tmp_pa->pa_lock); 4917 4917 + try_group_pa: 4818 4918 read_unlock(&ei->i_prealloc_lock); 4819 4919 4820 4920 /* can we use group allocation? */

+14

fs/ext4/xattr.c

reviewed

··· 1782 1782 memmove(here, (void *)here + size, 1783 1783 (void *)last - (void *)here + sizeof(__u32)); 1784 1784 memset(last, 0, size); 1785 1785 + 1786 1786 + /* 1787 1787 + * Update i_inline_off - moved ibody region might contain 1788 1788 + * system.data attribute. Handling a failure here won't 1789 1789 + * cause other complications for setting an xattr. 1790 1790 + */ 1791 1791 + if (!is_block && ext4_has_inline_data(inode)) { 1792 1792 + ret = ext4_find_inline_data_nolock(inode); 1793 1793 + if (ret) { 1794 1794 + ext4_warning_inode(inode, 1795 1795 + "unable to update i_inline_off"); 1796 1796 + goto out; 1797 1797 + } 1798 1798 + } 1785 1799 } else if (s->not_found) { 1786 1800 /* Insert new name. */ 1787 1801 size_t size = EXT4_XATTR_LEN(name_len);

+2 -4

fs/file.c

reviewed

··· 1042 1042 struct file *file = (struct file *)(v & ~3); 1043 1043 1044 1044 if (file && (file->f_mode & FMODE_ATOMIC_POS)) { 1045 1045 - if (file_count(file) > 1) { 1046 1046 - v |= FDPUT_POS_UNLOCK; 1047 1047 - mutex_lock(&file->f_pos_lock); 1048 1048 - } 1045 1045 + v |= FDPUT_POS_UNLOCK; 1046 1046 + mutex_lock(&file->f_pos_lock); 1049 1047 } 1050 1048 return v; 1051 1049 }

+100 -189

fs/jbd2/checkpoint.c

reviewed

··· 27 27 * 28 28 * Called with j_list_lock held. 29 29 */ 30 30 - static inline void __buffer_unlink_first(struct journal_head *jh) 30 30 + static inline void __buffer_unlink(struct journal_head *jh) 31 31 { 32 32 transaction_t *transaction = jh->b_cp_transaction; 33 33 ··· 38 38 if (transaction->t_checkpoint_list == jh) 39 39 transaction->t_checkpoint_list = NULL; 40 40 } 41 41 - } 42 42 - 43 43 - /* 44 44 - * Unlink a buffer from a transaction checkpoint(io) list. 45 45 - * 46 46 - * Called with j_list_lock held. 47 47 - */ 48 48 - static inline void __buffer_unlink(struct journal_head *jh) 49 49 - { 50 50 - transaction_t *transaction = jh->b_cp_transaction; 51 51 - 52 52 - __buffer_unlink_first(jh); 53 53 - if (transaction->t_checkpoint_io_list == jh) { 54 54 - transaction->t_checkpoint_io_list = jh->b_cpnext; 55 55 - if (transaction->t_checkpoint_io_list == jh) 56 56 - transaction->t_checkpoint_io_list = NULL; 57 57 - } 58 58 - } 59 59 - 60 60 - /* 61 61 - * Move a buffer from the checkpoint list to the checkpoint io list 62 62 - * 63 63 - * Called with j_list_lock held 64 64 - */ 65 65 - static inline void __buffer_relink_io(struct journal_head *jh) 66 66 - { 67 67 - transaction_t *transaction = jh->b_cp_transaction; 68 68 - 69 69 - __buffer_unlink_first(jh); 70 70 - 71 71 - if (!transaction->t_checkpoint_io_list) { 72 72 - jh->b_cpnext = jh->b_cpprev = jh; 73 73 - } else { 74 74 - jh->b_cpnext = transaction->t_checkpoint_io_list; 75 75 - jh->b_cpprev = transaction->t_checkpoint_io_list->b_cpprev; 76 76 - jh->b_cpprev->b_cpnext = jh; 77 77 - jh->b_cpnext->b_cpprev = jh; 78 78 - } 79 79 - transaction->t_checkpoint_io_list = jh; 80 41 } 81 42 82 43 /* ··· 144 183 struct buffer_head *bh = journal->j_chkpt_bhs[i]; 145 184 BUFFER_TRACE(bh, "brelse"); 146 185 __brelse(bh); 186 186 + journal->j_chkpt_bhs[i] = NULL; 147 187 } 148 188 *batch_count = 0; 149 189 } ··· 204 242 jh = transaction->t_checkpoint_list; 205 243 bh = jh2bh(jh); 206 244 207 207 - if (buffer_locked(bh)) { 208 208 - get_bh(bh); 209 209 - spin_unlock(&journal->j_list_lock); 210 210 - wait_on_buffer(bh); 211 211 - /* the journal_head may have gone by now */ 212 212 - BUFFER_TRACE(bh, "brelse"); 213 213 - __brelse(bh); 214 214 - goto retry; 215 215 - } 216 245 if (jh->b_transaction != NULL) { 217 246 transaction_t *t = jh->b_transaction; 218 247 tid_t tid = t->t_tid; ··· 238 285 spin_lock(&journal->j_list_lock); 239 286 goto restart; 240 287 } 241 241 - if (!buffer_dirty(bh)) { 288 288 + if (!trylock_buffer(bh)) { 289 289 + /* 290 290 + * The buffer is locked, it may be writing back, or 291 291 + * flushing out in the last couple of cycles, or 292 292 + * re-adding into a new transaction, need to check 293 293 + * it again until it's unlocked. 294 294 + */ 295 295 + get_bh(bh); 296 296 + spin_unlock(&journal->j_list_lock); 297 297 + wait_on_buffer(bh); 298 298 + /* the journal_head may have gone by now */ 299 299 + BUFFER_TRACE(bh, "brelse"); 300 300 + __brelse(bh); 301 301 + goto retry; 302 302 + } else if (!buffer_dirty(bh)) { 303 303 + unlock_buffer(bh); 242 304 BUFFER_TRACE(bh, "remove from checkpoint"); 243 243 - if (__jbd2_journal_remove_checkpoint(jh)) 244 244 - /* The transaction was released; we're done */ 305 305 + /* 306 306 + * If the transaction was released or the checkpoint 307 307 + * list was empty, we're done. 308 308 + */ 309 309 + if (__jbd2_journal_remove_checkpoint(jh) || 310 310 + !transaction->t_checkpoint_list) 245 311 goto out; 246 246 - continue; 312 312 + } else { 313 313 + unlock_buffer(bh); 314 314 + /* 315 315 + * We are about to write the buffer, it could be 316 316 + * raced by some other transaction shrink or buffer 317 317 + * re-log logic once we release the j_list_lock, 318 318 + * leave it on the checkpoint list and check status 319 319 + * again to make sure it's clean. 320 320 + */ 321 321 + BUFFER_TRACE(bh, "queue"); 322 322 + get_bh(bh); 323 323 + J_ASSERT_BH(bh, !buffer_jwrite(bh)); 324 324 + journal->j_chkpt_bhs[batch_count++] = bh; 325 325 + transaction->t_chp_stats.cs_written++; 326 326 + transaction->t_checkpoint_list = jh->b_cpnext; 247 327 } 248 248 - /* 249 249 - * Important: we are about to write the buffer, and 250 250 - * possibly block, while still holding the journal 251 251 - * lock. We cannot afford to let the transaction 252 252 - * logic start messing around with this buffer before 253 253 - * we write it to disk, as that would break 254 254 - * recoverability. 255 255 - */ 256 256 - BUFFER_TRACE(bh, "queue"); 257 257 - get_bh(bh); 258 258 - J_ASSERT_BH(bh, !buffer_jwrite(bh)); 259 259 - journal->j_chkpt_bhs[batch_count++] = bh; 260 260 - __buffer_relink_io(jh); 261 261 - transaction->t_chp_stats.cs_written++; 328 328 + 262 329 if ((batch_count == JBD2_NR_BATCH) || 263 263 - need_resched() || 264 264 - spin_needbreak(&journal->j_list_lock)) 330 330 + need_resched() || spin_needbreak(&journal->j_list_lock) || 331 331 + jh2bh(transaction->t_checkpoint_list) == journal->j_chkpt_bhs[0]) 265 332 goto unlock_and_flush; 266 333 } 267 334 ··· 295 322 goto restart; 296 323 } 297 324 298 298 - /* 299 299 - * Now we issued all of the transaction's buffers, let's deal 300 300 - * with the buffers that are out for I/O. 301 301 - */ 302 302 - restart2: 303 303 - /* Did somebody clean up the transaction in the meanwhile? */ 304 304 - if (journal->j_checkpoint_transactions != transaction || 305 305 - transaction->t_tid != this_tid) 306 306 - goto out; 307 307 - 308 308 - while (transaction->t_checkpoint_io_list) { 309 309 - jh = transaction->t_checkpoint_io_list; 310 310 - bh = jh2bh(jh); 311 311 - if (buffer_locked(bh)) { 312 312 - get_bh(bh); 313 313 - spin_unlock(&journal->j_list_lock); 314 314 - wait_on_buffer(bh); 315 315 - /* the journal_head may have gone by now */ 316 316 - BUFFER_TRACE(bh, "brelse"); 317 317 - __brelse(bh); 318 318 - spin_lock(&journal->j_list_lock); 319 319 - goto restart2; 320 320 - } 321 321 - 322 322 - /* 323 323 - * Now in whatever state the buffer currently is, we 324 324 - * know that it has been written out and so we can 325 325 - * drop it from the list 326 326 - */ 327 327 - if (__jbd2_journal_remove_checkpoint(jh)) 328 328 - break; 329 329 - } 330 325 out: 331 326 spin_unlock(&journal->j_list_lock); 332 327 result = jbd2_cleanup_journal_tail(journal); ··· 350 409 /* Checkpoint list management */ 351 410 352 411 /* 353 353 - * journal_clean_one_cp_list 412 412 + * journal_shrink_one_cp_list 354 413 * 355 355 - * Find all the written-back checkpoint buffers in the given list and 356 356 - * release them. If 'destroy' is set, clean all buffers unconditionally. 414 414 + * Find all the written-back checkpoint buffers in the given list 415 415 + * and try to release them. If the whole transaction is released, set 416 416 + * the 'released' parameter. Return the number of released checkpointed 417 417 + * buffers. 357 418 * 358 419 * Called with j_list_lock held. 359 359 - * Returns 1 if we freed the transaction, 0 otherwise. 360 420 */ 361 361 - static int journal_clean_one_cp_list(struct journal_head *jh, bool destroy) 421 421 + static unsigned long journal_shrink_one_cp_list(struct journal_head *jh, 422 422 + bool destroy, bool *released) 362 423 { 363 424 struct journal_head *last_jh; 364 425 struct journal_head *next_jh = jh; 426 426 + unsigned long nr_freed = 0; 427 427 + int ret; 365 428 429 429 + *released = false; 366 430 if (!jh) 367 431 return 0; 368 432 ··· 376 430 jh = next_jh; 377 431 next_jh = jh->b_cpnext; 378 432 379 379 - if (!destroy && __cp_buffer_busy(jh)) 380 380 - return 0; 381 381 - 382 382 - if (__jbd2_journal_remove_checkpoint(jh)) 383 383 - return 1; 384 384 - /* 385 385 - * This function only frees up some memory 386 386 - * if possible so we dont have an obligation 387 387 - * to finish processing. Bail out if preemption 388 388 - * requested: 389 389 - */ 390 390 - if (need_resched()) 391 391 - return 0; 392 392 - } while (jh != last_jh); 393 393 - 394 394 - return 0; 395 395 - } 396 396 - 397 397 - /* 398 398 - * journal_shrink_one_cp_list 399 399 - * 400 400 - * Find 'nr_to_scan' written-back checkpoint buffers in the given list 401 401 - * and try to release them. If the whole transaction is released, set 402 402 - * the 'released' parameter. Return the number of released checkpointed 403 403 - * buffers. 404 404 - * 405 405 - * Called with j_list_lock held. 406 406 - */ 407 407 - static unsigned long journal_shrink_one_cp_list(struct journal_head *jh, 408 408 - unsigned long *nr_to_scan, 409 409 - bool *released) 410 410 - { 411 411 - struct journal_head *last_jh; 412 412 - struct journal_head *next_jh = jh; 413 413 - unsigned long nr_freed = 0; 414 414 - int ret; 415 415 - 416 416 - if (!jh || *nr_to_scan == 0) 417 417 - return 0; 418 418 - 419 419 - last_jh = jh->b_cpprev; 420 420 - do { 421 421 - jh = next_jh; 422 422 - next_jh = jh->b_cpnext; 423 423 - 424 424 - (*nr_to_scan)--; 425 425 - if (__cp_buffer_busy(jh)) 426 426 - continue; 433 433 + if (destroy) { 434 434 + ret = __jbd2_journal_remove_checkpoint(jh); 435 435 + } else { 436 436 + ret = jbd2_journal_try_remove_checkpoint(jh); 437 437 + if (ret < 0) 438 438 + continue; 439 439 + } 427 440 428 441 nr_freed++; 429 429 - ret = __jbd2_journal_remove_checkpoint(jh); 430 442 if (ret) { 431 443 *released = true; 432 444 break; ··· 392 488 393 489 if (need_resched()) 394 490 break; 395 395 - } while (jh != last_jh && *nr_to_scan); 491 491 + } while (jh != last_jh); 396 492 397 493 return nr_freed; 398 494 } ··· 410 506 unsigned long *nr_to_scan) 411 507 { 412 508 transaction_t *transaction, *last_transaction, *next_transaction; 413 413 - bool released; 509 509 + bool __maybe_unused released; 414 510 tid_t first_tid = 0, last_tid = 0, next_tid = 0; 415 511 tid_t tid = 0; 416 512 unsigned long nr_freed = 0; 417 417 - unsigned long nr_scanned = *nr_to_scan; 513 513 + unsigned long freed; 418 514 419 515 again: 420 516 spin_lock(&journal->j_list_lock); ··· 443 539 transaction = next_transaction; 444 540 next_transaction = transaction->t_cpnext; 445 541 tid = transaction->t_tid; 446 446 - released = false; 447 542 448 448 - nr_freed += journal_shrink_one_cp_list(transaction->t_checkpoint_list, 449 449 - nr_to_scan, &released); 450 450 - if (*nr_to_scan == 0) 451 451 - break; 452 452 - if (need_resched() || spin_needbreak(&journal->j_list_lock)) 453 453 - break; 454 454 - if (released) 455 455 - continue; 456 456 - 457 457 - nr_freed += journal_shrink_one_cp_list(transaction->t_checkpoint_io_list, 458 458 - nr_to_scan, &released); 543 543 + freed = journal_shrink_one_cp_list(transaction->t_checkpoint_list, 544 544 + false, &released); 545 545 + nr_freed += freed; 546 546 + (*nr_to_scan) -= min(*nr_to_scan, freed); 459 547 if (*nr_to_scan == 0) 460 548 break; 461 549 if (need_resched() || spin_needbreak(&journal->j_list_lock)) ··· 468 572 if (*nr_to_scan && next_tid) 469 573 goto again; 470 574 out: 471 471 - nr_scanned -= *nr_to_scan; 472 575 trace_jbd2_shrink_checkpoint_list(journal, first_tid, tid, last_tid, 473 473 - nr_freed, nr_scanned, next_tid); 576 576 + nr_freed, next_tid); 474 577 475 578 return nr_freed; 476 579 } ··· 485 590 void __jbd2_journal_clean_checkpoint_list(journal_t *journal, bool destroy) 486 591 { 487 592 transaction_t *transaction, *last_transaction, *next_transaction; 488 488 - int ret; 593 593 + bool released; 489 594 490 595 transaction = journal->j_checkpoint_transactions; 491 596 if (!transaction) ··· 496 601 do { 497 602 transaction = next_transaction; 498 603 next_transaction = transaction->t_cpnext; 499 499 - ret = journal_clean_one_cp_list(transaction->t_checkpoint_list, 500 500 - destroy); 604 604 + journal_shrink_one_cp_list(transaction->t_checkpoint_list, 605 605 + destroy, &released); 501 606 /* 502 607 * This function only frees up some memory if possible so we 503 608 * dont have an obligation to finish processing. Bail out if ··· 505 610 */ 506 611 if (need_resched()) 507 612 return; 508 508 - if (ret) 509 509 - continue; 510 510 - /* 511 511 - * It is essential that we are as careful as in the case of 512 512 - * t_checkpoint_list with removing the buffer from the list as 513 513 - * we can possibly see not yet submitted buffers on io_list 514 514 - */ 515 515 - ret = journal_clean_one_cp_list(transaction-> 516 516 - t_checkpoint_io_list, destroy); 517 517 - if (need_resched()) 518 518 - return; 519 613 /* 520 614 * Stop scanning if we couldn't free the transaction. This 521 615 * avoids pointless scanning of transactions which still 522 616 * weren't checkpointed. 523 617 */ 524 524 - if (!ret) 618 618 + if (!released) 525 619 return; 526 620 } while (transaction != last_transaction); 527 621 } ··· 589 705 jbd2_journal_put_journal_head(jh); 590 706 591 707 /* Is this transaction empty? */ 592 592 - if (transaction->t_checkpoint_list || transaction->t_checkpoint_io_list) 708 708 + if (transaction->t_checkpoint_list) 593 709 return 0; 594 710 595 711 /* ··· 618 734 __jbd2_journal_drop_transaction(journal, transaction); 619 735 jbd2_journal_free_transaction(transaction); 620 736 return 1; 737 737 + } 738 738 + 739 739 + /* 740 740 + * Check the checkpoint buffer and try to remove it from the checkpoint 741 741 + * list if it's clean. Returns -EBUSY if it is not clean, returns 1 if 742 742 + * it frees the transaction, 0 otherwise. 743 743 + * 744 744 + * This function is called with j_list_lock held. 745 745 + */ 746 746 + int jbd2_journal_try_remove_checkpoint(struct journal_head *jh) 747 747 + { 748 748 + struct buffer_head *bh = jh2bh(jh); 749 749 + 750 750 + if (!trylock_buffer(bh)) 751 751 + return -EBUSY; 752 752 + if (buffer_dirty(bh)) { 753 753 + unlock_buffer(bh); 754 754 + return -EBUSY; 755 755 + } 756 756 + unlock_buffer(bh); 757 757 + 758 758 + /* 759 759 + * Buffer is clean and the IO has finished (we held the buffer 760 760 + * lock) so the checkpoint is done. We can safely remove the 761 761 + * buffer from this transaction. 762 762 + */ 763 763 + JBUFFER_TRACE(jh, "remove from checkpoint list"); 764 764 + return __jbd2_journal_remove_checkpoint(jh); 621 765 } 622 766 623 767 /* ··· 709 797 J_ASSERT(transaction->t_forget == NULL); 710 798 J_ASSERT(transaction->t_shadow_list == NULL); 711 799 J_ASSERT(transaction->t_checkpoint_list == NULL); 712 712 - J_ASSERT(transaction->t_checkpoint_io_list == NULL); 713 800 J_ASSERT(atomic_read(&transaction->t_updates) == 0); 714 801 J_ASSERT(journal->j_committing_transaction != transaction); 715 802 J_ASSERT(journal->j_running_transaction != transaction);

+1 -2

fs/jbd2/commit.c

reviewed

··· 1141 1141 spin_lock(&journal->j_list_lock); 1142 1142 commit_transaction->t_state = T_FINISHED; 1143 1143 /* Check if the transaction can be dropped now that we are finished */ 1144 1144 - if (commit_transaction->t_checkpoint_list == NULL && 1145 1145 - commit_transaction->t_checkpoint_io_list == NULL) { 1144 1144 + if (commit_transaction->t_checkpoint_list == NULL) { 1146 1145 __jbd2_journal_drop_transaction(journal, commit_transaction); 1147 1146 jbd2_journal_free_transaction(commit_transaction); 1148 1147 }

+8 -32

fs/jbd2/transaction.c

reviewed

··· 1784 1784 * Otherwise, if the buffer has been written to disk, 1785 1785 * it is safe to remove the checkpoint and drop it. 1786 1786 */ 1787 1787 - if (!buffer_dirty(bh)) { 1788 1788 - __jbd2_journal_remove_checkpoint(jh); 1787 1787 + if (jbd2_journal_try_remove_checkpoint(jh) >= 0) { 1789 1788 spin_unlock(&journal->j_list_lock); 1790 1789 goto drop; 1791 1790 } ··· 2099 2100 __brelse(bh); 2100 2101 } 2101 2102 2102 2102 - /* 2103 2103 - * Called from jbd2_journal_try_to_free_buffers(). 2104 2104 - * 2105 2105 - * Called under jh->b_state_lock 2106 2106 - */ 2107 2107 - static void 2108 2108 - __journal_try_to_free_buffer(journal_t *journal, struct buffer_head *bh) 2109 2109 - { 2110 2110 - struct journal_head *jh; 2111 2111 - 2112 2112 - jh = bh2jh(bh); 2113 2113 - 2114 2114 - if (buffer_locked(bh) || buffer_dirty(bh)) 2115 2115 - goto out; 2116 2116 - 2117 2117 - if (jh->b_next_transaction != NULL || jh->b_transaction != NULL) 2118 2118 - goto out; 2119 2119 - 2120 2120 - spin_lock(&journal->j_list_lock); 2121 2121 - if (jh->b_cp_transaction != NULL) { 2122 2122 - /* written-back checkpointed metadata buffer */ 2123 2123 - JBUFFER_TRACE(jh, "remove from checkpoint list"); 2124 2124 - __jbd2_journal_remove_checkpoint(jh); 2125 2125 - } 2126 2126 - spin_unlock(&journal->j_list_lock); 2127 2127 - out: 2128 2128 - return; 2129 2129 - } 2130 2130 - 2131 2103 /** 2132 2104 * jbd2_journal_try_to_free_buffers() - try to free page buffers. 2133 2105 * @journal: journal for operation ··· 2156 2186 continue; 2157 2187 2158 2188 spin_lock(&jh->b_state_lock); 2159 2159 - __journal_try_to_free_buffer(journal, bh); 2189 2189 + if (!jh->b_transaction && !jh->b_next_transaction) { 2190 2190 + spin_lock(&journal->j_list_lock); 2191 2191 + /* Remove written-back checkpointed metadata buffer */ 2192 2192 + if (jh->b_cp_transaction != NULL) 2193 2193 + jbd2_journal_try_remove_checkpoint(jh); 2194 2194 + spin_unlock(&journal->j_list_lock); 2195 2195 + } 2160 2196 spin_unlock(&jh->b_state_lock); 2161 2197 jbd2_journal_put_journal_head(jh); 2162 2198 if (buffer_jbd(bh))

-2

fs/nfsd/nfs4state.c

reviewed

··· 6341 6341 if (ZERO_STATEID(stateid) || ONE_STATEID(stateid) || 6342 6342 CLOSE_STATEID(stateid)) 6343 6343 return status; 6344 6344 - if (!same_clid(&stateid->si_opaque.so_clid, &cl->cl_clientid)) 6345 6345 - return status; 6346 6344 spin_lock(&cl->cl_lock); 6347 6345 s = find_stateid_locked(cl, stateid); 6348 6346 if (!s)

+1 -1

fs/overlayfs/super.c

reviewed

··· 1460 1460 ovl_trusted_xattr_handlers; 1461 1461 sb->s_fs_info = ofs; 1462 1462 sb->s_flags |= SB_POSIXACL; 1463 1463 - sb->s_iflags |= SB_I_SKIP_SYNC; 1463 1463 + sb->s_iflags |= SB_I_SKIP_SYNC | SB_I_IMA_UNVERIFIABLE_SIGNATURE; 1464 1464 1465 1465 err = -ENOMEM; 1466 1466 root_dentry = ovl_get_root(sb, ctx->upper.dentry, oe);

+2 -2

fs/smb/client/cifsfs.h

reviewed

··· 159 159 #endif /* CONFIG_CIFS_NFSD_EXPORT */ 160 160 161 161 /* when changing internal version - update following two lines at same time */ 162 162 - #define SMB3_PRODUCT_BUILD 43 163 163 - #define CIFS_VERSION "2.43" 162 162 + #define SMB3_PRODUCT_BUILD 44 163 163 + #define CIFS_VERSION "2.44" 164 164 #endif /* _CIFSFS_H */

+13 -4

fs/smb/client/ioctl.c

reviewed

··· 433 433 * Dump encryption keys. This is an old ioctl that only 434 434 * handles AES-128-{CCM,GCM}. 435 435 */ 436 436 - if (pSMBFile == NULL) 437 437 - break; 438 436 if (!capable(CAP_SYS_ADMIN)) { 439 437 rc = -EACCES; 440 438 break; 441 439 } 442 440 443 443 - tcon = tlink_tcon(pSMBFile->tlink); 441 441 + cifs_sb = CIFS_SB(inode->i_sb); 442 442 + tlink = cifs_sb_tlink(cifs_sb); 443 443 + if (IS_ERR(tlink)) { 444 444 + rc = PTR_ERR(tlink); 445 445 + break; 446 446 + } 447 447 + tcon = tlink_tcon(tlink); 444 448 if (!smb3_encryption_required(tcon)) { 445 449 rc = -EOPNOTSUPP; 450 450 + cifs_put_tlink(tlink); 446 451 break; 447 452 } 448 453 pkey_inf.cipher_type = ··· 464 459 rc = -EFAULT; 465 460 else 466 461 rc = 0; 462 462 + cifs_put_tlink(tlink); 467 463 break; 468 464 case CIFS_DUMP_FULL_KEY: 469 465 /* ··· 476 470 rc = -EACCES; 477 471 break; 478 472 } 479 479 - tcon = tlink_tcon(pSMBFile->tlink); 473 473 + cifs_sb = CIFS_SB(inode->i_sb); 474 474 + tlink = cifs_sb_tlink(cifs_sb); 475 475 + tcon = tlink_tcon(tlink); 480 476 rc = cifs_dump_full_key(tcon, (void __user *)arg); 477 477 + cifs_put_tlink(tlink); 481 478 break; 482 479 case CIFS_IOC_NOTIFY: 483 480 if (!S_ISDIR(inode->i_mode)) {

+2 -1

fs/smb/server/ksmbd_netlink.h

reviewed

··· 352 352 #define KSMBD_SHARE_FLAG_STREAMS BIT(11) 353 353 #define KSMBD_SHARE_FLAG_FOLLOW_SYMLINKS BIT(12) 354 354 #define KSMBD_SHARE_FLAG_ACL_XATTR BIT(13) 355 355 - #define KSMBD_SHARE_FLAG_UPDATE BIT(14) 355 355 + #define KSMBD_SHARE_FLAG_UPDATE BIT(14) 356 356 + #define KSMBD_SHARE_FLAG_CROSSMNT BIT(15) 356 357 357 358 /* 358 359 * Tree connect request flags.

+6 -1

fs/smb/server/server.c

reviewed

··· 286 286 static int queue_ksmbd_work(struct ksmbd_conn *conn) 287 287 { 288 288 struct ksmbd_work *work; 289 289 + int err; 289 290 290 291 work = ksmbd_alloc_work_struct(); 291 292 if (!work) { ··· 298 297 work->request_buf = conn->request_buf; 299 298 conn->request_buf = NULL; 300 299 301 301 - ksmbd_init_smb_server(work); 300 300 + err = ksmbd_init_smb_server(work); 301 301 + if (err) { 302 302 + ksmbd_free_work_struct(work); 303 303 + return 0; 304 304 + } 302 305 303 306 ksmbd_conn_enqueue_request(work); 304 307 atomic_inc(&conn->r_count);

+29 -18

fs/smb/server/smb2pdu.c

reviewed

··· 87 87 */ 88 88 int smb2_get_ksmbd_tcon(struct ksmbd_work *work) 89 89 { 90 90 - struct smb2_hdr *req_hdr = smb2_get_msg(work->request_buf); 90 90 + struct smb2_hdr *req_hdr = ksmbd_req_buf_next(work); 91 91 unsigned int cmd = le16_to_cpu(req_hdr->Command); 92 92 - int tree_id; 92 92 + unsigned int tree_id; 93 93 94 94 if (cmd == SMB2_TREE_CONNECT_HE || 95 95 cmd == SMB2_CANCEL_HE || ··· 114 114 pr_err("The first operation in the compound does not have tcon\n"); 115 115 return -EINVAL; 116 116 } 117 117 - if (work->tcon->id != tree_id) { 117 117 + if (tree_id != UINT_MAX && work->tcon->id != tree_id) { 118 118 pr_err("tree id(%u) is different with id(%u) in first operation\n", 119 119 tree_id, work->tcon->id); 120 120 return -EINVAL; ··· 559 559 */ 560 560 int smb2_check_user_session(struct ksmbd_work *work) 561 561 { 562 562 - struct smb2_hdr *req_hdr = smb2_get_msg(work->request_buf); 562 562 + struct smb2_hdr *req_hdr = ksmbd_req_buf_next(work); 563 563 struct ksmbd_conn *conn = work->conn; 564 564 - unsigned int cmd = conn->ops->get_cmd_val(work); 564 564 + unsigned int cmd = le16_to_cpu(req_hdr->Command); 565 565 unsigned long long sess_id; 566 566 567 567 /* ··· 587 587 pr_err("The first operation in the compound does not have sess\n"); 588 588 return -EINVAL; 589 589 } 590 590 - if (work->sess->id != sess_id) { 590 590 + if (sess_id != ULLONG_MAX && work->sess->id != sess_id) { 591 591 pr_err("session id(%llu) is different with the first operation(%lld)\n", 592 592 sess_id, work->sess->id); 593 593 return -EINVAL; ··· 2467 2467 } 2468 2468 } 2469 2469 2470 2470 - static int smb2_creat(struct ksmbd_work *work, struct path *path, char *name, 2471 2471 - int open_flags, umode_t posix_mode, bool is_dir) 2470 2470 + static int smb2_creat(struct ksmbd_work *work, struct path *parent_path, 2471 2471 + struct path *path, char *name, int open_flags, 2472 2472 + umode_t posix_mode, bool is_dir) 2472 2473 { 2473 2474 struct ksmbd_tree_connect *tcon = work->tcon; 2474 2475 struct ksmbd_share_config *share = tcon->share_conf; ··· 2496 2495 return rc; 2497 2496 } 2498 2497 2499 2499 - rc = ksmbd_vfs_kern_path_locked(work, name, 0, path, 0); 2498 2498 + rc = ksmbd_vfs_kern_path_locked(work, name, 0, parent_path, path, 0); 2500 2499 if (rc) { 2501 2500 pr_err("cannot get linux path (%s), err = %d\n", 2502 2501 name, rc); ··· 2566 2565 struct ksmbd_tree_connect *tcon = work->tcon; 2567 2566 struct smb2_create_req *req; 2568 2567 struct smb2_create_rsp *rsp; 2569 2569 - struct path path; 2568 2568 + struct path path, parent_path; 2570 2569 struct ksmbd_share_config *share = tcon->share_conf; 2571 2570 struct ksmbd_file *fp = NULL; 2572 2571 struct file *filp = NULL; ··· 2787 2786 goto err_out1; 2788 2787 } 2789 2788 2790 2790 - rc = ksmbd_vfs_kern_path_locked(work, name, LOOKUP_NO_SYMLINKS, &path, 1); 2789 2789 + rc = ksmbd_vfs_kern_path_locked(work, name, LOOKUP_NO_SYMLINKS, 2790 2790 + &parent_path, &path, 1); 2791 2791 if (!rc) { 2792 2792 file_present = true; 2793 2793 ··· 2908 2906 2909 2907 /*create file if not present */ 2910 2908 if (!file_present) { 2911 2911 - rc = smb2_creat(work, &path, name, open_flags, posix_mode, 2909 2909 + rc = smb2_creat(work, &parent_path, &path, name, open_flags, 2910 2910 + posix_mode, 2912 2911 req->CreateOptions & FILE_DIRECTORY_FILE_LE); 2913 2912 if (rc) { 2914 2913 if (rc == -ENOENT) { ··· 3324 3321 3325 3322 err_out: 3326 3323 if (file_present || created) { 3327 3327 - inode_unlock(d_inode(path.dentry->d_parent)); 3328 3328 - dput(path.dentry); 3324 3324 + inode_unlock(d_inode(parent_path.dentry)); 3325 3325 + path_put(&path); 3326 3326 + path_put(&parent_path); 3329 3327 } 3330 3328 ksmbd_revert_fsids(work); 3331 3329 err_out1: ··· 5549 5545 struct nls_table *local_nls) 5550 5546 { 5551 5547 char *link_name = NULL, *target_name = NULL, *pathname = NULL; 5552 5552 - struct path path; 5548 5548 + struct path path, parent_path; 5553 5549 bool file_present = false; 5554 5550 int rc; 5555 5551 ··· 5579 5575 5580 5576 ksmbd_debug(SMB, "target name is %s\n", target_name); 5581 5577 rc = ksmbd_vfs_kern_path_locked(work, link_name, LOOKUP_NO_SYMLINKS, 5582 5582 - &path, 0); 5578 5578 + &parent_path, &path, 0); 5583 5579 if (rc) { 5584 5580 if (rc != -ENOENT) 5585 5581 goto out; ··· 5609 5605 rc = -EINVAL; 5610 5606 out: 5611 5607 if (file_present) { 5612 5612 - inode_unlock(d_inode(path.dentry->d_parent)); 5608 5608 + inode_unlock(d_inode(parent_path.dentry)); 5613 5609 path_put(&path); 5610 5610 + path_put(&parent_path); 5614 5611 } 5615 5612 if (!IS_ERR(link_name)) 5616 5613 kfree(link_name); ··· 6214 6209 unsigned int max_read_size = conn->vals->max_read_size; 6215 6210 6216 6211 WORK_BUFFERS(work, req, rsp); 6212 6212 + if (work->next_smb2_rcv_hdr_off) { 6213 6213 + work->send_no_response = 1; 6214 6214 + err = -EOPNOTSUPP; 6215 6215 + goto out; 6216 6216 + } 6217 6217 6218 6218 if (test_share_config_flag(work->tcon->share_conf, 6219 6219 KSMBD_SHARE_FLAG_PIPE)) { ··· 8619 8609 struct smb2_transform_hdr *tr_hdr = smb2_get_msg(buf); 8620 8610 int rc = 0; 8621 8611 8622 8622 - if (buf_data_size < sizeof(struct smb2_hdr)) { 8612 8612 + if (pdu_length < sizeof(struct smb2_transform_hdr) || 8613 8613 + buf_data_size < sizeof(struct smb2_hdr)) { 8623 8614 pr_err("Transform message is too small (%u)\n", 8624 8615 pdu_length); 8625 8616 return -ECONNABORTED;

+11 -8

fs/smb/server/smb_common.c

reviewed

··· 388 388 [SMB_COM_NEGOTIATE_EX] = { .proc = smb1_negotiate, }, 389 389 }; 390 390 391 391 - static void init_smb1_server(struct ksmbd_conn *conn) 391 391 + static int init_smb1_server(struct ksmbd_conn *conn) 392 392 { 393 393 conn->ops = &smb1_server_ops; 394 394 conn->cmds = smb1_server_cmds; 395 395 conn->max_cmds = ARRAY_SIZE(smb1_server_cmds); 396 396 + return 0; 396 397 } 397 398 398 398 - void ksmbd_init_smb_server(struct ksmbd_work *work) 399 399 + int ksmbd_init_smb_server(struct ksmbd_work *work) 399 400 { 400 401 struct ksmbd_conn *conn = work->conn; 401 402 __le32 proto; 402 403 403 403 - if (conn->need_neg == false) 404 404 - return; 405 405 - 406 404 proto = *(__le32 *)((struct smb_hdr *)work->request_buf)->Protocol; 405 405 + if (conn->need_neg == false) { 406 406 + if (proto == SMB1_PROTO_NUMBER) 407 407 + return -EINVAL; 408 408 + return 0; 409 409 + } 410 410 + 407 411 if (proto == SMB1_PROTO_NUMBER) 408 408 - init_smb1_server(conn); 409 409 - else 410 410 - init_smb3_11_server(conn); 412 412 + return init_smb1_server(conn); 413 413 + return init_smb3_11_server(conn); 411 414 } 412 415 413 416 int ksmbd_populate_dot_dotdot_entries(struct ksmbd_work *work, int info_level,

+1 -1

fs/smb/server/smb_common.h

reviewed

··· 427 427 428 428 int ksmbd_lookup_dialect_by_id(__le16 *cli_dialects, __le16 dialects_count); 429 429 430 430 - void ksmbd_init_smb_server(struct ksmbd_work *work); 430 430 + int ksmbd_init_smb_server(struct ksmbd_work *work); 431 431 432 432 struct ksmbd_kstat; 433 433 int ksmbd_populate_dot_dotdot_entries(struct ksmbd_work *work,

+37 -28

fs/smb/server/vfs.c

reviewed

··· 63 63 64 64 static int ksmbd_vfs_path_lookup_locked(struct ksmbd_share_config *share_conf, 65 65 char *pathname, unsigned int flags, 66 66 + struct path *parent_path, 66 67 struct path *path) 67 68 { 68 69 struct qstr last; 69 70 struct filename *filename; 70 71 struct path *root_share_path = &share_conf->vfs_path; 71 72 int err, type; 72 72 - struct path parent_path; 73 73 struct dentry *d; 74 74 75 75 if (pathname[0] == '\0') { ··· 84 84 return PTR_ERR(filename); 85 85 86 86 err = vfs_path_parent_lookup(filename, flags, 87 87 - &parent_path, &last, &type, 87 87 + parent_path, &last, &type, 88 88 root_share_path); 89 89 if (err) { 90 90 putname(filename); ··· 92 92 } 93 93 94 94 if (unlikely(type != LAST_NORM)) { 95 95 - path_put(&parent_path); 95 95 + path_put(parent_path); 96 96 putname(filename); 97 97 return -ENOENT; 98 98 } 99 99 100 100 - inode_lock_nested(parent_path.dentry->d_inode, I_MUTEX_PARENT); 101 101 - d = lookup_one_qstr_excl(&last, parent_path.dentry, 0); 100 100 + inode_lock_nested(parent_path->dentry->d_inode, I_MUTEX_PARENT); 101 101 + d = lookup_one_qstr_excl(&last, parent_path->dentry, 0); 102 102 if (IS_ERR(d)) 103 103 goto err_out; 104 104 ··· 108 108 } 109 109 110 110 path->dentry = d; 111 111 - path->mnt = share_conf->vfs_path.mnt; 112 112 - path_put(&parent_path); 113 113 - putname(filename); 111 111 + path->mnt = mntget(parent_path->mnt); 114 112 113 113 + if (test_share_config_flag(share_conf, KSMBD_SHARE_FLAG_CROSSMNT)) { 114 114 + err = follow_down(path, 0); 115 115 + if (err < 0) { 116 116 + path_put(path); 117 117 + goto err_out; 118 118 + } 119 119 + } 120 120 + 121 121 + putname(filename); 115 122 return 0; 116 123 117 124 err_out: 118 118 - inode_unlock(parent_path.dentry->d_inode); 119 119 - path_put(&parent_path); 125 125 + inode_unlock(d_inode(parent_path->dentry)); 126 126 + path_put(parent_path); 120 127 putname(filename); 121 128 return -ENOENT; 122 129 } ··· 419 412 { 420 413 char *stream_buf = NULL, *wbuf; 421 414 struct mnt_idmap *idmap = file_mnt_idmap(fp->filp); 422 422 - size_t size, v_len; 415 415 + size_t size; 416 416 + ssize_t v_len; 423 417 int err = 0; 424 418 425 419 ksmbd_debug(VFS, "write stream data pos : %llu, count : %zd\n", ··· 437 429 fp->stream.name, 438 430 fp->stream.size, 439 431 &stream_buf); 440 440 - if ((int)v_len < 0) { 432 432 + if (v_len < 0) { 441 433 pr_err("not found stream in xattr : %zd\n", v_len); 442 442 - err = (int)v_len; 434 434 + err = v_len; 443 435 goto out; 444 436 } 445 437 ··· 1202 1194 * Return: 0 on success, otherwise error 1203 1195 */ 1204 1196 int ksmbd_vfs_kern_path_locked(struct ksmbd_work *work, char *name, 1205 1205 - unsigned int flags, struct path *path, 1206 1206 - bool caseless) 1197 1197 + unsigned int flags, struct path *parent_path, 1198 1198 + struct path *path, bool caseless) 1207 1199 { 1208 1200 struct ksmbd_share_config *share_conf = work->tcon->share_conf; 1209 1201 int err; 1210 1210 - struct path parent_path; 1211 1202 1212 1212 - err = ksmbd_vfs_path_lookup_locked(share_conf, name, flags, path); 1203 1203 + err = ksmbd_vfs_path_lookup_locked(share_conf, name, flags, parent_path, 1204 1204 + path); 1213 1205 if (!err) 1214 1206 return 0; 1215 1207 ··· 1224 1216 path_len = strlen(filepath); 1225 1217 remain_len = path_len; 1226 1218 1227 1227 - parent_path = share_conf->vfs_path; 1228 1228 - path_get(&parent_path); 1219 1219 + *parent_path = share_conf->vfs_path; 1220 1220 + path_get(parent_path); 1229 1221 1230 1230 - while (d_can_lookup(parent_path.dentry)) { 1222 1222 + while (d_can_lookup(parent_path->dentry)) { 1231 1223 char *filename = filepath + path_len - remain_len; 1232 1224 char *next = strchrnul(filename, '/'); 1233 1225 size_t filename_len = next - filename; ··· 1236 1228 if (filename_len == 0) 1237 1229 break; 1238 1230 1239 1239 - err = ksmbd_vfs_lookup_in_dir(&parent_path, filename, 1231 1231 + err = ksmbd_vfs_lookup_in_dir(parent_path, filename, 1240 1232 filename_len, 1241 1233 work->conn->um); 1242 1234 if (err) ··· 1253 1245 goto out2; 1254 1246 else if (is_last) 1255 1247 goto out1; 1256 1256 - path_put(&parent_path); 1257 1257 - parent_path = *path; 1248 1248 + path_put(parent_path); 1249 1249 + *parent_path = *path; 1258 1250 1259 1251 next[0] = '/'; 1260 1252 remain_len -= filename_len + 1; ··· 1262 1254 1263 1255 err = -EINVAL; 1264 1256 out2: 1265 1265 - path_put(&parent_path); 1257 1257 + path_put(parent_path); 1266 1258 out1: 1267 1259 kfree(filepath); 1268 1260 } 1269 1261 1270 1262 if (!err) { 1271 1271 - err = ksmbd_vfs_lock_parent(parent_path.dentry, path->dentry); 1272 1272 - if (err) 1273 1273 - dput(path->dentry); 1274 1274 - path_put(&parent_path); 1263 1263 + err = ksmbd_vfs_lock_parent(parent_path->dentry, path->dentry); 1264 1264 + if (err) { 1265 1265 + path_put(path); 1266 1266 + path_put(parent_path); 1267 1267 + } 1275 1268 } 1276 1269 return err; 1277 1270 }

+2 -2

fs/smb/server/vfs.h

reviewed

··· 115 115 int ksmbd_vfs_remove_xattr(struct mnt_idmap *idmap, 116 116 const struct path *path, char *attr_name); 117 117 int ksmbd_vfs_kern_path_locked(struct ksmbd_work *work, char *name, 118 118 - unsigned int flags, struct path *path, 119 119 - bool caseless); 118 118 + unsigned int flags, struct path *parent_path, 119 119 + struct path *path, bool caseless); 120 120 struct dentry *ksmbd_vfs_kern_path_create(struct ksmbd_work *work, 121 121 const char *name, 122 122 unsigned int flags,

+2

fs/splice.c

reviewed

··· 876 876 msg.msg_flags |= MSG_MORE; 877 877 if (remain && pipe_occupancy(pipe->head, tail) > 0) 878 878 msg.msg_flags |= MSG_MORE; 879 879 + if (out->f_flags & O_NONBLOCK) 880 880 + msg.msg_flags |= MSG_DONTWAIT; 879 881 880 882 iov_iter_bvec(&msg.msg_iter, ITER_SOURCE, bvec, bc, 881 883 len - remain);

+1 -1

include/kvm/arm_vgic.h

reviewed

··· 431 431 432 432 int vgic_v4_load(struct kvm_vcpu *vcpu); 433 433 void vgic_v4_commit(struct kvm_vcpu *vcpu); 434 434 - int vgic_v4_put(struct kvm_vcpu *vcpu, bool need_db); 434 434 + int vgic_v4_put(struct kvm_vcpu *vcpu); 435 435 436 436 /* CPU HP callbacks */ 437 437 void kvm_vgic_cpu_up(void);

-2

include/linux/blk-mq.h

reviewed

··· 397 397 */ 398 398 struct blk_mq_tags *sched_tags; 399 399 400 400 - /** @queued: Number of queued requests. */ 401 401 - unsigned long queued; 402 400 /** @run: Number of dispatched requests. */ 403 401 unsigned long run; 404 402

+1 -6

include/linux/jbd2.h

reviewed

··· 614 614 struct journal_head *t_checkpoint_list; 615 615 616 616 /* 617 617 - * Doubly-linked circular list of all buffers submitted for IO while 618 618 - * checkpointing. [j_list_lock] 619 619 - */ 620 620 - struct journal_head *t_checkpoint_io_list; 621 621 - 622 622 - /* 623 617 * Doubly-linked circular list of metadata buffers being 624 618 * shadowed by log IO. The IO buffers on the iobuf list and 625 619 * the shadow buffers on this list match each other one for ··· 1443 1449 void __jbd2_journal_clean_checkpoint_list(journal_t *journal, bool destroy); 1444 1450 unsigned long jbd2_journal_shrink_checkpoint_list(journal_t *journal, unsigned long *nr_to_scan); 1445 1451 int __jbd2_journal_remove_checkpoint(struct journal_head *); 1452 1452 + int jbd2_journal_try_remove_checkpoint(struct journal_head *jh); 1446 1453 void jbd2_journal_destroy_checkpoint(journal_t *journal); 1447 1454 void __jbd2_journal_insert_checkpoint(struct journal_head *, transaction_t *); 1448 1455

+2 -6

include/net/ipv6.h

reviewed

··· 752 752 /* more secured version of ipv6_addr_hash() */ 753 753 static inline u32 __ipv6_addr_jhash(const struct in6_addr *a, const u32 initval) 754 754 { 755 755 - u32 v = (__force u32)a->s6_addr32[0] ^ (__force u32)a->s6_addr32[1]; 756 756 - 757 757 - return jhash_3words(v, 758 758 - (__force u32)a->s6_addr32[2], 759 759 - (__force u32)a->s6_addr32[3], 760 760 - initval); 755 755 + return jhash2((__force const u32 *)a->s6_addr32, 756 756 + ARRAY_SIZE(a->s6_addr32), initval); 761 757 } 762 758 763 759 static inline bool ipv6_addr_loopback(const struct in6_addr *a)

+9 -4

include/net/vxlan.h

reviewed

··· 386 386 return features; 387 387 } 388 388 389 389 - /* IP header + UDP + VXLAN + Ethernet header */ 390 390 - #define VXLAN_HEADROOM (20 + 8 + 8 + 14) 391 391 - /* IPv6 header + UDP + VXLAN + Ethernet header */ 392 392 - #define VXLAN6_HEADROOM (40 + 8 + 8 + 14) 389 389 + static inline int vxlan_headroom(u32 flags) 390 390 + { 391 391 + /* VXLAN: IP4/6 header + UDP + VXLAN + Ethernet header */ 392 392 + /* VXLAN-GPE: IP4/6 header + UDP + VXLAN */ 393 393 + return (flags & VXLAN_F_IPV6 ? sizeof(struct ipv6hdr) : 394 394 + sizeof(struct iphdr)) + 395 395 + sizeof(struct udphdr) + sizeof(struct vxlanhdr) + 396 396 + (flags & VXLAN_F_GPE ? 0 : ETH_HLEN); 397 397 + } 393 398 394 399 static inline struct vxlanhdr *vxlan_hdr(struct sk_buff *skb) 395 400 {

+4 -8

include/trace/events/jbd2.h

reviewed

··· 462 462 TRACE_EVENT(jbd2_shrink_checkpoint_list, 463 463 464 464 TP_PROTO(journal_t *journal, tid_t first_tid, tid_t tid, tid_t last_tid, 465 465 - unsigned long nr_freed, unsigned long nr_scanned, 466 466 - tid_t next_tid), 465 465 + unsigned long nr_freed, tid_t next_tid), 467 466 468 468 - TP_ARGS(journal, first_tid, tid, last_tid, nr_freed, 469 469 - nr_scanned, next_tid), 467 467 + TP_ARGS(journal, first_tid, tid, last_tid, nr_freed, next_tid), 470 468 471 469 TP_STRUCT__entry( 472 470 __field(dev_t, dev) ··· 472 474 __field(tid_t, tid) 473 475 __field(tid_t, last_tid) 474 476 __field(unsigned long, nr_freed) 475 475 - __field(unsigned long, nr_scanned) 476 477 __field(tid_t, next_tid) 477 478 ), 478 479 ··· 481 484 __entry->tid = tid; 482 485 __entry->last_tid = last_tid; 483 486 __entry->nr_freed = nr_freed; 484 484 - __entry->nr_scanned = nr_scanned; 485 487 __entry->next_tid = next_tid; 486 488 ), 487 489 488 490 TP_printk("dev %d,%d shrink transaction %u-%u(%u) freed %lu " 489 489 - "scanned %lu next transaction %u", 491 491 + "next transaction %u", 490 492 MAJOR(__entry->dev), MINOR(__entry->dev), 491 493 __entry->first_tid, __entry->tid, __entry->last_tid, 492 492 - __entry->nr_freed, __entry->nr_scanned, __entry->next_tid) 494 494 + __entry->nr_freed, __entry->next_tid) 493 495 ); 494 496 495 497 #endif /* _TRACE_JBD2_H */

+5 -1

include/uapi/linux/if_packet.h

reviewed

··· 18 18 unsigned short sll_hatype; 19 19 unsigned char sll_pkttype; 20 20 unsigned char sll_halen; 21 21 - unsigned char sll_addr[8]; 21 21 + union { 22 22 + unsigned char sll_addr[8]; 23 23 + /* Actual length is in sll_halen. */ 24 24 + __DECLARE_FLEX_ARRAY(unsigned char, sll_addr_flex); 25 25 + }; 22 26 }; 23 27 24 28 /* Packet types */

+27 -27

io_uring/io_uring.c

reviewed

··· 1948 1948 ret = io_issue_sqe(req, issue_flags); 1949 1949 if (ret != -EAGAIN) 1950 1950 break; 1951 1951 + 1952 1952 + /* 1953 1953 + * If REQ_F_NOWAIT is set, then don't wait or retry with 1954 1954 + * poll. -EAGAIN is final for that case. 1955 1955 + */ 1956 1956 + if (req->flags & REQ_F_NOWAIT) 1957 1957 + break; 1958 1958 + 1951 1959 /* 1952 1960 * We can get EAGAIN for iopolled IO even though we're 1953 1961 * forcing a sync submission from here, since we can't ··· 3437 3429 unsigned long addr, unsigned long len, 3438 3430 unsigned long pgoff, unsigned long flags) 3439 3431 { 3440 3440 - const unsigned long mmap_end = arch_get_mmap_end(addr, len, flags); 3441 3441 - struct vm_unmapped_area_info info; 3442 3432 void *ptr; 3443 3433 3444 3434 /* ··· 3451 3445 if (IS_ERR(ptr)) 3452 3446 return -ENOMEM; 3453 3447 3454 3454 - info.flags = VM_UNMAPPED_AREA_TOPDOWN; 3455 3455 - info.length = len; 3456 3456 - info.low_limit = max(PAGE_SIZE, mmap_min_addr); 3457 3457 - info.high_limit = arch_get_mmap_base(addr, current->mm->mmap_base); 3458 3458 - #ifdef SHM_COLOUR 3459 3459 - info.align_mask = PAGE_MASK & (SHM_COLOUR - 1UL); 3460 3460 - #else 3461 3461 - info.align_mask = PAGE_MASK & (SHMLBA - 1UL); 3462 3462 - #endif 3463 3463 - info.align_offset = (unsigned long) ptr; 3464 3464 - 3465 3448 /* 3466 3466 - * A failed mmap() very likely causes application failure, 3467 3467 - * so fall back to the bottom-up function here. This scenario 3468 3468 - * can happen with large stack limits and large mmap() 3469 3469 - * allocations. 3449 3449 + * Some architectures have strong cache aliasing requirements. 3450 3450 + * For such architectures we need a coherent mapping which aliases 3451 3451 + * kernel memory *and* userspace memory. To achieve that: 3452 3452 + * - use a NULL file pointer to reference physical memory, and 3453 3453 + * - use the kernel virtual address of the shared io_uring context 3454 3454 + * (instead of the userspace-provided address, which has to be 0UL 3455 3455 + * anyway). 3456 3456 + * For architectures without such aliasing requirements, the 3457 3457 + * architecture will return any suitable mapping because addr is 0. 3470 3458 */ 3471 3471 - addr = vm_unmapped_area(&info); 3472 3472 - if (offset_in_page(addr)) { 3473 3473 - info.flags = 0; 3474 3474 - info.low_limit = TASK_UNMAPPED_BASE; 3475 3475 - info.high_limit = mmap_end; 3476 3476 - addr = vm_unmapped_area(&info); 3477 3477 - } 3478 3478 - 3479 3479 - return addr; 3459 3459 + filp = NULL; 3460 3460 + flags |= MAP_SHARED; 3461 3461 + pgoff = 0; /* has been translated to ptr above */ 3462 3462 + #ifdef SHM_COLOUR 3463 3463 + addr = (uintptr_t) ptr; 3464 3464 + #else 3465 3465 + addr = 0UL; 3466 3466 + #endif 3467 3467 + return current->mm->get_unmapped_area(filp, addr, len, pgoff, flags); 3480 3468 } 3481 3469 3482 3470 #else /* !CONFIG_MMU */ ··· 3870 3870 ctx->syscall_iopoll = 1; 3871 3871 3872 3872 ctx->compat = in_compat_syscall(); 3873 3873 - if (!capable(CAP_IPC_LOCK)) 3873 3873 + if (!ns_capable_noaudit(&init_user_ns, CAP_IPC_LOCK)) 3874 3874 ctx->user = get_uid(current_user()); 3875 3875 3876 3876 /*

+4

kernel/signal.c

reviewed

··· 562 562 if (handler != SIG_IGN && handler != SIG_DFL) 563 563 return false; 564 564 565 565 + /* If dying, we handle all new signals by ignoring them */ 566 566 + if (fatal_signal_pending(tsk)) 567 567 + return false; 568 568 + 565 569 /* if ptraced, let the tracer determine */ 566 570 return !tsk->ptrace; 567 571 }

+13 -1

kernel/trace/ring_buffer.c

reviewed

··· 536 536 unsigned flags; 537 537 int cpus; 538 538 atomic_t record_disabled; 539 539 + atomic_t resizing; 539 540 cpumask_var_t cpumask; 540 541 541 542 struct lock_class_key *reader_lock_key; ··· 2168 2167 2169 2168 /* prevent another thread from changing buffer sizes */ 2170 2169 mutex_lock(&buffer->mutex); 2171 2171 - 2170 2170 + atomic_inc(&buffer->resizing); 2172 2171 2173 2172 if (cpu_id == RING_BUFFER_ALL_CPUS) { 2174 2173 /* ··· 2323 2322 atomic_dec(&buffer->record_disabled); 2324 2323 } 2325 2324 2325 2325 + atomic_dec(&buffer->resizing); 2326 2326 mutex_unlock(&buffer->mutex); 2327 2327 return 0; 2328 2328 ··· 2344 2342 } 2345 2343 } 2346 2344 out_err_unlock: 2345 2345 + atomic_dec(&buffer->resizing); 2347 2346 mutex_unlock(&buffer->mutex); 2348 2347 return err; 2349 2348 } ··· 5542 5539 if (local_read(&cpu_buffer_a->committing)) 5543 5540 goto out_dec; 5544 5541 if (local_read(&cpu_buffer_b->committing)) 5542 5542 + goto out_dec; 5543 5543 + 5544 5544 + /* 5545 5545 + * When resize is in progress, we cannot swap it because 5546 5546 + * it will mess the state of the cpu buffer. 5547 5547 + */ 5548 5548 + if (atomic_read(&buffer_a->resizing)) 5549 5549 + goto out_dec; 5550 5550 + if (atomic_read(&buffer_b->resizing)) 5545 5551 goto out_dec; 5546 5552 5547 5553 buffer_a->buffers[cpu] = cpu_buffer_b;

+2 -1

kernel/trace/trace.c

reviewed

··· 1928 1928 * place on this CPU. We fail to record, but we reset 1929 1929 * the max trace buffer (no one writes directly to it) 1930 1930 * and flag that it failed. 1931 1931 + * Another reason is resize is in progress. 1931 1932 */ 1932 1933 trace_array_printk_buf(tr->max_buffer.buffer, _THIS_IP_, 1933 1933 - "Failed to swap buffers due to commit in progress\n"); 1934 1934 + "Failed to swap buffers due to commit or resize in progress\n"); 1934 1935 } 1935 1936 1936 1937 WARN_ON_ONCE(ret && ret != -EAGAIN && ret != -EBUSY);

+2 -1

kernel/trace/trace_events_hist.c

reviewed

··· 6668 6668 goto out_unreg; 6669 6669 6670 6670 if (has_hist_vars(hist_data) || hist_data->n_var_refs) { 6671 6671 - if (save_hist_vars(hist_data)) 6671 6671 + ret = save_hist_vars(hist_data); 6672 6672 + if (ret) 6672 6673 goto out_unreg; 6673 6674 } 6674 6675

-4

kernel/trace/tracing_map.h

reviewed

··· 272 272 extern u64 tracing_map_read_var(struct tracing_map_elt *elt, unsigned int i); 273 273 extern u64 tracing_map_read_var_once(struct tracing_map_elt *elt, unsigned int i); 274 274 275 275 - extern void tracing_map_set_field_descr(struct tracing_map *map, 276 276 - unsigned int i, 277 277 - unsigned int key_offset, 278 278 - tracing_map_cmp_fn_t cmp_fn); 279 275 extern int 280 276 tracing_map_sort_entries(struct tracing_map *map, 281 277 struct tracing_map_sort_key *sort_keys,

+7 -8

lib/sbitmap.c

reviewed

··· 550 550 551 551 static void __sbitmap_queue_wake_up(struct sbitmap_queue *sbq, int nr) 552 552 { 553 553 - int i, wake_index; 553 553 + int i, wake_index, woken; 554 554 555 555 if (!atomic_read(&sbq->ws_active)) 556 556 return; ··· 567 567 */ 568 568 wake_index = sbq_index_inc(wake_index); 569 569 570 570 - /* 571 571 - * It is sufficient to wake up at least one waiter to 572 572 - * guarantee forward progress. 573 573 - */ 574 574 - if (waitqueue_active(&ws->wait) && 575 575 - wake_up_nr(&ws->wait, nr)) 576 576 - break; 570 570 + if (waitqueue_active(&ws->wait)) { 571 571 + woken = wake_up_nr(&ws->wait, nr); 572 572 + if (woken == nr) 573 573 + break; 574 574 + nr -= woken; 575 575 + } 577 576 } 578 577 579 578 if (wake_index != atomic_read(&sbq->wake_index))

+4

mm/memblock.c

reviewed

··· 374 374 kfree(memblock.reserved.regions); 375 375 else 376 376 memblock_free_late(addr, size); 377 377 + /* Reset to prevent UAF from stray frees. */ 378 378 + memblock.reserved.regions = memblock_reserved_init_regions; 379 379 + memblock.reserved.cnt = 1; 380 380 + memblock_remove_region(&memblock.reserved, 0); 377 381 } 378 382 379 383 if (memblock.memory.regions != memblock_memory_init_regions) {

+16 -12

mm/memory.c

reviewed

··· 5393 5393 if (!vma_is_anonymous(vma) && !vma_is_tcp(vma)) 5394 5394 goto inval; 5395 5395 5396 5396 - /* find_mergeable_anon_vma uses adjacent vmas which are not locked */ 5397 5397 - if (!vma->anon_vma && !vma_is_tcp(vma)) 5398 5398 - goto inval; 5399 5399 - 5400 5396 if (!vma_start_read(vma)) 5401 5397 goto inval; 5398 5398 + 5399 5399 + /* 5400 5400 + * find_mergeable_anon_vma uses adjacent vmas which are not locked. 5401 5401 + * This check must happen after vma_start_read(); otherwise, a 5402 5402 + * concurrent mremap() with MREMAP_DONTUNMAP could dissociate the VMA 5403 5403 + * from its anon_vma. 5404 5404 + */ 5405 5405 + if (unlikely(!vma->anon_vma && !vma_is_tcp(vma))) 5406 5406 + goto inval_end_read; 5402 5407 5403 5408 /* 5404 5409 * Due to the possibility of userfault handler dropping mmap_lock, avoid 5405 5410 * it for now and fall back to page fault handling under mmap_lock. 5406 5411 */ 5407 5407 - if (userfaultfd_armed(vma)) { 5408 5408 - vma_end_read(vma); 5409 5409 - goto inval; 5410 5410 - } 5412 5412 + if (userfaultfd_armed(vma)) 5413 5413 + goto inval_end_read; 5411 5414 5412 5415 /* Check since vm_start/vm_end might change before we lock the VMA */ 5413 5413 - if (unlikely(address < vma->vm_start || address >= vma->vm_end)) { 5414 5414 - vma_end_read(vma); 5415 5415 - goto inval; 5416 5416 - } 5416 5416 + if (unlikely(address < vma->vm_start || address >= vma->vm_end)) 5417 5417 + goto inval_end_read; 5417 5418 5418 5419 /* Check if the VMA got isolated after we found it */ 5419 5420 if (vma->detached) { ··· 5426 5425 5427 5426 rcu_read_unlock(); 5428 5427 return vma; 5428 5428 + 5429 5429 + inval_end_read: 5430 5430 + vma_end_read(vma); 5429 5431 inval: 5430 5432 rcu_read_unlock(); 5431 5433 count_vm_vma_lock_event(VMA_LOCK_ABORT);

+3 -2

net/can/raw.c

reviewed

··· 386 386 list_del(&ro->notifier); 387 387 spin_unlock(&raw_notifier_lock); 388 388 389 389 + rtnl_lock(); 389 390 lock_sock(sk); 390 391 391 391 - rtnl_lock(); 392 392 /* remove current filters & unregister */ 393 393 if (ro->bound) { 394 394 if (ro->dev) ··· 405 405 ro->dev = NULL; 406 406 ro->count = 0; 407 407 free_percpu(ro->uniq); 408 408 - rtnl_unlock(); 409 408 410 409 sock_orphan(sk); 411 410 sock->sk = NULL; 412 411 413 412 release_sock(sk); 413 413 + rtnl_unlock(); 414 414 + 414 415 sock_put(sk); 415 416 416 417 return 0;

+10 -4

net/ipv6/addrconf.c

reviewed

··· 2563 2563 ipv6_ifa_notify(0, ift); 2564 2564 } 2565 2565 2566 2566 - if ((create || list_empty(&idev->tempaddr_list)) && 2567 2567 - idev->cnf.use_tempaddr > 0) { 2566 2566 + /* Also create a temporary address if it's enabled but no temporary 2567 2567 + * address currently exists. 2568 2568 + * However, we get called with valid_lft == 0, prefered_lft == 0, create == false 2569 2569 + * as part of cleanup (ie. deleting the mngtmpaddr). 2570 2570 + * We don't want that to result in creating a new temporary ip address. 2571 2571 + */ 2572 2572 + if (list_empty(&idev->tempaddr_list) && (valid_lft || prefered_lft)) 2573 2573 + create = true; 2574 2574 + 2575 2575 + if (create && idev->cnf.use_tempaddr > 0) { 2568 2576 /* When a new public address is created as described 2569 2577 * in [ADDRCONF], also create a new temporary address. 2570 2570 - * Also create a temporary address if it's enabled but 2571 2571 - * no temporary address currently exists. 2572 2578 */ 2573 2579 read_unlock_bh(&idev->lock); 2574 2580 ipv6_create_tempaddr(ifp, false);

+1 -2

net/mptcp/protocol.c

reviewed

··· 3722 3722 if (!err) { 3723 3723 sock_prot_inuse_add(sock_net(sk), sk->sk_prot, 1); 3724 3724 mptcp_copy_inaddrs(sk, ssock->sk); 3725 3725 + mptcp_event_pm_listener(ssock->sk, MPTCP_EVENT_LISTENER_CREATED); 3725 3726 } 3726 3726 - 3727 3727 - mptcp_event_pm_listener(ssock->sk, MPTCP_EVENT_LISTENER_CREATED); 3728 3727 3729 3728 unlock: 3730 3729 release_sock(sk);

+3 -2

net/netfilter/nf_tables_api.c

reviewed

··· 3811 3811 NL_SET_BAD_ATTR(extack, nla[NFTA_RULE_CHAIN]); 3812 3812 return PTR_ERR(chain); 3813 3813 } 3814 3814 - if (nft_chain_is_bound(chain)) 3815 3815 - return -EOPNOTSUPP; 3816 3814 3817 3815 } else if (nla[NFTA_RULE_CHAIN_ID]) { 3818 3816 chain = nft_chain_lookup_byid(net, table, nla[NFTA_RULE_CHAIN_ID], ··· 3822 3824 } else { 3823 3825 return -EINVAL; 3824 3826 } 3827 3827 + 3828 3828 + if (nft_chain_is_bound(chain)) 3829 3829 + return -EOPNOTSUPP; 3825 3830 3826 3831 if (nla[NFTA_RULE_HANDLE]) { 3827 3832 handle = be64_to_cpu(nla_get_be64(nla[NFTA_RULE_HANDLE]));

+18 -9

net/netfilter/nft_immediate.c

reviewed

··· 125 125 return nft_data_hold(&priv->data, nft_dreg_to_type(priv->dreg)); 126 126 } 127 127 128 128 + static void nft_immediate_chain_deactivate(const struct nft_ctx *ctx, 129 129 + struct nft_chain *chain, 130 130 + enum nft_trans_phase phase) 131 131 + { 132 132 + struct nft_ctx chain_ctx; 133 133 + struct nft_rule *rule; 134 134 + 135 135 + chain_ctx = *ctx; 136 136 + chain_ctx.chain = chain; 137 137 + 138 138 + list_for_each_entry(rule, &chain->rules, list) 139 139 + nft_rule_expr_deactivate(&chain_ctx, rule, phase); 140 140 + } 141 141 + 128 142 static void nft_immediate_deactivate(const struct nft_ctx *ctx, 129 143 const struct nft_expr *expr, 130 144 enum nft_trans_phase phase) 131 145 { 132 146 const struct nft_immediate_expr *priv = nft_expr_priv(expr); 133 147 const struct nft_data *data = &priv->data; 134 134 - struct nft_ctx chain_ctx; 135 148 struct nft_chain *chain; 136 136 - struct nft_rule *rule; 137 149 138 150 if (priv->dreg == NFT_REG_VERDICT) { 139 151 switch (data->verdict.code) { ··· 155 143 if (!nft_chain_binding(chain)) 156 144 break; 157 145 158 158 - chain_ctx = *ctx; 159 159 - chain_ctx.chain = chain; 160 160 - 161 161 - list_for_each_entry(rule, &chain->rules, list) 162 162 - nft_rule_expr_deactivate(&chain_ctx, rule, phase); 163 163 - 164 146 switch (phase) { 165 147 case NFT_TRANS_PREPARE_ERROR: 166 148 nf_tables_unbind_chain(ctx, chain); 167 167 - fallthrough; 149 149 + nft_deactivate_next(ctx->net, chain); 150 150 + break; 168 151 case NFT_TRANS_PREPARE: 152 152 + nft_immediate_chain_deactivate(ctx, chain, phase); 169 153 nft_deactivate_next(ctx->net, chain); 170 154 break; 171 155 default: 156 156 + nft_immediate_chain_deactivate(ctx, chain, phase); 172 157 nft_chain_del(chain); 173 158 chain->bound = false; 174 159 nft_use_dec(&chain->table->use);

+14 -6

net/netfilter/nft_set_rbtree.c

reviewed

··· 217 217 218 218 static int nft_rbtree_gc_elem(const struct nft_set *__set, 219 219 struct nft_rbtree *priv, 220 220 - struct nft_rbtree_elem *rbe) 220 220 + struct nft_rbtree_elem *rbe, 221 221 + u8 genmask) 221 222 { 222 223 struct nft_set *set = (struct nft_set *)__set; 223 224 struct rb_node *prev = rb_prev(&rbe->node); 224 224 - struct nft_rbtree_elem *rbe_prev = NULL; 225 225 + struct nft_rbtree_elem *rbe_prev; 225 226 struct nft_set_gc_batch *gcb; 226 227 227 228 gcb = nft_set_gc_batch_check(set, NULL, GFP_ATOMIC); 228 229 if (!gcb) 229 230 return -ENOMEM; 230 231 231 231 - /* search for expired end interval coming before this element. */ 232 232 + /* search for end interval coming before this element. 233 233 + * end intervals don't carry a timeout extension, they 234 234 + * are coupled with the interval start element. 235 235 + */ 232 236 while (prev) { 233 237 rbe_prev = rb_entry(prev, struct nft_rbtree_elem, node); 234 234 - if (nft_rbtree_interval_end(rbe_prev)) 238 238 + if (nft_rbtree_interval_end(rbe_prev) && 239 239 + nft_set_elem_active(&rbe_prev->ext, genmask)) 235 240 break; 236 241 237 242 prev = rb_prev(prev); 238 243 } 239 244 240 240 - if (rbe_prev) { 245 245 + if (prev) { 246 246 + rbe_prev = rb_entry(prev, struct nft_rbtree_elem, node); 247 247 + 241 248 rb_erase(&rbe_prev->node, &priv->root); 242 249 atomic_dec(&set->nelems); 250 250 + nft_set_gc_batch_add(gcb, rbe_prev); 243 251 } 244 252 245 253 rb_erase(&rbe->node, &priv->root); ··· 329 321 330 322 /* perform garbage collection to avoid bogus overlap reports. */ 331 323 if (nft_set_elem_expired(&rbe->ext)) { 332 332 - err = nft_rbtree_gc_elem(set, priv, rbe); 324 324 + err = nft_rbtree_gc_elem(set, priv, rbe, genmask); 333 325 if (err < 0) 334 326 return err; 335 327

+1 -1

net/packet/af_packet.c

reviewed

··· 3601 3601 if (dev) { 3602 3602 sll->sll_hatype = dev->type; 3603 3603 sll->sll_halen = dev->addr_len; 3604 3604 - memcpy(sll->sll_addr, dev->dev_addr, dev->addr_len); 3604 3604 + memcpy(sll->sll_addr_flex, dev->dev_addr, dev->addr_len); 3605 3605 } else { 3606 3606 sll->sll_hatype = 0; /* Bad: we have no ARPHRD_UNSPEC */ 3607 3607 sll->sll_halen = 0;

+14

net/sched/sch_mqprio.c

reviewed

··· 290 290 "Attribute type expected to be TCA_MQPRIO_MIN_RATE64"); 291 291 return -EINVAL; 292 292 } 293 293 + 294 294 + if (nla_len(attr) != sizeof(u64)) { 295 295 + NL_SET_ERR_MSG_ATTR(extack, attr, 296 296 + "Attribute TCA_MQPRIO_MIN_RATE64 expected to have 8 bytes length"); 297 297 + return -EINVAL; 298 298 + } 299 299 + 293 300 if (i >= qopt->num_tc) 294 301 break; 295 302 priv->min_rate[i] = nla_get_u64(attr); ··· 319 312 "Attribute type expected to be TCA_MQPRIO_MAX_RATE64"); 320 313 return -EINVAL; 321 314 } 315 315 + 316 316 + if (nla_len(attr) != sizeof(u64)) { 317 317 + NL_SET_ERR_MSG_ATTR(extack, attr, 318 318 + "Attribute TCA_MQPRIO_MAX_RATE64 expected to have 8 bytes length"); 319 319 + return -EINVAL; 320 320 + } 321 321 + 322 322 if (i >= qopt->num_tc) 323 323 break; 324 324 priv->max_rate[i] = nla_get_u64(attr);

+2 -1

net/tipc/crypto.c

reviewed

··· 1960 1960 1961 1961 skb_reset_network_header(*skb); 1962 1962 skb_pull(*skb, tipc_ehdr_size(ehdr)); 1963 1963 - pskb_trim(*skb, (*skb)->len - aead->authsize); 1963 1963 + if (pskb_trim(*skb, (*skb)->len - aead->authsize)) 1964 1964 + goto free_skb; 1964 1965 1965 1966 /* Validate TIPCv2 message */ 1966 1967 if (unlikely(!tipc_msg_validate(skb))) {

+1 -1

net/tipc/node.c

reviewed

··· 583 583 n->capabilities, &n->bc_entry.inputq1, 584 584 &n->bc_entry.namedq, snd_l, &n->bc_entry.link)) { 585 585 pr_warn("Broadcast rcv link creation failed, no memory\n"); 586 586 - kfree(n); 586 586 + tipc_node_put(n); 587 587 n = NULL; 588 588 goto exit; 589 589 }

+16 -7

net/unix/af_unix.c

reviewed

··· 289 289 return 0; 290 290 } 291 291 292 292 - static void unix_mkname_bsd(struct sockaddr_un *sunaddr, int addr_len) 292 292 + static int unix_mkname_bsd(struct sockaddr_un *sunaddr, int addr_len) 293 293 { 294 294 + struct sockaddr_storage *addr = (struct sockaddr_storage *)sunaddr; 295 295 + short offset = offsetof(struct sockaddr_storage, __data); 296 296 + 297 297 + BUILD_BUG_ON(offset != offsetof(struct sockaddr_un, sun_path)); 298 298 + 294 299 /* This may look like an off by one error but it is a bit more 295 300 * subtle. 108 is the longest valid AF_UNIX path for a binding. 296 301 * sun_path[108] doesn't as such exist. However in kernel space 297 302 * we are guaranteed that it is a valid memory location in our 298 303 * kernel address buffer because syscall functions always pass 299 304 * a pointer of struct sockaddr_storage which has a bigger buffer 300 300 - * than 108. 305 305 + * than 108. Also, we must terminate sun_path for strlen() in 306 306 + * getname_kernel(). 301 307 */ 302 302 - ((char *)sunaddr)[addr_len] = 0; 308 308 + addr->__data[addr_len - offset] = 0; 309 309 + 310 310 + /* Don't pass sunaddr->sun_path to strlen(). Otherwise, 108 will 311 311 + * cause panic if CONFIG_FORTIFY_SOURCE=y. Let __fortify_strlen() 312 312 + * know the actual buffer. 313 313 + */ 314 314 + return strlen(addr->__data) + offset + 1; 303 315 } 304 316 305 317 static void __unix_remove_socket(struct sock *sk) ··· 1220 1208 struct path parent; 1221 1209 int err; 1222 1210 1223 1223 - unix_mkname_bsd(sunaddr, addr_len); 1224 1224 - addr_len = strlen(sunaddr->sun_path) + 1225 1225 - offsetof(struct sockaddr_un, sun_path) + 1; 1226 1226 - 1211 1211 + addr_len = unix_mkname_bsd(sunaddr, addr_len); 1227 1212 addr = unix_create_addr(sunaddr, addr_len); 1228 1213 if (!addr) 1229 1214 return -ENOMEM;

+4 -1

scripts/Makefile.build

reviewed

··· 264 264 265 265 rust_allowed_features := new_uninit 266 266 267 267 + # `--out-dir` is required to avoid temporaries being created by `rustc` in the 268 268 + # current working directory, which may be not accessible in the out-of-tree 269 269 + # modules case. 267 270 rust_common_cmd = \ 268 271 RUST_MODFILE=$(modfile) $(RUSTC_OR_CLIPPY) $(rust_flags) \ 269 272 -Zallow-features=$(rust_allowed_features) \ ··· 275 272 --extern alloc --extern kernel \ 276 273 --crate-type rlib -L $(objtree)/rust/ \ 277 274 --crate-name $(basename $(notdir $@)) \ 278 278 - --emit=dep-info=$(depfile) 275 275 + --out-dir $(dir $@) --emit=dep-info=$(depfile) 279 276 280 277 # `--emit=obj`, `--emit=asm` and `--emit=llvm-ir` imply a single codegen unit 281 278 # will be used. We explicitly request `-Ccodegen-units=1` in any case, and

+5 -1

scripts/Makefile.host

reviewed

··· 86 86 hostcxx_flags = -Wp,-MMD,$(depfile) \ 87 87 $(KBUILD_HOSTCXXFLAGS) $(HOST_EXTRACXXFLAGS) \ 88 88 $(HOSTCXXFLAGS_$(target-stem).o) 89 89 - hostrust_flags = --emit=dep-info=$(depfile) \ 89 89 + 90 90 + # `--out-dir` is required to avoid temporaries being created by `rustc` in the 91 91 + # current working directory, which may be not accessible in the out-of-tree 92 92 + # modules case. 93 93 + hostrust_flags = --out-dir $(dir $@) --emit=dep-info=$(depfile) \ 90 94 $(KBUILD_HOSTRUSTFLAGS) $(HOST_EXTRARUSTFLAGS) \ 91 95 $(HOSTRUSTFLAGS_$(target-stem)) 92 96

+1 -1

scripts/clang-tools/gen_compile_commands.py

reviewed

··· 19 19 _DEFAULT_LOG_LEVEL = 'WARNING' 20 20 21 21 _FILENAME_PATTERN = r'^\..*\.cmd$' 22 22 - _LINE_PATTERN = r'^savedcmd_[^ ]*\.o := (.* )([^ ]*\.c) *(;|$)' 22 22 + _LINE_PATTERN = r'^savedcmd_[^ ]*\.o := (.* )([^ ]*\.[cS]) *(;|$)' 23 23 _VALID_LOG_LEVELS = ['DEBUG', 'INFO', 'WARNING', 'ERROR', 'CRITICAL'] 24 24 # The tools/ directory adopts a different build system, and produces .cmd 25 25 # files in a different format. Do not support it.

+4 -7

scripts/kconfig/gconf.c

reviewed

··· 636 636 { 637 637 GtkWidget *dialog; 638 638 const gchar *intro_text = 639 639 - "Welcome to gkc, the GTK+ graphical configuration tool\n" 639 639 + "Welcome to gconfig, the GTK+ graphical configuration tool.\n" 640 640 "For each option, a blank box indicates the feature is disabled, a\n" 641 641 "check indicates it is enabled, and a dot indicates that it is to\n" 642 642 "be compiled as a module. Clicking on the box will cycle through the three states.\n" ··· 647 647 "Although there is no cross reference yet to help you figure out\n" 648 648 "what other options must be enabled to support the option you\n" 649 649 "are interested in, you can still view the help of a grayed-out\n" 650 650 - "option.\n" 651 651 - "\n" 652 652 - "Toggling Show Debug Info under the Options menu will show \n" 653 653 - "the dependencies, which you can then match by examining other options."; 650 650 + "option."; 654 651 655 652 dialog = gtk_message_dialog_new(GTK_WINDOW(main_wnd), 656 653 GTK_DIALOG_DESTROY_WITH_PARENT, ··· 664 667 { 665 668 GtkWidget *dialog; 666 669 const gchar *about_text = 667 667 - "gkc is copyright (c) 2002 Romain Lievin <roms@lpg.ticalc.org>.\n" 670 670 + "gconfig is copyright (c) 2002 Romain Lievin <roms@lpg.ticalc.org>.\n" 668 671 "Based on the source code from Roman Zippel.\n"; 669 672 670 673 dialog = gtk_message_dialog_new(GTK_WINDOW(main_wnd), ··· 682 685 { 683 686 GtkWidget *dialog; 684 687 const gchar *license_text = 685 685 - "gkc is released under the terms of the GNU GPL v2.\n" 688 688 + "gconfig is released under the terms of the GNU GPL v2.\n" 686 689 "For more information, please see the source code or\n" 687 690 "visit http://www.fsf.org/licenses/licenses.html\n"; 688 691

+1

sound/core/seq/seq_ports.c

reviewed

··· 149 149 write_lock_irq(&client->ports_lock); 150 150 list_for_each_entry(p, &client->ports_list_head, list) { 151 151 if (p->addr.port == port) { 152 152 + kfree(new_port); 152 153 num = -EBUSY; 153 154 goto unlock; 154 155 }

+7 -5

sound/drivers/pcmtest.c

reviewed

··· 110 110 struct timer_list timer_instance; 111 111 }; 112 112 113 113 - static struct pcmtst *pcmtst; 114 114 - 115 113 static struct snd_pcm_hardware snd_pcmtst_hw = { 116 114 .info = (SNDRV_PCM_INFO_INTERLEAVED | 117 115 SNDRV_PCM_INFO_BLOCK_TRANSFER | ··· 550 552 static int pcmtst_probe(struct platform_device *pdev) 551 553 { 552 554 struct snd_card *card; 555 555 + struct pcmtst *pcmtst; 553 556 int err; 554 557 555 558 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); ··· 572 573 if (err < 0) 573 574 return err; 574 575 576 576 + platform_set_drvdata(pdev, pcmtst); 577 577 + 575 578 return 0; 576 579 } 577 580 578 578 - static int pdev_remove(struct platform_device *dev) 581 581 + static void pdev_remove(struct platform_device *pdev) 579 582 { 583 583 + struct pcmtst *pcmtst = platform_get_drvdata(pdev); 584 584 + 580 585 snd_pcmtst_free(pcmtst); 581 581 - return 0; 582 586 } 583 587 584 588 static struct platform_device pcmtst_pdev = { ··· 591 589 592 590 static struct platform_driver pcmtst_pdrv = { 593 591 .probe = pcmtst_probe, 594 594 - .remove = pdev_remove, 592 592 + .remove_new = pdev_remove, 595 593 .driver = { 596 594 .name = "pcmtest", 597 595 },

+50 -12

sound/pci/hda/patch_realtek.c

reviewed

··· 122 122 unsigned int ultra_low_power:1; 123 123 unsigned int has_hs_key:1; 124 124 unsigned int no_internal_mic_pin:1; 125 125 + unsigned int en_3kpull_low:1; 125 126 126 127 /* for PLL fix */ 127 128 hda_nid_t pll_nid; ··· 3623 3622 if (!hp_pin) 3624 3623 hp_pin = 0x21; 3625 3624 3625 3625 + alc_update_coefex_idx(codec, 0x57, 0x04, 0x0007, 0x1); /* Low power */ 3626 3626 hp_pin_sense = snd_hda_jack_detect(codec, hp_pin); 3627 3627 3628 3628 if (hp_pin_sense) ··· 3640 3638 /* If disable 3k pulldown control for alc257, the Mic detection will not work correctly 3641 3639 * when booting with headset plugged. So skip setting it for the codec alc257 3642 3640 */ 3643 3643 - if (codec->core.vendor_id != 0x10ec0236 && 3644 3644 - codec->core.vendor_id != 0x10ec0257) 3641 3641 + if (spec->en_3kpull_low) 3645 3642 alc_update_coef_idx(codec, 0x46, 0, 3 << 12); 3646 3643 3647 3644 if (!spec->no_shutup_pins) ··· 4620 4619 spec->mute_led_coef.mask = 1 << 5; 4621 4620 spec->mute_led_coef.on = 0; 4622 4621 spec->mute_led_coef.off = 1 << 5; 4622 4622 + snd_hda_gen_add_mute_led_cdev(codec, coef_mute_led_set); 4623 4623 + } 4624 4624 + } 4625 4625 + 4626 4626 + static void alc236_fixup_hp_mute_led_coefbit2(struct hda_codec *codec, 4627 4627 + const struct hda_fixup *fix, int action) 4628 4628 + { 4629 4629 + struct alc_spec *spec = codec->spec; 4630 4630 + 4631 4631 + if (action == HDA_FIXUP_ACT_PRE_PROBE) { 4632 4632 + spec->mute_led_polarity = 0; 4633 4633 + spec->mute_led_coef.idx = 0x07; 4634 4634 + spec->mute_led_coef.mask = 1; 4635 4635 + spec->mute_led_coef.on = 1; 4636 4636 + spec->mute_led_coef.off = 0; 4623 4637 snd_hda_gen_add_mute_led_cdev(codec, coef_mute_led_set); 4624 4638 } 4625 4639 } ··· 7159 7143 ALC285_FIXUP_HP_GPIO_LED, 7160 7144 ALC285_FIXUP_HP_MUTE_LED, 7161 7145 ALC285_FIXUP_HP_SPECTRE_X360_MUTE_LED, 7146 7146 + ALC236_FIXUP_HP_MUTE_LED_COEFBIT2, 7162 7147 ALC236_FIXUP_HP_GPIO_LED, 7163 7148 ALC236_FIXUP_HP_MUTE_LED, 7164 7149 ALC236_FIXUP_HP_MUTE_LED_MICMUTE_VREF, ··· 7230 7213 ALC287_FIXUP_YOGA9_14IAP7_BASS_SPK_PIN, 7231 7214 ALC295_FIXUP_DELL_INSPIRON_TOP_SPEAKERS, 7232 7215 ALC236_FIXUP_DELL_DUAL_CODECS, 7216 7216 + ALC287_FIXUP_CS35L41_I2C_2_THINKPAD_ACPI, 7233 7217 }; 7234 7218 7235 7219 /* A special fixup for Lenovo C940 and Yoga Duet 7; ··· 8650 8632 .type = HDA_FIXUP_FUNC, 8651 8633 .v.func = alc285_fixup_hp_spectre_x360_mute_led, 8652 8634 }, 8635 8635 + [ALC236_FIXUP_HP_MUTE_LED_COEFBIT2] = { 8636 8636 + .type = HDA_FIXUP_FUNC, 8637 8637 + .v.func = alc236_fixup_hp_mute_led_coefbit2, 8638 8638 + }, 8653 8639 [ALC236_FIXUP_HP_GPIO_LED] = { 8654 8640 .type = HDA_FIXUP_FUNC, 8655 8641 .v.func = alc236_fixup_hp_gpio_led, ··· 9167 9145 [ALC287_FIXUP_CS35L41_I2C_2] = { 9168 9146 .type = HDA_FIXUP_FUNC, 9169 9147 .v.func = cs35l41_fixup_i2c_two, 9170 9170 - .chained = true, 9171 9171 - .chain_id = ALC269_FIXUP_THINKPAD_ACPI, 9172 9148 }, 9173 9149 [ALC287_FIXUP_CS35L41_I2C_2_HP_GPIO_LED] = { 9174 9150 .type = HDA_FIXUP_FUNC, ··· 9303 9283 .chained = true, 9304 9284 .chain_id = ALC255_FIXUP_DELL1_MIC_NO_PRESENCE, 9305 9285 }, 9286 9286 + [ALC287_FIXUP_CS35L41_I2C_2_THINKPAD_ACPI] = { 9287 9287 + .type = HDA_FIXUP_FUNC, 9288 9288 + .v.func = cs35l41_fixup_i2c_two, 9289 9289 + .chained = true, 9290 9290 + .chain_id = ALC269_FIXUP_THINKPAD_ACPI, 9291 9291 + }, 9306 9292 }; 9307 9293 9308 9294 static const struct snd_pci_quirk alc269_fixup_tbl[] = { ··· 9419 9393 SND_PCI_QUIRK(0x1028, 0x0c1c, "Dell Precision 3540", ALC236_FIXUP_DELL_DUAL_CODECS), 9420 9394 SND_PCI_QUIRK(0x1028, 0x0c1d, "Dell Precision 3440", ALC236_FIXUP_DELL_DUAL_CODECS), 9421 9395 SND_PCI_QUIRK(0x1028, 0x0c1e, "Dell Precision 3540", ALC236_FIXUP_DELL_DUAL_CODECS), 9396 9396 + SND_PCI_QUIRK(0x1028, 0x0cbd, "Dell Oasis 13 CS MTL-U", ALC245_FIXUP_CS35L41_SPI_2), 9397 9397 + SND_PCI_QUIRK(0x1028, 0x0cbe, "Dell Oasis 13 2-IN-1 MTL-U", ALC245_FIXUP_CS35L41_SPI_2), 9398 9398 + SND_PCI_QUIRK(0x1028, 0x0cbf, "Dell Oasis 13 Low Weight MTU-L", ALC245_FIXUP_CS35L41_SPI_2), 9399 9399 + SND_PCI_QUIRK(0x1028, 0x0cc1, "Dell Oasis 14 MTL-H/U", ALC287_FIXUP_CS35L41_I2C_2), 9400 9400 + SND_PCI_QUIRK(0x1028, 0x0cc2, "Dell Oasis 14 2-in-1 MTL-H/U", ALC287_FIXUP_CS35L41_I2C_2), 9401 9401 + SND_PCI_QUIRK(0x1028, 0x0cc3, "Dell Oasis 14 Low Weight MTL-U", ALC287_FIXUP_CS35L41_I2C_2), 9402 9402 + SND_PCI_QUIRK(0x1028, 0x0cc4, "Dell Oasis 16 MTL-H/U", ALC287_FIXUP_CS35L41_I2C_2), 9403 9403 + SND_PCI_QUIRK(0x1028, 0x0cc5, "Dell Oasis MLK 14 RPL-P", ALC287_FIXUP_CS35L41_I2C_2), 9422 9404 SND_PCI_QUIRK(0x1028, 0x164a, "Dell", ALC293_FIXUP_DELL1_MIC_NO_PRESENCE), 9423 9405 SND_PCI_QUIRK(0x1028, 0x164b, "Dell", ALC293_FIXUP_DELL1_MIC_NO_PRESENCE), 9424 9406 SND_PCI_QUIRK(0x103c, 0x1586, "HP", ALC269_FIXUP_HP_MUTE_LED_MIC2), ··· 9550 9516 SND_PCI_QUIRK(0x103c, 0x886d, "HP ZBook Fury 17.3 Inch G8 Mobile Workstation PC", ALC285_FIXUP_HP_GPIO_AMP_INIT), 9551 9517 SND_PCI_QUIRK(0x103c, 0x8870, "HP ZBook Fury 15.6 Inch G8 Mobile Workstation PC", ALC285_FIXUP_HP_GPIO_AMP_INIT), 9552 9518 SND_PCI_QUIRK(0x103c, 0x8873, "HP ZBook Studio 15.6 Inch G8 Mobile Workstation PC", ALC285_FIXUP_HP_GPIO_AMP_INIT), 9519 9519 + SND_PCI_QUIRK(0x103c, 0x887a, "HP Laptop 15s-eq2xxx", ALC236_FIXUP_HP_MUTE_LED_COEFBIT2), 9553 9520 SND_PCI_QUIRK(0x103c, 0x888d, "HP ZBook Power 15.6 inch G8 Mobile Workstation PC", ALC236_FIXUP_HP_GPIO_LED), 9554 9521 SND_PCI_QUIRK(0x103c, 0x8895, "HP EliteBook 855 G8 Notebook PC", ALC285_FIXUP_HP_SPEAKERS_MICMUTE_LED), 9555 9522 SND_PCI_QUIRK(0x103c, 0x8896, "HP EliteBook 855 G8 Notebook PC", ALC285_FIXUP_HP_MUTE_LED), ··· 9762 9727 SND_PCI_QUIRK(0x1558, 0x5157, "Clevo W517GU1", ALC293_FIXUP_SYSTEM76_MIC_NO_PRESENCE), 9763 9728 SND_PCI_QUIRK(0x1558, 0x51a1, "Clevo NS50MU", ALC293_FIXUP_SYSTEM76_MIC_NO_PRESENCE), 9764 9729 SND_PCI_QUIRK(0x1558, 0x51b1, "Clevo NS50AU", ALC256_FIXUP_SYSTEM76_MIC_NO_PRESENCE), 9730 9730 + SND_PCI_QUIRK(0x1558, 0x51b3, "Clevo NS70AU", ALC256_FIXUP_SYSTEM76_MIC_NO_PRESENCE), 9765 9731 SND_PCI_QUIRK(0x1558, 0x5630, "Clevo NP50RNJS", ALC256_FIXUP_SYSTEM76_MIC_NO_PRESENCE), 9766 9732 SND_PCI_QUIRK(0x1558, 0x70a1, "Clevo NB70T[HJK]", ALC293_FIXUP_SYSTEM76_MIC_NO_PRESENCE), 9767 9733 SND_PCI_QUIRK(0x1558, 0x70b3, "Clevo NK70SB", ALC293_FIXUP_SYSTEM76_MIC_NO_PRESENCE), ··· 9846 9810 SND_PCI_QUIRK(0x17aa, 0x22be, "Thinkpad X1 Carbon 8th", ALC285_FIXUP_THINKPAD_HEADSET_JACK), 9847 9811 SND_PCI_QUIRK(0x17aa, 0x22c1, "Thinkpad P1 Gen 3", ALC285_FIXUP_THINKPAD_NO_BASS_SPK_HEADSET_JACK), 9848 9812 SND_PCI_QUIRK(0x17aa, 0x22c2, "Thinkpad X1 Extreme Gen 3", ALC285_FIXUP_THINKPAD_NO_BASS_SPK_HEADSET_JACK), 9849 9849 - SND_PCI_QUIRK(0x17aa, 0x22f1, "Thinkpad", ALC287_FIXUP_CS35L41_I2C_2), 9850 9850 - SND_PCI_QUIRK(0x17aa, 0x22f2, "Thinkpad", ALC287_FIXUP_CS35L41_I2C_2), 9851 9851 - SND_PCI_QUIRK(0x17aa, 0x22f3, "Thinkpad", ALC287_FIXUP_CS35L41_I2C_2), 9852 9852 - SND_PCI_QUIRK(0x17aa, 0x2316, "Thinkpad P1 Gen 6", ALC287_FIXUP_CS35L41_I2C_2), 9853 9853 - SND_PCI_QUIRK(0x17aa, 0x2317, "Thinkpad P1 Gen 6", ALC287_FIXUP_CS35L41_I2C_2), 9854 9854 - SND_PCI_QUIRK(0x17aa, 0x2318, "Thinkpad Z13 Gen2", ALC287_FIXUP_CS35L41_I2C_2), 9855 9855 - SND_PCI_QUIRK(0x17aa, 0x2319, "Thinkpad Z16 Gen2", ALC287_FIXUP_CS35L41_I2C_2), 9856 9856 - SND_PCI_QUIRK(0x17aa, 0x231a, "Thinkpad Z16 Gen2", ALC287_FIXUP_CS35L41_I2C_2), 9813 9813 + SND_PCI_QUIRK(0x17aa, 0x22f1, "Thinkpad", ALC287_FIXUP_CS35L41_I2C_2_THINKPAD_ACPI), 9814 9814 + SND_PCI_QUIRK(0x17aa, 0x22f2, "Thinkpad", ALC287_FIXUP_CS35L41_I2C_2_THINKPAD_ACPI), 9815 9815 + SND_PCI_QUIRK(0x17aa, 0x22f3, "Thinkpad", ALC287_FIXUP_CS35L41_I2C_2_THINKPAD_ACPI), 9816 9816 + SND_PCI_QUIRK(0x17aa, 0x2316, "Thinkpad P1 Gen 6", ALC287_FIXUP_CS35L41_I2C_2_THINKPAD_ACPI), 9817 9817 + SND_PCI_QUIRK(0x17aa, 0x2317, "Thinkpad P1 Gen 6", ALC287_FIXUP_CS35L41_I2C_2_THINKPAD_ACPI), 9818 9818 + SND_PCI_QUIRK(0x17aa, 0x2318, "Thinkpad Z13 Gen2", ALC287_FIXUP_CS35L41_I2C_2_THINKPAD_ACPI), 9819 9819 + SND_PCI_QUIRK(0x17aa, 0x2319, "Thinkpad Z16 Gen2", ALC287_FIXUP_CS35L41_I2C_2_THINKPAD_ACPI), 9820 9820 + SND_PCI_QUIRK(0x17aa, 0x231a, "Thinkpad Z16 Gen2", ALC287_FIXUP_CS35L41_I2C_2_THINKPAD_ACPI), 9857 9821 SND_PCI_QUIRK(0x17aa, 0x30bb, "ThinkCentre AIO", ALC233_FIXUP_LENOVO_LINE2_MIC_HOTKEY), 9858 9822 SND_PCI_QUIRK(0x17aa, 0x30e2, "ThinkCentre AIO", ALC233_FIXUP_LENOVO_LINE2_MIC_HOTKEY), 9859 9823 SND_PCI_QUIRK(0x17aa, 0x310c, "ThinkCentre Station", ALC294_FIXUP_LENOVO_MIC_LOCATION), ··· 10718 10682 spec->shutup = alc256_shutup; 10719 10683 spec->init_hook = alc256_init; 10720 10684 spec->gen.mixer_nid = 0; /* ALC256 does not have any loopback mixer path */ 10685 10685 + if (codec->bus->pci->vendor == PCI_VENDOR_ID_AMD) 10686 10686 + spec->en_3kpull_low = true; 10721 10687 break; 10722 10688 case 0x10ec0257: 10723 10689 spec->codec_variant = ALC269_TYPE_ALC257;

+4 -3

sound/soc/amd/acp/amd.h

reviewed

··· 173 173 174 174 static inline u64 acp_get_byte_count(struct acp_dev_data *adata, int dai_id, int direction) 175 175 { 176 176 - u64 byte_count, low = 0, high = 0; 176 176 + u64 byte_count = 0, low = 0, high = 0; 177 177 178 178 if (direction == SNDRV_PCM_STREAM_PLAYBACK) { 179 179 switch (dai_id) { ··· 191 191 break; 192 192 default: 193 193 dev_err(adata->dev, "Invalid dai id %x\n", dai_id); 194 194 - return -EINVAL; 194 194 + goto POINTER_RETURN_BYTES; 195 195 } 196 196 } else { 197 197 switch (dai_id) { ··· 213 213 break; 214 214 default: 215 215 dev_err(adata->dev, "Invalid dai id %x\n", dai_id); 216 216 - return -EINVAL; 216 216 + goto POINTER_RETURN_BYTES; 217 217 } 218 218 } 219 219 /* Get 64 bit value from two 32 bit registers */ 220 220 byte_count = (high << 32) | low; 221 221 222 222 + POINTER_RETURN_BYTES: 222 223 return byte_count; 223 224 } 224 225

+21 -1

sound/soc/amd/ps/acp63.h

reviewed

··· 116 116 #define ACP63_SDW0_DMA_MAX_STREAMS 6 117 117 #define ACP63_SDW1_DMA_MAX_STREAMS 2 118 118 #define ACP_P1_AUDIO_TX_THRESHOLD 6 119 119 + 120 120 + /* 121 121 + * Below entries describes SDW0 instance DMA stream id and DMA irq bit mapping 122 122 + * in ACP_EXTENAL_INTR_CNTL register. 123 123 + * Stream id IRQ Bit 124 124 + * 0 (SDW0_AUDIO0_TX) 28 125 125 + * 1 (SDW0_AUDIO1_TX) 26 126 126 + * 2 (SDW0_AUDIO2_TX) 24 127 127 + * 3 (SDW0_AUDIO0_RX) 27 128 128 + * 4 (SDW0_AUDIO1_RX) 25 129 129 + * 5 (SDW0_AUDIO2_RX) 23 130 130 + */ 119 131 #define SDW0_DMA_TX_IRQ_MASK(i) (ACP_AUDIO0_TX_THRESHOLD - (2 * (i))) 120 120 - #define SDW0_DMA_RX_IRQ_MASK(i) (ACP_AUDIO0_RX_THRESHOLD - (2 * (i))) 132 132 + #define SDW0_DMA_RX_IRQ_MASK(i) (ACP_AUDIO0_RX_THRESHOLD - (2 * ((i) - 3))) 133 133 + 134 134 + /* 135 135 + * Below entries describes SDW1 instance DMA stream id and DMA irq bit mapping 136 136 + * in ACP_EXTENAL_INTR_CNTL1 register. 137 137 + * Stream id IRQ Bit 138 138 + * 0 (SDW1_AUDIO1_TX) 6 139 139 + * 1 (SDW1_AUDIO1_RX) 5 140 140 + */ 121 141 #define SDW1_DMA_IRQ_MASK(i) (ACP_P1_AUDIO_TX_THRESHOLD - (i)) 122 142 123 143 #define ACP_DELAY_US 5

+2 -2

sound/soc/amd/ps/pci-ps.c

reviewed

··· 257 257 &sdw_manager_bitmap, 1); 258 258 259 259 if (ret) { 260 260 - dev_err(dev, "Failed to read mipi-sdw-manager-list: %d\n", ret); 260 260 + dev_dbg(dev, "Failed to read mipi-sdw-manager-list: %d\n", ret); 261 261 return -EINVAL; 262 262 } 263 263 count = hweight32(sdw_manager_bitmap); ··· 641 641 ret = get_acp63_device_config(val, pci, adata); 642 642 /* ACP PCI driver probe should be continued even PDM or SoundWire Devices are not found */ 643 643 if (ret) { 644 644 - dev_err(&pci->dev, "get acp device config failed:%d\n", ret); 644 644 + dev_dbg(&pci->dev, "get acp device config failed:%d\n", ret); 645 645 goto skip_pdev_creation; 646 646 } 647 647 ret = create_acp63_platform_devs(pci, adata, addr);

+14 -2

sound/soc/amd/ps/ps-sdw-dma.c

reviewed

··· 30 30 ACP_AUDIO2_TX_LINEARPOSITIONCNTR_LOW, ACP_AUDIO2_TX_LINEARPOSITIONCNTR_HIGH}, 31 31 {ACP_AUDIO0_RX_DMA_SIZE, ACP_AUDIO0_RX_FIFOADDR, ACP_AUDIO0_RX_FIFOSIZE, 32 32 ACP_AUDIO0_RX_RINGBUFSIZE, ACP_AUDIO0_RX_RINGBUFADDR, ACP_AUDIO0_RX_INTR_WATERMARK_SIZE, 33 33 - ACP_AUDIO0_TX_LINEARPOSITIONCNTR_LOW, ACP_AUDIO0_TX_LINEARPOSITIONCNTR_HIGH}, 33 33 + ACP_AUDIO0_RX_LINEARPOSITIONCNTR_LOW, ACP_AUDIO0_RX_LINEARPOSITIONCNTR_HIGH}, 34 34 {ACP_AUDIO1_RX_DMA_SIZE, ACP_AUDIO1_RX_FIFOADDR, ACP_AUDIO1_RX_FIFOSIZE, 35 35 ACP_AUDIO1_RX_RINGBUFSIZE, ACP_AUDIO1_RX_RINGBUFADDR, ACP_AUDIO1_RX_INTR_WATERMARK_SIZE, 36 36 ACP_AUDIO1_RX_LINEARPOSITIONCNTR_LOW, ACP_AUDIO1_RX_LINEARPOSITIONCNTR_HIGH}, ··· 39 39 ACP_AUDIO2_RX_LINEARPOSITIONCNTR_LOW, ACP_AUDIO2_RX_LINEARPOSITIONCNTR_HIGH} 40 40 }; 41 41 42 42 + /* 43 43 + * SDW1 instance supports one TX stream and one RX stream. 44 44 + * For TX/RX streams DMA registers programming for SDW1 instance, it uses ACP_P1_AUDIO1 register 45 45 + * set as per hardware register documentation 46 46 + */ 42 47 static struct sdw_dma_ring_buf_reg sdw1_dma_ring_buf_reg[ACP63_SDW1_DMA_MAX_STREAMS] = { 43 48 {ACP_P1_AUDIO1_TX_DMA_SIZE, ACP_P1_AUDIO1_TX_FIFOADDR, ACP_P1_AUDIO1_TX_FIFOSIZE, 44 49 ACP_P1_AUDIO1_TX_RINGBUFSIZE, ACP_P1_AUDIO1_TX_RINGBUFADDR, ··· 64 59 ACP_SW0_AUDIO2_RX_EN, 65 60 }; 66 61 62 62 + /* 63 63 + * SDW1 instance supports one TX stream and one RX stream. 64 64 + * For TX/RX streams DMA enable register programming for SDW1 instance, 65 65 + * it uses ACP_SW1_AUDIO1_TX_EN and ACP_SW1_AUDIO1_RX_EN registers 66 66 + * as per hardware register documentation. 67 67 + */ 67 68 static u32 sdw1_dma_enable_reg[ACP63_SDW1_DMA_MAX_STREAMS] = { 68 69 ACP_SW1_AUDIO1_TX_EN, 69 70 ACP_SW1_AUDIO1_RX_EN, ··· 318 307 pos_high_reg = sdw1_dma_ring_buf_reg[stream->stream_id].pos_high_reg; 319 308 break; 320 309 default: 321 321 - return -EINVAL; 310 310 + goto POINTER_RETURN_BYTES; 322 311 } 323 312 if (pos_low_reg) { 324 313 byte_count.bcount.high = readl(acp_base + pos_high_reg); 325 314 byte_count.bcount.low = readl(acp_base + pos_low_reg); 326 315 } 316 316 + POINTER_RETURN_BYTES: 327 317 return byte_count.bytescount; 328 318 } 329 319

+2

sound/soc/codecs/Kconfig

reviewed

··· 715 715 716 716 config SND_SOC_CS35L45 717 717 tristate 718 718 + select REGMAP_IRQ 718 719 719 720 config SND_SOC_CS35L45_SPI 720 721 tristate "Cirrus Logic CS35L45 CODEC (SPI)" ··· 1943 1942 tristate "WCD9340/WCD9341 Codec" 1944 1943 depends on COMMON_CLK 1945 1944 depends on SLIMBUS 1945 1945 + select REGMAP_IRQ 1946 1946 select REGMAP_SLIMBUS 1947 1947 select SND_SOC_WCD_MBHC 1948 1948 depends on MFD_WCD934X || COMPILE_TEST

+6

sound/soc/codecs/cs42l51-i2c.c

reviewed

··· 19 19 }; 20 20 MODULE_DEVICE_TABLE(i2c, cs42l51_i2c_id); 21 21 22 22 + const struct of_device_id cs42l51_of_match[] = { 23 23 + { .compatible = "cirrus,cs42l51", }, 24 24 + { } 25 25 + }; 26 26 + MODULE_DEVICE_TABLE(of, cs42l51_of_match); 27 27 + 22 28 static int cs42l51_i2c_probe(struct i2c_client *i2c) 23 29 { 24 30 struct regmap_config config;

-7

sound/soc/codecs/cs42l51.c

reviewed

··· 823 823 } 824 824 EXPORT_SYMBOL_GPL(cs42l51_resume); 825 825 826 826 - const struct of_device_id cs42l51_of_match[] = { 827 827 - { .compatible = "cirrus,cs42l51", }, 828 828 - { } 829 829 - }; 830 830 - MODULE_DEVICE_TABLE(of, cs42l51_of_match); 831 831 - EXPORT_SYMBOL_GPL(cs42l51_of_match); 832 832 - 833 826 MODULE_AUTHOR("Arnaud Patard <arnaud.patard@rtp-net.org>"); 834 827 MODULE_DESCRIPTION("Cirrus Logic CS42L51 ALSA SoC Codec Driver"); 835 828 MODULE_LICENSE("GPL");

-1

sound/soc/codecs/cs42l51.h

reviewed

··· 16 16 void cs42l51_remove(struct device *dev); 17 17 int __maybe_unused cs42l51_suspend(struct device *dev); 18 18 int __maybe_unused cs42l51_resume(struct device *dev); 19 19 - extern const struct of_device_id cs42l51_of_match[]; 20 19 21 20 #define CS42L51_CHIP_ID 0x1B 22 21 #define CS42L51_CHIP_REV_A 0x00

+7 -6

sound/soc/codecs/rt5640.c

reviewed

··· 53 53 {RT5640_PR_BASE + 0x3d, 0x3600}, 54 54 {RT5640_PR_BASE + 0x12, 0x0aa8}, 55 55 {RT5640_PR_BASE + 0x14, 0x0aaa}, 56 56 - {RT5640_PR_BASE + 0x20, 0x6110}, 57 56 {RT5640_PR_BASE + 0x21, 0xe0e0}, 58 57 {RT5640_PR_BASE + 0x23, 0x1804}, 59 58 }; ··· 2566 2567 if (jack_data && jack_data->use_platform_clock) 2567 2568 rt5640->use_platform_clock = jack_data->use_platform_clock; 2568 2569 2569 2569 - ret = request_irq(rt5640->irq, rt5640_irq, 2570 2570 - IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 2571 2571 - "rt5640", rt5640); 2570 2570 + ret = devm_request_threaded_irq(component->dev, rt5640->irq, 2571 2571 + NULL, rt5640_irq, 2572 2572 + IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 2573 2573 + "rt5640", rt5640); 2572 2574 if (ret) { 2573 2575 dev_warn(component->dev, "Failed to reguest IRQ %d: %d\n", rt5640->irq, ret); 2574 2576 rt5640_disable_jack_detect(component); ··· 2622 2622 2623 2623 rt5640->jack = jack; 2624 2624 2625 2625 - ret = request_irq(rt5640->irq, rt5640_irq, 2626 2626 - IRQF_TRIGGER_RISING | IRQF_ONESHOT, "rt5640", rt5640); 2625 2625 + ret = devm_request_threaded_irq(component->dev, rt5640->irq, 2626 2626 + NULL, rt5640_irq, IRQF_TRIGGER_RISING | IRQF_ONESHOT, 2627 2627 + "rt5640", rt5640); 2627 2628 if (ret) { 2628 2629 dev_warn(component->dev, "Failed to reguest IRQ %d: %d\n", rt5640->irq, ret); 2629 2630 rt5640->irq = -ENXIO;

+5 -1

sound/soc/codecs/rt5645.c

reviewed

··· 3950 3950 * read and power On. 3951 3951 */ 3952 3952 msleep(TIME_TO_POWER_MS); 3953 3953 - regmap_read(regmap, RT5645_VENDOR_ID2, &val); 3953 3953 + ret = regmap_read(regmap, RT5645_VENDOR_ID2, &val); 3954 3954 + if (ret < 0) { 3955 3955 + dev_err(&i2c->dev, "Failed to read: 0x%02X\n, ret = %d", RT5645_VENDOR_ID2, ret); 3956 3956 + goto err_enable; 3957 3957 + } 3954 3958 3955 3959 switch (val) { 3956 3960 case RT5645_DEVICE_ID:

+41 -16

sound/soc/codecs/wcd-mbhc-v2.c

reviewed

··· 1454 1454 return ERR_PTR(-EINVAL); 1455 1455 } 1456 1456 1457 1457 - mbhc = devm_kzalloc(dev, sizeof(*mbhc), GFP_KERNEL); 1457 1457 + mbhc = kzalloc(sizeof(*mbhc), GFP_KERNEL); 1458 1458 if (!mbhc) 1459 1459 return ERR_PTR(-ENOMEM); 1460 1460 ··· 1474 1474 1475 1475 INIT_WORK(&mbhc->correct_plug_swch, wcd_correct_swch_plug); 1476 1476 1477 1477 - ret = devm_request_threaded_irq(dev, mbhc->intr_ids->mbhc_sw_intr, NULL, 1477 1477 + ret = request_threaded_irq(mbhc->intr_ids->mbhc_sw_intr, NULL, 1478 1478 wcd_mbhc_mech_plug_detect_irq, 1479 1479 IRQF_ONESHOT | IRQF_TRIGGER_RISING, 1480 1480 "mbhc sw intr", mbhc); 1481 1481 if (ret) 1482 1482 - goto err; 1482 1482 + goto err_free_mbhc; 1483 1483 1484 1484 - ret = devm_request_threaded_irq(dev, mbhc->intr_ids->mbhc_btn_press_intr, NULL, 1484 1484 + ret = request_threaded_irq(mbhc->intr_ids->mbhc_btn_press_intr, NULL, 1485 1485 wcd_mbhc_btn_press_handler, 1486 1486 IRQF_ONESHOT | IRQF_TRIGGER_RISING, 1487 1487 "Button Press detect", mbhc); 1488 1488 if (ret) 1489 1489 - goto err; 1489 1489 + goto err_free_sw_intr; 1490 1490 1491 1491 - ret = devm_request_threaded_irq(dev, mbhc->intr_ids->mbhc_btn_release_intr, NULL, 1491 1491 + ret = request_threaded_irq(mbhc->intr_ids->mbhc_btn_release_intr, NULL, 1492 1492 wcd_mbhc_btn_release_handler, 1493 1493 IRQF_ONESHOT | IRQF_TRIGGER_RISING, 1494 1494 "Button Release detect", mbhc); 1495 1495 if (ret) 1496 1496 - goto err; 1496 1496 + goto err_free_btn_press_intr; 1497 1497 1498 1498 - ret = devm_request_threaded_irq(dev, mbhc->intr_ids->mbhc_hs_ins_intr, NULL, 1498 1498 + ret = request_threaded_irq(mbhc->intr_ids->mbhc_hs_ins_intr, NULL, 1499 1499 wcd_mbhc_adc_hs_ins_irq, 1500 1500 IRQF_ONESHOT | IRQF_TRIGGER_RISING, 1501 1501 "Elect Insert", mbhc); 1502 1502 if (ret) 1503 1503 - goto err; 1503 1503 + goto err_free_btn_release_intr; 1504 1504 1505 1505 disable_irq_nosync(mbhc->intr_ids->mbhc_hs_ins_intr); 1506 1506 1507 1507 - ret = devm_request_threaded_irq(dev, mbhc->intr_ids->mbhc_hs_rem_intr, NULL, 1507 1507 + ret = request_threaded_irq(mbhc->intr_ids->mbhc_hs_rem_intr, NULL, 1508 1508 wcd_mbhc_adc_hs_rem_irq, 1509 1509 IRQF_ONESHOT | IRQF_TRIGGER_RISING, 1510 1510 "Elect Remove", mbhc); 1511 1511 if (ret) 1512 1512 - goto err; 1512 1512 + goto err_free_hs_ins_intr; 1513 1513 1514 1514 disable_irq_nosync(mbhc->intr_ids->mbhc_hs_rem_intr); 1515 1515 1516 1516 - ret = devm_request_threaded_irq(dev, mbhc->intr_ids->hph_left_ocp, NULL, 1516 1516 + ret = request_threaded_irq(mbhc->intr_ids->hph_left_ocp, NULL, 1517 1517 wcd_mbhc_hphl_ocp_irq, 1518 1518 IRQF_ONESHOT | IRQF_TRIGGER_RISING, 1519 1519 "HPH_L OCP detect", mbhc); 1520 1520 if (ret) 1521 1521 - goto err; 1521 1521 + goto err_free_hs_rem_intr; 1522 1522 1523 1523 - ret = devm_request_threaded_irq(dev, mbhc->intr_ids->hph_right_ocp, NULL, 1523 1523 + ret = request_threaded_irq(mbhc->intr_ids->hph_right_ocp, NULL, 1524 1524 wcd_mbhc_hphr_ocp_irq, 1525 1525 IRQF_ONESHOT | IRQF_TRIGGER_RISING, 1526 1526 "HPH_R OCP detect", mbhc); 1527 1527 if (ret) 1528 1528 - goto err; 1528 1528 + goto err_free_hph_left_ocp; 1529 1529 1530 1530 return mbhc; 1531 1531 - err: 1531 1531 + 1532 1532 + err_free_hph_left_ocp: 1533 1533 + free_irq(mbhc->intr_ids->hph_left_ocp, mbhc); 1534 1534 + err_free_hs_rem_intr: 1535 1535 + free_irq(mbhc->intr_ids->mbhc_hs_rem_intr, mbhc); 1536 1536 + err_free_hs_ins_intr: 1537 1537 + free_irq(mbhc->intr_ids->mbhc_hs_ins_intr, mbhc); 1538 1538 + err_free_btn_release_intr: 1539 1539 + free_irq(mbhc->intr_ids->mbhc_btn_release_intr, mbhc); 1540 1540 + err_free_btn_press_intr: 1541 1541 + free_irq(mbhc->intr_ids->mbhc_btn_press_intr, mbhc); 1542 1542 + err_free_sw_intr: 1543 1543 + free_irq(mbhc->intr_ids->mbhc_sw_intr, mbhc); 1544 1544 + err_free_mbhc: 1545 1545 + kfree(mbhc); 1546 1546 + 1532 1547 dev_err(dev, "Failed to request mbhc interrupts %d\n", ret); 1533 1548 1534 1549 return ERR_PTR(ret); ··· 1552 1537 1553 1538 void wcd_mbhc_deinit(struct wcd_mbhc *mbhc) 1554 1539 { 1540 1540 + free_irq(mbhc->intr_ids->hph_right_ocp, mbhc); 1541 1541 + free_irq(mbhc->intr_ids->hph_left_ocp, mbhc); 1542 1542 + free_irq(mbhc->intr_ids->mbhc_hs_rem_intr, mbhc); 1543 1543 + free_irq(mbhc->intr_ids->mbhc_hs_ins_intr, mbhc); 1544 1544 + free_irq(mbhc->intr_ids->mbhc_btn_release_intr, mbhc); 1545 1545 + free_irq(mbhc->intr_ids->mbhc_btn_press_intr, mbhc); 1546 1546 + free_irq(mbhc->intr_ids->mbhc_sw_intr, mbhc); 1547 1547 + 1555 1548 mutex_lock(&mbhc->lock); 1556 1549 wcd_cancel_hs_detect_plug(mbhc, &mbhc->correct_plug_swch); 1557 1550 mutex_unlock(&mbhc->lock); 1551 1551 + 1552 1552 + kfree(mbhc); 1558 1553 } 1559 1554 EXPORT_SYMBOL(wcd_mbhc_deinit); 1560 1555

+16 -4

sound/soc/codecs/wcd934x.c

reviewed

··· 2642 2642 return rc; 2643 2643 } 2644 2644 2645 2645 - static inline void wcd934x_mbhc_get_result_params(struct wcd934x_codec *wcd934x, 2645 2645 + static void wcd934x_mbhc_get_result_params(struct wcd934x_codec *wcd934x, 2646 2646 s16 *d1_a, u16 noff, 2647 2647 int32_t *zdet) 2648 2648 { ··· 2683 2683 else if (x1 < minCode_param[noff]) 2684 2684 *zdet = WCD934X_ZDET_FLOATING_IMPEDANCE; 2685 2685 2686 2686 - dev_info(wcd934x->dev, "%s: d1=%d, c1=%d, x1=0x%x, z_val=%d(milliOhm)\n", 2686 2686 + dev_dbg(wcd934x->dev, "%s: d1=%d, c1=%d, x1=0x%x, z_val=%di (milliohm)\n", 2687 2687 __func__, d1, c1, x1, *zdet); 2688 2688 ramp_down: 2689 2689 i = 0; ··· 2740 2740 *zr = zdet; 2741 2741 } 2742 2742 2743 2743 - static inline void wcd934x_wcd_mbhc_qfuse_cal(struct snd_soc_component *component, 2744 2744 - int32_t *z_val, int flag_l_r) 2743 2743 + static void wcd934x_wcd_mbhc_qfuse_cal(struct snd_soc_component *component, 2744 2744 + int32_t *z_val, int flag_l_r) 2745 2745 { 2746 2746 s16 q1; 2747 2747 int q1_cal; ··· 3044 3044 3045 3045 return 0; 3046 3046 } 3047 3047 + 3048 3048 + static void wcd934x_mbhc_deinit(struct snd_soc_component *component) 3049 3049 + { 3050 3050 + struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(component); 3051 3051 + 3052 3052 + if (!wcd->mbhc) 3053 3053 + return; 3054 3054 + 3055 3055 + wcd_mbhc_deinit(wcd->mbhc); 3056 3056 + } 3057 3057 + 3047 3058 static int wcd934x_comp_probe(struct snd_soc_component *component) 3048 3059 { 3049 3060 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); ··· 3088 3077 { 3089 3078 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 3090 3079 3080 3080 + wcd934x_mbhc_deinit(comp); 3091 3081 wcd_clsh_ctrl_free(wcd->clsh_ctrl); 3092 3082 } 3093 3083

+81 -18

sound/soc/codecs/wcd938x.c

reviewed

··· 210 210 }; 211 211 212 212 static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(ear_pa_gain, 600, -1800); 213 213 - static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(line_gain, 600, -3000); 213 213 + static const DECLARE_TLV_DB_SCALE(line_gain, -3000, 150, -3000); 214 214 static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(analog_gain, 0, 3000); 215 215 216 216 struct wcd938x_mbhc_zdet_param { ··· 2124 2124 return wcd938x_mbhc_micb_adjust_voltage(component, micb_mv, MIC_BIAS_2); 2125 2125 } 2126 2126 2127 2127 - static inline void wcd938x_mbhc_get_result_params(struct wcd938x_priv *wcd938x, 2127 2127 + static void wcd938x_mbhc_get_result_params(struct snd_soc_component *component, 2128 2128 s16 *d1_a, u16 noff, 2129 2129 int32_t *zdet) 2130 2130 { 2131 2131 + struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2131 2132 int i; 2132 2133 int val, val1; 2133 2134 s16 c1; ··· 2155 2154 usleep_range(5000, 5050); 2156 2155 2157 2156 if (!c1 || !x1) { 2158 2158 - pr_err("%s: Impedance detect ramp error, c1=%d, x1=0x%x\n", 2159 2159 - __func__, c1, x1); 2157 2157 + dev_err(component->dev, "Impedance detect ramp error, c1=%d, x1=0x%x\n", 2158 2158 + c1, x1); 2160 2159 goto ramp_down; 2161 2160 } 2162 2161 d1 = d1_a[c1]; ··· 2166 2165 else if (x1 < minCode_param[noff]) 2167 2166 *zdet = WCD938X_ZDET_FLOATING_IMPEDANCE; 2168 2167 2169 2169 - pr_err("%s: d1=%d, c1=%d, x1=0x%x, z_val=%d(milliOhm)\n", 2168 2168 + dev_dbg(component->dev, "%s: d1=%d, c1=%d, x1=0x%x, z_val=%d (milliohm)\n", 2170 2169 __func__, d1, c1, x1, *zdet); 2171 2170 ramp_down: 2172 2171 i = 0; ··· 2211 2210 WCD938X_ANA_MBHC_ZDET, 0x80, 0x80); 2212 2211 dev_dbg(component->dev, "%s: ramp for HPH_L, noff = %d\n", 2213 2212 __func__, zdet_param->noff); 2214 2214 - wcd938x_mbhc_get_result_params(wcd938x, d1_a, zdet_param->noff, &zdet); 2213 2213 + wcd938x_mbhc_get_result_params(component, d1_a, zdet_param->noff, &zdet); 2215 2214 regmap_update_bits(wcd938x->regmap, 2216 2215 WCD938X_ANA_MBHC_ZDET, 0x80, 0x00); 2217 2216 ··· 2225 2224 WCD938X_ANA_MBHC_ZDET, 0x40, 0x40); 2226 2225 dev_dbg(component->dev, "%s: ramp for HPH_R, noff = %d\n", 2227 2226 __func__, zdet_param->noff); 2228 2228 - wcd938x_mbhc_get_result_params(wcd938x, d1_a, zdet_param->noff, &zdet); 2227 2227 + wcd938x_mbhc_get_result_params(component, d1_a, zdet_param->noff, &zdet); 2229 2228 regmap_update_bits(wcd938x->regmap, 2230 2229 WCD938X_ANA_MBHC_ZDET, 0x40, 0x00); 2231 2230 2232 2231 *zr = zdet; 2233 2232 } 2234 2233 2235 2235 - static inline void wcd938x_wcd_mbhc_qfuse_cal(struct snd_soc_component *component, 2236 2236 - int32_t *z_val, int flag_l_r) 2234 2234 + static void wcd938x_wcd_mbhc_qfuse_cal(struct snd_soc_component *component, 2235 2235 + int32_t *z_val, int flag_l_r) 2237 2236 { 2238 2237 s16 q1; 2239 2238 int q1_cal; ··· 2626 2625 WCD938X_IRQ_HPHR_OCP_INT); 2627 2626 2628 2627 wcd938x->wcd_mbhc = wcd_mbhc_init(component, &mbhc_cb, intr_ids, wcd_mbhc_fields, true); 2628 2628 + if (IS_ERR(wcd938x->wcd_mbhc)) 2629 2629 + return PTR_ERR(wcd938x->wcd_mbhc); 2629 2630 2630 2631 snd_soc_add_component_controls(component, impedance_detect_controls, 2631 2632 ARRAY_SIZE(impedance_detect_controls)); ··· 2636 2633 2637 2634 return 0; 2638 2635 } 2636 2636 + 2637 2637 + static void wcd938x_mbhc_deinit(struct snd_soc_component *component) 2638 2638 + { 2639 2639 + struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2640 2640 + 2641 2641 + wcd_mbhc_deinit(wcd938x->wcd_mbhc); 2642 2642 + } 2643 2643 + 2639 2644 /* END MBHC */ 2640 2645 2641 2646 static const struct snd_kcontrol_new wcd938x_snd_controls[] = { ··· 2663 2652 wcd938x_get_swr_port, wcd938x_set_swr_port), 2664 2653 SOC_SINGLE_EXT("DSD_R Switch", WCD938X_DSD_R, 0, 1, 0, 2665 2654 wcd938x_get_swr_port, wcd938x_set_swr_port), 2666 2666 - SOC_SINGLE_TLV("HPHL Volume", WCD938X_HPH_L_EN, 0, 0x18, 0, line_gain), 2667 2667 - SOC_SINGLE_TLV("HPHR Volume", WCD938X_HPH_R_EN, 0, 0x18, 0, line_gain), 2655 2655 + SOC_SINGLE_TLV("HPHL Volume", WCD938X_HPH_L_EN, 0, 0x18, 1, line_gain), 2656 2656 + SOC_SINGLE_TLV("HPHR Volume", WCD938X_HPH_R_EN, 0, 0x18, 1, line_gain), 2668 2657 WCD938X_EAR_PA_GAIN_TLV("EAR_PA Volume", WCD938X_ANA_EAR_COMPANDER_CTL, 2669 2658 2, 0x10, 0, ear_pa_gain), 2670 2659 SOC_SINGLE_EXT("ADC1 Switch", WCD938X_ADC1, 1, 1, 0, ··· 3091 3080 static int wcd938x_soc_codec_probe(struct snd_soc_component *component) 3092 3081 { 3093 3082 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 3083 3083 + struct sdw_slave *tx_sdw_dev = wcd938x->tx_sdw_dev; 3094 3084 struct device *dev = component->dev; 3085 3085 + unsigned long time_left; 3095 3086 int ret, i; 3096 3087 3088 3088 + time_left = wait_for_completion_timeout(&tx_sdw_dev->initialization_complete, 3089 3089 + msecs_to_jiffies(2000)); 3090 3090 + if (!time_left) { 3091 3091 + dev_err(dev, "soundwire device init timeout\n"); 3092 3092 + return -ETIMEDOUT; 3093 3093 + } 3094 3094 + 3097 3095 snd_soc_component_init_regmap(component, wcd938x->regmap); 3096 3096 + 3097 3097 + ret = pm_runtime_resume_and_get(dev); 3098 3098 + if (ret < 0) 3099 3099 + return ret; 3098 3100 3099 3101 wcd938x->variant = snd_soc_component_read_field(component, 3100 3102 WCD938X_DIGITAL_EFUSE_REG_0, 3101 3103 WCD938X_ID_MASK); 3102 3104 3103 3105 wcd938x->clsh_info = wcd_clsh_ctrl_alloc(component, WCD938X); 3106 3106 + if (IS_ERR(wcd938x->clsh_info)) { 3107 3107 + pm_runtime_put(dev); 3108 3108 + return PTR_ERR(wcd938x->clsh_info); 3109 3109 + } 3104 3110 3105 3111 wcd938x_io_init(wcd938x); 3106 3112 /* Set all interrupts as edge triggered */ ··· 3125 3097 regmap_write(wcd938x->regmap, 3126 3098 (WCD938X_DIGITAL_INTR_LEVEL_0 + i), 0); 3127 3099 } 3100 3100 + 3101 3101 + pm_runtime_put(dev); 3128 3102 3129 3103 wcd938x->hphr_pdm_wd_int = regmap_irq_get_virq(wcd938x->irq_chip, 3130 3104 WCD938X_IRQ_HPHR_PDM_WD_INT); ··· 3139 3109 ret = request_threaded_irq(wcd938x->hphr_pdm_wd_int, NULL, wcd938x_wd_handle_irq, 3140 3110 IRQF_ONESHOT | IRQF_TRIGGER_RISING, 3141 3111 "HPHR PDM WD INT", wcd938x); 3142 3142 - if (ret) 3112 3112 + if (ret) { 3143 3113 dev_err(dev, "Failed to request HPHR WD interrupt (%d)\n", ret); 3114 3114 + goto err_free_clsh_ctrl; 3115 3115 + } 3144 3116 3145 3117 ret = request_threaded_irq(wcd938x->hphl_pdm_wd_int, NULL, wcd938x_wd_handle_irq, 3146 3118 IRQF_ONESHOT | IRQF_TRIGGER_RISING, 3147 3119 "HPHL PDM WD INT", wcd938x); 3148 3148 - if (ret) 3120 3120 + if (ret) { 3149 3121 dev_err(dev, "Failed to request HPHL WD interrupt (%d)\n", ret); 3122 3122 + goto err_free_hphr_pdm_wd_int; 3123 3123 + } 3150 3124 3151 3125 ret = request_threaded_irq(wcd938x->aux_pdm_wd_int, NULL, wcd938x_wd_handle_irq, 3152 3126 IRQF_ONESHOT | IRQF_TRIGGER_RISING, 3153 3127 "AUX PDM WD INT", wcd938x); 3154 3154 - if (ret) 3128 3128 + if (ret) { 3155 3129 dev_err(dev, "Failed to request Aux WD interrupt (%d)\n", ret); 3130 3130 + goto err_free_hphl_pdm_wd_int; 3131 3131 + } 3156 3132 3157 3133 /* Disable watchdog interrupt for HPH and AUX */ 3158 3134 disable_irq_nosync(wcd938x->hphr_pdm_wd_int); ··· 3173 3137 dev_err(component->dev, 3174 3138 "%s: Failed to add snd ctrls for variant: %d\n", 3175 3139 __func__, wcd938x->variant); 3176 3176 - goto err; 3140 3140 + goto err_free_aux_pdm_wd_int; 3177 3141 } 3178 3142 break; 3179 3143 case WCD9385: ··· 3183 3147 dev_err(component->dev, 3184 3148 "%s: Failed to add snd ctrls for variant: %d\n", 3185 3149 __func__, wcd938x->variant); 3186 3186 - goto err; 3150 3150 + goto err_free_aux_pdm_wd_int; 3187 3151 } 3188 3152 break; 3189 3153 default: ··· 3191 3155 } 3192 3156 3193 3157 ret = wcd938x_mbhc_init(component); 3194 3194 - if (ret) 3158 3158 + if (ret) { 3195 3159 dev_err(component->dev, "mbhc initialization failed\n"); 3196 3196 - err: 3160 3160 + goto err_free_aux_pdm_wd_int; 3161 3161 + } 3162 3162 + 3163 3163 + return 0; 3164 3164 + 3165 3165 + err_free_aux_pdm_wd_int: 3166 3166 + free_irq(wcd938x->aux_pdm_wd_int, wcd938x); 3167 3167 + err_free_hphl_pdm_wd_int: 3168 3168 + free_irq(wcd938x->hphl_pdm_wd_int, wcd938x); 3169 3169 + err_free_hphr_pdm_wd_int: 3170 3170 + free_irq(wcd938x->hphr_pdm_wd_int, wcd938x); 3171 3171 + err_free_clsh_ctrl: 3172 3172 + wcd_clsh_ctrl_free(wcd938x->clsh_info); 3173 3173 + 3197 3174 return ret; 3175 3175 + } 3176 3176 + 3177 3177 + static void wcd938x_soc_codec_remove(struct snd_soc_component *component) 3178 3178 + { 3179 3179 + struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 3180 3180 + 3181 3181 + wcd938x_mbhc_deinit(component); 3182 3182 + 3183 3183 + free_irq(wcd938x->aux_pdm_wd_int, wcd938x); 3184 3184 + free_irq(wcd938x->hphl_pdm_wd_int, wcd938x); 3185 3185 + free_irq(wcd938x->hphr_pdm_wd_int, wcd938x); 3186 3186 + 3187 3187 + wcd_clsh_ctrl_free(wcd938x->clsh_info); 3198 3188 } 3199 3189 3200 3190 static int wcd938x_codec_set_jack(struct snd_soc_component *comp, ··· 3239 3177 static const struct snd_soc_component_driver soc_codec_dev_wcd938x = { 3240 3178 .name = "wcd938x_codec", 3241 3179 .probe = wcd938x_soc_codec_probe, 3180 3180 + .remove = wcd938x_soc_codec_remove, 3242 3181 .controls = wcd938x_snd_controls, 3243 3182 .num_controls = ARRAY_SIZE(wcd938x_snd_controls), 3244 3183 .dapm_widgets = wcd938x_dapm_widgets,

+1 -7

sound/soc/fsl/fsl_sai.c

reviewed

··· 507 507 savediv / 2 - 1); 508 508 } 509 509 510 510 - if (sai->soc_data->max_register >= FSL_SAI_MCTL) { 511 511 - /* SAI is in master mode at this point, so enable MCLK */ 512 512 - regmap_update_bits(sai->regmap, FSL_SAI_MCTL, 513 513 - FSL_SAI_MCTL_MCLK_EN, FSL_SAI_MCTL_MCLK_EN); 514 514 - } 515 515 - 516 510 return 0; 517 511 } 518 512 ··· 713 719 u32 xcsr, count = 100; 714 720 715 721 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 716 716 - FSL_SAI_CSR_TERE, 0); 722 722 + FSL_SAI_CSR_TERE | FSL_SAI_CSR_BCE, 0); 717 723 718 724 /* TERE will remain set till the end of current frame */ 719 725 do {

+1

sound/soc/fsl/fsl_sai.h

reviewed

··· 91 91 /* SAI Transmit/Receive Control Register */ 92 92 #define FSL_SAI_CSR_TERE BIT(31) 93 93 #define FSL_SAI_CSR_SE BIT(30) 94 94 + #define FSL_SAI_CSR_BCE BIT(28) 94 95 #define FSL_SAI_CSR_FR BIT(25) 95 96 #define FSL_SAI_CSR_SR BIT(24) 96 97 #define FSL_SAI_CSR_xF_SHIFT 16

+1 -1

sound/soc/qcom/qdsp6/q6afe-dai.c

reviewed

··· 476 476 477 477 static const struct snd_soc_dapm_route q6afe_dapm_routes[] = { 478 478 {"HDMI Playback", NULL, "HDMI_RX"}, 479 479 - {"Display Port Playback", NULL, "DISPLAY_PORT_RX"}, 479 479 + {"DISPLAY_PORT_RX_0 Playback", NULL, "DISPLAY_PORT_RX"}, 480 480 {"Slimbus Playback", NULL, "SLIMBUS_0_RX"}, 481 481 {"Slimbus1 Playback", NULL, "SLIMBUS_1_RX"}, 482 482 {"Slimbus2 Playback", NULL, "SLIMBUS_2_RX"},

+1

sound/soc/qcom/qdsp6/q6apm-dai.c

reviewed

··· 840 840 .pointer = q6apm_dai_pointer, 841 841 .trigger = q6apm_dai_trigger, 842 842 .compress_ops = &q6apm_dai_compress_ops, 843 843 + .use_dai_pcm_id = true, 843 844 }; 844 845 845 846 static int q6apm_dai_probe(struct platform_device *pdev)

+6 -1

sound/soc/qcom/qdsp6/q6apm.c

reviewed

··· 511 511 512 512 switch (hdr->opcode) { 513 513 case DATA_CMD_RSP_WR_SH_MEM_EP_DATA_BUFFER_DONE_V2: 514 514 + if (!graph->ar_graph) 515 515 + break; 514 516 client_event = APM_CLIENT_EVENT_DATA_WRITE_DONE; 515 517 mutex_lock(&graph->lock); 516 518 token = hdr->token & APM_WRITE_TOKEN_MASK; ··· 546 544 wake_up(&graph->cmd_wait); 547 545 break; 548 546 case DATA_CMD_RSP_RD_SH_MEM_EP_DATA_BUFFER_V2: 547 547 + if (!graph->ar_graph) 548 548 + break; 549 549 client_event = APM_CLIENT_EVENT_DATA_READ_DONE; 550 550 mutex_lock(&graph->lock); 551 551 rd_done = data->payload; ··· 653 649 { 654 650 struct audioreach_graph *ar_graph = graph->ar_graph; 655 651 656 656 - gpr_free_port(graph->port); 652 652 + graph->ar_graph = NULL; 657 653 kref_put(&ar_graph->refcount, q6apm_put_audioreach_graph); 654 654 + gpr_free_port(graph->port); 658 655 kfree(graph); 659 656 660 657 return 0;

+2 -2

sound/soc/qcom/qdsp6/topology.c

reviewed

··· 1277 1277 1278 1278 ret = snd_soc_tplg_component_load(component, &audioreach_tplg_ops, fw); 1279 1279 if (ret < 0) { 1280 1280 - dev_err(dev, "tplg component load failed%d\n", ret); 1281 1281 - ret = -EINVAL; 1280 1280 + if (ret != -EPROBE_DEFER) 1281 1281 + dev_err(dev, "tplg component load failed: %d\n", ret); 1282 1282 } 1283 1283 1284 1284 release_firmware(fw);

+4 -2

sound/soc/soc-core.c

reviewed

··· 1988 1988 /* probe all components used by DAI links on this card */ 1989 1989 ret = soc_probe_link_components(card); 1990 1990 if (ret < 0) { 1991 1991 - dev_err(card->dev, 1992 1992 - "ASoC: failed to instantiate card %d\n", ret); 1991 1991 + if (ret != -EPROBE_DEFER) { 1992 1992 + dev_err(card->dev, 1993 1993 + "ASoC: failed to instantiate card %d\n", ret); 1994 1994 + } 1993 1995 goto probe_end; 1994 1996 } 1995 1997

+7 -3

sound/soc/soc-topology.c

reviewed

··· 1732 1732 1733 1733 ret = snd_soc_add_pcm_runtimes(tplg->comp->card, link, 1); 1734 1734 if (ret < 0) { 1735 1735 - dev_err(tplg->dev, "ASoC: adding FE link failed\n"); 1735 1735 + if (ret != -EPROBE_DEFER) 1736 1736 + dev_err(tplg->dev, "ASoC: adding FE link failed\n"); 1736 1737 goto err; 1737 1738 } 1738 1739 ··· 2493 2492 /* load the header object */ 2494 2493 ret = soc_tplg_load_header(tplg, hdr); 2495 2494 if (ret < 0) { 2496 2496 - dev_err(tplg->dev, 2497 2497 - "ASoC: topology: could not load header: %d\n", ret); 2495 2495 + if (ret != -EPROBE_DEFER) { 2496 2496 + dev_err(tplg->dev, 2497 2497 + "ASoC: topology: could not load header: %d\n", 2498 2498 + ret); 2499 2499 + } 2498 2500 return ret; 2499 2501 } 2500 2502

+7 -3

sound/soc/sof/amd/acp.c

reviewed

··· 217 217 unsigned int image_length) 218 218 { 219 219 struct snd_sof_dev *sdev = adata->dev; 220 220 + const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 220 221 unsigned int tx_count, fw_qualifier, val; 221 222 int ret; 222 223 ··· 252 251 return ret; 253 252 } 254 253 255 255 - ret = psp_send_cmd(adata, MBOX_ACP_SHA_DMA_COMMAND); 256 256 - if (ret) 257 257 - return ret; 254 254 + /* psp_send_cmd only required for renoir platform (rev - 3) */ 255 255 + if (desc->rev == 3) { 256 256 + ret = psp_send_cmd(adata, MBOX_ACP_SHA_DMA_COMMAND); 257 257 + if (ret) 258 258 + return ret; 259 259 + } 258 260 259 261 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_DSP_FW_QUALIFIER, 260 262 fw_qualifier, fw_qualifier & DSP_FW_RUN_ENABLE,

+4 -5

sound/soc/sof/ipc3-dtrace.c

reviewed

··· 186 186 struct snd_sof_dfsentry *dfse = file->private_data; 187 187 struct sof_ipc_trace_filter_elem *elems = NULL; 188 188 struct snd_sof_dev *sdev = dfse->sdev; 189 189 - loff_t pos = 0; 190 189 int num_elems; 191 190 char *string; 192 191 int ret; ··· 200 201 if (!string) 201 202 return -ENOMEM; 202 203 203 203 - /* assert null termination */ 204 204 - string[count] = 0; 205 205 - ret = simple_write_to_buffer(string, count, &pos, from, count); 206 206 - if (ret < 0) 204 204 + if (copy_from_user(string, from, count)) { 205 205 + ret = -EFAULT; 207 206 goto error; 207 207 + } 208 208 + string[count] = '\0'; 208 209 209 210 ret = trace_filter_parse(sdev, string, &num_elems, &elems); 210 211 if (ret < 0)

+22 -12

sound/soc/tegra/tegra210_adx.c

reviewed

··· 2 2 // 3 3 // tegra210_adx.c - Tegra210 ADX driver 4 4 // 5 5 - // Copyright (c) 2021 NVIDIA CORPORATION. All rights reserved. 5 5 + // Copyright (c) 2021-2023 NVIDIA CORPORATION. All rights reserved. 6 6 7 7 #include <linux/clk.h> 8 8 #include <linux/device.h> ··· 175 175 mc = (struct soc_mixer_control *)kcontrol->private_value; 176 176 enabled = adx->byte_mask[mc->reg / 32] & (1 << (mc->reg % 32)); 177 177 178 178 + /* 179 179 + * TODO: Simplify this logic to just return from bytes_map[] 180 180 + * 181 181 + * Presently below is required since bytes_map[] is 182 182 + * tightly packed and cannot store the control value of 256. 183 183 + * Byte mask state is used to know if 256 needs to be returned. 184 184 + * Note that for control value of 256, the put() call stores 0 185 185 + * in the bytes_map[] and disables the corresponding bit in 186 186 + * byte_mask[]. 187 187 + */ 178 188 if (enabled) 179 189 ucontrol->value.integer.value[0] = bytes_map[mc->reg]; 180 190 else 181 181 - ucontrol->value.integer.value[0] = 0; 191 191 + ucontrol->value.integer.value[0] = 256; 182 192 183 193 return 0; 184 194 } ··· 202 192 int value = ucontrol->value.integer.value[0]; 203 193 struct soc_mixer_control *mc = 204 194 (struct soc_mixer_control *)kcontrol->private_value; 195 195 + unsigned int mask_val = adx->byte_mask[mc->reg / 32]; 205 196 206 206 - if (value == bytes_map[mc->reg]) 197 197 + if (value >= 0 && value <= 255) 198 198 + mask_val |= (1 << (mc->reg % 32)); 199 199 + else 200 200 + mask_val &= ~(1 << (mc->reg % 32)); 201 201 + 202 202 + if (mask_val == adx->byte_mask[mc->reg / 32]) 207 203 return 0; 208 204 209 209 - if (value >= 0 && value <= 255) { 210 210 - /* update byte map and enable slot */ 211 211 - bytes_map[mc->reg] = value; 212 212 - adx->byte_mask[mc->reg / 32] |= (1 << (mc->reg % 32)); 213 213 - } else { 214 214 - /* reset byte map and disable slot */ 215 215 - bytes_map[mc->reg] = 0; 216 216 - adx->byte_mask[mc->reg / 32] &= ~(1 << (mc->reg % 32)); 217 217 - } 205 205 + /* Update byte map and slot */ 206 206 + bytes_map[mc->reg] = value % 256; 207 207 + adx->byte_mask[mc->reg / 32] = mask_val; 218 208 219 209 return 1; 220 210 }

+22 -18

sound/soc/tegra/tegra210_amx.c

reviewed

··· 2 2 // 3 3 // tegra210_amx.c - Tegra210 AMX driver 4 4 // 5 5 - // Copyright (c) 2021 NVIDIA CORPORATION. All rights reserved. 5 5 + // Copyright (c) 2021-2023 NVIDIA CORPORATION. All rights reserved. 6 6 7 7 #include <linux/clk.h> 8 8 #include <linux/device.h> ··· 203 203 else 204 204 enabled = amx->byte_mask[0] & (1 << reg); 205 205 206 206 + /* 207 207 + * TODO: Simplify this logic to just return from bytes_map[] 208 208 + * 209 209 + * Presently below is required since bytes_map[] is 210 210 + * tightly packed and cannot store the control value of 256. 211 211 + * Byte mask state is used to know if 256 needs to be returned. 212 212 + * Note that for control value of 256, the put() call stores 0 213 213 + * in the bytes_map[] and disables the corresponding bit in 214 214 + * byte_mask[]. 215 215 + */ 206 216 if (enabled) 207 217 ucontrol->value.integer.value[0] = bytes_map[reg]; 208 218 else 209 209 - ucontrol->value.integer.value[0] = 0; 219 219 + ucontrol->value.integer.value[0] = 256; 210 220 211 221 return 0; 212 222 } ··· 231 221 unsigned char *bytes_map = (unsigned char *)&amx->map; 232 222 int reg = mc->reg; 233 223 int value = ucontrol->value.integer.value[0]; 224 224 + unsigned int mask_val = amx->byte_mask[reg / 32]; 234 225 235 235 - if (value == bytes_map[reg]) 226 226 + if (value >= 0 && value <= 255) 227 227 + mask_val |= (1 << (reg % 32)); 228 228 + else 229 229 + mask_val &= ~(1 << (reg % 32)); 230 230 + 231 231 + if (mask_val == amx->byte_mask[reg / 32]) 236 232 return 0; 237 233 238 238 - if (value >= 0 && value <= 255) { 239 239 - /* Update byte map and enable slot */ 240 240 - bytes_map[reg] = value; 241 241 - if (reg > 31) 242 242 - amx->byte_mask[1] |= (1 << (reg - 32)); 243 243 - else 244 244 - amx->byte_mask[0] |= (1 << reg); 245 245 - } else { 246 246 - /* Reset byte map and disable slot */ 247 247 - bytes_map[reg] = 0; 248 248 - if (reg > 31) 249 249 - amx->byte_mask[1] &= ~(1 << (reg - 32)); 250 250 - else 251 251 - amx->byte_mask[0] &= ~(1 << reg); 252 252 - } 234 234 + /* Update byte map and slot */ 235 235 + bytes_map[reg] = value % 256; 236 236 + amx->byte_mask[reg / 32] = mask_val; 253 237 254 238 return 1; 255 239 }

+8 -8

tools/net/ynl/lib/ynl.py

reviewed

··· 417 417 pad = b'\x00' * ((4 - len(attr_payload) % 4) % 4) 418 418 return struct.pack('HH', len(attr_payload) + 4, nl_type) + attr_payload + pad 419 419 420 420 - def _decode_enum(self, rsp, attr_spec): 421 421 - raw = rsp[attr_spec['name']] 420 420 + def _decode_enum(self, raw, attr_spec): 422 421 enum = self.consts[attr_spec['enum']] 423 423 - i = attr_spec.get('value-start', 0) 424 422 if 'enum-as-flags' in attr_spec and attr_spec['enum-as-flags']: 423 423 + i = 0 425 424 value = set() 426 425 while raw: 427 426 if raw & 1: ··· 428 429 raw >>= 1 429 430 i += 1 430 431 else: 431 431 - value = enum.entries_by_val[raw - i].name 432 432 - rsp[attr_spec['name']] = value 432 432 + value = enum.entries_by_val[raw].name 433 433 + return value 433 434 434 435 def _decode_binary(self, attr, attr_spec): 435 436 if attr_spec.struct_name: ··· 437 438 decoded = attr.as_struct(members) 438 439 for m in members: 439 440 if m.enum: 440 440 - self._decode_enum(decoded, m) 441 441 + decoded[m.name] = self._decode_enum(decoded[m.name], m) 441 442 elif attr_spec.sub_type: 442 443 decoded = attr.as_c_array(attr_spec.sub_type) 443 444 else: ··· 465 466 else: 466 467 raise Exception(f'Unknown {attr_spec["type"]} with name {attr_spec["name"]}') 467 468 469 469 + if 'enum' in attr_spec: 470 470 + decoded = self._decode_enum(decoded, attr_spec) 471 471 + 468 472 if not attr_spec.is_multi: 469 473 rsp[attr_spec['name']] = decoded 470 474 elif attr_spec.name in rsp: ··· 475 473 else: 476 474 rsp[attr_spec.name] = [decoded] 477 475 478 478 - if 'enum' in attr_spec: 479 479 - self._decode_enum(rsp, attr_spec) 480 476 return rsp 481 477 482 478 def _decode_extack_path(self, attrs, attr_set, offset, target):

+1

tools/testing/selftests/alsa/.gitignore

reviewed

··· 1 1 mixer-test 2 2 pcm-test 3 3 + test-pcmtest-driver

+1 -3

tools/testing/selftests/alsa/test-pcmtest-driver.c

reviewed

··· 47 47 48 48 sprintf(pf, "/sys/kernel/debug/pcmtest/fill_pattern%d", i); 49 49 fp = fopen(pf, "r"); 50 50 - if (!fp) { 51 51 - fclose(fpl); 50 50 + if (!fp) 52 51 return -1; 53 53 - } 54 52 fread(patterns[i].buf, 1, patterns[i].len, fp); 55 53 fclose(fp); 56 54 }

+1 -3

tools/testing/selftests/net/mptcp/mptcp_join.sh

reviewed

··· 166 166 elif ! iptables -V &> /dev/null; then 167 167 echo "SKIP: Could not run all tests without iptables tool" 168 168 exit $ksft_skip 169 169 - fi 170 170 - 171 171 - if ! ip6tables -V &> /dev/null; then 169 169 + elif ! ip6tables -V &> /dev/null; then 172 170 echo "SKIP: Could not run all tests without ip6tables tool" 173 171 exit $ksft_skip 174 172 fi