ASoC: nau8821: Improve AMIC recording performance.

+66 -1

2 changed files

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sound

soc

codecs

nau8821.c

nau8821.h

+41 -1

sound/soc/codecs/nau8821.c

··· 624 624 return 0; 625 625 } 626 626 627 + static int nau8821_left_fepga_event(struct snd_soc_dapm_widget *w, 628 + struct snd_kcontrol *kcontrol, int event) 629 + { 630 + struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 631 + struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 632 + 633 + if (!nau8821->left_input_single_end) 634 + return 0; 635 + 636 + switch (event) { 637 + case SND_SOC_DAPM_POST_PMU: 638 + regmap_update_bits(nau8821->regmap, NAU8821_R77_FEPGA, 639 + NAU8821_ACDC_CTRL_MASK | NAU8821_FEPGA_MODEL_MASK, 640 + NAU8821_ACDC_VREF_MICN | NAU8821_FEPGA_MODEL_AAF); 641 + regmap_update_bits(nau8821->regmap, NAU8821_R76_BOOST, 642 + NAU8821_HP_BOOST_DISCHRG_EN, NAU8821_HP_BOOST_DISCHRG_EN); 643 + break; 644 + case SND_SOC_DAPM_POST_PMD: 645 + regmap_update_bits(nau8821->regmap, NAU8821_R77_FEPGA, 646 + NAU8821_ACDC_CTRL_MASK | NAU8821_FEPGA_MODEL_MASK, 0); 647 + regmap_update_bits(nau8821->regmap, NAU8821_R76_BOOST, 648 + NAU8821_HP_BOOST_DISCHRG_EN, 0); 649 + break; 650 + default: 651 + break; 652 + } 653 + 654 + return 0; 655 + } 656 + 627 657 static const struct snd_soc_dapm_widget nau8821_dapm_widgets[] = { 628 658 SND_SOC_DAPM_SUPPLY("System Clock", SND_SOC_NOPM, 0, 0, 629 659 system_clock_control, SND_SOC_DAPM_POST_PMD), ··· 665 635 NAU8821_POWERUP_ADCL_SFT, 0), 666 636 SND_SOC_DAPM_ADC("ADCR Power", NULL, NAU8821_R72_ANALOG_ADC_2, 667 637 NAU8821_POWERUP_ADCR_SFT, 0), 638 + /* single-ended design only on the left */ 668 639 SND_SOC_DAPM_PGA_S("Frontend PGA L", 1, NAU8821_R7F_POWER_UP_CONTROL, 669 - NAU8821_PUP_PGA_L_SFT, 0, NULL, 0), 640 + NAU8821_PUP_PGA_L_SFT, 0, nau8821_left_fepga_event, 641 + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 670 642 SND_SOC_DAPM_PGA_S("Frontend PGA R", 1, NAU8821_R7F_POWER_UP_CONTROL, 671 643 NAU8821_PUP_PGA_R_SFT, 0, NULL, 0), 672 644 SND_SOC_DAPM_PGA_S("ADCL Digital path", 0, NAU8821_R01_ENA_CTRL, ··· 1709 1677 "nuvoton,jkdet-pull-up"); 1710 1678 nau8821->key_enable = device_property_read_bool(dev, 1711 1679 "nuvoton,key-enable"); 1680 + nau8821->left_input_single_end = device_property_read_bool(dev, 1681 + "nuvoton,left-input-single-end"); 1712 1682 ret = device_property_read_u32(dev, "nuvoton,jkdet-polarity", 1713 1683 &nau8821->jkdet_polarity); 1714 1684 if (ret) ··· 1794 1760 NAU8821_ADC_SYNC_DOWN_MASK, NAU8821_ADC_SYNC_DOWN_64); 1795 1761 regmap_update_bits(regmap, NAU8821_R2C_DAC_CTRL1, 1796 1762 NAU8821_DAC_OVERSAMPLE_MASK, NAU8821_DAC_OVERSAMPLE_64); 1763 + if (nau8821->left_input_single_end) { 1764 + regmap_update_bits(regmap, NAU8821_R6B_PGA_MUTE, 1765 + NAU8821_MUTE_MICNL_EN, NAU8821_MUTE_MICNL_EN); 1766 + regmap_update_bits(regmap, NAU8821_R74_MIC_BIAS, 1767 + NAU8821_MICBIAS_LOWNOISE_EN, NAU8821_MICBIAS_LOWNOISE_EN); 1768 + } 1797 1769 } 1798 1770 1799 1771 static int nau8821_setup_irq(struct nau8821 *nau8821)

+25

sound/soc/codecs/nau8821.h

··· 433 433 #define NAU8821_DAC_CAPACITOR_MSB (0x1 << 1) 434 434 #define NAU8821_DAC_CAPACITOR_LSB 0x1 435 435 436 + /* MUTE_MIC_L_N (0x6b) */ 437 + #define NAU8821_MUTE_MICNL_SFT 5 438 + #define NAU8821_MUTE_MICNL_EN (0x1 << NAU8821_MUTE_MICNL_SFT) 439 + #define NAU8821_MUTE_MICNR_SFT 4 440 + #define NAU8821_MUTE_MICNR_EN (0x1 << NAU8821_MUTE_MICNR_SFT) 441 + #define NAU8821_MUTE_MICRP_SFT 2 442 + #define NAU8821_MUTE_MICRP_EN (0x1 << NAU8821_MUTE_MICRP_SFT) 443 + 436 444 /* ANALOG_ADC_1 (0x71) */ 437 445 #define NAU8821_MICDET_EN_SFT 0 438 446 #define NAU8821_MICDET_MASK 0x1 ··· 471 463 472 464 /* MIC_BIAS (0x74) */ 473 465 #define NAU8821_MICBIAS_JKR2 (0x1 << 12) 466 + #define NAU8821_MICBIAS_LOWNOISE_SFT 10 467 + #define NAU8821_MICBIAS_LOWNOISE_EN (0x1 << NAU8821_MICBIAS_LOWNOISE_SFT) 474 468 #define NAU8821_MICBIAS_POWERUP_SFT 8 469 + #define NAU8821_MICBIAS_POWERUP_EN (0x1 << NAU8821_MICBIAS_POWERUP_SFT) 475 470 #define NAU8821_MICBIAS_VOLTAGE_SFT 0 476 471 #define NAU8821_MICBIAS_VOLTAGE_MASK 0x7 477 472 478 473 /* BOOST (0x76) */ 479 474 #define NAU8821_PRECHARGE_DIS (0x1 << 13) 480 475 #define NAU8821_GLOBAL_BIAS_EN (0x1 << 12) 476 + #define NAU8821_HP_BOOST_DISCHRG_SFT 11 477 + #define NAU8821_HP_BOOST_DISCHRG_EN (0x1 << NAU8821_HP_BOOST_DISCHRG_SFT) 481 478 #define NAU8821_HP_BOOST_DIS_SFT 9 482 479 #define NAU8821_HP_BOOST_DIS (0x1 << NAU8821_HP_BOOST_DIS_SFT) 483 480 #define NAU8821_HP_BOOST_G_DIS (0x1 << 8) 484 481 #define NAU8821_SHORT_SHUTDOWN_EN (0x1 << 6) 485 482 486 483 /* FEPGA (0x77) */ 484 + #define NAU8821_ACDC_CTRL_SFT 14 485 + #define NAU8821_ACDC_CTRL_MASK (0x3 << NAU8821_ACDC_CTRL_SFT) 486 + #define NAU8821_ACDC_VREF_MICP (0x1 << NAU8821_ACDC_CTRL_SFT) 487 + #define NAU8821_ACDC_VREF_MICN (0x2 << NAU8821_ACDC_CTRL_SFT) 487 488 #define NAU8821_FEPGA_MODEL_SFT 4 488 489 #define NAU8821_FEPGA_MODEL_MASK (0xf << NAU8821_FEPGA_MODEL_SFT) 490 + #define NAU8821_FEPGA_MODEL_AAF (0x1 << NAU8821_FEPGA_MODEL_SFT) 491 + #define NAU8821_FEPGA_MODEL_DIS (0x2 << NAU8821_FEPGA_MODEL_SFT) 492 + #define NAU8821_FEPGA_MODEL_IMP12K (0x8 << NAU8821_FEPGA_MODEL_SFT) 489 493 #define NAU8821_FEPGA_MODER_SFT 0 490 494 #define NAU8821_FEPGA_MODER_MASK 0xf 495 + #define NAU8821_FEPGA_MODER_AAF 0x1 496 + #define NAU8821_FEPGA_MODER_DIS 0x2 497 + #define NAU8821_FEPGA_MODER_IMP12K 0x8 498 + 491 499 492 500 /* PGA_GAIN (0x7e) */ 493 501 #define NAU8821_PGA_GAIN_L_SFT 8 ··· 567 543 bool jkdet_enable; 568 544 bool jkdet_pull_enable; 569 545 bool jkdet_pull_up; 546 + bool left_input_single_end; 570 547 int jkdet_polarity; 571 548 int jack_insert_debounce; 572 549 int jack_eject_debounce;

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