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dt-bindings: interrupt-controller: Add RISC-V incoming MSI controller
Add DT bindings document for the RISC-V incoming MSI controller (IMSIC)
defined by the RISC-V advanced interrupt architecture (AIA) specification.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Björn Töpel <bjorn@rivosinc.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Björn Töpel <bjorn@rivosinc.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240307140307.646078-2-apatel@ventanamicro.com
authored by
Anup Patel
and committed by
Thomas Gleixner
0151a8db
46efb305
+172
+172
Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml
+172
Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interrupt-controller/riscv,imsics.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: RISC-V Incoming MSI Controller (IMSIC)
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maintainers:
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- Anup Patel <anup@brainfault.org>
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description: |
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The RISC-V advanced interrupt architecture (AIA) defines a per-CPU incoming
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MSI controller (IMSIC) for handling MSIs in a RISC-V platform. The RISC-V
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AIA specification can be found at https://github.com/riscv/riscv-aia.
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The IMSIC is a per-CPU (or per-HART) device with separate interrupt file
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for each privilege level (machine or supervisor). The configuration of
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a IMSIC interrupt file is done using AIA CSRs and it also has a 4KB MMIO
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space to receive MSIs from devices. Each IMSIC interrupt file supports a
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fixed number of interrupt identities (to distinguish MSIs from devices)
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which is same for given privilege level across CPUs (or HARTs).
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The device tree of a RISC-V platform will have one IMSIC device tree node
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for each privilege level (machine or supervisor) which collectively describe
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IMSIC interrupt files at that privilege level across CPUs (or HARTs).
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The arrangement of IMSIC interrupt files in MMIO space of a RISC-V platform
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follows a particular scheme defined by the RISC-V AIA specification. A IMSIC
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group is a set of IMSIC interrupt files co-located in MMIO space and we can
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have multiple IMSIC groups (i.e. clusters, sockets, chiplets, etc) in a
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RISC-V platform. The MSI target address of a IMSIC interrupt file at given
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privilege level (machine or supervisor) encodes group index, HART index,
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and guest index (shown below).
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XLEN-1 > (HART Index MSB) 12 0
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| | | |
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-------------------------------------------------------------
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|xxxxxx|Group Index|xxxxxxxxxxx|HART Index|Guest Index| 0 |
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-------------------------------------------------------------
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allOf:
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- $ref: /schemas/interrupt-controller.yaml#
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- $ref: /schemas/interrupt-controller/msi-controller.yaml#
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properties:
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compatible:
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items:
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- enum:
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- qemu,imsics
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- const: riscv,imsics
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reg:
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minItems: 1
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maxItems: 16384
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description:
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Base address of each IMSIC group.
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interrupt-controller: true
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"#interrupt-cells":
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const: 0
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msi-controller: true
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"#msi-cells":
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const: 0
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interrupts-extended:
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minItems: 1
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maxItems: 16384
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description:
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This property represents the set of CPUs (or HARTs) for which given
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device tree node describes the IMSIC interrupt files. Each node pointed
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to should be a riscv,cpu-intc node, which has a CPU node (i.e. RISC-V
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HART) as parent.
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riscv,num-ids:
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 63
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maximum: 2047
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description:
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Number of interrupt identities supported by IMSIC interrupt file.
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riscv,num-guest-ids:
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 63
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maximum: 2047
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description:
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Number of interrupt identities are supported by IMSIC guest interrupt
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file. When not specified it is assumed to be same as specified by the
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riscv,num-ids property.
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riscv,guest-index-bits:
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minimum: 0
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maximum: 7
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default: 0
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description:
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Number of guest index bits in the MSI target address.
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riscv,hart-index-bits:
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minimum: 0
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maximum: 15
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description:
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Number of HART index bits in the MSI target address. When not
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specified it is calculated based on the interrupts-extended property.
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riscv,group-index-bits:
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minimum: 0
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maximum: 7
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default: 0
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description:
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Number of group index bits in the MSI target address.
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riscv,group-index-shift:
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 55
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default: 24
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description:
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The least significant bit position of the group index bits in the
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MSI target address.
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required:
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- compatible
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- reg
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- interrupt-controller
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- msi-controller
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- "#msi-cells"
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- interrupts-extended
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- riscv,num-ids
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unevaluatedProperties: false
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examples:
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- |
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// Example 1 (Machine-level IMSIC files with just one group):
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interrupt-controller@24000000 {
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compatible = "qemu,imsics", "riscv,imsics";
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interrupts-extended = <&cpu1_intc 11>,
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<&cpu2_intc 11>,
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<&cpu3_intc 11>,
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<&cpu4_intc 11>;
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reg = <0x28000000 0x4000>;
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interrupt-controller;
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#interrupt-cells = <0>;
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msi-controller;
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#msi-cells = <0>;
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riscv,num-ids = <127>;
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};
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- |
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// Example 2 (Supervisor-level IMSIC files with two groups):
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interrupt-controller@28000000 {
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compatible = "qemu,imsics", "riscv,imsics";
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interrupts-extended = <&cpu1_intc 9>,
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<&cpu2_intc 9>,
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<&cpu3_intc 9>,
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<&cpu4_intc 9>;
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reg = <0x28000000 0x2000>, /* Group0 IMSICs */
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<0x29000000 0x2000>; /* Group1 IMSICs */
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interrupt-controller;
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#interrupt-cells = <0>;
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msi-controller;
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#msi-cells = <0>;
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riscv,num-ids = <127>;
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riscv,group-index-bits = <1>;
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riscv,group-index-shift = <24>;
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};
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...