Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/msm: Remove dpu_encoder_phys_ops->hw_reset()
We call out of the virt encoder into phys only to call back into the
virt for hw reset. So remove the indirection and just call the virt
function directly.
Reviewed-by: Jeykumar Sankaran <jsanka@codeaurora.org>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
+2
-18
+2
-4
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+2
-4
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
···
1507
1507
return rc;
1508
1508
}
1509
1509
1510
-
void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc)
1510
+
static void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc)
1511
1511
{
1512
1512
struct dpu_encoder_virt *dpu_enc;
1513
1513
struct dpu_hw_ctl *ctl;
···
1803
1803
if (needs_hw_reset) {
1804
1804
trace_dpu_enc_prepare_kickoff_reset(DRMID(drm_enc));
1805
1805
for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1806
-
phys = dpu_enc->phys_encs[i];
1807
-
if (phys && phys->ops.hw_reset)
1808
-
phys->ops.hw_reset(phys);
1806
+
dpu_encoder_helper_hw_reset(dpu_enc->phys_encs[i]);
1809
1807
}
1810
1808
}
1811
1809
}
-12
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
-12
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
···
114
114
* @handle_post_kickoff: Do any work necessary post-kickoff work
115
115
* @trigger_start: Process start event on physical encoder
116
116
* @needs_single_flush: Whether encoder slaves need to be flushed
117
-
* @hw_reset: Issue HW recovery such as CTL reset and clear
118
-
* DPU_ENC_ERR_NEEDS_HW_RESET state
119
117
* @irq_control: Handler to enable/disable all the encoder IRQs
120
118
* @prepare_idle_pc: phys encoder can update the vsync_enable status
121
119
* on idle power collapse prepare
···
149
151
void (*handle_post_kickoff)(struct dpu_encoder_phys *phys_enc);
150
152
void (*trigger_start)(struct dpu_encoder_phys *phys_enc);
151
153
bool (*needs_single_flush)(struct dpu_encoder_phys *phys_enc);
152
-
void (*hw_reset)(struct dpu_encoder_phys *phys_enc);
153
154
void (*irq_control)(struct dpu_encoder_phys *phys, bool enable);
154
155
void (*prepare_idle_pc)(struct dpu_encoder_phys *phys_enc);
155
156
void (*restore)(struct dpu_encoder_phys *phys);
···
338
341
* @phys_enc: Pointer to physical encoder structure
339
342
*/
340
343
void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc);
341
-
342
-
/**
343
-
* dpu_encoder_helper_hw_reset - issue ctl hw reset
344
-
* This helper function may be optionally specified by physical
345
-
* encoders if they require ctl hw reset. If state is currently
346
-
* DPU_ENC_ERR_NEEDS_HW_RESET, it is set back to DPU_ENC_ENABLED.
347
-
* @phys_enc: Pointer to physical encoder structure
348
-
*/
349
-
void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc);
350
344
351
345
static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode(
352
346
struct dpu_encoder_phys *phys_enc)
-1
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
-1
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
···
776
776
ops->wait_for_vblank = dpu_encoder_phys_cmd_wait_for_vblank;
777
777
ops->trigger_start = dpu_encoder_phys_cmd_trigger_start;
778
778
ops->needs_single_flush = dpu_encoder_phys_cmd_needs_single_flush;
779
-
ops->hw_reset = dpu_encoder_helper_hw_reset;
780
779
ops->irq_control = dpu_encoder_phys_cmd_irq_control;
781
780
ops->restore = dpu_encoder_phys_cmd_enable_helper;
782
781
ops->prepare_idle_pc = dpu_encoder_phys_cmd_prepare_idle_pc;
-1
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
-1
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
···
766
766
ops->prepare_for_kickoff = dpu_encoder_phys_vid_prepare_for_kickoff;
767
767
ops->handle_post_kickoff = dpu_encoder_phys_vid_handle_post_kickoff;
768
768
ops->needs_single_flush = dpu_encoder_phys_vid_needs_single_flush;
769
-
ops->hw_reset = dpu_encoder_helper_hw_reset;
770
769
ops->get_line_count = dpu_encoder_phys_vid_get_line_count;
771
770
}
772
771