Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
perf vendor events: Update sandybridge metrics add event counter information
Add counter information necessary for optimizing event grouping the
perf tool.
The most recent RFC patch set using this information:
https://lore.kernel.org/lkml/20240412210756.309828-1-weilin.wang@intel.com/
The information was added in:
https://github.com/intel/perfmon/commit/475892a9690cb048949e593fe39cee65cd4765e1
and later patches.
The TMA 4.8 information was updated in:
https://github.com/intel/perfmon/commit/59194d4d90ca50a3fcb2de0d82b9f6fc0c9a5736
Co-authored-by: Weilin Wang <weilin.wang@intel.com>
Co-authored-by: Caleb Biggers <caleb.biggers@intel.com>
Signed-off-by: Ian Rogers <irogers@google.com>
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Namhyung Kim <namhyung@kernel.org>
Link: https://lore.kernel.org/r/20240620181752.3945845-28-irogers@google.com
authored by
Ian Rogers
Weilin Wang
Caleb Biggers
and committed by
Namhyung Kim
01cb5e3d
bf0dd1f4
+481
-12
+173
tools/perf/pmu-events/arch/x86/sandybridge/cache.json
+173
tools/perf/pmu-events/arch/x86/sandybridge/cache.json
···
1
1
[
2
2
{
3
3
"BriefDescription": "Allocated L1D data cache lines in M state.",
4
+
"Counter": "0,1,2,3",
4
5
"EventCode": "0x51",
5
6
"EventName": "L1D.ALLOCATED_IN_M",
6
7
"SampleAfterValue": "2000003",
···
9
8
},
10
9
{
11
10
"BriefDescription": "Cache lines in M state evicted out of L1D due to Snoop HitM or dirty line replacement.",
11
+
"Counter": "0,1,2,3",
12
12
"EventCode": "0x51",
13
13
"EventName": "L1D.ALL_M_REPLACEMENT",
14
14
"SampleAfterValue": "2000003",
···
17
15
},
18
16
{
19
17
"BriefDescription": "L1D data cache lines in M state evicted due to replacement.",
18
+
"Counter": "0,1,2,3",
20
19
"EventCode": "0x51",
21
20
"EventName": "L1D.EVICTION",
22
21
"SampleAfterValue": "2000003",
···
25
22
},
26
23
{
27
24
"BriefDescription": "L1D data line replacements.",
25
+
"Counter": "0,1,2,3",
28
26
"EventCode": "0x51",
29
27
"EventName": "L1D.REPLACEMENT",
30
28
"PublicDescription": "This event counts L1D data line replacements. Replacements occur when a new line is brought into the cache, causing eviction of a line loaded earlier.",
···
34
30
},
35
31
{
36
32
"BriefDescription": "Cycles when dispatched loads are cancelled due to L1D bank conflicts with other load ports.",
33
+
"Counter": "0,1,2,3",
37
34
"CounterMask": "1",
38
35
"EventCode": "0xBF",
39
36
"EventName": "L1D_BLOCKS.BANK_CONFLICT_CYCLES",
···
43
38
},
44
39
{
45
40
"BriefDescription": "Cycles a demand request was blocked due to Fill Buffers unavailability.",
41
+
"Counter": "0,1,2,3",
46
42
"CounterMask": "1",
47
43
"EventCode": "0x48",
48
44
"EventName": "L1D_PEND_MISS.FB_FULL",
···
52
46
},
53
47
{
54
48
"BriefDescription": "L1D miss outstanding duration in cycles.",
49
+
"Counter": "2",
55
50
"EventCode": "0x48",
56
51
"EventName": "L1D_PEND_MISS.PENDING",
57
52
"SampleAfterValue": "2000003",
···
60
53
},
61
54
{
62
55
"BriefDescription": "Cycles with L1D load Misses outstanding.",
56
+
"Counter": "2",
63
57
"CounterMask": "1",
64
58
"EventCode": "0x48",
65
59
"EventName": "L1D_PEND_MISS.PENDING_CYCLES",
···
70
62
{
71
63
"AnyThread": "1",
72
64
"BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.",
65
+
"Counter": "2",
73
66
"CounterMask": "1",
74
67
"EventCode": "0x48",
75
68
"EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
···
79
70
},
80
71
{
81
72
"BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.",
73
+
"Counter": "0,1,2,3",
82
74
"EventCode": "0x28",
83
75
"EventName": "L2_L1D_WB_RQSTS.ALL",
84
76
"SampleAfterValue": "200003",
···
87
77
},
88
78
{
89
79
"BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.",
80
+
"Counter": "0,1,2,3",
90
81
"EventCode": "0x28",
91
82
"EventName": "L2_L1D_WB_RQSTS.HIT_E",
92
83
"SampleAfterValue": "200003",
···
95
84
},
96
85
{
97
86
"BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state.",
87
+
"Counter": "0,1,2,3",
98
88
"EventCode": "0x28",
99
89
"EventName": "L2_L1D_WB_RQSTS.HIT_M",
100
90
"SampleAfterValue": "200003",
···
103
91
},
104
92
{
105
93
"BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in S state.",
94
+
"Counter": "0,1,2,3",
106
95
"EventCode": "0x28",
107
96
"EventName": "L2_L1D_WB_RQSTS.HIT_S",
108
97
"SampleAfterValue": "200003",
···
111
98
},
112
99
{
113
100
"BriefDescription": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.).",
101
+
"Counter": "0,1,2,3",
114
102
"EventCode": "0x28",
115
103
"EventName": "L2_L1D_WB_RQSTS.MISS",
116
104
"SampleAfterValue": "200003",
···
119
105
},
120
106
{
121
107
"BriefDescription": "L2 cache lines filling L2.",
108
+
"Counter": "0,1,2,3",
122
109
"EventCode": "0xF1",
123
110
"EventName": "L2_LINES_IN.ALL",
124
111
"PublicDescription": "This event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2 cache when there was an L2 miss.",
···
128
113
},
129
114
{
130
115
"BriefDescription": "L2 cache lines in E state filling L2.",
116
+
"Counter": "0,1,2,3",
131
117
"EventCode": "0xF1",
132
118
"EventName": "L2_LINES_IN.E",
133
119
"SampleAfterValue": "100003",
···
136
120
},
137
121
{
138
122
"BriefDescription": "L2 cache lines in I state filling L2.",
123
+
"Counter": "0,1,2,3",
139
124
"EventCode": "0xF1",
140
125
"EventName": "L2_LINES_IN.I",
141
126
"SampleAfterValue": "100003",
···
144
127
},
145
128
{
146
129
"BriefDescription": "L2 cache lines in S state filling L2.",
130
+
"Counter": "0,1,2,3",
147
131
"EventCode": "0xF1",
148
132
"EventName": "L2_LINES_IN.S",
149
133
"SampleAfterValue": "100003",
···
152
134
},
153
135
{
154
136
"BriefDescription": "Clean L2 cache lines evicted by demand.",
137
+
"Counter": "0,1,2,3",
155
138
"EventCode": "0xF2",
156
139
"EventName": "L2_LINES_OUT.DEMAND_CLEAN",
157
140
"SampleAfterValue": "100003",
···
160
141
},
161
142
{
162
143
"BriefDescription": "Dirty L2 cache lines evicted by demand.",
144
+
"Counter": "0,1,2,3",
163
145
"EventCode": "0xF2",
164
146
"EventName": "L2_LINES_OUT.DEMAND_DIRTY",
165
147
"SampleAfterValue": "100003",
···
168
148
},
169
149
{
170
150
"BriefDescription": "Dirty L2 cache lines filling the L2.",
151
+
"Counter": "0,1,2,3",
171
152
"EventCode": "0xF2",
172
153
"EventName": "L2_LINES_OUT.DIRTY_ALL",
173
154
"SampleAfterValue": "100003",
···
176
155
},
177
156
{
178
157
"BriefDescription": "Clean L2 cache lines evicted by L2 prefetch.",
158
+
"Counter": "0,1,2,3",
179
159
"EventCode": "0xF2",
180
160
"EventName": "L2_LINES_OUT.PF_CLEAN",
181
161
"SampleAfterValue": "100003",
···
184
162
},
185
163
{
186
164
"BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch.",
165
+
"Counter": "0,1,2,3",
187
166
"EventCode": "0xF2",
188
167
"EventName": "L2_LINES_OUT.PF_DIRTY",
189
168
"SampleAfterValue": "100003",
···
192
169
},
193
170
{
194
171
"BriefDescription": "L2 code requests.",
172
+
"Counter": "0,1,2,3",
195
173
"EventCode": "0x24",
196
174
"EventName": "L2_RQSTS.ALL_CODE_RD",
197
175
"SampleAfterValue": "200003",
···
200
176
},
201
177
{
202
178
"BriefDescription": "Demand Data Read requests.",
179
+
"Counter": "0,1,2,3",
203
180
"EventCode": "0x24",
204
181
"EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
205
182
"SampleAfterValue": "200003",
···
208
183
},
209
184
{
210
185
"BriefDescription": "Requests from L2 hardware prefetchers.",
186
+
"Counter": "0,1,2,3",
211
187
"EventCode": "0x24",
212
188
"EventName": "L2_RQSTS.ALL_PF",
213
189
"SampleAfterValue": "200003",
···
216
190
},
217
191
{
218
192
"BriefDescription": "RFO requests to L2 cache.",
193
+
"Counter": "0,1,2,3",
219
194
"EventCode": "0x24",
220
195
"EventName": "L2_RQSTS.ALL_RFO",
221
196
"SampleAfterValue": "200003",
···
224
197
},
225
198
{
226
199
"BriefDescription": "L2 cache hits when fetching instructions, code reads.",
200
+
"Counter": "0,1,2,3",
227
201
"EventCode": "0x24",
228
202
"EventName": "L2_RQSTS.CODE_RD_HIT",
229
203
"SampleAfterValue": "200003",
···
232
204
},
233
205
{
234
206
"BriefDescription": "L2 cache misses when fetching instructions.",
207
+
"Counter": "0,1,2,3",
235
208
"EventCode": "0x24",
236
209
"EventName": "L2_RQSTS.CODE_RD_MISS",
237
210
"SampleAfterValue": "200003",
···
240
211
},
241
212
{
242
213
"BriefDescription": "Demand Data Read requests that hit L2 cache.",
214
+
"Counter": "0,1,2,3",
243
215
"EventCode": "0x24",
244
216
"EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
245
217
"SampleAfterValue": "200003",
···
248
218
},
249
219
{
250
220
"BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache.",
221
+
"Counter": "0,1,2,3",
251
222
"EventCode": "0x24",
252
223
"EventName": "L2_RQSTS.PF_HIT",
253
224
"SampleAfterValue": "200003",
···
256
225
},
257
226
{
258
227
"BriefDescription": "Requests from the L2 hardware prefetchers that miss L2 cache.",
228
+
"Counter": "0,1,2,3",
259
229
"EventCode": "0x24",
260
230
"EventName": "L2_RQSTS.PF_MISS",
261
231
"SampleAfterValue": "200003",
···
264
232
},
265
233
{
266
234
"BriefDescription": "RFO requests that hit L2 cache.",
235
+
"Counter": "0,1,2,3",
267
236
"EventCode": "0x24",
268
237
"EventName": "L2_RQSTS.RFO_HIT",
269
238
"SampleAfterValue": "200003",
···
272
239
},
273
240
{
274
241
"BriefDescription": "RFO requests that miss L2 cache.",
242
+
"Counter": "0,1,2,3",
275
243
"EventCode": "0x24",
276
244
"EventName": "L2_RQSTS.RFO_MISS",
277
245
"SampleAfterValue": "200003",
···
280
246
},
281
247
{
282
248
"BriefDescription": "RFOs that access cache lines in any state.",
249
+
"Counter": "0,1,2,3",
283
250
"EventCode": "0x27",
284
251
"EventName": "L2_STORE_LOCK_RQSTS.ALL",
285
252
"SampleAfterValue": "200003",
···
288
253
},
289
254
{
290
255
"BriefDescription": "RFOs that hit cache lines in E state.",
256
+
"Counter": "0,1,2,3",
291
257
"EventCode": "0x27",
292
258
"EventName": "L2_STORE_LOCK_RQSTS.HIT_E",
293
259
"SampleAfterValue": "200003",
···
296
260
},
297
261
{
298
262
"BriefDescription": "RFOs that hit cache lines in M state.",
263
+
"Counter": "0,1,2,3",
299
264
"EventCode": "0x27",
300
265
"EventName": "L2_STORE_LOCK_RQSTS.HIT_M",
301
266
"SampleAfterValue": "200003",
···
304
267
},
305
268
{
306
269
"BriefDescription": "RFOs that miss cache lines.",
270
+
"Counter": "0,1,2,3",
307
271
"EventCode": "0x27",
308
272
"EventName": "L2_STORE_LOCK_RQSTS.MISS",
309
273
"SampleAfterValue": "200003",
···
312
274
},
313
275
{
314
276
"BriefDescription": "L2 or LLC HW prefetches that access L2 cache.",
277
+
"Counter": "0,1,2,3",
315
278
"EventCode": "0xF0",
316
279
"EventName": "L2_TRANS.ALL_PF",
317
280
"SampleAfterValue": "200003",
···
320
281
},
321
282
{
322
283
"BriefDescription": "Transactions accessing L2 pipe.",
284
+
"Counter": "0,1,2,3",
323
285
"EventCode": "0xF0",
324
286
"EventName": "L2_TRANS.ALL_REQUESTS",
325
287
"SampleAfterValue": "200003",
···
328
288
},
329
289
{
330
290
"BriefDescription": "L2 cache accesses when fetching instructions.",
291
+
"Counter": "0,1,2,3",
331
292
"EventCode": "0xF0",
332
293
"EventName": "L2_TRANS.CODE_RD",
333
294
"SampleAfterValue": "200003",
···
336
295
},
337
296
{
338
297
"BriefDescription": "Demand Data Read requests that access L2 cache.",
298
+
"Counter": "0,1,2,3",
339
299
"EventCode": "0xF0",
340
300
"EventName": "L2_TRANS.DEMAND_DATA_RD",
341
301
"SampleAfterValue": "200003",
···
344
302
},
345
303
{
346
304
"BriefDescription": "L1D writebacks that access L2 cache.",
305
+
"Counter": "0,1,2,3",
347
306
"EventCode": "0xF0",
348
307
"EventName": "L2_TRANS.L1D_WB",
349
308
"SampleAfterValue": "200003",
···
352
309
},
353
310
{
354
311
"BriefDescription": "L2 fill requests that access L2 cache.",
312
+
"Counter": "0,1,2,3",
355
313
"EventCode": "0xF0",
356
314
"EventName": "L2_TRANS.L2_FILL",
357
315
"SampleAfterValue": "200003",
···
360
316
},
361
317
{
362
318
"BriefDescription": "L2 writebacks that access L2 cache.",
319
+
"Counter": "0,1,2,3",
363
320
"EventCode": "0xF0",
364
321
"EventName": "L2_TRANS.L2_WB",
365
322
"SampleAfterValue": "200003",
···
368
323
},
369
324
{
370
325
"BriefDescription": "RFO requests that access L2 cache.",
326
+
"Counter": "0,1,2,3",
371
327
"EventCode": "0xF0",
372
328
"EventName": "L2_TRANS.RFO",
373
329
"SampleAfterValue": "200003",
···
376
330
},
377
331
{
378
332
"BriefDescription": "Cycles when L1D is locked.",
333
+
"Counter": "0,1,2,3",
379
334
"EventCode": "0x63",
380
335
"EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",
381
336
"SampleAfterValue": "2000003",
···
384
337
},
385
338
{
386
339
"BriefDescription": "Core-originated cacheable demand requests missed LLC.",
340
+
"Counter": "0,1,2,3",
387
341
"EventCode": "0x2E",
388
342
"EventName": "LONGEST_LAT_CACHE.MISS",
389
343
"SampleAfterValue": "100003",
···
392
344
},
393
345
{
394
346
"BriefDescription": "Core-originated cacheable demand requests that refer to LLC.",
347
+
"Counter": "0,1,2,3",
395
348
"EventCode": "0x2E",
396
349
"EventName": "LONGEST_LAT_CACHE.REFERENCE",
397
350
"SampleAfterValue": "100003",
···
400
351
},
401
352
{
402
353
"BriefDescription": "Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache. (Precise Event - PEBS).",
354
+
"Counter": "0,1,2,3",
403
355
"EventCode": "0xD2",
404
356
"EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT",
405
357
"PEBS": "1",
···
410
360
},
411
361
{
412
362
"BriefDescription": "Retired load uops which data sources were HitM responses from shared LLC. (Precise Event - PEBS).",
363
+
"Counter": "0,1,2,3",
413
364
"EventCode": "0xD2",
414
365
"EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM",
415
366
"PEBS": "1",
···
420
369
},
421
370
{
422
371
"BriefDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache. (Precise Event - PEBS).",
372
+
"Counter": "0,1,2,3",
423
373
"EventCode": "0xD2",
424
374
"EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS",
425
375
"PEBS": "1",
···
429
377
},
430
378
{
431
379
"BriefDescription": "Retired load uops which data sources were hits in LLC without snoops required. (Precise Event - PEBS).",
380
+
"Counter": "0,1,2,3",
432
381
"EventCode": "0xD2",
433
382
"EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE",
434
383
"PEBS": "1",
···
438
385
},
439
386
{
440
387
"BriefDescription": "Retired load uops with unknown information as data source in cache serviced the load. (Precise Event - PEBS).",
388
+
"Counter": "0,1,2,3",
441
389
"EventCode": "0xD4",
442
390
"EventName": "MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS",
443
391
"PEBS": "1",
···
448
394
},
449
395
{
450
396
"BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. (Precise Event - PEBS).",
397
+
"Counter": "0,1,2,3",
451
398
"EventCode": "0xD1",
452
399
"EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB",
453
400
"PEBS": "1",
···
457
402
},
458
403
{
459
404
"BriefDescription": "Retired load uops with L1 cache hits as data sources. (Precise Event - PEBS).",
405
+
"Counter": "0,1,2,3",
460
406
"EventCode": "0xD1",
461
407
"EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",
462
408
"PEBS": "1",
···
466
410
},
467
411
{
468
412
"BriefDescription": "Retired load uops with L2 cache hits as data sources. (Precise Event - PEBS).",
413
+
"Counter": "0,1,2,3",
469
414
"EventCode": "0xD1",
470
415
"EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",
471
416
"PEBS": "1",
···
475
418
},
476
419
{
477
420
"BriefDescription": "Retired load uops which data sources were data hits in LLC without snoops required. (Precise Event - PEBS).",
421
+
"Counter": "0,1,2,3",
478
422
"EventCode": "0xD1",
479
423
"EventName": "MEM_LOAD_UOPS_RETIRED.LLC_HIT",
480
424
"PEBS": "1",
···
485
427
},
486
428
{
487
429
"BriefDescription": "All retired load uops. (Precise Event - PEBS).",
430
+
"Counter": "0,1,2,3",
488
431
"EventCode": "0xD0",
489
432
"EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
490
433
"PEBS": "1",
···
495
436
},
496
437
{
497
438
"BriefDescription": "All retired store uops. (Precise Event - PEBS).",
439
+
"Counter": "0,1,2,3",
498
440
"EventCode": "0xD0",
499
441
"EventName": "MEM_UOPS_RETIRED.ALL_STORES",
500
442
"PEBS": "1",
···
505
445
},
506
446
{
507
447
"BriefDescription": "Retired load uops with locked access. (Precise Event - PEBS).",
448
+
"Counter": "0,1,2,3",
508
449
"EventCode": "0xD0",
509
450
"EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",
510
451
"PEBS": "1",
···
514
453
},
515
454
{
516
455
"BriefDescription": "Retired load uops that split across a cacheline boundary. (Precise Event - PEBS).",
456
+
"Counter": "0,1,2,3",
517
457
"EventCode": "0xD0",
518
458
"EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
519
459
"PEBS": "1",
···
524
462
},
525
463
{
526
464
"BriefDescription": "Retired store uops that split across a cacheline boundary. (Precise Event - PEBS).",
465
+
"Counter": "0,1,2,3",
527
466
"EventCode": "0xD0",
528
467
"EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
529
468
"PEBS": "1",
···
534
471
},
535
472
{
536
473
"BriefDescription": "Retired load uops that miss the STLB. (Precise Event - PEBS).",
474
+
"Counter": "0,1,2,3",
537
475
"EventCode": "0xD0",
538
476
"EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS",
539
477
"PEBS": "1",
···
543
479
},
544
480
{
545
481
"BriefDescription": "Retired store uops that miss the STLB. (Precise Event - PEBS).",
482
+
"Counter": "0,1,2,3",
546
483
"EventCode": "0xD0",
547
484
"EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES",
548
485
"PEBS": "1",
···
552
487
},
553
488
{
554
489
"BriefDescription": "Demand and prefetch data reads.",
490
+
"Counter": "0,1,2,3",
555
491
"EventCode": "0xB0",
556
492
"EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
557
493
"SampleAfterValue": "100003",
···
560
494
},
561
495
{
562
496
"BriefDescription": "Cacheable and noncacheable code read requests.",
497
+
"Counter": "0,1,2,3",
563
498
"EventCode": "0xB0",
564
499
"EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
565
500
"SampleAfterValue": "100003",
···
568
501
},
569
502
{
570
503
"BriefDescription": "Demand Data Read requests sent to uncore.",
504
+
"Counter": "0,1,2,3",
571
505
"EventCode": "0xB0",
572
506
"EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
573
507
"SampleAfterValue": "100003",
···
576
508
},
577
509
{
578
510
"BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM.",
511
+
"Counter": "0,1,2,3",
579
512
"EventCode": "0xB0",
580
513
"EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
581
514
"SampleAfterValue": "100003",
···
584
515
},
585
516
{
586
517
"BriefDescription": "Cases when offcore requests buffer cannot take more entries for core.",
518
+
"Counter": "0,1,2,3",
587
519
"EventCode": "0xB2",
588
520
"EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",
589
521
"SampleAfterValue": "2000003",
···
592
522
},
593
523
{
594
524
"BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore.",
525
+
"Counter": "0,1,2,3",
595
526
"EventCode": "0x60",
596
527
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
597
528
"SampleAfterValue": "2000003",
···
600
529
},
601
530
{
602
531
"BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
532
+
"Counter": "0,1,2,3",
603
533
"CounterMask": "1",
604
534
"EventCode": "0x60",
605
535
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
···
609
537
},
610
538
{
611
539
"BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
540
+
"Counter": "0,1,2,3",
612
541
"CounterMask": "1",
613
542
"EventCode": "0x60",
614
543
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
···
618
545
},
619
546
{
620
547
"BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.",
548
+
"Counter": "0,1,2,3",
621
549
"CounterMask": "1",
622
550
"EventCode": "0x60",
623
551
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
···
627
553
},
628
554
{
629
555
"BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",
556
+
"Counter": "0,1,2,3",
630
557
"EventCode": "0x60",
631
558
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
632
559
"SampleAfterValue": "2000003",
···
635
560
},
636
561
{
637
562
"BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",
563
+
"Counter": "0,1,2,3",
638
564
"CounterMask": "6",
639
565
"EventCode": "0x60",
640
566
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_C6",
···
644
568
},
645
569
{
646
570
"BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore.",
571
+
"Counter": "0,1,2,3",
647
572
"EventCode": "0x60",
648
573
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
649
574
"SampleAfterValue": "2000003",
···
652
575
},
653
576
{
654
577
"BriefDescription": "Counts demand & prefetch code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
578
+
"Counter": "0,1,2,3",
655
579
"EventCode": "0xB7, 0xBB",
656
580
"EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.HITM_OTHER_CORE",
657
581
"MSRIndex": "0x1a6,0x1a7",
···
662
584
},
663
585
{
664
586
"BriefDescription": "Counts demand & prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
587
+
"Counter": "0,1,2,3",
665
588
"EventCode": "0xB7, 0xBB",
666
589
"EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED",
667
590
"MSRIndex": "0x1a6,0x1a7",
···
672
593
},
673
594
{
674
595
"BriefDescription": "Counts demand & prefetch code reads that hit in the LLC and the snoops sent to sibling cores return clean response.",
596
+
"Counter": "0,1,2,3",
675
597
"EventCode": "0xB7, 0xBB",
676
598
"EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.SNOOP_MISS",
677
599
"MSRIndex": "0x1a6,0x1a7",
···
682
602
},
683
603
{
684
604
"BriefDescription": "Counts all demand & prefetch data reads.",
605
+
"Counter": "0,1,2,3",
685
606
"EventCode": "0xB7, 0xBB",
686
607
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE",
687
608
"MSRIndex": "0x1a6,0x1a7",
···
692
611
},
693
612
{
694
613
"BriefDescription": "Counts all demand & prefetch data reads that hit in the LLC.",
614
+
"Counter": "0,1,2,3",
695
615
"EventCode": "0xB7, 0xBB",
696
616
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.ANY_RESPONSE",
697
617
"MSRIndex": "0x1a6,0x1a7",
···
702
620
},
703
621
{
704
622
"BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
623
+
"Counter": "0,1,2,3",
705
624
"EventCode": "0xB7, 0xBB",
706
625
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
707
626
"MSRIndex": "0x1a6,0x1a7",
···
712
629
},
713
630
{
714
631
"BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
632
+
"Counter": "0,1,2,3",
715
633
"EventCode": "0xB7, 0xBB",
716
634
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
717
635
"MSRIndex": "0x1a6,0x1a7",
···
722
638
},
723
639
{
724
640
"BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
641
+
"Counter": "0,1,2,3",
725
642
"EventCode": "0xB7, 0xBB",
726
643
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
727
644
"MSRIndex": "0x1a6,0x1a7",
···
732
647
},
733
648
{
734
649
"BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoops sent to sibling cores return clean response.",
650
+
"Counter": "0,1,2,3",
735
651
"EventCode": "0xB7, 0xBB",
736
652
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.SNOOP_MISS",
737
653
"MSRIndex": "0x1a6,0x1a7",
···
742
656
},
743
657
{
744
658
"BriefDescription": "Counts all prefetch code reads that hit in the LLC.",
659
+
"Counter": "0,1,2,3",
745
660
"EventCode": "0xB7, 0xBB",
746
661
"EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.ANY_RESPONSE",
747
662
"MSRIndex": "0x1a6,0x1a7",
···
752
665
},
753
666
{
754
667
"BriefDescription": "Counts prefetch code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
668
+
"Counter": "0,1,2,3",
755
669
"EventCode": "0xB7, 0xBB",
756
670
"EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.HITM_OTHER_CORE",
757
671
"MSRIndex": "0x1a6,0x1a7",
···
762
674
},
763
675
{
764
676
"BriefDescription": "Counts prefetch code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
677
+
"Counter": "0,1,2,3",
765
678
"EventCode": "0xB7, 0xBB",
766
679
"EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
767
680
"MSRIndex": "0x1a6,0x1a7",
···
772
683
},
773
684
{
774
685
"BriefDescription": "Counts prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
686
+
"Counter": "0,1,2,3",
775
687
"EventCode": "0xB7, 0xBB",
776
688
"EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED",
777
689
"MSRIndex": "0x1a6,0x1a7",
···
782
692
},
783
693
{
784
694
"BriefDescription": "Counts prefetch code reads that hit in the LLC and the snoops sent to sibling cores return clean response.",
695
+
"Counter": "0,1,2,3",
785
696
"EventCode": "0xB7, 0xBB",
786
697
"EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.SNOOP_MISS",
787
698
"MSRIndex": "0x1a6,0x1a7",
···
792
701
},
793
702
{
794
703
"BriefDescription": "Counts all prefetch data reads that hit in the LLC.",
704
+
"Counter": "0,1,2,3",
795
705
"EventCode": "0xB7, 0xBB",
796
706
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.ANY_RESPONSE",
797
707
"MSRIndex": "0x1a6,0x1a7",
···
802
710
},
803
711
{
804
712
"BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
713
+
"Counter": "0,1,2,3",
805
714
"EventCode": "0xB7, 0xBB",
806
715
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
807
716
"MSRIndex": "0x1a6,0x1a7",
···
812
719
},
813
720
{
814
721
"BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
722
+
"Counter": "0,1,2,3",
815
723
"EventCode": "0xB7, 0xBB",
816
724
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
817
725
"MSRIndex": "0x1a6,0x1a7",
···
822
728
},
823
729
{
824
730
"BriefDescription": "Counts prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
731
+
"Counter": "0,1,2,3",
825
732
"EventCode": "0xB7, 0xBB",
826
733
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
827
734
"MSRIndex": "0x1a6,0x1a7",
···
832
737
},
833
738
{
834
739
"BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoops sent to sibling cores return clean response.",
740
+
"Counter": "0,1,2,3",
835
741
"EventCode": "0xB7, 0xBB",
836
742
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.SNOOP_MISS",
837
743
"MSRIndex": "0x1a6,0x1a7",
···
842
746
},
843
747
{
844
748
"BriefDescription": "Counts all prefetch RFOs that hit in the LLC.",
749
+
"Counter": "0,1,2,3",
845
750
"EventCode": "0xB7, 0xBB",
846
751
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.ANY_RESPONSE",
847
752
"MSRIndex": "0x1a6,0x1a7",
···
852
755
},
853
756
{
854
757
"BriefDescription": "Counts prefetch RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
758
+
"Counter": "0,1,2,3",
855
759
"EventCode": "0xB7, 0xBB",
856
760
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.HITM_OTHER_CORE",
857
761
"MSRIndex": "0x1a6,0x1a7",
···
862
764
},
863
765
{
864
766
"BriefDescription": "Counts prefetch RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
767
+
"Counter": "0,1,2,3",
865
768
"EventCode": "0xB7, 0xBB",
866
769
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
867
770
"MSRIndex": "0x1a6,0x1a7",
···
872
773
},
873
774
{
874
775
"BriefDescription": "Counts prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
776
+
"Counter": "0,1,2,3",
875
777
"EventCode": "0xB7, 0xBB",
876
778
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.NO_SNOOP_NEEDED",
877
779
"MSRIndex": "0x1a6,0x1a7",
···
882
782
},
883
783
{
884
784
"BriefDescription": "Counts prefetch RFOs that hit in the LLC and the snoops sent to sibling cores return clean response.",
785
+
"Counter": "0,1,2,3",
885
786
"EventCode": "0xB7, 0xBB",
886
787
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.SNOOP_MISS",
887
788
"MSRIndex": "0x1a6,0x1a7",
···
892
791
},
893
792
{
894
793
"BriefDescription": "Counts all data/code/rfo references (demand & prefetch) .",
794
+
"Counter": "0,1,2,3",
895
795
"EventCode": "0xB7, 0xBB",
896
796
"EventName": "OFFCORE_RESPONSE.ALL_READS.ANY_RESPONSE",
897
797
"MSRIndex": "0x1a6,0x1a7",
···
902
800
},
903
801
{
904
802
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC.",
803
+
"Counter": "0,1,2,3",
905
804
"EventCode": "0xB7, 0xBB",
906
805
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.ANY_RESPONSE",
907
806
"MSRIndex": "0x1a6,0x1a7",
···
912
809
},
913
810
{
914
811
"BriefDescription": "Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
812
+
"Counter": "0,1,2,3",
915
813
"EventCode": "0xB7, 0xBB",
916
814
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE",
917
815
"MSRIndex": "0x1a6,0x1a7",
···
922
818
},
923
819
{
924
820
"BriefDescription": "Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
821
+
"Counter": "0,1,2,3",
925
822
"EventCode": "0xB7, 0xBB",
926
823
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
927
824
"MSRIndex": "0x1a6,0x1a7",
···
932
827
},
933
828
{
934
829
"BriefDescription": "Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
830
+
"Counter": "0,1,2,3",
935
831
"EventCode": "0xB7, 0xBB",
936
832
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.NO_SNOOP_NEEDED",
937
833
"MSRIndex": "0x1a6,0x1a7",
···
942
836
},
943
837
{
944
838
"BriefDescription": "Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops sent to sibling cores return clean response.",
839
+
"Counter": "0,1,2,3",
945
840
"EventCode": "0xB7, 0xBB",
946
841
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.SNOOP_MISS",
947
842
"MSRIndex": "0x1a6,0x1a7",
···
952
845
},
953
846
{
954
847
"BriefDescription": "Counts all demand & prefetch prefetch RFOs .",
848
+
"Counter": "0,1,2,3",
955
849
"EventCode": "0xB7, 0xBB",
956
850
"EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE",
957
851
"MSRIndex": "0x1a6,0x1a7",
···
962
854
},
963
855
{
964
856
"BriefDescription": "Counts all demand & prefetch RFOs that hit in the LLC.",
857
+
"Counter": "0,1,2,3",
965
858
"EventCode": "0xB7, 0xBB",
966
859
"EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.ANY_RESPONSE",
967
860
"MSRIndex": "0x1a6,0x1a7",
···
972
863
},
973
864
{
974
865
"BriefDescription": "Counts demand & prefetch RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
866
+
"Counter": "0,1,2,3",
975
867
"EventCode": "0xB7, 0xBB",
976
868
"EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HITM_OTHER_CORE",
977
869
"MSRIndex": "0x1a6,0x1a7",
···
982
872
},
983
873
{
984
874
"BriefDescription": "Counts demand & prefetch RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
875
+
"Counter": "0,1,2,3",
985
876
"EventCode": "0xB7, 0xBB",
986
877
"EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
987
878
"MSRIndex": "0x1a6,0x1a7",
···
992
881
},
993
882
{
994
883
"BriefDescription": "Counts demand & prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
884
+
"Counter": "0,1,2,3",
995
885
"EventCode": "0xB7, 0xBB",
996
886
"EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.NO_SNOOP_NEEDED",
997
887
"MSRIndex": "0x1a6,0x1a7",
···
1002
890
},
1003
891
{
1004
892
"BriefDescription": "Counts demand & prefetch RFOs that hit in the LLC and the snoops sent to sibling cores return clean response.",
893
+
"Counter": "0,1,2,3",
1005
894
"EventCode": "0xB7, 0xBB",
1006
895
"EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.SNOOP_MISS",
1007
896
"MSRIndex": "0x1a6,0x1a7",
···
1012
899
},
1013
900
{
1014
901
"BriefDescription": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE",
902
+
"Counter": "0,1,2,3",
1015
903
"EventCode": "0xB7, 0xBB",
1016
904
"EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE",
1017
905
"MSRIndex": "0x1a6,0x1a7",
···
1022
908
},
1023
909
{
1024
910
"BriefDescription": "REQUEST = DATA_INTO_CORE and RESPONSE = ANY_RESPONSE",
911
+
"Counter": "0,1,2,3",
1025
912
"EventCode": "0xB7, 0xBB",
1026
913
"EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_RESPONSE",
1027
914
"MSRIndex": "0x1a6,0x1a7",
···
1032
917
},
1033
918
{
1034
919
"BriefDescription": "Counts all demand code reads.",
920
+
"Counter": "0,1,2,3",
1035
921
"EventCode": "0xB7, 0xBB",
1036
922
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE",
1037
923
"MSRIndex": "0x1a6,0x1a7",
···
1042
926
},
1043
927
{
1044
928
"BriefDescription": "Counts all demand code reads that hit in the LLC.",
929
+
"Counter": "0,1,2,3",
1045
930
"EventCode": "0xB7, 0xBB",
1046
931
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE",
1047
932
"MSRIndex": "0x1a6,0x1a7",
···
1052
935
},
1053
936
{
1054
937
"BriefDescription": "Counts demand code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
938
+
"Counter": "0,1,2,3",
1055
939
"EventCode": "0xB7, 0xBB",
1056
940
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HITM_OTHER_CORE",
1057
941
"MSRIndex": "0x1a6,0x1a7",
···
1062
944
},
1063
945
{
1064
946
"BriefDescription": "Counts demand code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
947
+
"Counter": "0,1,2,3",
1065
948
"EventCode": "0xB7, 0xBB",
1066
949
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
1067
950
"MSRIndex": "0x1a6,0x1a7",
···
1072
953
},
1073
954
{
1074
955
"BriefDescription": "Counts demand code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
956
+
"Counter": "0,1,2,3",
1075
957
"EventCode": "0xB7, 0xBB",
1076
958
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED",
1077
959
"MSRIndex": "0x1a6,0x1a7",
···
1082
962
},
1083
963
{
1084
964
"BriefDescription": "Counts demand code reads that hit in the LLC and the snoops sent to sibling cores return clean response.",
965
+
"Counter": "0,1,2,3",
1085
966
"EventCode": "0xB7, 0xBB",
1086
967
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.SNOOP_MISS",
1087
968
"MSRIndex": "0x1a6,0x1a7",
···
1092
971
},
1093
972
{
1094
973
"BriefDescription": "Counts all demand data reads .",
974
+
"Counter": "0,1,2,3",
1095
975
"EventCode": "0xB7, 0xBB",
1096
976
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE",
1097
977
"MSRIndex": "0x1a6,0x1a7",
···
1102
980
},
1103
981
{
1104
982
"BriefDescription": "Counts all demand data reads that hit in the LLC.",
983
+
"Counter": "0,1,2,3",
1105
984
"EventCode": "0xB7, 0xBB",
1106
985
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE",
1107
986
"MSRIndex": "0x1a6,0x1a7",
···
1112
989
},
1113
990
{
1114
991
"BriefDescription": "Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
992
+
"Counter": "0,1,2,3",
1115
993
"EventCode": "0xB7, 0xBB",
1116
994
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
1117
995
"MSRIndex": "0x1a6,0x1a7",
···
1122
998
},
1123
999
{
1124
1000
"BriefDescription": "Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
1001
+
"Counter": "0,1,2,3",
1125
1002
"EventCode": "0xB7, 0xBB",
1126
1003
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
1127
1004
"MSRIndex": "0x1a6,0x1a7",
···
1132
1007
},
1133
1008
{
1134
1009
"BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
1010
+
"Counter": "0,1,2,3",
1135
1011
"EventCode": "0xB7, 0xBB",
1136
1012
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
1137
1013
"MSRIndex": "0x1a6,0x1a7",
···
1142
1016
},
1143
1017
{
1144
1018
"BriefDescription": "Counts demand data reads that hit in the LLC and the snoops sent to sibling cores return clean response.",
1019
+
"Counter": "0,1,2,3",
1145
1020
"EventCode": "0xB7, 0xBB",
1146
1021
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.SNOOP_MISS",
1147
1022
"MSRIndex": "0x1a6,0x1a7",
···
1152
1025
},
1153
1026
{
1154
1027
"BriefDescription": "Counts all demand rfo's .",
1028
+
"Counter": "0,1,2,3",
1155
1029
"EventCode": "0xB7, 0xBB",
1156
1030
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE",
1157
1031
"MSRIndex": "0x1a6,0x1a7",
···
1162
1034
},
1163
1035
{
1164
1036
"BriefDescription": "Counts all demand data writes (RFOs) that hit in the LLC.",
1037
+
"Counter": "0,1,2,3",
1165
1038
"EventCode": "0xB7, 0xBB",
1166
1039
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.ANY_RESPONSE",
1167
1040
"MSRIndex": "0x1a6,0x1a7",
···
1172
1043
},
1173
1044
{
1174
1045
"BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
1046
+
"Counter": "0,1,2,3",
1175
1047
"EventCode": "0xB7, 0xBB",
1176
1048
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE",
1177
1049
"MSRIndex": "0x1a6,0x1a7",
···
1182
1052
},
1183
1053
{
1184
1054
"BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
1055
+
"Counter": "0,1,2,3",
1185
1056
"EventCode": "0xB7, 0xBB",
1186
1057
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
1187
1058
"MSRIndex": "0x1a6,0x1a7",
···
1192
1061
},
1193
1062
{
1194
1063
"BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
1064
+
"Counter": "0,1,2,3",
1195
1065
"EventCode": "0xB7, 0xBB",
1196
1066
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.NO_SNOOP_NEEDED",
1197
1067
"MSRIndex": "0x1a6,0x1a7",
···
1202
1070
},
1203
1071
{
1204
1072
"BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and the snoops sent to sibling cores return clean response.",
1073
+
"Counter": "0,1,2,3",
1205
1074
"EventCode": "0xB7, 0xBB",
1206
1075
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.SNOOP_MISS",
1207
1076
"MSRIndex": "0x1a6,0x1a7",
···
1212
1079
},
1213
1080
{
1214
1081
"BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_M and SNOOP = HITM",
1082
+
"Counter": "0,1,2,3",
1215
1083
"EventCode": "0xB7, 0xBB",
1216
1084
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_M.HITM",
1217
1085
"MSRIndex": "0x1a6,0x1a7",
···
1222
1088
},
1223
1089
{
1224
1090
"BriefDescription": "Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses. It also includes L2 hints sent to LLC to keep a line from being evicted out of the core caches.",
1091
+
"Counter": "0,1,2,3",
1225
1092
"EventCode": "0xB7, 0xBB",
1226
1093
"EventName": "OFFCORE_RESPONSE.OTHER.ANY_RESPONSE",
1227
1094
"MSRIndex": "0x1a6,0x1a7",
···
1232
1097
},
1233
1098
{
1234
1099
"BriefDescription": "Counts L2 hints sent to LLC to keep a line from being evicted out of the core caches.",
1100
+
"Counter": "0,1,2,3",
1235
1101
"EventCode": "0xB7, 0xBB",
1236
1102
"EventName": "OFFCORE_RESPONSE.OTHER.LRU_HINTS",
1237
1103
"MSRIndex": "0x1a6,0x1a7",
···
1242
1106
},
1243
1107
{
1244
1108
"BriefDescription": "Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses.",
1109
+
"Counter": "0,1,2,3",
1245
1110
"EventCode": "0xB7, 0xBB",
1246
1111
"EventName": "OFFCORE_RESPONSE.OTHER.PORTIO_MMIO_UC",
1247
1112
"MSRIndex": "0x1a6,0x1a7",
···
1252
1115
},
1253
1116
{
1254
1117
"BriefDescription": "REQUEST = PF_RFO and RESPONSE = ANY_RESPONSE",
1118
+
"Counter": "0,1,2,3",
1255
1119
"EventCode": "0xB7, 0xBB",
1256
1120
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_RESPONSE",
1257
1121
"MSRIndex": "0x1a6,0x1a7",
···
1262
1124
},
1263
1125
{
1264
1126
"BriefDescription": "Counts all prefetch (that bring data to L2) code reads that hit in the LLC.",
1127
+
"Counter": "0,1,2,3",
1265
1128
"EventCode": "0xB7, 0xBB",
1266
1129
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE",
1267
1130
"MSRIndex": "0x1a6,0x1a7",
···
1272
1133
},
1273
1134
{
1274
1135
"BriefDescription": "Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
1136
+
"Counter": "0,1,2,3",
1275
1137
"EventCode": "0xB7, 0xBB",
1276
1138
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.HITM_OTHER_CORE",
1277
1139
"MSRIndex": "0x1a6,0x1a7",
···
1282
1142
},
1283
1143
{
1284
1144
"BriefDescription": "Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
1145
+
"Counter": "0,1,2,3",
1285
1146
"EventCode": "0xB7, 0xBB",
1286
1147
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
1287
1148
"MSRIndex": "0x1a6,0x1a7",
···
1292
1151
},
1293
1152
{
1294
1153
"BriefDescription": "Counts prefetch (that bring data to L2) code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
1154
+
"Counter": "0,1,2,3",
1295
1155
"EventCode": "0xB7, 0xBB",
1296
1156
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED",
1297
1157
"MSRIndex": "0x1a6,0x1a7",
···
1302
1160
},
1303
1161
{
1304
1162
"BriefDescription": "Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoops sent to sibling cores return clean response.",
1163
+
"Counter": "0,1,2,3",
1305
1164
"EventCode": "0xB7, 0xBB",
1306
1165
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.SNOOP_MISS",
1307
1166
"MSRIndex": "0x1a6,0x1a7",
···
1312
1169
},
1313
1170
{
1314
1171
"BriefDescription": "Counts all prefetch (that bring data to L2) data reads that hit in the LLC.",
1172
+
"Counter": "0,1,2,3",
1315
1173
"EventCode": "0xB7, 0xBB",
1316
1174
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE",
1317
1175
"MSRIndex": "0x1a6,0x1a7",
···
1322
1178
},
1323
1179
{
1324
1180
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
1181
+
"Counter": "0,1,2,3",
1325
1182
"EventCode": "0xB7, 0xBB",
1326
1183
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
1327
1184
"MSRIndex": "0x1a6,0x1a7",
···
1332
1187
},
1333
1188
{
1334
1189
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
1190
+
"Counter": "0,1,2,3",
1335
1191
"EventCode": "0xB7, 0xBB",
1336
1192
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
1337
1193
"MSRIndex": "0x1a6,0x1a7",
···
1342
1196
},
1343
1197
{
1344
1198
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
1199
+
"Counter": "0,1,2,3",
1345
1200
"EventCode": "0xB7, 0xBB",
1346
1201
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
1347
1202
"MSRIndex": "0x1a6,0x1a7",
···
1352
1205
},
1353
1206
{
1354
1207
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops sent to sibling cores return clean response.",
1208
+
"Counter": "0,1,2,3",
1355
1209
"EventCode": "0xB7, 0xBB",
1356
1210
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.SNOOP_MISS",
1357
1211
"MSRIndex": "0x1a6,0x1a7",
···
1362
1214
},
1363
1215
{
1364
1216
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the LLC.",
1217
+
"Counter": "0,1,2,3",
1365
1218
"EventCode": "0xB7, 0xBB",
1366
1219
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.ANY_RESPONSE",
1367
1220
"MSRIndex": "0x1a6,0x1a7",
···
1372
1223
},
1373
1224
{
1374
1225
"BriefDescription": "Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
1226
+
"Counter": "0,1,2,3",
1375
1227
"EventCode": "0xB7, 0xBB",
1376
1228
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.HITM_OTHER_CORE",
1377
1229
"MSRIndex": "0x1a6,0x1a7",
···
1382
1232
},
1383
1233
{
1384
1234
"BriefDescription": "Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
1235
+
"Counter": "0,1,2,3",
1385
1236
"EventCode": "0xB7, 0xBB",
1386
1237
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
1387
1238
"MSRIndex": "0x1a6,0x1a7",
···
1392
1241
},
1393
1242
{
1394
1243
"BriefDescription": "Counts prefetch (that bring data to L2) RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
1244
+
"Counter": "0,1,2,3",
1395
1245
"EventCode": "0xB7, 0xBB",
1396
1246
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.NO_SNOOP_NEEDED",
1397
1247
"MSRIndex": "0x1a6,0x1a7",
···
1402
1250
},
1403
1251
{
1404
1252
"BriefDescription": "Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoops sent to sibling cores return clean response.",
1253
+
"Counter": "0,1,2,3",
1405
1254
"EventCode": "0xB7, 0xBB",
1406
1255
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.SNOOP_MISS",
1407
1256
"MSRIndex": "0x1a6,0x1a7",
···
1412
1259
},
1413
1260
{
1414
1261
"BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the LLC.",
1262
+
"Counter": "0,1,2,3",
1415
1263
"EventCode": "0xB7, 0xBB",
1416
1264
"EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE",
1417
1265
"MSRIndex": "0x1a6,0x1a7",
···
1422
1268
},
1423
1269
{
1424
1270
"BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
1271
+
"Counter": "0,1,2,3",
1425
1272
"EventCode": "0xB7, 0xBB",
1426
1273
"EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.HITM_OTHER_CORE",
1427
1274
"MSRIndex": "0x1a6,0x1a7",
···
1432
1277
},
1433
1278
{
1434
1279
"BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
1280
+
"Counter": "0,1,2,3",
1435
1281
"EventCode": "0xB7, 0xBB",
1436
1282
"EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
1437
1283
"MSRIndex": "0x1a6,0x1a7",
···
1442
1286
},
1443
1287
{
1444
1288
"BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
1289
+
"Counter": "0,1,2,3",
1445
1290
"EventCode": "0xB7, 0xBB",
1446
1291
"EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED",
1447
1292
"MSRIndex": "0x1a6,0x1a7",
···
1452
1295
},
1453
1296
{
1454
1297
"BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoops sent to sibling cores return clean response.",
1298
+
"Counter": "0,1,2,3",
1455
1299
"EventCode": "0xB7, 0xBB",
1456
1300
"EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.SNOOP_MISS",
1457
1301
"MSRIndex": "0x1a6,0x1a7",
···
1462
1304
},
1463
1305
{
1464
1306
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the LLC.",
1307
+
"Counter": "0,1,2,3",
1465
1308
"EventCode": "0xB7, 0xBB",
1466
1309
"EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE",
1467
1310
"MSRIndex": "0x1a6,0x1a7",
···
1472
1313
},
1473
1314
{
1474
1315
"BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
1316
+
"Counter": "0,1,2,3",
1475
1317
"EventCode": "0xB7, 0xBB",
1476
1318
"EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
1477
1319
"MSRIndex": "0x1a6,0x1a7",
···
1482
1322
},
1483
1323
{
1484
1324
"BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
1325
+
"Counter": "0,1,2,3",
1485
1326
"EventCode": "0xB7, 0xBB",
1486
1327
"EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
1487
1328
"MSRIndex": "0x1a6,0x1a7",
···
1492
1331
},
1493
1332
{
1494
1333
"BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
1334
+
"Counter": "0,1,2,3",
1495
1335
"EventCode": "0xB7, 0xBB",
1496
1336
"EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
1497
1337
"MSRIndex": "0x1a6,0x1a7",
···
1502
1340
},
1503
1341
{
1504
1342
"BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response.",
1343
+
"Counter": "0,1,2,3",
1505
1344
"EventCode": "0xB7, 0xBB",
1506
1345
"EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.SNOOP_MISS",
1507
1346
"MSRIndex": "0x1a6,0x1a7",
···
1512
1349
},
1513
1350
{
1514
1351
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the LLC.",
1352
+
"Counter": "0,1,2,3",
1515
1353
"EventCode": "0xB7, 0xBB",
1516
1354
"EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.ANY_RESPONSE",
1517
1355
"MSRIndex": "0x1a6,0x1a7",
···
1522
1358
},
1523
1359
{
1524
1360
"BriefDescription": "Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
1361
+
"Counter": "0,1,2,3",
1525
1362
"EventCode": "0xB7, 0xBB",
1526
1363
"EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.HITM_OTHER_CORE",
1527
1364
"MSRIndex": "0x1a6,0x1a7",
···
1532
1367
},
1533
1368
{
1534
1369
"BriefDescription": "Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
1370
+
"Counter": "0,1,2,3",
1535
1371
"EventCode": "0xB7, 0xBB",
1536
1372
"EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
1537
1373
"MSRIndex": "0x1a6,0x1a7",
···
1542
1376
},
1543
1377
{
1544
1378
"BriefDescription": "Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
1379
+
"Counter": "0,1,2,3",
1545
1380
"EventCode": "0xB7, 0xBB",
1546
1381
"EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.NO_SNOOP_NEEDED",
1547
1382
"MSRIndex": "0x1a6,0x1a7",
···
1552
1385
},
1553
1386
{
1554
1387
"BriefDescription": "Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoops sent to sibling cores return clean response.",
1388
+
"Counter": "0,1,2,3",
1555
1389
"EventCode": "0xB7, 0xBB",
1556
1390
"EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.SNOOP_MISS",
1557
1391
"MSRIndex": "0x1a6,0x1a7",
···
1562
1394
},
1563
1395
{
1564
1396
"BriefDescription": "REQUEST = PF_LLC_DATA_RD and RESPONSE = ANY_RESPONSE",
1397
+
"Counter": "0,1,2,3",
1565
1398
"EventCode": "0xB7, 0xBB",
1566
1399
"EventName": "OFFCORE_RESPONSE.PF_L_DATA_RD.ANY_RESPONSE",
1567
1400
"MSRIndex": "0x1a6,0x1a7",
···
1572
1403
},
1573
1404
{
1574
1405
"BriefDescription": "REQUEST = PF_LLC_IFETCH and RESPONSE = ANY_RESPONSE",
1406
+
"Counter": "0,1,2,3",
1575
1407
"EventCode": "0xB7, 0xBB",
1576
1408
"EventName": "OFFCORE_RESPONSE.PF_L_IFETCH.ANY_RESPONSE",
1577
1409
"MSRIndex": "0x1a6,0x1a7",
···
1582
1412
},
1583
1413
{
1584
1414
"BriefDescription": "Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address.",
1415
+
"Counter": "0,1,2,3",
1585
1416
"EventCode": "0xB7, 0xBB",
1586
1417
"EventName": "OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE",
1587
1418
"MSRIndex": "0x1a6,0x1a7",
···
1592
1421
},
1593
1422
{
1594
1423
"BriefDescription": "Counts non-temporal stores.",
1424
+
"Counter": "0,1,2,3",
1595
1425
"EventCode": "0xB7, 0xBB",
1596
1426
"EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE",
1597
1427
"MSRIndex": "0x1a6,0x1a7",
···
1602
1430
},
1603
1431
{
1604
1432
"BriefDescription": "Split locks in SQ.",
1433
+
"Counter": "0,1,2,3",
1605
1434
"EventCode": "0xF4",
1606
1435
"EventName": "SQ_MISC.SPLIT_LOCK",
1607
1436
"SampleAfterValue": "100003",
+17
tools/perf/pmu-events/arch/x86/sandybridge/counter.json
+17
tools/perf/pmu-events/arch/x86/sandybridge/counter.json
+15
tools/perf/pmu-events/arch/x86/sandybridge/floating-point.json
+15
tools/perf/pmu-events/arch/x86/sandybridge/floating-point.json
···
1
1
[
2
2
{
3
3
"BriefDescription": "Cycles with any input/output SSE or FP assist.",
4
+
"Counter": "0,1,2,3",
4
5
"CounterMask": "1",
5
6
"EventCode": "0xCA",
6
7
"EventName": "FP_ASSIST.ANY",
···
10
9
},
11
10
{
12
11
"BriefDescription": "Number of SIMD FP assists due to input values.",
12
+
"Counter": "0,1,2,3",
13
13
"EventCode": "0xCA",
14
14
"EventName": "FP_ASSIST.SIMD_INPUT",
15
15
"SampleAfterValue": "100003",
···
18
16
},
19
17
{
20
18
"BriefDescription": "Number of SIMD FP assists due to Output values.",
19
+
"Counter": "0,1,2,3",
21
20
"EventCode": "0xCA",
22
21
"EventName": "FP_ASSIST.SIMD_OUTPUT",
23
22
"SampleAfterValue": "100003",
···
26
23
},
27
24
{
28
25
"BriefDescription": "Number of X87 assists due to input value.",
26
+
"Counter": "0,1,2,3",
29
27
"EventCode": "0xCA",
30
28
"EventName": "FP_ASSIST.X87_INPUT",
31
29
"SampleAfterValue": "100003",
···
34
30
},
35
31
{
36
32
"BriefDescription": "Number of X87 assists due to output value.",
33
+
"Counter": "0,1,2,3",
37
34
"EventCode": "0xCA",
38
35
"EventName": "FP_ASSIST.X87_OUTPUT",
39
36
"SampleAfterValue": "100003",
···
42
37
},
43
38
{
44
39
"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle.",
40
+
"Counter": "0,1,2,3",
45
41
"EventCode": "0x10",
46
42
"EventName": "FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE",
47
43
"SampleAfterValue": "2000003",
···
50
44
},
51
45
{
52
46
"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle.",
47
+
"Counter": "0,1,2,3",
53
48
"EventCode": "0x10",
54
49
"EventName": "FP_COMP_OPS_EXE.SSE_PACKED_SINGLE",
55
50
"SampleAfterValue": "2000003",
···
58
51
},
59
52
{
60
53
"BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle.",
54
+
"Counter": "0,1,2,3",
61
55
"EventCode": "0x10",
62
56
"EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE",
63
57
"SampleAfterValue": "2000003",
···
66
58
},
67
59
{
68
60
"BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle.",
61
+
"Counter": "0,1,2,3",
69
62
"EventCode": "0x10",
70
63
"EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE",
71
64
"SampleAfterValue": "2000003",
···
74
65
},
75
66
{
76
67
"BriefDescription": "Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULs and IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s.",
68
+
"Counter": "0,1,2,3",
77
69
"EventCode": "0x10",
78
70
"EventName": "FP_COMP_OPS_EXE.X87",
79
71
"SampleAfterValue": "2000003",
···
82
72
},
83
73
{
84
74
"BriefDescription": "Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations.",
75
+
"Counter": "0,1,2,3",
85
76
"EventCode": "0xC1",
86
77
"EventName": "OTHER_ASSISTS.AVX_STORE",
87
78
"SampleAfterValue": "100003",
···
90
79
},
91
80
{
92
81
"BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",
82
+
"Counter": "0,1,2,3",
93
83
"EventCode": "0xC1",
94
84
"EventName": "OTHER_ASSISTS.AVX_TO_SSE",
95
85
"SampleAfterValue": "100003",
···
98
86
},
99
87
{
100
88
"BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",
89
+
"Counter": "0,1,2,3",
101
90
"EventCode": "0xC1",
102
91
"EventName": "OTHER_ASSISTS.SSE_TO_AVX",
103
92
"SampleAfterValue": "100003",
···
106
93
},
107
94
{
108
95
"BriefDescription": "Number of AVX-256 Computational FP double precision uops issued this cycle.",
96
+
"Counter": "0,1,2,3",
109
97
"EventCode": "0x11",
110
98
"EventName": "SIMD_FP_256.PACKED_DOUBLE",
111
99
"SampleAfterValue": "2000003",
···
114
100
},
115
101
{
116
102
"BriefDescription": "Number of GSSE-256 Computational FP single precision uops issued this cycle.",
103
+
"Counter": "0,1,2,3",
117
104
"EventCode": "0x11",
118
105
"EventName": "SIMD_FP_256.PACKED_SINGLE",
119
106
"SampleAfterValue": "2000003",
+32
tools/perf/pmu-events/arch/x86/sandybridge/frontend.json
+32
tools/perf/pmu-events/arch/x86/sandybridge/frontend.json
···
1
1
[
2
2
{
3
3
"BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
4
+
"Counter": "0,1,2,3",
4
5
"EventCode": "0xE6",
5
6
"EventName": "BACLEARS.ANY",
6
7
"SampleAfterValue": "100003",
···
9
8
},
10
9
{
11
10
"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches.",
11
+
"Counter": "0,1,2,3",
12
12
"EventCode": "0xAB",
13
13
"EventName": "DSB2MITE_SWITCHES.COUNT",
14
14
"SampleAfterValue": "2000003",
···
17
15
},
18
16
{
19
17
"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
18
+
"Counter": "0,1,2,3",
20
19
"EventCode": "0xAB",
21
20
"EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
22
21
"PublicDescription": "This event counts the cycles attributed to a switch from the Decoded Stream Buffer (DSB), which holds decoded instructions, to the legacy decode pipeline. It excludes cycles when the back-end cannot accept new micro-ops. The penalty for these switches is potentially several cycles of instruction starvation, where no micro-ops are delivered to the back-end.",
···
26
23
},
27
24
{
28
25
"BriefDescription": "Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exceeding way limit.",
26
+
"Counter": "0,1,2,3",
29
27
"EventCode": "0xAC",
30
28
"EventName": "DSB_FILL.ALL_CANCEL",
31
29
"SampleAfterValue": "2000003",
···
34
30
},
35
31
{
36
32
"BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines.",
33
+
"Counter": "0,1,2,3",
37
34
"EventCode": "0xAC",
38
35
"EventName": "DSB_FILL.EXCEED_DSB_LINES",
39
36
"SampleAfterValue": "2000003",
···
42
37
},
43
38
{
44
39
"BriefDescription": "Cases of cancelling valid DSB fill not because of exceeding way limit.",
40
+
"Counter": "0,1,2,3",
45
41
"EventCode": "0xAC",
46
42
"EventName": "DSB_FILL.OTHER_CANCEL",
47
43
"SampleAfterValue": "2000003",
···
50
44
},
51
45
{
52
46
"BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.",
47
+
"Counter": "0,1,2,3",
53
48
"EventCode": "0x80",
54
49
"EventName": "ICACHE.HIT",
55
50
"SampleAfterValue": "2000003",
···
58
51
},
59
52
{
60
53
"BriefDescription": "Instruction cache, streaming buffer and victim cache misses.",
54
+
"Counter": "0,1,2,3",
61
55
"EventCode": "0x80",
62
56
"EventName": "ICACHE.MISSES",
63
57
"PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes unchacheable accesses.",
···
67
59
},
68
60
{
69
61
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops.",
62
+
"Counter": "0,1,2,3",
70
63
"CounterMask": "4",
71
64
"EventCode": "0x79",
72
65
"EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
···
76
67
},
77
68
{
78
69
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop.",
70
+
"Counter": "0,1,2,3",
79
71
"CounterMask": "1",
80
72
"EventCode": "0x79",
81
73
"EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
···
85
75
},
86
76
{
87
77
"BriefDescription": "Cycles MITE is delivering 4 Uops.",
78
+
"Counter": "0,1,2,3",
88
79
"CounterMask": "4",
89
80
"EventCode": "0x79",
90
81
"EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
···
94
83
},
95
84
{
96
85
"BriefDescription": "Cycles MITE is delivering any Uop.",
86
+
"Counter": "0,1,2,3",
97
87
"CounterMask": "1",
98
88
"EventCode": "0x79",
99
89
"EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
···
103
91
},
104
92
{
105
93
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.",
94
+
"Counter": "0,1,2,3",
106
95
"CounterMask": "1",
107
96
"EventCode": "0x79",
108
97
"EventName": "IDQ.DSB_CYCLES",
···
112
99
},
113
100
{
114
101
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",
102
+
"Counter": "0,1,2,3",
115
103
"EventCode": "0x79",
116
104
"EventName": "IDQ.DSB_UOPS",
117
105
"SampleAfterValue": "2000003",
···
120
106
},
121
107
{
122
108
"BriefDescription": "Instruction Decode Queue (IDQ) empty cycles.",
109
+
"Counter": "0,1,2,3",
123
110
"EventCode": "0x79",
124
111
"EventName": "IDQ.EMPTY",
125
112
"SampleAfterValue": "2000003",
···
128
113
},
129
114
{
130
115
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path.",
116
+
"Counter": "0,1,2,3",
131
117
"EventCode": "0x79",
132
118
"EventName": "IDQ.MITE_ALL_UOPS",
133
119
"SampleAfterValue": "2000003",
···
136
120
},
137
121
{
138
122
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.",
123
+
"Counter": "0,1,2,3",
139
124
"CounterMask": "1",
140
125
"EventCode": "0x79",
141
126
"EventName": "IDQ.MITE_CYCLES",
···
145
128
},
146
129
{
147
130
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path.",
131
+
"Counter": "0,1,2,3",
148
132
"EventCode": "0x79",
149
133
"EventName": "IDQ.MITE_UOPS",
150
134
"SampleAfterValue": "2000003",
···
153
135
},
154
136
{
155
137
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy.",
138
+
"Counter": "0,1,2,3",
156
139
"CounterMask": "1",
157
140
"EventCode": "0x79",
158
141
"EventName": "IDQ.MS_CYCLES",
···
163
144
},
164
145
{
165
146
"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy.",
147
+
"Counter": "0,1,2,3",
166
148
"CounterMask": "1",
167
149
"EventCode": "0x79",
168
150
"EventName": "IDQ.MS_DSB_CYCLES",
···
172
152
},
173
153
{
174
154
"BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is busy.",
155
+
"Counter": "0,1,2,3",
175
156
"CounterMask": "1",
176
157
"EdgeDetect": "1",
177
158
"EventCode": "0x79",
···
182
161
},
183
162
{
184
163
"BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy.",
164
+
"Counter": "0,1,2,3",
185
165
"EventCode": "0x79",
186
166
"EventName": "IDQ.MS_DSB_UOPS",
187
167
"SampleAfterValue": "2000003",
···
190
168
},
191
169
{
192
170
"BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy.",
171
+
"Counter": "0,1,2,3",
193
172
"EventCode": "0x79",
194
173
"EventName": "IDQ.MS_MITE_UOPS",
195
174
"SampleAfterValue": "2000003",
···
198
175
},
199
176
{
200
177
"BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
178
+
"Counter": "0,1,2,3",
201
179
"CounterMask": "1",
202
180
"EdgeDetect": "1",
203
181
"EventCode": "0x79",
···
208
184
},
209
185
{
210
186
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy.",
187
+
"Counter": "0,1,2,3",
211
188
"EventCode": "0x79",
212
189
"EventName": "IDQ.MS_UOPS",
213
190
"SampleAfterValue": "2000003",
···
216
191
},
217
192
{
218
193
"BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled .",
194
+
"Counter": "0,1,2,3",
219
195
"EventCode": "0x9C",
220
196
"EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
221
197
"PublicDescription": "This event counts the number of uops not delivered to the back-end per cycle, per thread, when the back-end was not stalled. In the ideal case 4 uops can be delivered each cycle. The event counts the undelivered uops - so if 3 were delivered in one cycle, the counter would be incremented by 1 for that cycle (4 - 3). If the back-end is stalled, the count for this event is not incremented even when uops were not delivered, because the back-end would not have been able to accept them. This event is used in determining the front-end bound category of the top-down pipeline slots characterization.",
···
225
199
},
226
200
{
227
201
"BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.",
202
+
"Counter": "0,1,2,3",
228
203
"CounterMask": "4",
229
204
"EventCode": "0x9C",
230
205
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
···
234
207
},
235
208
{
236
209
"BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
210
+
"Counter": "0,1,2,3",
237
211
"CounterMask": "1",
238
212
"EventCode": "0x9C",
239
213
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
···
244
216
},
245
217
{
246
218
"BriefDescription": "Cycles when 1 or more uops were delivered to the by the front end.",
219
+
"Counter": "0,1,2,3",
247
220
"CounterMask": "4",
248
221
"EventCode": "0x9C",
249
222
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_GE_1_UOP_DELIV.CORE",
···
254
225
},
255
226
{
256
227
"BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.",
228
+
"Counter": "0,1,2,3",
257
229
"CounterMask": "3",
258
230
"EventCode": "0x9C",
259
231
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
···
263
233
},
264
234
{
265
235
"BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
236
+
"Counter": "0,1,2,3",
266
237
"CounterMask": "2",
267
238
"EventCode": "0x9C",
268
239
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",
···
272
241
},
273
242
{
274
243
"BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
244
+
"Counter": "0,1,2,3",
275
245
"CounterMask": "1",
276
246
"EventCode": "0x9C",
277
247
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",
+37
tools/perf/pmu-events/arch/x86/sandybridge/memory.json
+37
tools/perf/pmu-events/arch/x86/sandybridge/memory.json
···
1
1
[
2
2
{
3
3
"BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
4
+
"Counter": "0,1,2,3",
4
5
"EventCode": "0xC3",
5
6
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
6
7
"PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from memory disambiguation, external snoops, or cross SMT-HW-thread snoop (stores) hitting load buffers. Machine clears can have a significant performance impact if they are happening frequently.",
···
10
9
},
11
10
{
12
11
"BriefDescription": "Loads with latency value being above 128.",
12
+
"Counter": "3",
13
13
"EventCode": "0xCD",
14
14
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
15
15
"MSRIndex": "0x3F6",
···
21
19
},
22
20
{
23
21
"BriefDescription": "Loads with latency value being above 16.",
22
+
"Counter": "3",
24
23
"EventCode": "0xCD",
25
24
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
26
25
"MSRIndex": "0x3F6",
···
32
29
},
33
30
{
34
31
"BriefDescription": "Loads with latency value being above 256.",
32
+
"Counter": "3",
35
33
"EventCode": "0xCD",
36
34
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
37
35
"MSRIndex": "0x3F6",
···
43
39
},
44
40
{
45
41
"BriefDescription": "Loads with latency value being above 32.",
42
+
"Counter": "3",
46
43
"EventCode": "0xCD",
47
44
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
48
45
"MSRIndex": "0x3F6",
···
54
49
},
55
50
{
56
51
"BriefDescription": "Loads with latency value being above 4 .",
52
+
"Counter": "3",
57
53
"EventCode": "0xCD",
58
54
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
59
55
"MSRIndex": "0x3F6",
···
65
59
},
66
60
{
67
61
"BriefDescription": "Loads with latency value being above 512.",
62
+
"Counter": "3",
68
63
"EventCode": "0xCD",
69
64
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
70
65
"MSRIndex": "0x3F6",
···
76
69
},
77
70
{
78
71
"BriefDescription": "Loads with latency value being above 64.",
72
+
"Counter": "3",
79
73
"EventCode": "0xCD",
80
74
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
81
75
"MSRIndex": "0x3F6",
···
87
79
},
88
80
{
89
81
"BriefDescription": "Loads with latency value being above 8.",
82
+
"Counter": "3",
90
83
"EventCode": "0xCD",
91
84
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
92
85
"MSRIndex": "0x3F6",
···
98
89
},
99
90
{
100
91
"BriefDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only. (Precise Event - PEBS).",
92
+
"Counter": "3",
101
93
"EventCode": "0xCD",
102
94
"EventName": "MEM_TRANS_RETIRED.PRECISE_STORE",
103
95
"PEBS": "2",
···
107
97
},
108
98
{
109
99
"BriefDescription": "Speculative cache line split load uops dispatched to L1 cache.",
100
+
"Counter": "0,1,2,3",
110
101
"EventCode": "0x05",
111
102
"EventName": "MISALIGN_MEM_REF.LOADS",
112
103
"SampleAfterValue": "2000003",
···
115
104
},
116
105
{
117
106
"BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache.",
107
+
"Counter": "0,1,2,3",
118
108
"EventCode": "0x05",
119
109
"EventName": "MISALIGN_MEM_REF.STORES",
120
110
"SampleAfterValue": "2000003",
···
123
111
},
124
112
{
125
113
"BriefDescription": "Counts all demand & prefetch code reads that miss the LLC and the data returned from dram.",
114
+
"Counter": "0,1,2,3",
126
115
"EventCode": "0xB7, 0xBB",
127
116
"EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.DRAM",
128
117
"MSRIndex": "0x1a6,0x1a7",
···
133
120
},
134
121
{
135
122
"BriefDescription": "Counts all demand & prefetch data reads that miss the LLC and the data returned from dram.",
123
+
"Counter": "0,1,2,3",
136
124
"EventCode": "0xB7, 0xBB",
137
125
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.DRAM",
138
126
"MSRIndex": "0x1a6,0x1a7",
···
143
129
},
144
130
{
145
131
"BriefDescription": "Counts all prefetch code reads that miss the LLC and the data returned from dram.",
132
+
"Counter": "0,1,2,3",
146
133
"EventCode": "0xB7, 0xBB",
147
134
"EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_MISS.DRAM",
148
135
"MSRIndex": "0x1a6,0x1a7",
···
153
138
},
154
139
{
155
140
"BriefDescription": "Counts all prefetch data reads that miss the LLC and the data returned from dram.",
141
+
"Counter": "0,1,2,3",
156
142
"EventCode": "0xB7, 0xBB",
157
143
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_MISS.DRAM",
158
144
"MSRIndex": "0x1a6,0x1a7",
···
163
147
},
164
148
{
165
149
"BriefDescription": "Counts all prefetch RFOs that miss the LLC and the data returned from dram.",
150
+
"Counter": "0,1,2,3",
166
151
"EventCode": "0xB7, 0xBB",
167
152
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_MISS.DRAM",
168
153
"MSRIndex": "0x1a6,0x1a7",
···
173
156
},
174
157
{
175
158
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC and the data returned from dram.",
159
+
"Counter": "0,1,2,3",
176
160
"EventCode": "0xB7, 0xBB",
177
161
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.DRAM",
178
162
"MSRIndex": "0x1a6,0x1a7",
···
183
165
},
184
166
{
185
167
"BriefDescription": "Counts all demand & prefetch RFOs that miss the LLC and the data returned from dram.",
168
+
"Counter": "0,1,2,3",
186
169
"EventCode": "0xB7, 0xBB",
187
170
"EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.DRAM",
188
171
"MSRIndex": "0x1a6,0x1a7",
···
193
174
},
194
175
{
195
176
"BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",
177
+
"Counter": "0,1,2,3",
196
178
"EventCode": "0xB7, 0xBB",
197
179
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_MISS_LOCAL.DRAM",
198
180
"MSRIndex": "0x1a6,0x1a7",
···
204
184
},
205
185
{
206
186
"BriefDescription": "Counts LLC replacements.",
187
+
"Counter": "0,1,2,3",
207
188
"EventCode": "0xB7, 0xBB",
208
189
"EventName": "OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS.LOCAL_DRAM",
209
190
"MSRIndex": "0x1a6,0x1a7",
···
215
194
},
216
195
{
217
196
"BriefDescription": "REQUEST = DATA_IN_SOCKET and RESPONSE = LLC_MISS_LOCAL and SNOOP = ANY_LLC_HIT",
197
+
"Counter": "0,1,2,3",
218
198
"EventCode": "0xB7, 0xBB",
219
199
"EventName": "OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS_LOCAL.ANY_LLC_HIT",
220
200
"MSRIndex": "0x1a6,0x1a7",
···
225
203
},
226
204
{
227
205
"BriefDescription": "Counts demand code reads that miss the LLC and the data returned from dram.",
206
+
"Counter": "0,1,2,3",
228
207
"EventCode": "0xB7, 0xBB",
229
208
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.DRAM",
230
209
"MSRIndex": "0x1a6,0x1a7",
···
235
212
},
236
213
{
237
214
"BriefDescription": "Counts demand data reads that miss the LLC and the data returned from dram.",
215
+
"Counter": "0,1,2,3",
238
216
"EventCode": "0xB7, 0xBB",
239
217
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.DRAM",
240
218
"MSRIndex": "0x1a6,0x1a7",
···
245
221
},
246
222
{
247
223
"BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",
224
+
"Counter": "0,1,2,3",
248
225
"EventCode": "0xB7, 0xBB",
249
226
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_MISS_LOCAL.DRAM",
250
227
"MSRIndex": "0x1a6,0x1a7",
···
255
230
},
256
231
{
257
232
"BriefDescription": "Counts demand data writes (RFOs) that miss the LLC and the data returned from dram.",
233
+
"Counter": "0,1,2,3",
258
234
"EventCode": "0xB7, 0xBB",
259
235
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.DRAM",
260
236
"MSRIndex": "0x1a6,0x1a7",
···
265
239
},
266
240
{
267
241
"BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",
242
+
"Counter": "0,1,2,3",
268
243
"EventCode": "0xB7, 0xBB",
269
244
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_MISS_LOCAL.DRAM",
270
245
"MSRIndex": "0x1a6,0x1a7",
···
275
248
},
276
249
{
277
250
"BriefDescription": "REQUEST = PF_RFO and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",
251
+
"Counter": "0,1,2,3",
278
252
"EventCode": "0xB7, 0xBB",
279
253
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_MISS_LOCAL.DRAM",
280
254
"MSRIndex": "0x1a6,0x1a7",
···
285
257
},
286
258
{
287
259
"BriefDescription": "Counts all prefetch (that bring data to L2) code reads that miss the LLC and the data returned from dram.",
260
+
"Counter": "0,1,2,3",
288
261
"EventCode": "0xB7, 0xBB",
289
262
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.DRAM",
290
263
"MSRIndex": "0x1a6,0x1a7",
···
295
266
},
296
267
{
297
268
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from dram.",
269
+
"Counter": "0,1,2,3",
298
270
"EventCode": "0xB7, 0xBB",
299
271
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.DRAM",
300
272
"MSRIndex": "0x1a6,0x1a7",
···
305
275
},
306
276
{
307
277
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the LLC and the data returned from dram.",
278
+
"Counter": "0,1,2,3",
308
279
"EventCode": "0xB7, 0xBB",
309
280
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_MISS.DRAM",
310
281
"MSRIndex": "0x1a6,0x1a7",
···
315
284
},
316
285
{
317
286
"BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss the LLC and the data returned from dram.",
287
+
"Counter": "0,1,2,3",
318
288
"EventCode": "0xB7, 0xBB",
319
289
"EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.DRAM",
320
290
"MSRIndex": "0x1a6,0x1a7",
···
325
293
},
326
294
{
327
295
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the LLC and the data returned from dram.",
296
+
"Counter": "0,1,2,3",
328
297
"EventCode": "0xB7, 0xBB",
329
298
"EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.DRAM",
330
299
"MSRIndex": "0x1a6,0x1a7",
···
335
302
},
336
303
{
337
304
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the LLC and the data returned from dram.",
305
+
"Counter": "0,1,2,3",
338
306
"EventCode": "0xB7, 0xBB",
339
307
"EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_MISS.DRAM",
340
308
"MSRIndex": "0x1a6,0x1a7",
···
345
311
},
346
312
{
347
313
"BriefDescription": "REQUEST = PF_LLC_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",
314
+
"Counter": "0,1,2,3",
348
315
"EventCode": "0xB7, 0xBB",
349
316
"EventName": "OFFCORE_RESPONSE.PF_L_DATA_RD.LLC_MISS_LOCAL.DRAM",
350
317
"MSRIndex": "0x1a6,0x1a7",
···
355
320
},
356
321
{
357
322
"BriefDescription": "REQUEST = PF_LLC_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",
323
+
"Counter": "0,1,2,3",
358
324
"EventCode": "0xB7, 0xBB",
359
325
"EventName": "OFFCORE_RESPONSE.PF_L_IFETCH.LLC_MISS_LOCAL.DRAM",
360
326
"MSRIndex": "0x1a6,0x1a7",
···
365
329
},
366
330
{
367
331
"BriefDescription": "Number of any page walk that had a miss in LLC. Does not necessary cause a SUSPEND.",
332
+
"Counter": "0,1,2,3",
368
333
"EventCode": "0xBE",
369
334
"EventName": "PAGE_WALKS.LLC_MISS",
370
335
"SampleAfterValue": "100003",
+11
tools/perf/pmu-events/arch/x86/sandybridge/metricgroups.json
+11
tools/perf/pmu-events/arch/x86/sandybridge/metricgroups.json
···
5
5
"BigFootprint": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
6
6
"BrMispredicts": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
7
7
"Branches": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
8
+
"BvBC": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
9
+
"BvCB": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
10
+
"BvFB": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
11
+
"BvIO": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
12
+
"BvML": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
13
+
"BvMP": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
14
+
"BvMS": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
15
+
"BvMT": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
16
+
"BvOB": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
17
+
"BvUW": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
8
18
"CacheHits": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
19
+
"CacheMisses": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
9
20
"Compute": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
10
21
"Cor": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
11
22
"DSB": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+6
tools/perf/pmu-events/arch/x86/sandybridge/other.json
+6
tools/perf/pmu-events/arch/x86/sandybridge/other.json
···
1
1
[
2
2
{
3
3
"BriefDescription": "Unhalted core cycles when the thread is in ring 0.",
4
+
"Counter": "0,1,2,3",
4
5
"EventCode": "0x5C",
5
6
"EventName": "CPL_CYCLES.RING0",
6
7
"SampleAfterValue": "2000003",
···
9
8
},
10
9
{
11
10
"BriefDescription": "Number of intervals between processor halts while thread is in ring 0.",
11
+
"Counter": "0,1,2,3",
12
12
"CounterMask": "1",
13
13
"EdgeDetect": "1",
14
14
"EventCode": "0x5C",
···
19
17
},
20
18
{
21
19
"BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3.",
20
+
"Counter": "0,1,2,3",
22
21
"EventCode": "0x5C",
23
22
"EventName": "CPL_CYCLES.RING123",
24
23
"SampleAfterValue": "2000003",
···
27
24
},
28
25
{
29
26
"BriefDescription": "Hardware Prefetch requests that miss the L1D cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for .",
27
+
"Counter": "0,1,2,3",
30
28
"EventCode": "0x4E",
31
29
"EventName": "HW_PRE_REQ.DL1_MISS",
32
30
"SampleAfterValue": "2000003",
···
35
31
},
36
32
{
37
33
"BriefDescription": "Valid instructions written to IQ per cycle.",
34
+
"Counter": "0,1,2,3",
38
35
"EventCode": "0x17",
39
36
"EventName": "INSTS_WRITTEN_TO_IQ.INSTS",
40
37
"SampleAfterValue": "2000003",
···
43
38
},
44
39
{
45
40
"BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock.",
41
+
"Counter": "0,1,2,3",
46
42
"EventCode": "0x63",
47
43
"EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
48
44
"SampleAfterValue": "2000003",
+128
tools/perf/pmu-events/arch/x86/sandybridge/pipeline.json
+128
tools/perf/pmu-events/arch/x86/sandybridge/pipeline.json
···
1
1
[
2
2
{
3
3
"BriefDescription": "This event counts executed load operations with all the following traits: 1. addressing of the format [base + offset], 2. the offset is between 1 and 2047, 3. the address specified in the base register is in one page and the address [base+offset] is in an.",
4
+
"Counter": "0,1,2,3",
4
5
"EventCode": "0xB6",
5
6
"EventName": "AGU_BYPASS_CANCEL.COUNT",
6
7
"SampleAfterValue": "100003",
···
9
8
},
10
9
{
11
10
"BriefDescription": "Divide operations executed.",
11
+
"Counter": "0,1,2,3",
12
12
"CounterMask": "1",
13
13
"EdgeDetect": "1",
14
14
"EventCode": "0x14",
···
20
18
},
21
19
{
22
20
"BriefDescription": "Cycles when divider is busy executing divide operations.",
21
+
"Counter": "0,1,2,3",
23
22
"EventCode": "0x14",
24
23
"EventName": "ARITH.FPU_DIV_ACTIVE",
25
24
"SampleAfterValue": "2000003",
···
28
25
},
29
26
{
30
27
"BriefDescription": "Speculative and retired branches.",
28
+
"Counter": "0,1,2,3",
31
29
"EventCode": "0x88",
32
30
"EventName": "BR_INST_EXEC.ALL_BRANCHES",
33
31
"SampleAfterValue": "200003",
···
36
32
},
37
33
{
38
34
"BriefDescription": "Speculative and retired macro-conditional branches.",
35
+
"Counter": "0,1,2,3",
39
36
"EventCode": "0x88",
40
37
"EventName": "BR_INST_EXEC.ALL_CONDITIONAL",
41
38
"SampleAfterValue": "200003",
···
44
39
},
45
40
{
46
41
"BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects.",
42
+
"Counter": "0,1,2,3",
47
43
"EventCode": "0x88",
48
44
"EventName": "BR_INST_EXEC.ALL_DIRECT_JMP",
49
45
"SampleAfterValue": "200003",
···
52
46
},
53
47
{
54
48
"BriefDescription": "Speculative and retired direct near calls.",
49
+
"Counter": "0,1,2,3",
55
50
"EventCode": "0x88",
56
51
"EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL",
57
52
"SampleAfterValue": "200003",
···
60
53
},
61
54
{
62
55
"BriefDescription": "Speculative and retired indirect branches excluding calls and returns.",
56
+
"Counter": "0,1,2,3",
63
57
"EventCode": "0x88",
64
58
"EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",
65
59
"SampleAfterValue": "200003",
···
68
60
},
69
61
{
70
62
"BriefDescription": "Speculative and retired indirect return branches.",
63
+
"Counter": "0,1,2,3",
71
64
"EventCode": "0x88",
72
65
"EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN",
73
66
"SampleAfterValue": "200003",
···
76
67
},
77
68
{
78
69
"BriefDescription": "Not taken macro-conditional branches.",
70
+
"Counter": "0,1,2,3",
79
71
"EventCode": "0x88",
80
72
"EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL",
81
73
"SampleAfterValue": "200003",
···
84
74
},
85
75
{
86
76
"BriefDescription": "Taken speculative and retired macro-conditional branches.",
77
+
"Counter": "0,1,2,3",
87
78
"EventCode": "0x88",
88
79
"EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL",
89
80
"SampleAfterValue": "200003",
···
92
81
},
93
82
{
94
83
"BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects.",
84
+
"Counter": "0,1,2,3",
95
85
"EventCode": "0x88",
96
86
"EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP",
97
87
"SampleAfterValue": "200003",
···
100
88
},
101
89
{
102
90
"BriefDescription": "Taken speculative and retired direct near calls.",
91
+
"Counter": "0,1,2,3",
103
92
"EventCode": "0x88",
104
93
"EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL",
105
94
"SampleAfterValue": "200003",
···
108
95
},
109
96
{
110
97
"BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns.",
98
+
"Counter": "0,1,2,3",
111
99
"EventCode": "0x88",
112
100
"EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",
113
101
"SampleAfterValue": "200003",
···
116
102
},
117
103
{
118
104
"BriefDescription": "Taken speculative and retired indirect calls.",
105
+
"Counter": "0,1,2,3",
119
106
"EventCode": "0x88",
120
107
"EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL",
121
108
"SampleAfterValue": "200003",
···
124
109
},
125
110
{
126
111
"BriefDescription": "Taken speculative and retired indirect branches with return mnemonic.",
112
+
"Counter": "0,1,2,3",
127
113
"EventCode": "0x88",
128
114
"EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN",
129
115
"SampleAfterValue": "200003",
···
132
116
},
133
117
{
134
118
"BriefDescription": "All (macro) branch instructions retired.",
119
+
"Counter": "0,1,2,3",
135
120
"EventCode": "0xC4",
136
121
"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
137
122
"SampleAfterValue": "400009"
138
123
},
139
124
{
140
125
"BriefDescription": "All (macro) branch instructions retired. (Precise Event - PEBS).",
126
+
"Counter": "0,1,2,3",
141
127
"EventCode": "0xC4",
142
128
"EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS",
143
129
"PEBS": "2",
···
148
130
},
149
131
{
150
132
"BriefDescription": "Conditional branch instructions retired. (Precise Event - PEBS).",
133
+
"Counter": "0,1,2,3",
151
134
"EventCode": "0xC4",
152
135
"EventName": "BR_INST_RETIRED.CONDITIONAL",
153
136
"PEBS": "1",
···
157
138
},
158
139
{
159
140
"BriefDescription": "Far branch instructions retired.",
141
+
"Counter": "0,1,2,3",
160
142
"EventCode": "0xC4",
161
143
"EventName": "BR_INST_RETIRED.FAR_BRANCH",
162
144
"SampleAfterValue": "100007",
···
165
145
},
166
146
{
167
147
"BriefDescription": "Direct and indirect near call instructions retired. (Precise Event - PEBS).",
148
+
"Counter": "0,1,2,3",
168
149
"EventCode": "0xC4",
169
150
"EventName": "BR_INST_RETIRED.NEAR_CALL",
170
151
"PEBS": "1",
···
174
153
},
175
154
{
176
155
"BriefDescription": "Direct and indirect macro near call instructions retired (captured in ring 3). (Precise Event - PEBS).",
156
+
"Counter": "0,1,2,3",
177
157
"EventCode": "0xC4",
178
158
"EventName": "BR_INST_RETIRED.NEAR_CALL_R3",
179
159
"PEBS": "1",
···
183
161
},
184
162
{
185
163
"BriefDescription": "Return instructions retired. (Precise Event - PEBS).",
164
+
"Counter": "0,1,2,3",
186
165
"EventCode": "0xC4",
187
166
"EventName": "BR_INST_RETIRED.NEAR_RETURN",
188
167
"PEBS": "1",
···
192
169
},
193
170
{
194
171
"BriefDescription": "Taken branch instructions retired. (Precise Event - PEBS).",
172
+
"Counter": "0,1,2,3",
195
173
"EventCode": "0xC4",
196
174
"EventName": "BR_INST_RETIRED.NEAR_TAKEN",
197
175
"PEBS": "1",
···
201
177
},
202
178
{
203
179
"BriefDescription": "Not taken branch instructions retired.",
180
+
"Counter": "0,1,2,3",
204
181
"EventCode": "0xC4",
205
182
"EventName": "BR_INST_RETIRED.NOT_TAKEN",
206
183
"SampleAfterValue": "400009",
···
209
184
},
210
185
{
211
186
"BriefDescription": "Speculative and retired mispredicted macro conditional branches.",
187
+
"Counter": "0,1,2,3",
212
188
"EventCode": "0x89",
213
189
"EventName": "BR_MISP_EXEC.ALL_BRANCHES",
214
190
"SampleAfterValue": "200003",
···
217
191
},
218
192
{
219
193
"BriefDescription": "Speculative and retired mispredicted macro conditional branches.",
194
+
"Counter": "0,1,2,3",
220
195
"EventCode": "0x89",
221
196
"EventName": "BR_MISP_EXEC.ALL_CONDITIONAL",
222
197
"SampleAfterValue": "200003",
···
225
198
},
226
199
{
227
200
"BriefDescription": "Speculative and retired mispredicted direct near calls.",
201
+
"Counter": "0,1,2,3",
228
202
"EventCode": "0x89",
229
203
"EventName": "BR_MISP_EXEC.ALL_DIRECT_NEAR_CALL",
230
204
"SampleAfterValue": "200003",
···
233
205
},
234
206
{
235
207
"BriefDescription": "Mispredicted indirect branches excluding calls and returns.",
208
+
"Counter": "0,1,2,3",
236
209
"EventCode": "0x89",
237
210
"EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",
238
211
"SampleAfterValue": "200003",
···
241
212
},
242
213
{
243
214
"BriefDescription": "Speculative mispredicted indirect branches",
215
+
"Counter": "0,1,2,3",
244
216
"EventCode": "0x89",
245
217
"EventName": "BR_MISP_EXEC.INDIRECT",
246
218
"PublicDescription": "Counts speculatively miss-predicted indirect branches at execution time. Counts for indirect near CALL or JMP instructions (RET excluded).",
···
250
220
},
251
221
{
252
222
"BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches.",
223
+
"Counter": "0,1,2,3",
253
224
"EventCode": "0x89",
254
225
"EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL",
255
226
"SampleAfterValue": "200003",
···
258
227
},
259
228
{
260
229
"BriefDescription": "Taken speculative and retired mispredicted macro conditional branches.",
230
+
"Counter": "0,1,2,3",
261
231
"EventCode": "0x89",
262
232
"EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL",
263
233
"SampleAfterValue": "200003",
···
266
234
},
267
235
{
268
236
"BriefDescription": "Taken speculative and retired mispredicted direct near calls.",
237
+
"Counter": "0,1,2,3",
269
238
"EventCode": "0x89",
270
239
"EventName": "BR_MISP_EXEC.TAKEN_DIRECT_NEAR_CALL",
271
240
"SampleAfterValue": "200003",
···
274
241
},
275
242
{
276
243
"BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns.",
244
+
"Counter": "0,1,2,3",
277
245
"EventCode": "0x89",
278
246
"EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",
279
247
"SampleAfterValue": "200003",
···
282
248
},
283
249
{
284
250
"BriefDescription": "Taken speculative and retired mispredicted indirect calls.",
251
+
"Counter": "0,1,2,3",
285
252
"EventCode": "0x89",
286
253
"EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL",
287
254
"SampleAfterValue": "200003",
···
290
255
},
291
256
{
292
257
"BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic.",
258
+
"Counter": "0,1,2,3",
293
259
"EventCode": "0x89",
294
260
"EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR",
295
261
"SampleAfterValue": "200003",
···
298
262
},
299
263
{
300
264
"BriefDescription": "All mispredicted macro branch instructions retired.",
265
+
"Counter": "0,1,2,3",
301
266
"EventCode": "0xC5",
302
267
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
303
268
"SampleAfterValue": "400009"
304
269
},
305
270
{
306
271
"BriefDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS).",
272
+
"Counter": "0,1,2,3",
307
273
"EventCode": "0xC5",
308
274
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS",
309
275
"PEBS": "2",
···
314
276
},
315
277
{
316
278
"BriefDescription": "Mispredicted conditional branch instructions retired. (Precise Event - PEBS).",
279
+
"Counter": "0,1,2,3",
317
280
"EventCode": "0xC5",
318
281
"EventName": "BR_MISP_RETIRED.CONDITIONAL",
319
282
"PEBS": "1",
···
323
284
},
324
285
{
325
286
"BriefDescription": "Direct and indirect mispredicted near call instructions retired. (Precise Event - PEBS).",
287
+
"Counter": "0,1,2,3",
326
288
"EventCode": "0xC5",
327
289
"EventName": "BR_MISP_RETIRED.NEAR_CALL",
328
290
"PEBS": "1",
···
332
292
},
333
293
{
334
294
"BriefDescription": "Mispredicted not taken branch instructions retired.(Precise Event - PEBS).",
295
+
"Counter": "0,1,2,3",
335
296
"EventCode": "0xC5",
336
297
"EventName": "BR_MISP_RETIRED.NOT_TAKEN",
337
298
"PEBS": "1",
···
341
300
},
342
301
{
343
302
"BriefDescription": "Mispredicted taken branch instructions retired. (Precise Event - PEBS).",
303
+
"Counter": "0,1,2,3",
344
304
"EventCode": "0xC5",
345
305
"EventName": "BR_MISP_RETIRED.TAKEN",
346
306
"PEBS": "1",
···
350
308
},
351
309
{
352
310
"BriefDescription": "Count XClk pulses when this thread is unhalted and the other is halted.",
311
+
"Counter": "0,1,2,3",
353
312
"EventCode": "0x3C",
354
313
"EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE",
355
314
"SampleAfterValue": "2000003",
···
358
315
},
359
316
{
360
317
"BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate).",
318
+
"Counter": "0,1,2,3",
361
319
"EventCode": "0x3C",
362
320
"EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK",
363
321
"SampleAfterValue": "2000003",
···
367
323
{
368
324
"AnyThread": "1",
369
325
"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).",
326
+
"Counter": "0,1,2,3",
370
327
"EventCode": "0x3C",
371
328
"EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY",
372
329
"SampleAfterValue": "2000003",
···
375
330
},
376
331
{
377
332
"BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.",
333
+
"Counter": "0,1,2,3",
378
334
"EventCode": "0x3C",
379
335
"EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",
380
336
"SampleAfterValue": "2000003",
···
383
337
},
384
338
{
385
339
"BriefDescription": "Reference cycles when the core is not in halt state.",
340
+
"Counter": "Fixed counter 2",
386
341
"EventName": "CPU_CLK_UNHALTED.REF_TSC",
387
342
"PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.",
388
343
"SampleAfterValue": "2000003",
···
391
344
},
392
345
{
393
346
"BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate).",
347
+
"Counter": "0,1,2,3",
394
348
"EventCode": "0x3C",
395
349
"EventName": "CPU_CLK_UNHALTED.REF_XCLK",
396
350
"SampleAfterValue": "2000003",
···
400
352
{
401
353
"AnyThread": "1",
402
354
"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).",
355
+
"Counter": "0,1,2,3",
403
356
"EventCode": "0x3C",
404
357
"EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY",
405
358
"SampleAfterValue": "2000003",
···
408
359
},
409
360
{
410
361
"BriefDescription": "Core cycles when the thread is not in halt state.",
362
+
"Counter": "Fixed counter 1",
411
363
"EventName": "CPU_CLK_UNHALTED.THREAD",
412
364
"PublicDescription": "This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.",
413
365
"SampleAfterValue": "2000003",
···
417
367
{
418
368
"AnyThread": "1",
419
369
"BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
370
+
"Counter": "Fixed counter 1",
420
371
"EventName": "CPU_CLK_UNHALTED.THREAD_ANY",
421
372
"SampleAfterValue": "2000003",
422
373
"UMask": "0x2"
423
374
},
424
375
{
425
376
"BriefDescription": "Thread cycles when thread is not in halt state.",
377
+
"Counter": "0,1,2,3",
426
378
"EventCode": "0x3C",
427
379
"EventName": "CPU_CLK_UNHALTED.THREAD_P",
428
380
"SampleAfterValue": "2000003"
···
432
380
{
433
381
"AnyThread": "1",
434
382
"BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
383
+
"Counter": "0,1,2,3",
435
384
"EventCode": "0x3C",
436
385
"EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY",
437
386
"SampleAfterValue": "2000003"
438
387
},
439
388
{
440
389
"BriefDescription": "Each cycle there was a miss-pending demand load this thread, increment by 1. Note this is in DCU and connected to Umask 1. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING.",
390
+
"Counter": "2",
441
391
"CounterMask": "2",
442
392
"EventCode": "0xA3",
443
393
"EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING",
···
448
394
},
449
395
{
450
396
"BriefDescription": "Each cycle there was a MLC-miss pending demand load this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0.",
397
+
"Counter": "0,1,2,3",
451
398
"CounterMask": "1",
452
399
"EventCode": "0xA3",
453
400
"EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING",
···
457
402
},
458
403
{
459
404
"BriefDescription": "Each cycle there was no dispatch for this thread, increment by 1. Note this is connect to Umask 2. No dispatch can be deduced from the UOPS_EXECUTED event.",
405
+
"Counter": "0,1,2,3",
460
406
"CounterMask": "4",
461
407
"EventCode": "0xA3",
462
408
"EventName": "CYCLE_ACTIVITY.CYCLES_NO_DISPATCH",
···
466
410
},
467
411
{
468
412
"BriefDescription": "Each cycle there was a miss-pending demand load this thread and no uops dispatched, increment by 1. Note this is in DCU and connected to Umask 1 and 2. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING.",
413
+
"Counter": "2",
469
414
"CounterMask": "6",
470
415
"EventCode": "0xA3",
471
416
"EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING",
···
475
418
},
476
419
{
477
420
"BriefDescription": "Each cycle there was a MLC-miss pending demand load and no uops dispatched on this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0 and 2.",
421
+
"Counter": "0,1,2,3",
478
422
"CounterMask": "5",
479
423
"EventCode": "0xA3",
480
424
"EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING",
···
484
426
},
485
427
{
486
428
"BriefDescription": "Stall cycles because IQ is full.",
429
+
"Counter": "0,1,2,3",
487
430
"EventCode": "0x87",
488
431
"EventName": "ILD_STALL.IQ_FULL",
489
432
"SampleAfterValue": "2000003",
···
492
433
},
493
434
{
494
435
"BriefDescription": "Stalls caused by changing prefix length of the instruction.",
436
+
"Counter": "0,1,2,3",
495
437
"EventCode": "0x87",
496
438
"EventName": "ILD_STALL.LCP",
497
439
"SampleAfterValue": "2000003",
···
500
440
},
501
441
{
502
442
"BriefDescription": "Instructions retired from execution.",
443
+
"Counter": "Fixed counter 0",
503
444
"EventName": "INST_RETIRED.ANY",
504
445
"PublicDescription": "This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers.",
505
446
"SampleAfterValue": "2000003",
···
508
447
},
509
448
{
510
449
"BriefDescription": "Number of instructions retired. General Counter - architectural event.",
450
+
"Counter": "0,1,2,3",
511
451
"EventCode": "0xC0",
512
452
"EventName": "INST_RETIRED.ANY_P",
513
453
"SampleAfterValue": "2000003"
514
454
},
515
455
{
516
456
"BriefDescription": "Instructions retired. (Precise Event - PEBS).",
457
+
"Counter": "1",
517
458
"EventCode": "0xC0",
518
459
"EventName": "INST_RETIRED.PREC_DIST",
519
460
"PEBS": "2",
···
524
461
},
525
462
{
526
463
"BriefDescription": "Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread.",
464
+
"Counter": "0,1,2,3",
527
465
"EventCode": "0x0D",
528
466
"EventName": "INT_MISC.RAT_STALL_CYCLES",
529
467
"SampleAfterValue": "2000003",
···
532
468
},
533
469
{
534
470
"BriefDescription": "Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...).",
471
+
"Counter": "0,1,2,3",
535
472
"CounterMask": "1",
536
473
"EventCode": "0x0D",
537
474
"EventName": "INT_MISC.RECOVERY_CYCLES",
···
542
477
{
543
478
"AnyThread": "1",
544
479
"BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).",
480
+
"Counter": "0,1,2,3",
545
481
"CounterMask": "1",
546
482
"EventCode": "0x0D",
547
483
"EventName": "INT_MISC.RECOVERY_CYCLES_ANY",
···
551
485
},
552
486
{
553
487
"BriefDescription": "Number of occurrences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...).",
488
+
"Counter": "0,1,2,3",
554
489
"CounterMask": "1",
555
490
"EdgeDetect": "1",
556
491
"EventCode": "0x0D",
···
561
494
},
562
495
{
563
496
"BriefDescription": "Number of cases where any load ends up with a valid block-code written to the load buffer (including blocks due to Memory Order Buffer (MOB), Data Cache Unit (DCU), TLB, but load has no DCU miss).",
497
+
"Counter": "0,1,2,3",
564
498
"EventCode": "0x03",
565
499
"EventName": "LD_BLOCKS.ALL_BLOCK",
566
500
"SampleAfterValue": "100003",
···
569
501
},
570
502
{
571
503
"BriefDescription": "Loads delayed due to SB blocks, preceding store operations with known addresses but unknown data.",
504
+
"Counter": "0,1,2,3",
572
505
"EventCode": "0x03",
573
506
"EventName": "LD_BLOCKS.DATA_UNKNOWN",
574
507
"SampleAfterValue": "100003",
···
577
508
},
578
509
{
579
510
"BriefDescription": "This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
511
+
"Counter": "0,1,2,3",
580
512
"EventCode": "0x03",
581
513
"EventName": "LD_BLOCKS.NO_SR",
582
514
"SampleAfterValue": "100003",
···
585
515
},
586
516
{
587
517
"BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwarding.",
518
+
"Counter": "0,1,2,3",
588
519
"EventCode": "0x03",
589
520
"EventName": "LD_BLOCKS.STORE_FORWARD",
590
521
"PublicDescription": "This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceding smaller uncompleted store. See the table of not supported store forwards in the Intel(R) 64 and IA-32 Architectures Optimization Reference Manual. The penalty for blocked store forwarding is that the load must wait for the store to complete before it can be issued.",
···
594
523
},
595
524
{
596
525
"BriefDescription": "False dependencies in MOB due to partial compare.",
526
+
"Counter": "0,1,2,3",
597
527
"EventCode": "0x07",
598
528
"EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",
599
529
"PublicDescription": "Aliasing occurs when a load is issued after a store and their memory addresses are offset by 4K. This event counts the number of loads that aliased with a preceding store, resulting in an extended address check in the pipeline. The enhanced address check typically has a performance penalty of 5 cycles.",
···
603
531
},
604
532
{
605
533
"BriefDescription": "This event counts the number of times that load operations are temporarily blocked because of older stores, with addresses that are not yet known. A load operation may incur more than one block of this type.",
534
+
"Counter": "0,1,2,3",
606
535
"EventCode": "0x07",
607
536
"EventName": "LD_BLOCKS_PARTIAL.ALL_STA_BLOCK",
608
537
"SampleAfterValue": "100003",
···
611
538
},
612
539
{
613
540
"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch.",
541
+
"Counter": "0,1,2,3",
614
542
"EventCode": "0x4C",
615
543
"EventName": "LOAD_HIT_PRE.HW_PF",
616
544
"SampleAfterValue": "100003",
···
619
545
},
620
546
{
621
547
"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch.",
548
+
"Counter": "0,1,2,3",
622
549
"EventCode": "0x4C",
623
550
"EventName": "LOAD_HIT_PRE.SW_PF",
624
551
"SampleAfterValue": "100003",
···
627
552
},
628
553
{
629
554
"BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.",
555
+
"Counter": "0,1,2,3",
630
556
"CounterMask": "4",
631
557
"EventCode": "0xA8",
632
558
"EventName": "LSD.CYCLES_4_UOPS",
···
636
560
},
637
561
{
638
562
"BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.",
563
+
"Counter": "0,1,2,3",
639
564
"CounterMask": "1",
640
565
"EventCode": "0xA8",
641
566
"EventName": "LSD.CYCLES_ACTIVE",
···
645
568
},
646
569
{
647
570
"BriefDescription": "Number of Uops delivered by the LSD.",
571
+
"Counter": "0,1,2,3",
648
572
"EventCode": "0xA8",
649
573
"EventName": "LSD.UOPS",
650
574
"SampleAfterValue": "2000003",
···
653
575
},
654
576
{
655
577
"BriefDescription": "Number of machine clears (nukes) of any type.",
578
+
"Counter": "0,1,2,3",
656
579
"CounterMask": "1",
657
580
"EdgeDetect": "1",
658
581
"EventCode": "0xc3",
···
663
584
},
664
585
{
665
586
"BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.",
587
+
"Counter": "0,1,2,3",
666
588
"EventCode": "0xC3",
667
589
"EventName": "MACHINE_CLEARS.MASKMOV",
668
590
"PublicDescription": "Maskmov false fault - counts number of time ucode passes through Maskmov flow due to instruction's mask being 0 while the flow was completed without raising a fault.",
···
672
592
},
673
593
{
674
594
"BriefDescription": "Self-modifying code (SMC) detected.",
595
+
"Counter": "0,1,2,3",
675
596
"EventCode": "0xC3",
676
597
"EventName": "MACHINE_CLEARS.SMC",
677
598
"PublicDescription": "This event is incremented when self-modifying code (SMC) is detected, which causes a machine clear. Machine clears can have a significant performance impact if they are happening frequently.",
···
681
600
},
682
601
{
683
602
"BriefDescription": "Retired instructions experiencing ITLB misses.",
603
+
"Counter": "0,1,2,3",
684
604
"EventCode": "0xC1",
685
605
"EventName": "OTHER_ASSISTS.ITLB_MISS_RETIRED",
686
606
"SampleAfterValue": "100003",
···
689
607
},
690
608
{
691
609
"BriefDescription": "Increments the number of flags-merge uops in flight each cycle.",
610
+
"Counter": "0,1,2,3",
692
611
"EventCode": "0x59",
693
612
"EventName": "PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP",
694
613
"SampleAfterValue": "2000003",
···
697
614
},
698
615
{
699
616
"BriefDescription": "Performance sensitive flags-merging uops added by Sandy Bridge u-arch.",
617
+
"Counter": "0,1,2,3",
700
618
"CounterMask": "1",
701
619
"EventCode": "0x59",
702
620
"EventName": "PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP_CYCLES",
···
707
623
},
708
624
{
709
625
"BriefDescription": "Multiply packed/scalar single precision uops allocated.",
626
+
"Counter": "0,1,2,3",
710
627
"EventCode": "0x59",
711
628
"EventName": "PARTIAL_RAT_STALLS.MUL_SINGLE_UOP",
712
629
"SampleAfterValue": "2000003",
···
715
630
},
716
631
{
717
632
"BriefDescription": "Cycles with at least one slow LEA uop being allocated.",
633
+
"Counter": "0,1,2,3",
718
634
"EventCode": "0x59",
719
635
"EventName": "PARTIAL_RAT_STALLS.SLOW_LEA_WINDOW",
720
636
"PublicDescription": "This event counts the number of cycles with at least one slow LEA uop being allocated. A uop is generally considered as slow LEA if it has three sources (for example, two sources and immediate) regardless of whether it is a result of LEA instruction or not. Examples of the slow LEA uop are or uops with base, index, and offset source operands using base and index reqisters, where base is EBR/RBP/R13, using RIP relative or 16-bit addressing modes. See the Intel(R) 64 and IA-32 Architectures Optimization Reference Manual for more details about slow LEA instructions.",
···
724
638
},
725
639
{
726
640
"BriefDescription": "Resource-related stall cycles.",
641
+
"Counter": "0,1,2,3",
727
642
"EventCode": "0xA2",
728
643
"EventName": "RESOURCE_STALLS.ANY",
729
644
"SampleAfterValue": "2000003",
···
732
645
},
733
646
{
734
647
"BriefDescription": "Counts the cycles of stall due to lack of load buffers.",
648
+
"Counter": "0,1,2,3",
735
649
"EventCode": "0xA2",
736
650
"EventName": "RESOURCE_STALLS.LB",
737
651
"SampleAfterValue": "2000003",
···
740
652
},
741
653
{
742
654
"BriefDescription": "Resource stalls due to load or store buffers all being in use.",
655
+
"Counter": "0,1,2,3",
743
656
"EventCode": "0xA2",
744
657
"EventName": "RESOURCE_STALLS.LB_SB",
745
658
"SampleAfterValue": "2000003",
···
748
659
},
749
660
{
750
661
"BriefDescription": "Resource stalls due to memory buffers or Reservation Station (RS) being fully utilized.",
662
+
"Counter": "0,1,2,3",
751
663
"EventCode": "0xA2",
752
664
"EventName": "RESOURCE_STALLS.MEM_RS",
753
665
"SampleAfterValue": "2000003",
···
756
666
},
757
667
{
758
668
"BriefDescription": "Resource stalls due to Rob being full, FCSW, MXCSR and OTHER.",
669
+
"Counter": "0,1,2,3",
759
670
"EventCode": "0xA2",
760
671
"EventName": "RESOURCE_STALLS.OOO_RSRC",
761
672
"SampleAfterValue": "2000003",
···
764
673
},
765
674
{
766
675
"BriefDescription": "Cycles stalled due to re-order buffer full.",
676
+
"Counter": "0,1,2,3",
767
677
"EventCode": "0xA2",
768
678
"EventName": "RESOURCE_STALLS.ROB",
769
679
"SampleAfterValue": "2000003",
···
772
680
},
773
681
{
774
682
"BriefDescription": "Cycles stalled due to no eligible RS entry available.",
683
+
"Counter": "0,1,2,3",
775
684
"EventCode": "0xA2",
776
685
"EventName": "RESOURCE_STALLS.RS",
777
686
"SampleAfterValue": "2000003",
···
780
687
},
781
688
{
782
689
"BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",
690
+
"Counter": "0,1,2,3",
783
691
"EventCode": "0xA2",
784
692
"EventName": "RESOURCE_STALLS.SB",
785
693
"SampleAfterValue": "2000003",
···
788
694
},
789
695
{
790
696
"BriefDescription": "Cycles with either free list is empty.",
697
+
"Counter": "0,1,2,3",
791
698
"EventCode": "0x5B",
792
699
"EventName": "RESOURCE_STALLS2.ALL_FL_EMPTY",
793
700
"SampleAfterValue": "2000003",
···
796
701
},
797
702
{
798
703
"BriefDescription": "Resource stalls2 control structures full for physical registers.",
704
+
"Counter": "0,1,2,3",
799
705
"EventCode": "0x5B",
800
706
"EventName": "RESOURCE_STALLS2.ALL_PRF_CONTROL",
801
707
"SampleAfterValue": "2000003",
···
804
708
},
805
709
{
806
710
"BriefDescription": "Cycles when Allocator is stalled if BOB is full and new branch needs it.",
711
+
"Counter": "0,1,2,3",
807
712
"EventCode": "0x5B",
808
713
"EventName": "RESOURCE_STALLS2.BOB_FULL",
809
714
"SampleAfterValue": "2000003",
···
812
715
},
813
716
{
814
717
"BriefDescription": "Resource stalls out of order resources full.",
718
+
"Counter": "0,1,2,3",
815
719
"EventCode": "0x5B",
816
720
"EventName": "RESOURCE_STALLS2.OOO_RSRC",
817
721
"SampleAfterValue": "2000003",
···
820
722
},
821
723
{
822
724
"BriefDescription": "Count cases of saving new LBR.",
725
+
"Counter": "0,1,2,3",
823
726
"EventCode": "0xCC",
824
727
"EventName": "ROB_MISC_EVENTS.LBR_INSERTS",
825
728
"SampleAfterValue": "2000003",
···
828
729
},
829
730
{
830
731
"BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread.",
732
+
"Counter": "0,1,2,3",
831
733
"EventCode": "0x5E",
832
734
"EventName": "RS_EVENTS.EMPTY_CYCLES",
833
735
"SampleAfterValue": "2000003",
···
836
736
},
837
737
{
838
738
"BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",
739
+
"Counter": "0,1,2,3",
839
740
"CounterMask": "1",
840
741
"EdgeDetect": "1",
841
742
"EventCode": "0x5E",
···
847
746
},
848
747
{
849
748
"BriefDescription": "Uops dispatched from any thread.",
749
+
"Counter": "0,1,2,3",
850
750
"EventCode": "0xB1",
851
751
"EventName": "UOPS_DISPATCHED.CORE",
852
752
"SampleAfterValue": "2000003",
···
855
753
},
856
754
{
857
755
"BriefDescription": "Uops dispatched per thread.",
756
+
"Counter": "0,1,2,3",
858
757
"EventCode": "0xB1",
859
758
"EventName": "UOPS_DISPATCHED.THREAD",
860
759
"SampleAfterValue": "2000003",
···
863
760
},
864
761
{
865
762
"BriefDescription": "Cycles per thread when uops are dispatched to port 0.",
763
+
"Counter": "0,1,2,3",
866
764
"EventCode": "0xA1",
867
765
"EventName": "UOPS_DISPATCHED_PORT.PORT_0",
868
766
"SampleAfterValue": "2000003",
···
872
768
{
873
769
"AnyThread": "1",
874
770
"BriefDescription": "Cycles per core when uops are dispatched to port 0.",
771
+
"Counter": "0,1,2,3",
875
772
"EventCode": "0xA1",
876
773
"EventName": "UOPS_DISPATCHED_PORT.PORT_0_CORE",
877
774
"SampleAfterValue": "2000003",
···
880
775
},
881
776
{
882
777
"BriefDescription": "Cycles per thread when uops are dispatched to port 1.",
778
+
"Counter": "0,1,2,3",
883
779
"EventCode": "0xA1",
884
780
"EventName": "UOPS_DISPATCHED_PORT.PORT_1",
885
781
"SampleAfterValue": "2000003",
···
889
783
{
890
784
"AnyThread": "1",
891
785
"BriefDescription": "Cycles per core when uops are dispatched to port 1.",
786
+
"Counter": "0,1,2,3",
892
787
"EventCode": "0xA1",
893
788
"EventName": "UOPS_DISPATCHED_PORT.PORT_1_CORE",
894
789
"SampleAfterValue": "2000003",
···
897
790
},
898
791
{
899
792
"BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 2.",
793
+
"Counter": "0,1,2,3",
900
794
"EventCode": "0xA1",
901
795
"EventName": "UOPS_DISPATCHED_PORT.PORT_2",
902
796
"SampleAfterValue": "2000003",
···
906
798
{
907
799
"AnyThread": "1",
908
800
"BriefDescription": "Cycles per core when load or STA uops are dispatched to port 2.",
801
+
"Counter": "0,1,2,3",
909
802
"EventCode": "0xA1",
910
803
"EventName": "UOPS_DISPATCHED_PORT.PORT_2_CORE",
911
804
"SampleAfterValue": "2000003",
···
914
805
},
915
806
{
916
807
"BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 3.",
808
+
"Counter": "0,1,2,3",
917
809
"EventCode": "0xA1",
918
810
"EventName": "UOPS_DISPATCHED_PORT.PORT_3",
919
811
"SampleAfterValue": "2000003",
···
923
813
{
924
814
"AnyThread": "1",
925
815
"BriefDescription": "Cycles per core when load or STA uops are dispatched to port 3.",
816
+
"Counter": "0,1,2,3",
926
817
"EventCode": "0xA1",
927
818
"EventName": "UOPS_DISPATCHED_PORT.PORT_3_CORE",
928
819
"SampleAfterValue": "2000003",
···
931
820
},
932
821
{
933
822
"BriefDescription": "Cycles per thread when uops are dispatched to port 4.",
823
+
"Counter": "0,1,2,3",
934
824
"EventCode": "0xA1",
935
825
"EventName": "UOPS_DISPATCHED_PORT.PORT_4",
936
826
"SampleAfterValue": "2000003",
···
940
828
{
941
829
"AnyThread": "1",
942
830
"BriefDescription": "Cycles per core when uops are dispatched to port 4.",
831
+
"Counter": "0,1,2,3",
943
832
"EventCode": "0xA1",
944
833
"EventName": "UOPS_DISPATCHED_PORT.PORT_4_CORE",
945
834
"SampleAfterValue": "2000003",
···
948
835
},
949
836
{
950
837
"BriefDescription": "Cycles per thread when uops are dispatched to port 5.",
838
+
"Counter": "0,1,2,3",
951
839
"EventCode": "0xA1",
952
840
"EventName": "UOPS_DISPATCHED_PORT.PORT_5",
953
841
"SampleAfterValue": "2000003",
···
957
843
{
958
844
"AnyThread": "1",
959
845
"BriefDescription": "Cycles per core when uops are dispatched to port 5.",
846
+
"Counter": "0,1,2,3",
960
847
"EventCode": "0xA1",
961
848
"EventName": "UOPS_DISPATCHED_PORT.PORT_5_CORE",
962
849
"SampleAfterValue": "2000003",
···
965
850
},
966
851
{
967
852
"BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
853
+
"Counter": "0,1,2,3",
968
854
"CounterMask": "1",
969
855
"EventCode": "0xB1",
970
856
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",
···
974
858
},
975
859
{
976
860
"BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
861
+
"Counter": "0,1,2,3",
977
862
"CounterMask": "2",
978
863
"EventCode": "0xB1",
979
864
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",
···
983
866
},
984
867
{
985
868
"BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
869
+
"Counter": "0,1,2,3",
986
870
"CounterMask": "3",
987
871
"EventCode": "0xB1",
988
872
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3",
···
992
874
},
993
875
{
994
876
"BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
877
+
"Counter": "0,1,2,3",
995
878
"CounterMask": "4",
996
879
"EventCode": "0xB1",
997
880
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",
···
1001
882
},
1002
883
{
1003
884
"BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.",
885
+
"Counter": "0,1,2,3",
1004
886
"EventCode": "0xB1",
1005
887
"EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE",
1006
888
"Invert": "1",
···
1010
890
},
1011
891
{
1012
892
"BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS).",
893
+
"Counter": "0,1,2,3",
1013
894
"EventCode": "0x0E",
1014
895
"EventName": "UOPS_ISSUED.ANY",
1015
896
"PublicDescription": "This event counts the number of Uops issued by the front-end of the pipeilne to the back-end.",
···
1020
899
{
1021
900
"AnyThread": "1",
1022
901
"BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads.",
902
+
"Counter": "0,1,2,3",
1023
903
"CounterMask": "1",
1024
904
"EventCode": "0x0E",
1025
905
"EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",
···
1030
908
},
1031
909
{
1032
910
"BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread.",
911
+
"Counter": "0,1,2,3",
1033
912
"CounterMask": "1",
1034
913
"EventCode": "0x0E",
1035
914
"EventName": "UOPS_ISSUED.STALL_CYCLES",
···
1040
917
},
1041
918
{
1042
919
"BriefDescription": "Actually retired uops. (Precise Event - PEBS).",
920
+
"Counter": "0,1,2,3",
1043
921
"EventCode": "0xC2",
1044
922
"EventName": "UOPS_RETIRED.ALL",
1045
923
"PEBS": "1",
···
1050
926
},
1051
927
{
1052
928
"BriefDescription": "Cycles without actually retired uops.",
929
+
"Counter": "0,1,2,3",
1053
930
"CounterMask": "1",
1054
931
"EventCode": "0xC2",
1055
932
"EventName": "UOPS_RETIRED.CORE_STALL_CYCLES",
···
1060
935
},
1061
936
{
1062
937
"BriefDescription": "Retirement slots used. (Precise Event - PEBS).",
938
+
"Counter": "0,1,2,3",
1063
939
"EventCode": "0xC2",
1064
940
"EventName": "UOPS_RETIRED.RETIRE_SLOTS",
1065
941
"PEBS": "1",
···
1070
944
},
1071
945
{
1072
946
"BriefDescription": "Cycles without actually retired uops.",
947
+
"Counter": "0,1,2,3",
1073
948
"CounterMask": "1",
1074
949
"EventCode": "0xC2",
1075
950
"EventName": "UOPS_RETIRED.STALL_CYCLES",
···
1080
953
},
1081
954
{
1082
955
"BriefDescription": "Cycles with less than 10 actually retired uops.",
956
+
"Counter": "0,1,2,3",
1083
957
"CounterMask": "10",
1084
958
"EventCode": "0xC2",
1085
959
"EventName": "UOPS_RETIRED.TOTAL_CYCLES",
+12
-12
tools/perf/pmu-events/arch/x86/sandybridge/snb-metrics.json
+12
-12
tools/perf/pmu-events/arch/x86/sandybridge/snb-metrics.json
···
73
73
"BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend",
74
74
"MetricConstraint": "NO_GROUP_EVENTS_NMI",
75
75
"MetricExpr": "1 - (tma_frontend_bound + tma_bad_speculation + tma_retiring)",
76
-
"MetricGroup": "TmaL1;TopdownL1;tma_L1_group",
76
+
"MetricGroup": "BvOB;TmaL1;TopdownL1;tma_L1_group",
77
77
"MetricName": "tma_backend_bound",
78
78
"MetricThreshold": "tma_backend_bound > 0.2",
79
79
"MetricgroupNoGroup": "TopdownL1",
···
94
94
"BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction",
95
95
"MetricConstraint": "NO_GROUP_EVENTS",
96
96
"MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation",
97
-
"MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM",
97
+
"MetricGroup": "BadSpec;BrMispredicts;BvMP;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM",
98
98
"MetricName": "tma_branch_mispredicts",
99
99
"MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15",
100
100
"MetricgroupNoGroup": "TopdownL2",
···
124
124
{
125
125
"BriefDescription": "This metric represents fraction of cycles where the Divider unit was active",
126
126
"MetricExpr": "ARITH.FPU_DIV_ACTIVE / tma_info_core_core_clks",
127
-
"MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group",
127
+
"MetricGroup": "BvCB;TopdownL3;tma_L3_group;tma_core_bound_group",
128
128
"MetricName": "tma_divider",
129
129
"MetricThreshold": "tma_divider > 0.2 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)",
130
130
"PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_UOPS",
···
152
152
{
153
153
"BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses",
154
154
"MetricExpr": "(7 * DTLB_LOAD_MISSES.STLB_HIT + DTLB_LOAD_MISSES.WALK_DURATION) / tma_info_thread_clks",
155
-
"MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_l1_bound_group",
155
+
"MetricGroup": "BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_l1_bound_group",
156
156
"MetricName": "tma_dtlb_load",
157
157
"MetricThreshold": "tma_dtlb_load > 0.1",
158
158
"PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_UOPS_RETIRED.STLB_MISS_LOADS_PS. Related metrics: tma_dtlb_store",
···
226
226
{
227
227
"BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend",
228
228
"MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / tma_info_thread_slots",
229
-
"MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group",
229
+
"MetricGroup": "BvFB;BvIO;PGO;TmaL1;TopdownL1;tma_L1_group",
230
230
"MetricName": "tma_frontend_bound",
231
231
"MetricThreshold": "tma_frontend_bound > 0.15",
232
232
"MetricgroupNoGroup": "TopdownL1",
···
296
296
},
297
297
{
298
298
"BriefDescription": "Average CPU Utilization (percentage)",
299
-
"MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC",
299
+
"MetricExpr": "tma_info_system_cpus_utilized / #num_cpus_online",
300
300
"MetricGroup": "HPC;Summary",
301
301
"MetricName": "tma_info_system_cpu_utilization"
302
302
},
303
303
{
304
304
"BriefDescription": "Average number of utilized CPUs",
305
-
"MetricExpr": "#num_cpus_online * tma_info_system_cpu_utilization",
305
+
"MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC",
306
306
"MetricGroup": "Summary",
307
307
"MetricName": "tma_info_system_cpus_utilized"
308
308
},
···
399
399
{
400
400
"BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses",
401
401
"MetricExpr": "(12 * ITLB_MISSES.STLB_HIT + ITLB_MISSES.WALK_DURATION) / tma_info_thread_clks",
402
-
"MetricGroup": "BigFootprint;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group",
402
+
"MetricGroup": "BigFootprint;BvBC;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group",
403
403
"MetricName": "tma_itlb_misses",
404
404
"MetricThreshold": "tma_itlb_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)",
405
405
"PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: ITLB_MISSES.WALK_COMPLETED",
···
438
438
"BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears",
439
439
"MetricConstraint": "NO_GROUP_EVENTS",
440
440
"MetricExpr": "tma_bad_speculation - tma_branch_mispredicts",
441
-
"MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn",
441
+
"MetricGroup": "BadSpec;BvMS;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn",
442
442
"MetricName": "tma_machine_clears",
443
443
"MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation > 0.15",
444
444
"MetricgroupNoGroup": "TopdownL2",
···
448
448
{
449
449
"BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM)",
450
450
"MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=6@) / tma_info_thread_clks",
451
-
"MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueBW",
451
+
"MetricGroup": "BvMS;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueBW",
452
452
"MetricName": "tma_mem_bandwidth",
453
453
"MetricThreshold": "tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))",
454
454
"PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that). Related metrics: tma_info_system_dram_bw_use",
···
457
457
{
458
458
"BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM)",
459
459
"MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / tma_info_thread_clks - tma_mem_bandwidth",
460
-
"MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueLat",
460
+
"MetricGroup": "BvML;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueLat",
461
461
"MetricName": "tma_mem_latency",
462
462
"MetricThreshold": "tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))",
463
463
"PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that). Related metrics: ",
···
505
505
{
506
506
"BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired",
507
507
"MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / tma_info_thread_slots",
508
-
"MetricGroup": "TmaL1;TopdownL1;tma_L1_group",
508
+
"MetricGroup": "BvUW;TmaL1;TopdownL1;tma_L1_group",
509
509
"MetricName": "tma_retiring",
510
510
"MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.1",
511
511
"MetricgroupNoGroup": "TopdownL1",
+25
tools/perf/pmu-events/arch/x86/sandybridge/uncore-cache.json
+25
tools/perf/pmu-events/arch/x86/sandybridge/uncore-cache.json
···
1
1
[
2
2
{
3
3
"BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state.",
4
+
"Counter": "0,1",
4
5
"EventCode": "0x34",
5
6
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_ES",
6
7
"PerPkg": "1",
···
10
9
},
11
10
{
12
11
"BriefDescription": "L3 Lookup any request that access cache and found line in I-state.",
12
+
"Counter": "0,1",
13
13
"EventCode": "0x34",
14
14
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_I",
15
15
"PerPkg": "1",
···
19
17
},
20
18
{
21
19
"BriefDescription": "L3 Lookup any request that access cache and found line in M-state.",
20
+
"Counter": "0,1",
22
21
"EventCode": "0x34",
23
22
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_M",
24
23
"PerPkg": "1",
···
28
25
},
29
26
{
30
27
"BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state.",
28
+
"Counter": "0,1",
31
29
"EventCode": "0x34",
32
30
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_MESI",
33
31
"PerPkg": "1",
···
37
33
},
38
34
{
39
35
"BriefDescription": "L3 Lookup external snoop request that access cache and found line in E or S-state.",
36
+
"Counter": "0,1",
40
37
"EventCode": "0x34",
41
38
"EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_ES",
42
39
"PerPkg": "1",
···
46
41
},
47
42
{
48
43
"BriefDescription": "L3 Lookup external snoop request that access cache and found line in I-state.",
44
+
"Counter": "0,1",
49
45
"EventCode": "0x34",
50
46
"EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_I",
51
47
"PerPkg": "1",
···
55
49
},
56
50
{
57
51
"BriefDescription": "L3 Lookup external snoop request that access cache and found line in M-state.",
52
+
"Counter": "0,1",
58
53
"EventCode": "0x34",
59
54
"EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_M",
60
55
"PerPkg": "1",
···
64
57
},
65
58
{
66
59
"BriefDescription": "L3 Lookup external snoop request that access cache and found line in MESI-state.",
60
+
"Counter": "0,1",
67
61
"EventCode": "0x34",
68
62
"EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_MESI",
69
63
"PerPkg": "1",
···
73
65
},
74
66
{
75
67
"BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state.",
68
+
"Counter": "0,1",
76
69
"EventCode": "0x34",
77
70
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_ES",
78
71
"PerPkg": "1",
···
82
73
},
83
74
{
84
75
"BriefDescription": "L3 Lookup read request that access cache and found line in I-state.",
76
+
"Counter": "0,1",
85
77
"EventCode": "0x34",
86
78
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_I",
87
79
"PerPkg": "1",
···
91
81
},
92
82
{
93
83
"BriefDescription": "L3 Lookup read request that access cache and found line in M-state.",
84
+
"Counter": "0,1",
94
85
"EventCode": "0x34",
95
86
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_M",
96
87
"PerPkg": "1",
···
100
89
},
101
90
{
102
91
"BriefDescription": "L3 Lookup read request that access cache and found line in any MESI-state.",
92
+
"Counter": "0,1",
103
93
"EventCode": "0x34",
104
94
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_MESI",
105
95
"PerPkg": "1",
···
109
97
},
110
98
{
111
99
"BriefDescription": "L3 Lookup write request that access cache and found line in E or S-state.",
100
+
"Counter": "0,1",
112
101
"EventCode": "0x34",
113
102
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_ES",
114
103
"PerPkg": "1",
···
118
105
},
119
106
{
120
107
"BriefDescription": "L3 Lookup write request that access cache and found line in I-state.",
108
+
"Counter": "0,1",
121
109
"EventCode": "0x34",
122
110
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_I",
123
111
"PerPkg": "1",
···
127
113
},
128
114
{
129
115
"BriefDescription": "L3 Lookup write request that access cache and found line in M-state.",
116
+
"Counter": "0,1",
130
117
"EventCode": "0x34",
131
118
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_M",
132
119
"PerPkg": "1",
···
136
121
},
137
122
{
138
123
"BriefDescription": "L3 Lookup write request that access cache and found line in MESI-state.",
124
+
"Counter": "0,1",
139
125
"EventCode": "0x34",
140
126
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_MESI",
141
127
"PerPkg": "1",
···
145
129
},
146
130
{
147
131
"BriefDescription": "A cross-core snoop resulted from L3 Eviction which hits a modified line in some processor core.",
132
+
"Counter": "0,1",
148
133
"EventCode": "0x22",
149
134
"EventName": "UNC_CBO_XSNP_RESPONSE.HITM_EVICTION",
150
135
"PerPkg": "1",
···
154
137
},
155
138
{
156
139
"BriefDescription": "An external snoop hits a modified line in some processor core.",
140
+
"Counter": "0,1",
157
141
"EventCode": "0x22",
158
142
"EventName": "UNC_CBO_XSNP_RESPONSE.HITM_EXTERNAL",
159
143
"PerPkg": "1",
···
163
145
},
164
146
{
165
147
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.",
148
+
"Counter": "0,1",
166
149
"EventCode": "0x22",
167
150
"EventName": "UNC_CBO_XSNP_RESPONSE.HITM_XCORE",
168
151
"PerPkg": "1",
···
172
153
},
173
154
{
174
155
"BriefDescription": "A cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor core.",
156
+
"Counter": "0,1",
175
157
"EventCode": "0x22",
176
158
"EventName": "UNC_CBO_XSNP_RESPONSE.HIT_EVICTION",
177
159
"PerPkg": "1",
···
181
161
},
182
162
{
183
163
"BriefDescription": "An external snoop hits a non-modified line in some processor core.",
164
+
"Counter": "0,1",
184
165
"EventCode": "0x22",
185
166
"EventName": "UNC_CBO_XSNP_RESPONSE.HIT_EXTERNAL",
186
167
"PerPkg": "1",
···
190
169
},
191
170
{
192
171
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.",
172
+
"Counter": "0,1",
193
173
"EventCode": "0x22",
194
174
"EventName": "UNC_CBO_XSNP_RESPONSE.HIT_XCORE",
195
175
"PerPkg": "1",
···
199
177
},
200
178
{
201
179
"BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
180
+
"Counter": "0,1",
202
181
"EventCode": "0x22",
203
182
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION",
204
183
"PerPkg": "1",
···
208
185
},
209
186
{
210
187
"BriefDescription": "An external snoop misses in some processor core.",
188
+
"Counter": "0,1",
211
189
"EventCode": "0x22",
212
190
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EXTERNAL",
213
191
"PerPkg": "1",
···
217
193
},
218
194
{
219
195
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.",
196
+
"Counter": "0,1",
220
197
"EventCode": "0x22",
221
198
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS_XCORE",
222
199
"PerPkg": "1",
+9
tools/perf/pmu-events/arch/x86/sandybridge/uncore-interconnect.json
+9
tools/perf/pmu-events/arch/x86/sandybridge/uncore-interconnect.json
···
1
1
[
2
2
{
3
3
"BriefDescription": "Cycles weighted by number of requests pending in Coherency Tracker.",
4
+
"Counter": "0",
4
5
"EventCode": "0x83",
5
6
"EventName": "UNC_ARB_COH_TRK_OCCUPANCY.ALL",
6
7
"PerPkg": "1",
···
10
9
},
11
10
{
12
11
"BriefDescription": "Number of requests allocated in Coherency Tracker.",
12
+
"Counter": "0,1",
13
13
"EventCode": "0x84",
14
14
"EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
15
15
"PerPkg": "1",
···
19
17
},
20
18
{
21
19
"BriefDescription": "Counts cycles weighted by the number of requests waiting for data returning from the memory controller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic units, or LLC.",
20
+
"Counter": "0",
22
21
"EventCode": "0x80",
23
22
"EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
24
23
"PerPkg": "1",
···
28
25
},
29
26
{
30
27
"BriefDescription": "Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
28
+
"Counter": "0,1",
31
29
"CounterMask": "10",
32
30
"EventCode": "0x80",
33
31
"EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_OVER_HALF_FULL",
···
38
34
},
39
35
{
40
36
"BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
37
+
"Counter": "0,1",
41
38
"CounterMask": "1",
42
39
"EventCode": "0x80",
43
40
"EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST",
···
48
43
},
49
44
{
50
45
"BriefDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.",
46
+
"Counter": "0,1",
51
47
"EventCode": "0x81",
52
48
"EventName": "UNC_ARB_TRK_REQUESTS.ALL",
53
49
"PerPkg": "1",
···
57
51
},
58
52
{
59
53
"BriefDescription": "Counts the number of LLC evictions allocated.",
54
+
"Counter": "0,1",
60
55
"EventCode": "0x81",
61
56
"EventName": "UNC_ARB_TRK_REQUESTS.EVICTIONS",
62
57
"PerPkg": "1",
···
66
59
},
67
60
{
68
61
"BriefDescription": "Counts the number of allocated write entries, include full, partial, and LLC evictions.",
62
+
"Counter": "0,1",
69
63
"EventCode": "0x81",
70
64
"EventName": "UNC_ARB_TRK_REQUESTS.WRITES",
71
65
"PerPkg": "1",
···
75
67
},
76
68
{
77
69
"BriefDescription": "This 48-bit fixed counter counts the UCLK cycles.",
70
+
"Counter": "Fixed",
78
71
"EventCode": "0xff",
79
72
"EventName": "UNC_CLOCK.SOCKET",
80
73
"PerPkg": "1",
+16
tools/perf/pmu-events/arch/x86/sandybridge/virtual-memory.json
+16
tools/perf/pmu-events/arch/x86/sandybridge/virtual-memory.json
···
1
1
[
2
2
{
3
3
"BriefDescription": "Load misses in all DTLB levels that cause page walks.",
4
+
"Counter": "0,1,2,3",
4
5
"EventCode": "0x08",
5
6
"EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
6
7
"SampleAfterValue": "100003",
···
9
8
},
10
9
{
11
10
"BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks.",
11
+
"Counter": "0,1,2,3",
12
12
"EventCode": "0x08",
13
13
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
14
14
"PublicDescription": "This event counts load operations that miss the first DTLB level but hit the second and do not cause any page walks. The penalty in this case is approximately 7 cycles.",
···
18
16
},
19
17
{
20
18
"BriefDescription": "Load misses at all DTLB levels that cause completed page walks.",
19
+
"Counter": "0,1,2,3",
21
20
"EventCode": "0x08",
22
21
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
23
22
"SampleAfterValue": "100003",
···
26
23
},
27
24
{
28
25
"BriefDescription": "Cycles when PMH is busy with page walks.",
26
+
"Counter": "0,1,2,3",
29
27
"EventCode": "0x08",
30
28
"EventName": "DTLB_LOAD_MISSES.WALK_DURATION",
31
29
"PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses.",
···
35
31
},
36
32
{
37
33
"BriefDescription": "Store misses in all DTLB levels that cause page walks.",
34
+
"Counter": "0,1,2,3",
38
35
"EventCode": "0x49",
39
36
"EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
40
37
"SampleAfterValue": "100003",
···
43
38
},
44
39
{
45
40
"BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
41
+
"Counter": "0,1,2,3",
46
42
"EventCode": "0x49",
47
43
"EventName": "DTLB_STORE_MISSES.STLB_HIT",
48
44
"SampleAfterValue": "100003",
···
51
45
},
52
46
{
53
47
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks.",
48
+
"Counter": "0,1,2,3",
54
49
"EventCode": "0x49",
55
50
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
56
51
"SampleAfterValue": "100003",
···
59
52
},
60
53
{
61
54
"BriefDescription": "Cycles when PMH is busy with page walks.",
55
+
"Counter": "0,1,2,3",
62
56
"EventCode": "0x49",
63
57
"EventName": "DTLB_STORE_MISSES.WALK_DURATION",
64
58
"SampleAfterValue": "2000003",
···
67
59
},
68
60
{
69
61
"BriefDescription": "Cycle count for an Extended Page table walk. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.",
62
+
"Counter": "0,1,2,3",
70
63
"EventCode": "0x4F",
71
64
"EventName": "EPT.WALK_CYCLES",
72
65
"SampleAfterValue": "2000003",
···
75
66
},
76
67
{
77
68
"BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
69
+
"Counter": "0,1,2,3",
78
70
"EventCode": "0xAE",
79
71
"EventName": "ITLB.ITLB_FLUSH",
80
72
"SampleAfterValue": "100007",
···
83
73
},
84
74
{
85
75
"BriefDescription": "Misses at all ITLB levels that cause page walks.",
76
+
"Counter": "0,1,2,3",
86
77
"EventCode": "0x85",
87
78
"EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
88
79
"SampleAfterValue": "100003",
···
91
80
},
92
81
{
93
82
"BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.",
83
+
"Counter": "0,1,2,3",
94
84
"EventCode": "0x85",
95
85
"EventName": "ITLB_MISSES.STLB_HIT",
96
86
"SampleAfterValue": "100003",
···
99
87
},
100
88
{
101
89
"BriefDescription": "Misses in all ITLB levels that cause completed page walks.",
90
+
"Counter": "0,1,2,3",
102
91
"EventCode": "0x85",
103
92
"EventName": "ITLB_MISSES.WALK_COMPLETED",
104
93
"SampleAfterValue": "100003",
···
107
94
},
108
95
{
109
96
"BriefDescription": "Cycles when PMH is busy with page walks.",
97
+
"Counter": "0,1,2,3",
110
98
"EventCode": "0x85",
111
99
"EventName": "ITLB_MISSES.WALK_DURATION",
112
100
"PublicDescription": "This event count cycles when Page Miss Handler (PMH) is servicing page walks caused by ITLB misses.",
···
116
102
},
117
103
{
118
104
"BriefDescription": "DTLB flush attempts of the thread-specific entries.",
105
+
"Counter": "0,1,2,3",
119
106
"EventCode": "0xBD",
120
107
"EventName": "TLB_FLUSH.DTLB_THREAD",
121
108
"SampleAfterValue": "100007",
···
124
109
},
125
110
{
126
111
"BriefDescription": "STLB flush attempts.",
112
+
"Counter": "0,1,2,3",
127
113
"EventCode": "0xBD",
128
114
"EventName": "TLB_FLUSH.STLB_ANY",
129
115
"SampleAfterValue": "100007",