Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'tty-6.8-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty
Pull tty and serial driver fixes from Greg KH:
"Here are some small tty and serial driver fixes for 6.8-rc3 that
resolve a number of reported issues. Included in here are:
- rs485 flag definition fix that affected the user/kernel abi in -rc1
- max310x driver fixes
- 8250_pci1xxxx driver off-by-one fix
- uart_tiocmget locking race fix
All of these have been in linux-next for over a week with no reported
issues"
* tag 'tty-6.8-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty:
serial: max310x: prevent infinite while() loop in port startup
serial: max310x: fail probe if clock crystal is unstable
serial: max310x: improve crystal stable clock detection
serial: max310x: set default value when reading clock ready bit
serial: core: Fix atomicity violation in uart_tiocmget
serial: 8250_pci1xxxx: fix off by one in pci1xxxx_process_read_data()
tty: serial: Fix bit order in RS485 flag definitions
+53
-19
+2
-2
drivers/tty/serial/8250/8250_pci1xxxx.c
+2
-2
drivers/tty/serial/8250/8250_pci1xxxx.c
···
302
302
* to read, the data is received one byte at a time.
303
303
*/
304
304
while (valid_burst_count--) {
305
-
if (*buff_index > (RX_BUF_SIZE - UART_BURST_SIZE))
305
+
if (*buff_index >= (RX_BUF_SIZE - UART_BURST_SIZE))
306
306
break;
307
307
burst_buf = (u32 *)&rx_buff[*buff_index];
308
308
*burst_buf = readl(port->membase + UART_RX_BURST_FIFO);
···
311
311
}
312
312
313
313
while (*valid_byte_count) {
314
-
if (*buff_index > RX_BUF_SIZE)
314
+
if (*buff_index >= RX_BUF_SIZE)
315
315
break;
316
316
rx_buff[*buff_index] = readb(port->membase +
317
317
UART_RX_BYTE_FIFO);
+43
-10
drivers/tty/serial/max310x.c
+43
-10
drivers/tty/serial/max310x.c
···
237
237
#define MAX310x_REV_MASK (0xf8)
238
238
#define MAX310X_WRITE_BIT 0x80
239
239
240
+
/* Port startup definitions */
241
+
#define MAX310X_PORT_STARTUP_WAIT_RETRIES 20 /* Number of retries */
242
+
#define MAX310X_PORT_STARTUP_WAIT_DELAY_MS 10 /* Delay between retries */
243
+
244
+
/* Crystal-related definitions */
245
+
#define MAX310X_XTAL_WAIT_RETRIES 20 /* Number of retries */
246
+
#define MAX310X_XTAL_WAIT_DELAY_MS 10 /* Delay between retries */
247
+
240
248
/* MAX3107 specific */
241
249
#define MAX3107_REV_ID (0xa0)
242
250
···
591
583
return 1;
592
584
}
593
585
594
-
static u32 max310x_set_ref_clk(struct device *dev, struct max310x_port *s,
586
+
static s32 max310x_set_ref_clk(struct device *dev, struct max310x_port *s,
595
587
unsigned long freq, bool xtal)
596
588
{
597
589
unsigned int div, clksrc, pllcfg = 0;
···
649
641
650
642
/* Wait for crystal */
651
643
if (xtal) {
652
-
unsigned int val;
653
-
msleep(10);
654
-
regmap_read(s->regmap, MAX310X_STS_IRQSTS_REG, &val);
655
-
if (!(val & MAX310X_STS_CLKREADY_BIT)) {
656
-
dev_warn(dev, "clock is not stable yet\n");
657
-
}
644
+
bool stable = false;
645
+
unsigned int try = 0, val = 0;
646
+
647
+
do {
648
+
msleep(MAX310X_XTAL_WAIT_DELAY_MS);
649
+
regmap_read(s->regmap, MAX310X_STS_IRQSTS_REG, &val);
650
+
651
+
if (val & MAX310X_STS_CLKREADY_BIT)
652
+
stable = true;
653
+
} while (!stable && (++try < MAX310X_XTAL_WAIT_RETRIES));
654
+
655
+
if (!stable)
656
+
return dev_err_probe(dev, -EAGAIN,
657
+
"clock is not stable\n");
658
658
}
659
659
660
660
return bestfreq;
···
1287
1271
{
1288
1272
int i, ret, fmin, fmax, freq;
1289
1273
struct max310x_port *s;
1290
-
u32 uartclk = 0;
1274
+
s32 uartclk = 0;
1291
1275
bool xtal;
1292
1276
1293
1277
for (i = 0; i < devtype->nr; i++)
···
1350
1334
goto out_clk;
1351
1335
1352
1336
for (i = 0; i < devtype->nr; i++) {
1337
+
bool started = false;
1338
+
unsigned int try = 0, val = 0;
1339
+
1353
1340
/* Reset port */
1354
1341
regmap_write(regmaps[i], MAX310X_MODE2_REG,
1355
1342
MAX310X_MODE2_RST_BIT);
···
1361
1342
1362
1343
/* Wait for port startup */
1363
1344
do {
1364
-
regmap_read(regmaps[i], MAX310X_BRGDIVLSB_REG, &ret);
1365
-
} while (ret != 0x01);
1345
+
msleep(MAX310X_PORT_STARTUP_WAIT_DELAY_MS);
1346
+
regmap_read(regmaps[i], MAX310X_BRGDIVLSB_REG, &val);
1347
+
1348
+
if (val == 0x01)
1349
+
started = true;
1350
+
} while (!started && (++try < MAX310X_PORT_STARTUP_WAIT_RETRIES));
1351
+
1352
+
if (!started) {
1353
+
ret = dev_err_probe(dev, -EAGAIN, "port reset failed\n");
1354
+
goto out_uart;
1355
+
}
1366
1356
1367
1357
regmap_write(regmaps[i], MAX310X_MODE1_REG, devtype->mode1);
1368
1358
}
1369
1359
1370
1360
uartclk = max310x_set_ref_clk(dev, s, freq, xtal);
1361
+
if (uartclk < 0) {
1362
+
ret = uartclk;
1363
+
goto out_uart;
1364
+
}
1365
+
1371
1366
dev_dbg(dev, "Reference clock set to %i Hz\n", uartclk);
1372
1367
1373
1368
for (i = 0; i < devtype->nr; i++) {
+1
-1
drivers/tty/serial/serial_core.c
+1
-1
drivers/tty/serial/serial_core.c
+7
-6
include/uapi/linux/serial.h
+7
-6
include/uapi/linux/serial.h
···
145
145
#define SER_RS485_ENABLED _BITUL(0)
146
146
#define SER_RS485_RTS_ON_SEND _BITUL(1)
147
147
#define SER_RS485_RTS_AFTER_SEND _BITUL(2)
148
-
#define SER_RS485_RX_DURING_TX _BITUL(3)
149
-
#define SER_RS485_TERMINATE_BUS _BITUL(4)
150
-
#define SER_RS485_ADDRB _BITUL(5)
151
-
#define SER_RS485_ADDR_RECV _BITUL(6)
152
-
#define SER_RS485_ADDR_DEST _BITUL(7)
153
-
#define SER_RS485_MODE_RS422 _BITUL(8)
148
+
/* Placeholder for bit 3: SER_RS485_RTS_BEFORE_SEND, which isn't used anymore */
149
+
#define SER_RS485_RX_DURING_TX _BITUL(4)
150
+
#define SER_RS485_TERMINATE_BUS _BITUL(5)
151
+
#define SER_RS485_ADDRB _BITUL(6)
152
+
#define SER_RS485_ADDR_RECV _BITUL(7)
153
+
#define SER_RS485_ADDR_DEST _BITUL(8)
154
+
#define SER_RS485_MODE_RS422 _BITUL(9)
154
155
155
156
__u32 delay_rts_before_send;
156
157
__u32 delay_rts_after_send;