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drm/msm/dpu: drop vbif_idx from WB configuration

All MDP / DPU implementations except for MSM8996 use VBIF_RT (or the
only VBIF) for WB2. Writeback on MSM8996 is not supported (nor planned
to be supported). In order to simplify the driver, drop the field form
the struct dpu_wb_cfg.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/707778/
Link: https://lore.kernel.org/r/20260227-drop-vbif-nrt-v1-5-2b97d0438182@oss.qualcomm.com
[DB: also handled Eliza platform]
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>

Dmitry Baryshkov 021fd8ca b26bfb5b

+4 -24
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
··· 322 322 .format_list = wb2_formats_rgb_yuv, 323 323 .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), 324 324 .xin_id = 6, 325 - .vbif_idx = VBIF_RT, 326 325 .maxlinewidth = 4096, 327 326 .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), 328 327 },
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h
··· 364 364 .format_list = wb2_formats_rgb_yuv, 365 365 .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), 366 366 .xin_id = 6, 367 - .vbif_idx = VBIF_RT, 368 367 .maxlinewidth = 4096, 369 368 .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), 370 369 },
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h
··· 371 371 .format_list = wb2_formats_rgb_yuv, 372 372 .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), 373 373 .xin_id = 6, 374 - .vbif_idx = VBIF_RT, 375 374 .maxlinewidth = 4096, 376 375 .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), 377 376 },
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_4_eliza.h
··· 235 235 .format_list = wb2_formats_rgb_yuv, 236 236 .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), 237 237 .xin_id = 6, 238 - .vbif_idx = VBIF_RT, 239 238 .maxlinewidth = 4096, 240 239 .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), 241 240 },
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h
··· 362 362 .format_list = wb2_formats_rgb_yuv, 363 363 .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), 364 364 .xin_id = 6, 365 - .vbif_idx = VBIF_RT, 366 365 .maxlinewidth = 4096, 367 366 .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), 368 367 },
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
··· 280 280 .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), 281 281 .clk_ctrl = DPU_CLK_CTRL_WB2, 282 282 .xin_id = 6, 283 - .vbif_idx = VBIF_RT, 284 283 .maxlinewidth = 4096, 285 284 .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), 286 285 },
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
··· 286 286 .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), 287 287 .clk_ctrl = DPU_CLK_CTRL_WB2, 288 288 .xin_id = 6, 289 - .vbif_idx = VBIF_RT, 290 289 .maxlinewidth = 4096, 291 290 .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), 292 291 },
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
··· 246 246 .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), 247 247 .clk_ctrl = DPU_CLK_CTRL_WB2, 248 248 .xin_id = 6, 249 - .vbif_idx = VBIF_RT, 250 249 .maxlinewidth = 4096, 251 250 .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), 252 251 },
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
··· 158 158 .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), 159 159 .clk_ctrl = DPU_CLK_CTRL_WB2, 160 160 .xin_id = 6, 161 - .vbif_idx = VBIF_RT, 162 161 .maxlinewidth = 2160, 163 162 .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), 164 163 },
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
··· 137 137 .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), 138 138 .clk_ctrl = DPU_CLK_CTRL_WB2, 139 139 .xin_id = 6, 140 - .vbif_idx = VBIF_RT, 141 140 .maxlinewidth = 2160, 142 141 .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), 143 142 },
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
··· 317 317 .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), 318 318 .clk_ctrl = DPU_CLK_CTRL_WB2, 319 319 .xin_id = 6, 320 - .vbif_idx = VBIF_RT, 321 320 .maxlinewidth = 4096, 322 321 .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), 323 322 },
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
··· 153 153 .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), 154 154 .clk_ctrl = DPU_CLK_CTRL_WB2, 155 155 .xin_id = 6, 156 - .vbif_idx = VBIF_RT, 157 156 .maxlinewidth = 4096, 158 157 .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), 159 158 },
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
··· 147 147 .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), 148 148 .clk_ctrl = DPU_CLK_CTRL_WB2, 149 149 .xin_id = 6, 150 - .vbif_idx = VBIF_RT, 151 150 .maxlinewidth = 1920, 152 151 .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), 153 152 },
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
··· 290 290 .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), 291 291 .clk_ctrl = DPU_CLK_CTRL_WB2, 292 292 .xin_id = 6, 293 - .vbif_idx = VBIF_RT, 294 293 .maxlinewidth = 4096, 295 294 .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), 296 295 },
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
··· 172 172 .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), 173 173 .clk_ctrl = DPU_CLK_CTRL_WB2, 174 174 .xin_id = 6, 175 - .vbif_idx = VBIF_RT, 176 175 .maxlinewidth = 4096, 177 176 .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), 178 177 },
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
··· 303 303 .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), 304 304 .clk_ctrl = DPU_CLK_CTRL_WB2, 305 305 .xin_id = 6, 306 - .vbif_idx = VBIF_RT, 307 306 .maxlinewidth = 4096, 308 307 .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), 309 308 },
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
··· 310 310 .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), 311 311 .clk_ctrl = DPU_CLK_CTRL_WB2, 312 312 .xin_id = 6, 313 - .vbif_idx = VBIF_RT, 314 313 .maxlinewidth = 4096, 315 314 .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), 316 315 },
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
··· 298 298 .format_list = wb2_formats_rgb_yuv, 299 299 .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), 300 300 .xin_id = 6, 301 - .vbif_idx = VBIF_RT, 302 301 .maxlinewidth = 4096, 303 302 .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), 304 303 },
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
··· 298 298 .format_list = wb2_formats_rgb_yuv, 299 299 .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), 300 300 .xin_id = 6, 301 - .vbif_idx = VBIF_RT, 302 301 .maxlinewidth = 4096, 303 302 .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), 304 303 },
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
··· 298 298 .format_list = wb2_formats_rgb_yuv, 299 299 .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), 300 300 .xin_id = 6, 301 - .vbif_idx = VBIF_RT, 302 301 .maxlinewidth = 4096, 303 302 .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), 304 303 },
+4 -2
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
··· 70 70 ot_params.height = phys_enc->cached_mode.vdisplay; 71 71 ot_params.is_wfd = !dpu_encoder_helper_get_cwb_mask(phys_enc); 72 72 ot_params.frame_rate = drm_mode_vrefresh(&phys_enc->cached_mode); 73 - ot_params.vbif_idx = hw_wb->caps->vbif_idx; 73 + /* XXX: WB on MSM8996 should use VBIF_NRT */ 74 + ot_params.vbif_idx = VBIF_RT; 74 75 ot_params.rd = false; 75 76 76 77 if (!_dpu_encoder_phys_wb_clk_force_ctrl(hw_wb, phys_enc->dpu_kms->hw_mdp, ··· 109 108 hw_wb = phys_enc->hw_wb; 110 109 111 110 memset(&qos_params, 0, sizeof(qos_params)); 112 - qos_params.vbif_idx = hw_wb->caps->vbif_idx; 111 + /* XXX: WB on MSM8996 should use VBIF_NRT */ 112 + qos_params.vbif_idx = VBIF_RT; 113 113 qos_params.xin_id = hw_wb->caps->xin_id; 114 114 qos_params.num = hw_wb->idx - WB_0; 115 115 qos_params.is_rt = dpu_encoder_helper_get_cwb_mask(phys_enc);
-2
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
··· 524 524 /** 525 525 * struct dpu_wb_cfg - information of writeback blocks 526 526 * @DPU_HW_BLK_INFO: refer to the description above for DPU_HW_BLK_INFO 527 - * @vbif_idx: vbif client index 528 527 * @maxlinewidth: max line width supported by writeback block 529 528 * @xin_id: bus client identifier 530 529 * @intr_wb_done: interrupt index for WB_DONE ··· 534 535 struct dpu_wb_cfg { 535 536 DPU_HW_BLK_INFO; 536 537 unsigned long features; 537 - u8 vbif_idx; 538 538 u32 maxlinewidth; 539 539 u32 xin_id; 540 540 unsigned int intr_wb_done;