Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'spi-v6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
Pull spi updates from Mark Brown:
"This release is almost entirely driver work, mostly new drivers with
the usual smattering of per driver updates anf fixes, with only
trivial changes in the core. Highlights include:
- Quite a bit of maintainence work on the STM32 and Qualcomm drivers
- Usage of the newly added devm_dma_request_chan() in the ateml
driver, pulling in the relevant dmaengine change
- Cleanups of our usage of the PM autosuspend functions, this pulls
in some PM core changes on a shared tag
- Support for ADI sigma-delta triggers, Amlogic SPISG, Mediatek
MT6991 and MT8196, Renesas RZ/V2H(P) and SOPHGO SG2042"
* tag 'spi-v6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (62 commits)
spi: SPISG: Fix less than zero comparison on a u32 variable
spi: intel: Allow writeable MTD partition with module param
spi: Add driver for the RZ/V2H(P) RSPI IP
spi: dt-bindings: Document the RZ/V2H(P) RSPI
MAINTAINERS: Add an entry for Amlogic spi driver
spi: Add Amlogic SPISG driver
spi: dt-bindings: Add binding document of Amlogic SPISG controller
spi: spi-sg2044-nor: Add SPI-NOR controller for SG2042
spi: spi-sg2044-nor: Add configurable chip_info
spi: dt-bindings: spi-sg2044-nor: Change SOPHGO SG2042
spi: spi-qpic-snand: simplify bad block marker duplication
spi: spidev: Add an entry for the ABB spi sensors
dt-bindings: trivial-devices: Document ABB sensors
spi: stm32-ospi: Fix NULL vs IS_ERR() bug in stm32_ospi_get_resources()
spi: gpio: Use explicit 'unsigned int' for parameter types
spi: dt-bindings: spi-mux: Drop "spi-max-frequency" as required
spi: st: Switch from CONFIG_PM_SLEEP guards to pm_sleep_ptr()
spi: rspi: Convert to DEFINE_SIMPLE_DEV_PM_OPS()
spi: sh-msiof: Convert to DEFINE_SIMPLE_DEV_PM_OPS()
spi: xilinx: Fix block comment style and minor cleanups
...
+2963
-545
+59
Documentation/devicetree/bindings/spi/amlogic,a4-spisg.yaml
+59
Documentation/devicetree/bindings/spi/amlogic,a4-spisg.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
# Copyright (C) 2025 Amlogic, Inc. All rights reserved
3
+
%YAML 1.2
4
+
---
5
+
$id: http://devicetree.org/schemas/spi/amlogic,a4-spisg.yaml#
6
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
7
+
8
+
title: Amlogic SPI Scatter-Gather Controller
9
+
10
+
maintainers:
11
+
- Xianwei Zhao <xianwei.zhao@amlogic.com>
12
+
- Sunny Luo <sunny.luo@amlogic.com>
13
+
14
+
allOf:
15
+
- $ref: spi-controller.yaml#
16
+
17
+
properties:
18
+
compatible:
19
+
const: amlogic,a4-spisg
20
+
21
+
reg:
22
+
maxItems: 1
23
+
24
+
interrupts:
25
+
maxItems: 1
26
+
27
+
clocks:
28
+
maxItems: 2
29
+
30
+
clock-names:
31
+
items:
32
+
- const: core
33
+
- const: pclk
34
+
35
+
resets:
36
+
maxItems: 1
37
+
38
+
required:
39
+
- compatible
40
+
- reg
41
+
- interrupts
42
+
- clocks
43
+
- clock-names
44
+
45
+
unevaluatedProperties: false
46
+
47
+
examples:
48
+
- |
49
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
50
+
spi@50000 {
51
+
compatible = "amlogic,a4-spisg";
52
+
reg = <0x50000 0x38>;
53
+
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
54
+
clocks = <&clkc 37>,
55
+
<&clkc 93>;
56
+
clock-names = "core", "pclk";
57
+
#address-cells = <1>;
58
+
#size-cells = <0>;
59
+
};
+18
Documentation/devicetree/bindings/spi/fsl,dspi.yaml
+18
Documentation/devicetree/bindings/spi/fsl,dspi.yaml
···
23
23
- fsl,ls2080a-dspi
24
24
- fsl,ls2085a-dspi
25
25
- fsl,lx2160a-dspi
26
+
- nxp,s32g2-dspi
26
27
- items:
27
28
- enum:
28
29
- fsl,ls1012a-dspi
···
38
37
- items:
39
38
- const: fsl,lx2160a-dspi
40
39
- const: fsl,ls2085a-dspi
40
+
- items:
41
+
- const: nxp,s32g3-dspi
42
+
- const: nxp,s32g2-dspi
41
43
42
44
reg:
43
45
maxItems: 1
···
117
113
spi-cs-setup-delay-ns = <100>;
118
114
spi-cs-hold-delay-ns = <50>;
119
115
};
116
+
};
117
+
# S32G3 in target mode
118
+
- |
119
+
spi@401d4000 {
120
+
compatible = "nxp,s32g3-dspi", "nxp,s32g2-dspi";
121
+
reg = <0x401d4000 0x1000>;
122
+
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
123
+
clocks = <&clks 26>;
124
+
clock-names = "dspi";
125
+
spi-num-chipselects = <8>;
126
+
bus-num = <0>;
127
+
dmas = <&edma0 0 7>, <&edma0 0 8>;
128
+
dma-names = "tx", "rx";
129
+
spi-slave;
120
130
};
+102
Documentation/devicetree/bindings/spi/marvell,orion-spi.yaml
+102
Documentation/devicetree/bindings/spi/marvell,orion-spi.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/spi/marvell,orion-spi.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Marvell Orion SPI controller
8
+
9
+
maintainers:
10
+
- Andrew Lunn <andrew@lunn.ch>
11
+
- Gregory CLEMENT <gregory.clement@bootlin.com>
12
+
13
+
allOf:
14
+
- $ref: /schemas/spi/spi-controller.yaml#
15
+
16
+
properties:
17
+
compatible:
18
+
oneOf:
19
+
- enum:
20
+
- marvell,orion-spi
21
+
- marvell,armada-380-spi # For ap80x and cp11x
22
+
- items:
23
+
- enum:
24
+
- marvell,armada-370-spi
25
+
- marvell,armada-375-spi
26
+
- marvell,armada-380-spi
27
+
- marvell,armada-390-spi
28
+
- marvell,armada-xp-spi
29
+
- const: marvell,orion-spi
30
+
31
+
cell-index:
32
+
description: Instance id for the SPI controller
33
+
deprecated: true
34
+
35
+
reg:
36
+
minItems: 1
37
+
items:
38
+
- description: control registers
39
+
- description: CS0 MBUS target/attribute registers for direct mode
40
+
- description: CS1 MBUS target/attribute registers for direct mode
41
+
- description: CS2 MBUS target/attribute registers for direct mode
42
+
- description: CS3 MBUS target/attribute registers for direct mode
43
+
- description: CS4 MBUS target/attribute registers for direct mode
44
+
- description: CS5 MBUS target/attribute registers for direct mode
45
+
- description: CS6 MBUS target/attribute registers for direct mode
46
+
- description: CS7 MBUS target/attribute registers for direct mode
47
+
48
+
clocks:
49
+
minItems: 1
50
+
maxItems: 2
51
+
52
+
clock-names:
53
+
items:
54
+
- const: core
55
+
- const: axi
56
+
57
+
interrupts:
58
+
maxItems: 1
59
+
60
+
required:
61
+
- compatible
62
+
- reg
63
+
- clocks
64
+
65
+
unevaluatedProperties: false
66
+
67
+
examples:
68
+
- |
69
+
spi@10600 {
70
+
compatible = "marvell,orion-spi";
71
+
#address-cells = <1>;
72
+
#size-cells = <0>;
73
+
cell-index = <0>;
74
+
reg = <0x10600 0x28>;
75
+
clocks = <&coreclk 0>;
76
+
interrupts = <23>;
77
+
};
78
+
- |
79
+
#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
80
+
81
+
bus {
82
+
#address-cells = <2>;
83
+
#size-cells = <1>;
84
+
85
+
spi@10600 {
86
+
compatible = "marvell,orion-spi";
87
+
#address-cells = <1>;
88
+
#size-cells = <0>;
89
+
cell-index = <0>;
90
+
reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x28>, /* control */
91
+
<MBUS_ID(0x01, 0x1e) 0 0xffffffff>, /* CS0 */
92
+
<MBUS_ID(0x01, 0x5e) 0 0xffffffff>, /* CS1 */
93
+
<MBUS_ID(0x01, 0x9e) 0 0xffffffff>, /* CS2 */
94
+
<MBUS_ID(0x01, 0xde) 0 0xffffffff>, /* CS3 */
95
+
<MBUS_ID(0x01, 0x1f) 0 0xffffffff>, /* CS4 */
96
+
<MBUS_ID(0x01, 0x5f) 0 0xffffffff>, /* CS5 */
97
+
<MBUS_ID(0x01, 0x9f) 0 0xffffffff>, /* CS6 */
98
+
<MBUS_ID(0x01, 0xdf) 0 0xffffffff>; /* CS7 */
99
+
clocks = <&coreclk 0>;
100
+
interrupts = <23>;
101
+
};
102
+
};
+5
Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml
+5
Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml
···
41
41
- const: mediatek,spi-ipm
42
42
- items:
43
43
- enum:
44
+
- mediatek,mt8196-spi
45
+
- const: mediatek,mt6991-spi
46
+
- items:
47
+
- enum:
44
48
- mediatek,mt2701-spi
45
49
- mediatek,mt2712-spi
46
50
- mediatek,mt6589-spi
47
51
- mediatek,mt6765-spi
48
52
- mediatek,mt6893-spi
53
+
- mediatek,mt6991-spi
49
54
- mediatek,mt7622-spi
50
55
- mediatek,mt8135-spi
51
56
- mediatek,mt8173-spi
+3
Documentation/devicetree/bindings/spi/mxs-spi.yaml
+3
Documentation/devicetree/bindings/spi/mxs-spi.yaml
+44
Documentation/devicetree/bindings/spi/nxp,lpc3220-spi.yaml
+44
Documentation/devicetree/bindings/spi/nxp,lpc3220-spi.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/spi/nxp,lpc3220-spi.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: NXP LPC3220 SPI controller
8
+
9
+
maintainers:
10
+
- Frank Li <Frank.Li@nxp.com>
11
+
12
+
properties:
13
+
compatible:
14
+
enum:
15
+
- nxp,lpc3220-spi
16
+
17
+
reg:
18
+
maxItems: 1
19
+
20
+
clocks:
21
+
maxItems: 1
22
+
23
+
allOf:
24
+
- $ref: spi-controller.yaml#
25
+
26
+
unevaluatedProperties: false
27
+
28
+
required:
29
+
- compatible
30
+
- reg
31
+
- clocks
32
+
33
+
examples:
34
+
- |
35
+
#include <dt-bindings/clock/lpc32xx-clock.h>
36
+
37
+
spi@20088000 {
38
+
compatible = "nxp,lpc3220-spi";
39
+
reg = <0x20088000 0x1000>;
40
+
clocks = <&clk LPC32XX_CLK_SPI1>;
41
+
#address-cells = <1>;
42
+
#size-cells = <0>;
43
+
};
44
+
+96
Documentation/devicetree/bindings/spi/renesas,rzv2h-rspi.yaml
+96
Documentation/devicetree/bindings/spi/renesas,rzv2h-rspi.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/spi/renesas,rzv2h-rspi.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Renesas RZ/V2H(P) Renesas Serial Peripheral Interface (RSPI)
8
+
9
+
maintainers:
10
+
- Fabrizio Castro <fabrizio.castro.jz@renesas.com>
11
+
12
+
allOf:
13
+
- $ref: spi-controller.yaml#
14
+
15
+
properties:
16
+
compatible:
17
+
const: renesas,r9a09g057-rspi # RZ/V2H(P)
18
+
19
+
reg:
20
+
maxItems: 1
21
+
22
+
interrupts:
23
+
items:
24
+
- description: Idle Interrupt
25
+
- description: Error Interrupt
26
+
- description: Communication End Interrupt
27
+
- description: Receive Buffer Full Interrupt
28
+
- description: Transmit Buffer Empty Interrupt
29
+
30
+
interrupt-names:
31
+
items:
32
+
- const: idle
33
+
- const: error
34
+
- const: end
35
+
- const: rx
36
+
- const: tx
37
+
38
+
clocks:
39
+
maxItems: 3
40
+
41
+
clock-names:
42
+
items:
43
+
- const: pclk
44
+
- const: pclk_sfr
45
+
- const: tclk
46
+
47
+
resets:
48
+
maxItems: 2
49
+
50
+
reset-names:
51
+
items:
52
+
- const: presetn
53
+
- const: tresetn
54
+
55
+
power-domains:
56
+
maxItems: 1
57
+
58
+
required:
59
+
- compatible
60
+
- reg
61
+
- interrupts
62
+
- interrupt-names
63
+
- clocks
64
+
- clock-names
65
+
- resets
66
+
- reset-names
67
+
- power-domains
68
+
- '#address-cells'
69
+
- '#size-cells'
70
+
71
+
unevaluatedProperties: false
72
+
73
+
examples:
74
+
- |
75
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
76
+
#include <dt-bindings/clock/renesas-cpg-mssr.h>
77
+
spi@12800800 {
78
+
compatible = "renesas,r9a09g057-rspi";
79
+
80
+
reg = <0x12800800 0x400>;
81
+
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
82
+
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
83
+
<GIC_SPI 113 IRQ_TYPE_EDGE_RISING>,
84
+
<GIC_SPI 504 IRQ_TYPE_EDGE_RISING>,
85
+
<GIC_SPI 505 IRQ_TYPE_EDGE_RISING>;
86
+
interrupt-names = "idle", "error", "end", "rx", "tx";
87
+
clocks = <&cpg CPG_MOD 0x5a>,
88
+
<&cpg CPG_MOD 0x5b>,
89
+
<&cpg CPG_MOD 0x5c>;
90
+
clock-names = "pclk", "pclk_sfr", "tclk";
91
+
resets = <&cpg 0x7f>, <&cpg 0x80>;
92
+
reset-names = "presetn", "tresetn";
93
+
power-domains = <&cpg>;
94
+
#address-cells = <1>;
95
+
#size-cells = <0>;
96
+
};
-1
Documentation/devicetree/bindings/spi/spi-mux.yaml
-1
Documentation/devicetree/bindings/spi/spi-mux.yaml
-79
Documentation/devicetree/bindings/spi/spi-orion.txt
-79
Documentation/devicetree/bindings/spi/spi-orion.txt
···
1
-
Marvell Orion SPI device
2
-
3
-
Required properties:
4
-
- compatible : should be on of the following:
5
-
- "marvell,orion-spi" for the Orion, mv78x00, Kirkwood and Dove SoCs
6
-
- "marvell,armada-370-spi", for the Armada 370 SoCs
7
-
- "marvell,armada-375-spi", for the Armada 375 SoCs
8
-
- "marvell,armada-380-spi", for the Armada 38x SoCs
9
-
- "marvell,armada-390-spi", for the Armada 39x SoCs
10
-
- "marvell,armada-xp-spi", for the Armada XP SoCs
11
-
- reg : offset and length of the register set for the device.
12
-
This property can optionally have additional entries to configure
13
-
the SPI direct access mode that some of the Marvell SoCs support
14
-
additionally to the normal indirect access (PIO) mode. The values
15
-
for the MBus "target" and "attribute" are defined in the Marvell
16
-
SoC "Functional Specifications" Manual in the chapter "Marvell
17
-
Core Processor Address Decoding".
18
-
The eight register sets following the control registers refer to
19
-
chip-select lines 0 through 7 respectively.
20
-
- cell-index : Which of multiple SPI controllers is this.
21
-
- clocks : pointers to the reference clocks for this device, the first
22
-
one is the one used for the clock on the spi bus, the
23
-
second one is optional and is the clock used for the
24
-
functional part of the controller
25
-
26
-
Optional properties:
27
-
- interrupts : Is currently not used.
28
-
- clock-names : names of used clocks, mandatory if the second clock is
29
-
used, the name must be "core", and "axi" (the latter
30
-
is only for Armada 7K/8K).
31
-
32
-
33
-
Example:
34
-
spi@10600 {
35
-
compatible = "marvell,orion-spi";
36
-
#address-cells = <1>;
37
-
#size-cells = <0>;
38
-
cell-index = <0>;
39
-
reg = <0x10600 0x28>;
40
-
interrupts = <23>;
41
-
};
42
-
43
-
Example with SPI direct mode support (optionally):
44
-
spi0: spi@10600 {
45
-
compatible = "marvell,orion-spi";
46
-
#address-cells = <1>;
47
-
#size-cells = <0>;
48
-
cell-index = <0>;
49
-
reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x28>, /* control */
50
-
<MBUS_ID(0x01, 0x1e) 0 0xffffffff>, /* CS0 */
51
-
<MBUS_ID(0x01, 0x5e) 0 0xffffffff>, /* CS1 */
52
-
<MBUS_ID(0x01, 0x9e) 0 0xffffffff>, /* CS2 */
53
-
<MBUS_ID(0x01, 0xde) 0 0xffffffff>, /* CS3 */
54
-
<MBUS_ID(0x01, 0x1f) 0 0xffffffff>, /* CS4 */
55
-
<MBUS_ID(0x01, 0x5f) 0 0xffffffff>, /* CS5 */
56
-
<MBUS_ID(0x01, 0x9f) 0 0xffffffff>, /* CS6 */
57
-
<MBUS_ID(0x01, 0xdf) 0 0xffffffff>; /* CS7 */
58
-
interrupts = <23>;
59
-
};
60
-
61
-
To enable the direct mode, the board specific 'ranges' property in the
62
-
'soc' node needs to add the entries for the desired SPI controllers
63
-
and its chip-selects that are used in the direct mode instead of PIO
64
-
mode. Here an example for this (SPI controller 0, device 1 and SPI
65
-
controller 1, device 2 are used in direct mode. All other SPI device
66
-
are used in the default indirect (PIO) mode):
67
-
soc {
68
-
/*
69
-
* Enable the SPI direct access by configuring an entry
70
-
* here in the board-specific ranges property
71
-
*/
72
-
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000>, /* internal regs */
73
-
<MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>, /* BootROM */
74
-
<MBUS_ID(0x01, 0x5e) 0 0 0xf1100000 0x10000>, /* SPI0-DEV1 */
75
-
<MBUS_ID(0x01, 0x9a) 0 0 0xf1110000 0x10000>; /* SPI1-DEV2 */
76
-
77
-
For further information on the MBus bindings, please see the MBus
78
-
DT documentation:
79
-
Documentation/devicetree/bindings/bus/mvebu-mbus.txt
+1
Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml
+1
Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml
+3
-6
Documentation/devicetree/bindings/spi/spi-sg2044-nor.yaml
+3
-6
Documentation/devicetree/bindings/spi/spi-sg2044-nor.yaml
···
14
14
15
15
properties:
16
16
compatible:
17
-
oneOf:
18
-
- const: sophgo,sg2044-spifmc-nor
19
-
- items:
20
-
- enum:
21
-
- sophgo,sg2042-spifmc-nor
22
-
- const: sophgo,sg2044-spifmc-nor
17
+
enum:
18
+
- sophgo,sg2042-spifmc-nor
19
+
- sophgo,sg2044-spifmc-nor
23
20
24
21
reg:
25
22
maxItems: 1
+46
-2
Documentation/devicetree/bindings/spi/st,stm32-spi.yaml
+46
-2
Documentation/devicetree/bindings/spi/st,stm32-spi.yaml
···
18
18
19
19
allOf:
20
20
- $ref: spi-controller.yaml#
21
+
- if:
22
+
properties:
23
+
compatible:
24
+
contains:
25
+
const: st,stm32f4-spi
26
+
27
+
then:
28
+
properties:
29
+
st,spi-midi-ns: false
30
+
sram: false
31
+
dmas:
32
+
maxItems: 2
33
+
dma-names:
34
+
items:
35
+
- const: rx
36
+
- const: tx
37
+
38
+
- if:
39
+
properties:
40
+
compatible:
41
+
contains:
42
+
const: st,stm32mp25-spi
43
+
44
+
then:
45
+
properties:
46
+
sram: false
47
+
dmas:
48
+
maxItems: 2
49
+
dma-names:
50
+
items:
51
+
- const: rx
52
+
- const: tx
21
53
22
54
properties:
23
55
compatible:
···
73
41
74
42
dmas:
75
43
description: |
76
-
DMA specifiers for tx and rx dma. DMA fifo mode must be used. See
77
-
the STM32 DMA controllers bindings Documentation/devicetree/bindings/dma/stm32/*.yaml.
44
+
DMA specifiers for tx and rx channels. DMA fifo mode must be used. See
45
+
the STM32 DMA bindings Documentation/devicetree/bindings/dma/stm32/st,*dma.yaml
46
+
minItems: 2
78
47
items:
79
48
- description: rx DMA channel
80
49
- description: tx DMA channel
50
+
- description: rxm2m MDMA channel
81
51
82
52
dma-names:
53
+
minItems: 2
83
54
items:
84
55
- const: rx
85
56
- const: tx
57
+
- const: rxm2m
58
+
59
+
sram:
60
+
$ref: /schemas/types.yaml#/definitions/phandle
61
+
description: |
62
+
Phandles to a reserved SRAM region which is used as temporary
63
+
storage memory between DMA and MDMA engines.
64
+
The region should be defined as child node of the AHB SRAM node
65
+
as per the generic bindings in Documentation/devicetree/bindings/sram/sram.yaml
86
66
87
67
access-controllers:
88
68
minItems: 1
+49
Documentation/devicetree/bindings/trigger-source/adi,util-sigma-delta-spi.yaml
+49
Documentation/devicetree/bindings/trigger-source/adi,util-sigma-delta-spi.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
# Copyright (c) 2025 Analog Devices, Inc.
3
+
# Copyright (c) 2025 BayLibre, SAS
4
+
5
+
%YAML 1.2
6
+
---
7
+
$id: http://devicetree.org/schemas/trigger-source/adi,util-sigma-delta-spi.yaml#
8
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
9
+
10
+
title: Analog Devices Util Sigma-Delta SPI IP Core
11
+
12
+
maintainers:
13
+
- David Lechner <dlechner@baylibre.com>
14
+
15
+
description:
16
+
The Util Sigma-Delta SPI is an FPGA IP core from Analog Devices that provides
17
+
a SPI offload trigger from the RDY signal of the combined DOUT/RDY pin of
18
+
the sigma-delta family of ADCs.
19
+
https://analogdevicesinc.github.io/hdl/library/util_sigma_delta_spi/index.html
20
+
21
+
properties:
22
+
compatible:
23
+
const: adi,util-sigma-delta-spi
24
+
25
+
reg:
26
+
maxItems: 1
27
+
28
+
clocks:
29
+
maxItems: 1
30
+
31
+
'#trigger-source-cells':
32
+
const: 0
33
+
34
+
required:
35
+
- compatible
36
+
- reg
37
+
- clocks
38
+
- '#trigger-source-cells'
39
+
40
+
additionalProperties: false
41
+
42
+
examples:
43
+
- |
44
+
trigger@40000 {
45
+
reg = <0x40000 0x1000>;
46
+
compatible = "adi,util-sigma-delta-spi";
47
+
clocks = <&clk 0>;
48
+
#trigger-source-cells = <0>;
49
+
};
+2
Documentation/devicetree/bindings/trivial-devices.yaml
+2
Documentation/devicetree/bindings/trivial-devices.yaml
···
30
30
items:
31
31
# Entries are sorted alphanumerically by the compatible
32
32
- enum:
33
+
# ABB register based spi sensors
34
+
- abb,spi-sensor
33
35
# Acbel fsg032 power supply
34
36
- acbel,fsg032
35
37
# SMBus/I2C Digital Temperature Sensor in 6-Pin SOT with SMBus Alert and Over Temperature Pin
+15
-1
MAINTAINERS
+15
-1
MAINTAINERS
···
1308
1308
F: Documentation/devicetree/bindings/rtc/amlogic,a4-rtc.yaml
1309
1309
F: drivers/rtc/rtc-amlogic-a4.c
1310
1310
1311
+
AMLOGIC SPISG DRIVER
1312
+
M: Sunny Luo <sunny.luo@amlogic.com>
1313
+
M: Xianwei Zhao <xianwei.zhao@amlogic.com>
1314
+
L: linux-amlogic@lists.infradead.org
1315
+
L: linux-spi@vger.kernel.org
1316
+
S: Maintained
1317
+
F: Documentation/devicetree/bindings/spi/amlogic,a4-spisg.yaml
1318
+
F: drivers/spi/spi-amlogic-spisg.c
1319
+
1311
1320
AMPHENOL CHIPCAP 2 DRIVER
1312
1321
M: Javier Carrasco <javier.carrasco.cruz@gmail.com>
1313
1322
L: linux-hwmon@vger.kernel.org
···
23441
23432
23442
23433
SPI OFFLOAD
23443
23434
R: David Lechner <dlechner@baylibre.com>
23444
-
F: drivers/spi/spi-offload-trigger-pwm.c
23435
+
F: drivers/spi/spi-offload-trigger-*.c
23445
23436
F: drivers/spi/spi-offload.c
23446
23437
F: include/linux/spi/offload/
23447
23438
K: spi_offload
···
25261
25252
W: https://github.com/srcres258/linux-doc
25262
25253
T: git git://github.com/srcres258/linux-doc.git doc-zh-tw
25263
25254
F: Documentation/translations/zh_TW/
25255
+
25256
+
TRIGGER SOURCE - ADI UTIL SIGMA DELTA SPI
25257
+
M: David Lechner <dlechner@baylibre.com>
25258
+
S: Maintained
25259
+
F: Documentation/devicetree/bindings/trigger-source/adi,util-sigma-delta-spi.yaml
25264
25260
25265
25261
TRIGGER SOURCE - PWM
25266
25262
M: David Lechner <dlechner@baylibre.com>
+30
drivers/dma/dmaengine.c
+30
drivers/dma/dmaengine.c
···
926
926
}
927
927
EXPORT_SYMBOL_GPL(dma_release_channel);
928
928
929
+
static void dmaenginem_release_channel(void *chan)
930
+
{
931
+
dma_release_channel(chan);
932
+
}
933
+
934
+
/**
935
+
* devm_dma_request_chan - try to allocate an exclusive slave channel
936
+
* @dev: pointer to client device structure
937
+
* @name: slave channel name
938
+
*
939
+
* Returns pointer to appropriate DMA channel on success or an error pointer.
940
+
*
941
+
* The operation is managed and will be undone on driver detach.
942
+
*/
943
+
944
+
struct dma_chan *devm_dma_request_chan(struct device *dev, const char *name)
945
+
{
946
+
struct dma_chan *chan = dma_request_chan(dev, name);
947
+
int ret = 0;
948
+
949
+
if (!IS_ERR(chan))
950
+
ret = devm_add_action_or_reset(dev, dmaenginem_release_channel, chan);
951
+
952
+
if (ret)
953
+
return ERR_PTR(ret);
954
+
955
+
return chan;
956
+
}
957
+
EXPORT_SYMBOL_GPL(devm_dma_request_chan);
958
+
929
959
/**
930
960
* dmaengine_get - register interest in dma_channels
931
961
*/
+3
-3
drivers/mtd/nand/raw/qcom_nandc.c
+3
-3
drivers/mtd/nand/raw/qcom_nandc.c
···
1379
1379
struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
1380
1380
int cwperpage, bad_block_byte, ret;
1381
1381
bool wide_bus;
1382
-
int ecc_mode = 1;
1382
+
int ecc_mode = ECC_MODE_8BIT;
1383
1383
1384
1384
/* controller only supports 512 bytes data steps */
1385
1385
ecc->size = NANDC_STEP_SIZE;
···
1400
1400
if (ecc->strength >= 8) {
1401
1401
/* 8 bit ECC defaults to BCH ECC on all platforms */
1402
1402
host->bch_enabled = true;
1403
-
ecc_mode = 1;
1403
+
ecc_mode = ECC_MODE_8BIT;
1404
1404
1405
1405
if (wide_bus) {
1406
1406
host->ecc_bytes_hw = 14;
···
1420
1420
if (nandc->props->ecc_modes & ECC_BCH_4BIT) {
1421
1421
/* BCH */
1422
1422
host->bch_enabled = true;
1423
-
ecc_mode = 0;
1423
+
ecc_mode = ECC_MODE_4BIT;
1424
1424
1425
1425
if (wide_bus) {
1426
1426
host->ecc_bytes_hw = 8;
+24
-2
drivers/spi/Kconfig
+24
-2
drivers/spi/Kconfig
···
99
99
This enables master mode support for the SPIFC (SPI flash
100
100
controller) available in Amlogic A1 (A113L SoC).
101
101
102
+
config SPI_AMLOGIC_SPISG
103
+
tristate "Amlogic SPISG controller"
104
+
depends on COMMON_CLK
105
+
depends on ARCH_MESON || COMPILE_TEST
106
+
help
107
+
This enables master mode support for the SPISG (SPI scatter-gather
108
+
communication controller), which is available on platforms such as
109
+
Amlogic A4 SoCs.
110
+
102
111
config SPI_APPLE
103
112
tristate "Apple SoC SPI Controller platform driver"
104
113
depends on ARCH_APPLE || COMPILE_TEST
···
656
647
config SPI_FSL_DSPI
657
648
tristate "Freescale DSPI controller"
658
649
select REGMAP_MMIO
659
-
depends on SOC_VF610 || SOC_LS1021A || ARCH_LAYERSCAPE || M5441x || COMPILE_TEST
650
+
depends on ARCH_MXC || ARCH_NXP || M5441x || COMPILE_TEST
660
651
help
661
652
This enables support for the Freescale DSPI controller in master
662
-
mode. VF610, LS1021A and ColdFire platforms uses the controller.
653
+
mode. S32, VF610, LS1021A and ColdFire platforms uses the controller.
663
654
664
655
config SPI_FSL_ESPI
665
656
tristate "Freescale eSPI controller"
···
931
922
depends on SUPERH || ARCH_RENESAS || COMPILE_TEST
932
923
help
933
924
SPI driver for Renesas RSPI and QSPI blocks.
925
+
926
+
config SPI_RZV2H_RSPI
927
+
tristate "Renesas RZ/V2H RSPI controller"
928
+
depends on ARCH_RENESAS || COMPILE_TEST
929
+
help
930
+
RSPI driver for the Renesas RZ/V2H Serial Peripheral Interface (RSPI).
931
+
RSPI supports both SPI host and SPI target roles. This option only
932
+
enables the SPI host role.
934
933
935
934
config SPI_RZV2M_CSI
936
935
tristate "Renesas RZ/V2M CSI controller"
···
1371
1354
if SPI_OFFLOAD
1372
1355
1373
1356
comment "SPI Offload triggers"
1357
+
1358
+
config SPI_OFFLOAD_TRIGGER_ADI_UTIL_SD
1359
+
tristate "SPI offload trigger using ADI sigma-delta utility"
1360
+
help
1361
+
SPI offload trigger from ADI sigma-delta utility FPGA IP block.
1374
1362
1375
1363
config SPI_OFFLOAD_TRIGGER_PWM
1376
1364
tristate "SPI offload trigger using PWM"
+3
drivers/spi/Makefile
+3
drivers/spi/Makefile
···
20
20
obj-$(CONFIG_SPI_ALTERA_CORE) += spi-altera-core.o
21
21
obj-$(CONFIG_SPI_ALTERA_DFL) += spi-altera-dfl.o
22
22
obj-$(CONFIG_SPI_AMLOGIC_SPIFC_A1) += spi-amlogic-spifc-a1.o
23
+
obj-$(CONFIG_SPI_AMLOGIC_SPISG) += spi-amlogic-spisg.o
23
24
obj-$(CONFIG_SPI_APPLE) += spi-apple.o
24
25
obj-$(CONFIG_SPI_AR934X) += spi-ar934x.o
25
26
obj-$(CONFIG_SPI_ARMADA_3700) += spi-armada-3700.o
···
127
126
obj-$(CONFIG_SPI_REALTEK_SNAND) += spi-realtek-rtl-snand.o
128
127
obj-$(CONFIG_SPI_RPCIF) += spi-rpc-if.o
129
128
obj-$(CONFIG_SPI_RSPI) += spi-rspi.o
129
+
obj-$(CONFIG_SPI_RZV2H_RSPI) += spi-rzv2h-rspi.o
130
130
obj-$(CONFIG_SPI_RZV2M_CSI) += spi-rzv2m-csi.o
131
131
obj-$(CONFIG_SPI_S3C64XX) += spi-s3c64xx.o
132
132
obj-$(CONFIG_SPI_SC18IS602) += spi-sc18is602.o
···
172
170
173
171
# SPI offload triggers
174
172
obj-$(CONFIG_SPI_OFFLOAD_TRIGGER_PWM) += spi-offload-trigger-pwm.o
173
+
obj-$(CONFIG_SPI_OFFLOAD_TRIGGER_ADI_UTIL_SD) += spi-offload-trigger-adi-util-sigma-delta.o
+13
-40
drivers/spi/atmel-quadspi.c
+13
-40
drivers/spi/atmel-quadspi.c
···
965
965
err = aq->ops->transfer(mem, op, offset);
966
966
967
967
pm_runtime_put:
968
-
pm_runtime_mark_last_busy(&aq->pdev->dev);
969
968
pm_runtime_put_autosuspend(&aq->pdev->dev);
970
969
return err;
971
970
}
···
1167
1168
aq->scr |= QSPI_SCR_SCBR(scbr);
1168
1169
atmel_qspi_write(aq->scr, aq, QSPI_SCR);
1169
1170
1170
-
pm_runtime_mark_last_busy(ctrl->dev.parent);
1171
1171
pm_runtime_put_autosuspend(ctrl->dev.parent);
1172
1172
1173
1173
return 0;
···
1228
1230
aq->mr |= QSPI_MR_DLYBCT(cs_hold) | QSPI_MR_DLYCS(cs_inactive);
1229
1231
atmel_qspi_write(aq->mr, aq, QSPI_MR);
1230
1232
1231
-
pm_runtime_mark_last_busy(ctrl->dev.parent);
1232
1233
pm_runtime_put_autosuspend(ctrl->dev.parent);
1233
1234
1234
1235
return 0;
···
1282
1285
struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
1283
1286
int ret;
1284
1287
1285
-
aq->rx_chan = dma_request_chan(&aq->pdev->dev, "rx");
1288
+
aq->rx_chan = devm_dma_request_chan(&aq->pdev->dev, "rx");
1286
1289
if (IS_ERR(aq->rx_chan)) {
1287
1290
ret = dev_err_probe(&aq->pdev->dev, PTR_ERR(aq->rx_chan),
1288
1291
"RX DMA channel is not available\n");
1289
-
goto null_rx_chan;
1292
+
aq->rx_chan = NULL;
1293
+
return ret;
1290
1294
}
1291
1295
1292
-
aq->tx_chan = dma_request_chan(&aq->pdev->dev, "tx");
1296
+
aq->tx_chan = devm_dma_request_chan(&aq->pdev->dev, "tx");
1293
1297
if (IS_ERR(aq->tx_chan)) {
1294
1298
ret = dev_err_probe(&aq->pdev->dev, PTR_ERR(aq->tx_chan),
1295
1299
"TX DMA channel is not available\n");
1296
-
goto release_rx_chan;
1300
+
aq->rx_chan = NULL;
1301
+
aq->tx_chan = NULL;
1302
+
return ret;
1297
1303
}
1298
1304
1299
1305
ctrl->dma_rx = aq->rx_chan;
···
1307
1307
dma_chan_name(aq->tx_chan), dma_chan_name(aq->rx_chan));
1308
1308
1309
1309
return 0;
1310
-
1311
-
release_rx_chan:
1312
-
dma_release_channel(aq->rx_chan);
1313
-
aq->tx_chan = NULL;
1314
-
null_rx_chan:
1315
-
aq->rx_chan = NULL;
1316
-
return ret;
1317
-
}
1318
-
1319
-
static void atmel_qspi_dma_release(struct atmel_qspi *aq)
1320
-
{
1321
-
if (aq->rx_chan)
1322
-
dma_release_channel(aq->rx_chan);
1323
-
if (aq->tx_chan)
1324
-
dma_release_channel(aq->tx_chan);
1325
1310
}
1326
1311
1327
1312
static const struct atmel_qspi_ops atmel_qspi_ops = {
···
1411
1426
1412
1427
/* Request the IRQ */
1413
1428
irq = platform_get_irq(pdev, 0);
1414
-
if (irq < 0) {
1415
-
err = irq;
1416
-
goto dma_release;
1417
-
}
1429
+
if (irq < 0)
1430
+
return irq;
1431
+
1418
1432
err = devm_request_irq(&pdev->dev, irq, atmel_qspi_interrupt,
1419
1433
0, dev_name(&pdev->dev), aq);
1420
1434
if (err)
1421
-
goto dma_release;
1435
+
return err;
1422
1436
1423
1437
pm_runtime_set_autosuspend_delay(&pdev->dev, 500);
1424
1438
pm_runtime_use_autosuspend(&pdev->dev);
···
1426
1442
1427
1443
err = atmel_qspi_init(aq);
1428
1444
if (err)
1429
-
goto dma_release;
1445
+
return err;
1430
1446
1431
1447
err = spi_register_controller(ctrl);
1432
1448
if (err)
1433
-
goto dma_release;
1449
+
return err;
1434
1450
1435
-
pm_runtime_mark_last_busy(&pdev->dev);
1436
1451
pm_runtime_put_autosuspend(&pdev->dev);
1437
1452
1438
1453
return 0;
1439
-
1440
-
dma_release:
1441
-
if (aq->caps->has_dma)
1442
-
atmel_qspi_dma_release(aq);
1443
-
1444
-
return err;
1445
1454
}
1446
1455
1447
1456
static int atmel_qspi_sama7g5_suspend(struct atmel_qspi *aq)
···
1484
1507
1485
1508
ret = pm_runtime_get_sync(&pdev->dev);
1486
1509
if (ret >= 0) {
1487
-
if (aq->caps->has_dma)
1488
-
atmel_qspi_dma_release(aq);
1489
-
1490
1510
if (aq->caps->has_gclk) {
1491
1511
ret = atmel_qspi_sama7g5_suspend(aq);
1492
1512
if (ret)
···
1556
1582
1557
1583
atmel_qspi_write(aq->scr, aq, QSPI_SCR);
1558
1584
1559
-
pm_runtime_mark_last_busy(dev);
1560
1585
pm_runtime_put_autosuspend(dev);
1561
1586
1562
1587
return 0;
+888
drivers/spi/spi-amlogic-spisg.c
+888
drivers/spi/spi-amlogic-spisg.c
···
1
+
// SPDX-License-Identifier: GPL-2.0+
2
+
/*
3
+
* Driver for Amlogic SPI communication Scatter-Gather Controller
4
+
*
5
+
* Copyright (C) 2025 Amlogic, Inc. All rights reserved
6
+
*
7
+
* Author: Sunny Luo <sunny.luo@amlogic.com>
8
+
* Author: Xianwei Zhao <xianwei.zhao@amlogic.com>
9
+
*/
10
+
11
+
#include <linux/bitfield.h>
12
+
#include <linux/device.h>
13
+
#include <linux/module.h>
14
+
#include <linux/of.h>
15
+
#include <linux/clk.h>
16
+
#include <linux/clk-provider.h>
17
+
#include <linux/dma-mapping.h>
18
+
#include <linux/platform_device.h>
19
+
#include <linux/pinctrl/consumer.h>
20
+
#include <linux/pm_runtime.h>
21
+
#include <linux/spi/spi.h>
22
+
#include <linux/types.h>
23
+
#include <linux/interrupt.h>
24
+
#include <linux/reset.h>
25
+
#include <linux/regmap.h>
26
+
27
+
/* Register Map */
28
+
#define SPISG_REG_CFG_READY 0x00
29
+
30
+
#define SPISG_REG_CFG_SPI 0x04
31
+
#define CFG_BUS64_EN BIT(0)
32
+
#define CFG_SLAVE_EN BIT(1)
33
+
#define CFG_SLAVE_SELECT GENMASK(3, 2)
34
+
#define CFG_SFLASH_WP BIT(4)
35
+
#define CFG_SFLASH_HD BIT(5)
36
+
/* start on vsync rising */
37
+
#define CFG_HW_POS BIT(6)
38
+
/* start on vsync falling */
39
+
#define CFG_HW_NEG BIT(7)
40
+
41
+
#define SPISG_REG_CFG_START 0x08
42
+
#define CFG_BLOCK_NUM GENMASK(19, 0)
43
+
#define CFG_BLOCK_SIZE GENMASK(22, 20)
44
+
#define CFG_DATA_COMMAND BIT(23)
45
+
#define CFG_OP_MODE GENMASK(25, 24)
46
+
#define CFG_RXD_MODE GENMASK(27, 26)
47
+
#define CFG_TXD_MODE GENMASK(29, 28)
48
+
#define CFG_EOC BIT(30)
49
+
#define CFG_PEND BIT(31)
50
+
51
+
#define SPISG_REG_CFG_BUS 0x0C
52
+
#define CFG_CLK_DIV GENMASK(7, 0)
53
+
#define CLK_DIV_WIDTH 8
54
+
#define CFG_RX_TUNING GENMASK(11, 8)
55
+
#define CFG_TX_TUNING GENMASK(15, 12)
56
+
#define CFG_CS_SETUP GENMASK(19, 16)
57
+
#define CFG_LANE GENMASK(21, 20)
58
+
#define CFG_HALF_DUPLEX BIT(22)
59
+
#define CFG_B_L_ENDIAN BIT(23)
60
+
#define CFG_DC_MODE BIT(24)
61
+
#define CFG_NULL_CTL BIT(25)
62
+
#define CFG_DUMMY_CTL BIT(26)
63
+
#define CFG_READ_TURN GENMASK(28, 27)
64
+
#define CFG_KEEP_SS BIT(29)
65
+
#define CFG_CPHA BIT(30)
66
+
#define CFG_CPOL BIT(31)
67
+
68
+
#define SPISG_REG_PIO_TX_DATA_L 0x10
69
+
#define SPISG_REG_PIO_TX_DATA_H 0x14
70
+
#define SPISG_REG_PIO_RX_DATA_L 0x18
71
+
#define SPISG_REG_PIO_RX_DATA_H 0x1C
72
+
#define SPISG_REG_MEM_TX_ADDR_L 0x10
73
+
#define SPISG_REG_MEM_TX_ADDR_H 0x14
74
+
#define SPISG_REG_MEM_RX_ADDR_L 0x18
75
+
#define SPISG_REG_MEM_RX_ADDR_H 0x1C
76
+
#define SPISG_REG_DESC_LIST_L 0x20
77
+
#define SPISG_REG_DESC_LIST_H 0x24
78
+
#define LIST_DESC_PENDING BIT(31)
79
+
#define SPISG_REG_DESC_CURRENT_L 0x28
80
+
#define SPISG_REG_DESC_CURRENT_H 0x2c
81
+
#define SPISG_REG_IRQ_STS 0x30
82
+
#define SPISG_REG_IRQ_ENABLE 0x34
83
+
#define IRQ_RCH_DESC_EOC BIT(0)
84
+
#define IRQ_RCH_DESC_INVALID BIT(1)
85
+
#define IRQ_RCH_DESC_RESP BIT(2)
86
+
#define IRQ_RCH_DATA_RESP BIT(3)
87
+
#define IRQ_WCH_DESC_EOC BIT(4)
88
+
#define IRQ_WCH_DESC_INVALID BIT(5)
89
+
#define IRQ_WCH_DESC_RESP BIT(6)
90
+
#define IRQ_WCH_DATA_RESP BIT(7)
91
+
#define IRQ_DESC_ERR BIT(8)
92
+
#define IRQ_SPI_READY BIT(9)
93
+
#define IRQ_DESC_DONE BIT(10)
94
+
#define IRQ_DESC_CHAIN_DONE BIT(11)
95
+
96
+
#define SPISG_MAX_REG 0x40
97
+
98
+
#define SPISG_BLOCK_MAX 0x100000
99
+
100
+
#define SPISG_OP_MODE_WRITE_CMD 0
101
+
#define SPISG_OP_MODE_READ_STS 1
102
+
#define SPISG_OP_MODE_WRITE 2
103
+
#define SPISG_OP_MODE_READ 3
104
+
105
+
#define SPISG_DATA_MODE_NONE 0
106
+
#define SPISG_DATA_MODE_PIO 1
107
+
#define SPISG_DATA_MODE_MEM 2
108
+
#define SPISG_DATA_MODE_SG 3
109
+
110
+
#define SPISG_CLK_DIV_MAX 256
111
+
/* recommended by specification */
112
+
#define SPISG_CLK_DIV_MIN 4
113
+
#define DIV_NUM (SPISG_CLK_DIV_MAX - SPISG_CLK_DIV_MIN + 1)
114
+
115
+
#define SPISG_PCLK_RATE_MIN 24000000
116
+
117
+
#define SPISG_SINGLE_SPI 0
118
+
#define SPISG_DUAL_SPI 1
119
+
#define SPISG_QUAD_SPI 2
120
+
121
+
struct spisg_sg_link {
122
+
#define LINK_ADDR_VALID BIT(0)
123
+
#define LINK_ADDR_EOC BIT(1)
124
+
#define LINK_ADDR_IRQ BIT(2)
125
+
#define LINK_ADDR_ACT GENMASK(5, 3)
126
+
#define LINK_ADDR_RING BIT(6)
127
+
#define LINK_ADDR_LEN GENMASK(31, 8)
128
+
u32 addr;
129
+
u32 addr1;
130
+
};
131
+
132
+
struct spisg_descriptor {
133
+
u32 cfg_start;
134
+
u32 cfg_bus;
135
+
u64 tx_paddr;
136
+
u64 rx_paddr;
137
+
};
138
+
139
+
struct spisg_descriptor_extra {
140
+
struct spisg_sg_link *tx_ccsg;
141
+
struct spisg_sg_link *rx_ccsg;
142
+
int tx_ccsg_len;
143
+
int rx_ccsg_len;
144
+
};
145
+
146
+
struct spisg_device {
147
+
struct spi_controller *controller;
148
+
struct platform_device *pdev;
149
+
struct regmap *map;
150
+
struct clk *core;
151
+
struct clk *pclk;
152
+
struct clk *sclk;
153
+
struct clk_div_table *tbl;
154
+
struct completion completion;
155
+
u32 status;
156
+
u32 speed_hz;
157
+
u32 effective_speed_hz;
158
+
u32 bytes_per_word;
159
+
u32 cfg_spi;
160
+
u32 cfg_start;
161
+
u32 cfg_bus;
162
+
};
163
+
164
+
static int spi_delay_to_sclk(u32 slck_speed_hz, struct spi_delay *delay)
165
+
{
166
+
s32 ns;
167
+
168
+
if (!delay)
169
+
return 0;
170
+
171
+
if (delay->unit == SPI_DELAY_UNIT_SCK)
172
+
return delay->value;
173
+
174
+
ns = spi_delay_to_ns(delay, NULL);
175
+
if (ns < 0)
176
+
return 0;
177
+
178
+
return DIV_ROUND_UP_ULL(slck_speed_hz * ns, NSEC_PER_SEC);
179
+
}
180
+
181
+
static inline u32 aml_spisg_sem_down_read(struct spisg_device *spisg)
182
+
{
183
+
u32 ret;
184
+
185
+
regmap_read(spisg->map, SPISG_REG_CFG_READY, &ret);
186
+
if (ret)
187
+
regmap_write(spisg->map, SPISG_REG_CFG_READY, 0);
188
+
189
+
return ret;
190
+
}
191
+
192
+
static inline void aml_spisg_sem_up_write(struct spisg_device *spisg)
193
+
{
194
+
regmap_write(spisg->map, SPISG_REG_CFG_READY, 1);
195
+
}
196
+
197
+
static int aml_spisg_set_speed(struct spisg_device *spisg, uint speed_hz)
198
+
{
199
+
u32 cfg_bus;
200
+
201
+
if (!speed_hz || speed_hz == spisg->speed_hz)
202
+
return 0;
203
+
204
+
spisg->speed_hz = speed_hz;
205
+
clk_set_rate(spisg->sclk, speed_hz);
206
+
/* Store the div for the descriptor mode */
207
+
regmap_read(spisg->map, SPISG_REG_CFG_BUS, &cfg_bus);
208
+
spisg->cfg_bus &= ~CFG_CLK_DIV;
209
+
spisg->cfg_bus |= cfg_bus & CFG_CLK_DIV;
210
+
spisg->effective_speed_hz = clk_get_rate(spisg->sclk);
211
+
dev_dbg(&spisg->pdev->dev,
212
+
"desired speed %dHz, effective speed %dHz\n",
213
+
speed_hz, spisg->effective_speed_hz);
214
+
215
+
return 0;
216
+
}
217
+
218
+
static bool aml_spisg_can_dma(struct spi_controller *ctlr,
219
+
struct spi_device *spi,
220
+
struct spi_transfer *xfer)
221
+
{
222
+
return true;
223
+
}
224
+
225
+
static void aml_spisg_sg_xlate(struct sg_table *sgt, struct spisg_sg_link *ccsg)
226
+
{
227
+
struct scatterlist *sg;
228
+
int i;
229
+
230
+
for_each_sg(sgt->sgl, sg, sgt->nents, i) {
231
+
ccsg->addr = FIELD_PREP(LINK_ADDR_VALID, 1) |
232
+
FIELD_PREP(LINK_ADDR_RING, 0) |
233
+
FIELD_PREP(LINK_ADDR_EOC, sg_is_last(sg)) |
234
+
FIELD_PREP(LINK_ADDR_LEN, sg_dma_len(sg));
235
+
ccsg->addr1 = (u32)sg_dma_address(sg);
236
+
ccsg++;
237
+
}
238
+
}
239
+
240
+
static int nbits_to_lane[] = {
241
+
SPISG_SINGLE_SPI,
242
+
SPISG_SINGLE_SPI,
243
+
SPISG_DUAL_SPI,
244
+
-EINVAL,
245
+
SPISG_QUAD_SPI
246
+
};
247
+
248
+
static int aml_spisg_setup_transfer(struct spisg_device *spisg,
249
+
struct spi_transfer *xfer,
250
+
struct spisg_descriptor *desc,
251
+
struct spisg_descriptor_extra *exdesc)
252
+
{
253
+
int block_size, blocks;
254
+
struct device *dev = &spisg->pdev->dev;
255
+
struct spisg_sg_link *ccsg;
256
+
int ccsg_len;
257
+
dma_addr_t paddr;
258
+
int ret;
259
+
260
+
memset(desc, 0, sizeof(*desc));
261
+
if (exdesc)
262
+
memset(exdesc, 0, sizeof(*exdesc));
263
+
aml_spisg_set_speed(spisg, xfer->speed_hz);
264
+
xfer->effective_speed_hz = spisg->effective_speed_hz;
265
+
266
+
desc->cfg_start = spisg->cfg_start;
267
+
desc->cfg_bus = spisg->cfg_bus;
268
+
269
+
block_size = xfer->bits_per_word >> 3;
270
+
blocks = xfer->len / block_size;
271
+
272
+
desc->cfg_start |= FIELD_PREP(CFG_EOC, 0);
273
+
desc->cfg_bus |= FIELD_PREP(CFG_KEEP_SS, !xfer->cs_change);
274
+
desc->cfg_bus |= FIELD_PREP(CFG_NULL_CTL, 0);
275
+
276
+
if (xfer->tx_buf || xfer->tx_dma) {
277
+
desc->cfg_bus |= FIELD_PREP(CFG_LANE, nbits_to_lane[xfer->tx_nbits]);
278
+
desc->cfg_start |= FIELD_PREP(CFG_OP_MODE, SPISG_OP_MODE_WRITE);
279
+
}
280
+
if (xfer->rx_buf || xfer->rx_dma) {
281
+
desc->cfg_bus |= FIELD_PREP(CFG_LANE, nbits_to_lane[xfer->rx_nbits]);
282
+
desc->cfg_start |= FIELD_PREP(CFG_OP_MODE, SPISG_OP_MODE_READ);
283
+
}
284
+
285
+
if (FIELD_GET(CFG_OP_MODE, desc->cfg_start) == SPISG_OP_MODE_READ_STS) {
286
+
desc->cfg_start |= FIELD_PREP(CFG_BLOCK_SIZE, blocks) |
287
+
FIELD_PREP(CFG_BLOCK_NUM, 1);
288
+
} else {
289
+
blocks = min_t(int, blocks, SPISG_BLOCK_MAX);
290
+
desc->cfg_start |= FIELD_PREP(CFG_BLOCK_SIZE, block_size & 0x7) |
291
+
FIELD_PREP(CFG_BLOCK_NUM, blocks);
292
+
}
293
+
294
+
if (xfer->tx_sg.nents && xfer->tx_sg.sgl) {
295
+
ccsg_len = xfer->tx_sg.nents * sizeof(struct spisg_sg_link);
296
+
ccsg = kzalloc(ccsg_len, GFP_KERNEL | GFP_DMA);
297
+
if (!ccsg) {
298
+
dev_err(dev, "alloc tx_ccsg failed\n");
299
+
return -ENOMEM;
300
+
}
301
+
302
+
aml_spisg_sg_xlate(&xfer->tx_sg, ccsg);
303
+
paddr = dma_map_single(dev, (void *)ccsg,
304
+
ccsg_len, DMA_TO_DEVICE);
305
+
ret = dma_mapping_error(dev, paddr);
306
+
if (ret) {
307
+
kfree(ccsg);
308
+
dev_err(dev, "tx ccsg map failed\n");
309
+
return ret;
310
+
}
311
+
312
+
desc->tx_paddr = paddr;
313
+
desc->cfg_start |= FIELD_PREP(CFG_TXD_MODE, SPISG_DATA_MODE_SG);
314
+
exdesc->tx_ccsg = ccsg;
315
+
exdesc->tx_ccsg_len = ccsg_len;
316
+
dma_sync_sgtable_for_device(spisg->controller->cur_tx_dma_dev,
317
+
&xfer->tx_sg, DMA_TO_DEVICE);
318
+
} else if (xfer->tx_buf || xfer->tx_dma) {
319
+
paddr = xfer->tx_dma;
320
+
if (!paddr) {
321
+
paddr = dma_map_single(dev, (void *)xfer->tx_buf,
322
+
xfer->len, DMA_TO_DEVICE);
323
+
ret = dma_mapping_error(dev, paddr);
324
+
if (ret) {
325
+
dev_err(dev, "tx buf map failed\n");
326
+
return ret;
327
+
}
328
+
}
329
+
desc->tx_paddr = paddr;
330
+
desc->cfg_start |= FIELD_PREP(CFG_TXD_MODE, SPISG_DATA_MODE_MEM);
331
+
}
332
+
333
+
if (xfer->rx_sg.nents && xfer->rx_sg.sgl) {
334
+
ccsg_len = xfer->rx_sg.nents * sizeof(struct spisg_sg_link);
335
+
ccsg = kzalloc(ccsg_len, GFP_KERNEL | GFP_DMA);
336
+
if (!ccsg) {
337
+
dev_err(dev, "alloc rx_ccsg failed\n");
338
+
return -ENOMEM;
339
+
}
340
+
341
+
aml_spisg_sg_xlate(&xfer->rx_sg, ccsg);
342
+
paddr = dma_map_single(dev, (void *)ccsg,
343
+
ccsg_len, DMA_TO_DEVICE);
344
+
ret = dma_mapping_error(dev, paddr);
345
+
if (ret) {
346
+
kfree(ccsg);
347
+
dev_err(dev, "rx ccsg map failed\n");
348
+
return ret;
349
+
}
350
+
351
+
desc->rx_paddr = paddr;
352
+
desc->cfg_start |= FIELD_PREP(CFG_RXD_MODE, SPISG_DATA_MODE_SG);
353
+
exdesc->rx_ccsg = ccsg;
354
+
exdesc->rx_ccsg_len = ccsg_len;
355
+
dma_sync_sgtable_for_device(spisg->controller->cur_rx_dma_dev,
356
+
&xfer->rx_sg, DMA_FROM_DEVICE);
357
+
} else if (xfer->rx_buf || xfer->rx_dma) {
358
+
paddr = xfer->rx_dma;
359
+
if (!paddr) {
360
+
paddr = dma_map_single(dev, xfer->rx_buf,
361
+
xfer->len, DMA_FROM_DEVICE);
362
+
ret = dma_mapping_error(dev, paddr);
363
+
if (ret) {
364
+
dev_err(dev, "rx buf map failed\n");
365
+
return ret;
366
+
}
367
+
}
368
+
369
+
desc->rx_paddr = paddr;
370
+
desc->cfg_start |= FIELD_PREP(CFG_RXD_MODE, SPISG_DATA_MODE_MEM);
371
+
}
372
+
373
+
return 0;
374
+
}
375
+
376
+
static void aml_spisg_cleanup_transfer(struct spisg_device *spisg,
377
+
struct spi_transfer *xfer,
378
+
struct spisg_descriptor *desc,
379
+
struct spisg_descriptor_extra *exdesc)
380
+
{
381
+
struct device *dev = &spisg->pdev->dev;
382
+
383
+
if (desc->tx_paddr) {
384
+
if (FIELD_GET(CFG_TXD_MODE, desc->cfg_start) == SPISG_DATA_MODE_SG) {
385
+
dma_unmap_single(dev, (dma_addr_t)desc->tx_paddr,
386
+
exdesc->tx_ccsg_len, DMA_TO_DEVICE);
387
+
kfree(exdesc->tx_ccsg);
388
+
dma_sync_sgtable_for_cpu(spisg->controller->cur_tx_dma_dev,
389
+
&xfer->tx_sg, DMA_TO_DEVICE);
390
+
} else if (!xfer->tx_dma) {
391
+
dma_unmap_single(dev, (dma_addr_t)desc->tx_paddr,
392
+
xfer->len, DMA_TO_DEVICE);
393
+
}
394
+
}
395
+
396
+
if (desc->rx_paddr) {
397
+
if (FIELD_GET(CFG_RXD_MODE, desc->cfg_start) == SPISG_DATA_MODE_SG) {
398
+
dma_unmap_single(dev, (dma_addr_t)desc->rx_paddr,
399
+
exdesc->rx_ccsg_len, DMA_TO_DEVICE);
400
+
kfree(exdesc->rx_ccsg);
401
+
dma_sync_sgtable_for_cpu(spisg->controller->cur_rx_dma_dev,
402
+
&xfer->rx_sg, DMA_FROM_DEVICE);
403
+
} else if (!xfer->rx_dma) {
404
+
dma_unmap_single(dev, (dma_addr_t)desc->rx_paddr,
405
+
xfer->len, DMA_FROM_DEVICE);
406
+
}
407
+
}
408
+
}
409
+
410
+
static void aml_spisg_setup_null_desc(struct spisg_device *spisg,
411
+
struct spisg_descriptor *desc,
412
+
u32 n_sclk)
413
+
{
414
+
/* unit is the last xfer sclk */
415
+
desc->cfg_start = spisg->cfg_start;
416
+
desc->cfg_bus = spisg->cfg_bus;
417
+
418
+
desc->cfg_start |= FIELD_PREP(CFG_OP_MODE, SPISG_OP_MODE_WRITE) |
419
+
FIELD_PREP(CFG_BLOCK_SIZE, 1) |
420
+
FIELD_PREP(CFG_BLOCK_NUM, DIV_ROUND_UP(n_sclk, 8));
421
+
422
+
desc->cfg_bus |= FIELD_PREP(CFG_NULL_CTL, 1);
423
+
}
424
+
425
+
static void aml_spisg_pending(struct spisg_device *spisg,
426
+
dma_addr_t desc_paddr,
427
+
bool trig,
428
+
bool irq_en)
429
+
{
430
+
u32 desc_l, desc_h, cfg_spi, irq_enable;
431
+
432
+
#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
433
+
desc_l = (u64)desc_paddr & 0xffffffff;
434
+
desc_h = (u64)desc_paddr >> 32;
435
+
#else
436
+
desc_l = desc_paddr & 0xffffffff;
437
+
desc_h = 0;
438
+
#endif
439
+
440
+
cfg_spi = spisg->cfg_spi;
441
+
if (trig)
442
+
cfg_spi |= CFG_HW_POS;
443
+
else
444
+
desc_h |= LIST_DESC_PENDING;
445
+
446
+
irq_enable = IRQ_RCH_DESC_INVALID | IRQ_RCH_DESC_RESP |
447
+
IRQ_RCH_DATA_RESP | IRQ_WCH_DESC_INVALID |
448
+
IRQ_WCH_DESC_RESP | IRQ_WCH_DATA_RESP |
449
+
IRQ_DESC_ERR | IRQ_DESC_CHAIN_DONE;
450
+
regmap_write(spisg->map, SPISG_REG_IRQ_ENABLE, irq_en ? irq_enable : 0);
451
+
regmap_write(spisg->map, SPISG_REG_CFG_SPI, cfg_spi);
452
+
regmap_write(spisg->map, SPISG_REG_DESC_LIST_L, desc_l);
453
+
regmap_write(spisg->map, SPISG_REG_DESC_LIST_H, desc_h);
454
+
}
455
+
456
+
static irqreturn_t aml_spisg_irq(int irq, void *data)
457
+
{
458
+
struct spisg_device *spisg = (void *)data;
459
+
u32 sts;
460
+
461
+
spisg->status = 0;
462
+
regmap_read(spisg->map, SPISG_REG_IRQ_STS, &sts);
463
+
regmap_write(spisg->map, SPISG_REG_IRQ_STS, sts);
464
+
if (sts & (IRQ_RCH_DESC_INVALID |
465
+
IRQ_RCH_DESC_RESP |
466
+
IRQ_RCH_DATA_RESP |
467
+
IRQ_WCH_DESC_INVALID |
468
+
IRQ_WCH_DESC_RESP |
469
+
IRQ_WCH_DATA_RESP |
470
+
IRQ_DESC_ERR))
471
+
spisg->status = sts;
472
+
else if (sts & IRQ_DESC_CHAIN_DONE)
473
+
spisg->status = 0;
474
+
else
475
+
return IRQ_NONE;
476
+
477
+
complete(&spisg->completion);
478
+
479
+
return IRQ_HANDLED;
480
+
}
481
+
482
+
static int aml_spisg_transfer_one_message(struct spi_controller *ctlr,
483
+
struct spi_message *msg)
484
+
{
485
+
struct spisg_device *spisg = spi_controller_get_devdata(ctlr);
486
+
struct device *dev = &spisg->pdev->dev;
487
+
unsigned long long ms = 0;
488
+
struct spi_transfer *xfer;
489
+
struct spisg_descriptor *descs, *desc;
490
+
struct spisg_descriptor_extra *exdescs, *exdesc;
491
+
dma_addr_t descs_paddr;
492
+
int desc_num = 1, descs_len;
493
+
u32 cs_hold_in_sclk = 0;
494
+
int ret = -EIO;
495
+
496
+
if (!aml_spisg_sem_down_read(spisg)) {
497
+
spi_finalize_current_message(ctlr);
498
+
dev_err(dev, "controller busy\n");
499
+
return -EBUSY;
500
+
}
501
+
502
+
/* calculate the desc num for all xfer */
503
+
list_for_each_entry(xfer, &msg->transfers, transfer_list)
504
+
desc_num++;
505
+
506
+
/* alloc descriptor/extra-descriptor table */
507
+
descs = kcalloc(desc_num, sizeof(*desc) + sizeof(*exdesc),
508
+
GFP_KERNEL | GFP_DMA);
509
+
if (!descs) {
510
+
spi_finalize_current_message(ctlr);
511
+
aml_spisg_sem_up_write(spisg);
512
+
return -ENOMEM;
513
+
}
514
+
descs_len = sizeof(*desc) * desc_num;
515
+
exdescs = (struct spisg_descriptor_extra *)(descs + desc_num);
516
+
517
+
/* config descriptor for each xfer */
518
+
desc = descs;
519
+
exdesc = exdescs;
520
+
list_for_each_entry(xfer, &msg->transfers, transfer_list) {
521
+
ret = aml_spisg_setup_transfer(spisg, xfer, desc, exdesc);
522
+
if (ret) {
523
+
dev_err(dev, "config descriptor failed\n");
524
+
goto end;
525
+
}
526
+
527
+
/* calculate cs-setup delay with the first xfer speed */
528
+
if (list_is_first(&xfer->transfer_list, &msg->transfers))
529
+
desc->cfg_bus |= FIELD_PREP(CFG_CS_SETUP,
530
+
spi_delay_to_sclk(xfer->effective_speed_hz, &msg->spi->cs_setup));
531
+
532
+
/* calculate cs-hold delay with the last xfer speed */
533
+
if (list_is_last(&xfer->transfer_list, &msg->transfers))
534
+
cs_hold_in_sclk =
535
+
spi_delay_to_sclk(xfer->effective_speed_hz, &msg->spi->cs_hold);
536
+
537
+
desc++;
538
+
exdesc++;
539
+
ms += DIV_ROUND_UP_ULL(8LL * MSEC_PER_SEC * xfer->len,
540
+
xfer->effective_speed_hz);
541
+
}
542
+
543
+
if (cs_hold_in_sclk)
544
+
/* additional null-descriptor to achieve the cs-hold delay */
545
+
aml_spisg_setup_null_desc(spisg, desc, cs_hold_in_sclk);
546
+
else
547
+
desc--;
548
+
549
+
desc->cfg_bus |= FIELD_PREP(CFG_KEEP_SS, 0);
550
+
desc->cfg_start |= FIELD_PREP(CFG_EOC, 1);
551
+
552
+
/* some tolerances */
553
+
ms += ms + 20;
554
+
if (ms > UINT_MAX)
555
+
ms = UINT_MAX;
556
+
557
+
descs_paddr = dma_map_single(dev, (void *)descs,
558
+
descs_len, DMA_TO_DEVICE);
559
+
ret = dma_mapping_error(dev, descs_paddr);
560
+
if (ret) {
561
+
dev_err(dev, "desc table map failed\n");
562
+
goto end;
563
+
}
564
+
565
+
reinit_completion(&spisg->completion);
566
+
aml_spisg_pending(spisg, descs_paddr, false, true);
567
+
if (wait_for_completion_timeout(&spisg->completion,
568
+
spi_controller_is_target(spisg->controller) ?
569
+
MAX_SCHEDULE_TIMEOUT : msecs_to_jiffies(ms)))
570
+
ret = spisg->status ? -EIO : 0;
571
+
else
572
+
ret = -ETIMEDOUT;
573
+
574
+
dma_unmap_single(dev, descs_paddr, descs_len, DMA_TO_DEVICE);
575
+
end:
576
+
desc = descs;
577
+
exdesc = exdescs;
578
+
list_for_each_entry(xfer, &msg->transfers, transfer_list)
579
+
aml_spisg_cleanup_transfer(spisg, xfer, desc++, exdesc++);
580
+
kfree(descs);
581
+
582
+
if (!ret)
583
+
msg->actual_length = msg->frame_length;
584
+
msg->status = ret;
585
+
spi_finalize_current_message(ctlr);
586
+
aml_spisg_sem_up_write(spisg);
587
+
588
+
return ret;
589
+
}
590
+
591
+
static int aml_spisg_prepare_message(struct spi_controller *ctlr,
592
+
struct spi_message *message)
593
+
{
594
+
struct spisg_device *spisg = spi_controller_get_devdata(ctlr);
595
+
struct spi_device *spi = message->spi;
596
+
597
+
if (!spi->bits_per_word || spi->bits_per_word % 8) {
598
+
dev_err(&spisg->pdev->dev, "invalid wordlen %d\n", spi->bits_per_word);
599
+
return -EINVAL;
600
+
}
601
+
602
+
spisg->bytes_per_word = spi->bits_per_word >> 3;
603
+
604
+
spisg->cfg_spi &= ~CFG_SLAVE_SELECT;
605
+
spisg->cfg_spi |= FIELD_PREP(CFG_SLAVE_SELECT, spi_get_chipselect(spi, 0));
606
+
607
+
spisg->cfg_bus &= ~(CFG_CPOL | CFG_CPHA | CFG_B_L_ENDIAN | CFG_HALF_DUPLEX);
608
+
spisg->cfg_bus |= FIELD_PREP(CFG_CPOL, !!(spi->mode & SPI_CPOL)) |
609
+
FIELD_PREP(CFG_CPHA, !!(spi->mode & SPI_CPHA)) |
610
+
FIELD_PREP(CFG_B_L_ENDIAN, !!(spi->mode & SPI_LSB_FIRST)) |
611
+
FIELD_PREP(CFG_HALF_DUPLEX, !!(spi->mode & SPI_3WIRE));
612
+
613
+
return 0;
614
+
}
615
+
616
+
static int aml_spisg_setup(struct spi_device *spi)
617
+
{
618
+
if (!spi->controller_state)
619
+
spi->controller_state = spi_controller_get_devdata(spi->controller);
620
+
621
+
return 0;
622
+
}
623
+
624
+
static void aml_spisg_cleanup(struct spi_device *spi)
625
+
{
626
+
spi->controller_state = NULL;
627
+
}
628
+
629
+
static int aml_spisg_target_abort(struct spi_controller *ctlr)
630
+
{
631
+
struct spisg_device *spisg = spi_controller_get_devdata(ctlr);
632
+
633
+
spisg->status = 0;
634
+
regmap_write(spisg->map, SPISG_REG_DESC_LIST_H, 0);
635
+
complete(&spisg->completion);
636
+
637
+
return 0;
638
+
}
639
+
640
+
static int aml_spisg_clk_init(struct spisg_device *spisg, void __iomem *base)
641
+
{
642
+
struct device *dev = &spisg->pdev->dev;
643
+
struct clk_init_data init;
644
+
struct clk_divider *div;
645
+
struct clk_div_table *tbl;
646
+
char name[32];
647
+
int ret, i;
648
+
649
+
spisg->core = devm_clk_get_enabled(dev, "core");
650
+
if (IS_ERR_OR_NULL(spisg->core)) {
651
+
dev_err(dev, "core clock request failed\n");
652
+
return PTR_ERR(spisg->core);
653
+
}
654
+
655
+
spisg->pclk = devm_clk_get_enabled(dev, "pclk");
656
+
if (IS_ERR_OR_NULL(spisg->pclk)) {
657
+
dev_err(dev, "pclk clock request failed\n");
658
+
return PTR_ERR(spisg->pclk);
659
+
}
660
+
661
+
clk_set_min_rate(spisg->pclk, SPISG_PCLK_RATE_MIN);
662
+
663
+
clk_disable_unprepare(spisg->pclk);
664
+
665
+
tbl = devm_kzalloc(dev, sizeof(struct clk_div_table) * (DIV_NUM + 1), GFP_KERNEL);
666
+
if (!tbl)
667
+
return -ENOMEM;
668
+
669
+
for (i = 0; i < DIV_NUM; i++) {
670
+
tbl[i].val = i + SPISG_CLK_DIV_MIN - 1;
671
+
tbl[i].div = i + SPISG_CLK_DIV_MIN;
672
+
}
673
+
spisg->tbl = tbl;
674
+
675
+
div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
676
+
if (!div)
677
+
return -ENOMEM;
678
+
679
+
div->flags = CLK_DIVIDER_ROUND_CLOSEST;
680
+
div->reg = base + SPISG_REG_CFG_BUS;
681
+
div->shift = __bf_shf(CFG_CLK_DIV);
682
+
div->width = CLK_DIV_WIDTH;
683
+
div->table = tbl;
684
+
685
+
/* Register value should not be outside of the table */
686
+
regmap_update_bits(spisg->map, SPISG_REG_CFG_BUS, CFG_CLK_DIV,
687
+
FIELD_PREP(CFG_CLK_DIV, SPISG_CLK_DIV_MIN - 1));
688
+
689
+
/* Register clk-divider */
690
+
snprintf(name, sizeof(name), "%s_div", dev_name(dev));
691
+
init.name = name;
692
+
init.ops = &clk_divider_ops;
693
+
init.flags = CLK_SET_RATE_PARENT;
694
+
init.parent_data = &(const struct clk_parent_data) {
695
+
.fw_name = "pclk",
696
+
};
697
+
init.num_parents = 1;
698
+
div->hw.init = &init;
699
+
ret = devm_clk_hw_register(dev, &div->hw);
700
+
if (ret) {
701
+
dev_err(dev, "clock registration failed\n");
702
+
return ret;
703
+
}
704
+
705
+
spisg->sclk = devm_clk_hw_get_clk(dev, &div->hw, NULL);
706
+
if (IS_ERR_OR_NULL(spisg->sclk)) {
707
+
dev_err(dev, "get clock failed\n");
708
+
return PTR_ERR(spisg->sclk);
709
+
}
710
+
711
+
clk_prepare_enable(spisg->sclk);
712
+
713
+
return 0;
714
+
}
715
+
716
+
static int aml_spisg_probe(struct platform_device *pdev)
717
+
{
718
+
struct spi_controller *ctlr;
719
+
struct spisg_device *spisg;
720
+
struct device *dev = &pdev->dev;
721
+
void __iomem *base;
722
+
int ret, irq;
723
+
724
+
const struct regmap_config aml_regmap_config = {
725
+
.reg_bits = 32,
726
+
.val_bits = 32,
727
+
.reg_stride = 4,
728
+
.max_register = SPISG_MAX_REG,
729
+
};
730
+
731
+
if (of_property_read_bool(dev->of_node, "spi-slave"))
732
+
ctlr = spi_alloc_target(dev, sizeof(*spisg));
733
+
else
734
+
ctlr = spi_alloc_host(dev, sizeof(*spisg));
735
+
if (!ctlr)
736
+
return dev_err_probe(dev, -ENOMEM, "controller allocation failed\n");
737
+
738
+
spisg = spi_controller_get_devdata(ctlr);
739
+
spisg->controller = ctlr;
740
+
741
+
spisg->pdev = pdev;
742
+
platform_set_drvdata(pdev, spisg);
743
+
744
+
base = devm_platform_ioremap_resource(pdev, 0);
745
+
if (IS_ERR(base))
746
+
return dev_err_probe(dev, PTR_ERR(base), "resource ioremap failed\n");
747
+
748
+
spisg->map = devm_regmap_init_mmio(dev, base, &aml_regmap_config);
749
+
if (IS_ERR(spisg->map))
750
+
return dev_err_probe(dev, PTR_ERR(spisg->map), "regmap init failed\n");
751
+
752
+
irq = platform_get_irq(pdev, 0);
753
+
if (irq < 0) {
754
+
ret = irq;
755
+
goto out_controller;
756
+
}
757
+
758
+
ret = device_reset_optional(dev);
759
+
if (ret)
760
+
return dev_err_probe(dev, ret, "reset dev failed\n");
761
+
762
+
ret = aml_spisg_clk_init(spisg, base);
763
+
if (ret)
764
+
return dev_err_probe(dev, ret, "clock init failed\n");
765
+
766
+
spisg->cfg_spi = 0;
767
+
spisg->cfg_start = 0;
768
+
spisg->cfg_bus = 0;
769
+
770
+
spisg->cfg_spi = FIELD_PREP(CFG_SFLASH_WP, 1) |
771
+
FIELD_PREP(CFG_SFLASH_HD, 1);
772
+
if (spi_controller_is_target(ctlr)) {
773
+
spisg->cfg_spi |= FIELD_PREP(CFG_SLAVE_EN, 1);
774
+
spisg->cfg_bus = FIELD_PREP(CFG_TX_TUNING, 0xf);
775
+
}
776
+
/* default pending */
777
+
spisg->cfg_start = FIELD_PREP(CFG_PEND, 1);
778
+
779
+
pm_runtime_set_active(&spisg->pdev->dev);
780
+
pm_runtime_enable(&spisg->pdev->dev);
781
+
pm_runtime_resume_and_get(&spisg->pdev->dev);
782
+
783
+
ctlr->num_chipselect = 4;
784
+
ctlr->dev.of_node = pdev->dev.of_node;
785
+
ctlr->mode_bits = SPI_CPHA | SPI_CPOL | SPI_LSB_FIRST |
786
+
SPI_3WIRE | SPI_TX_QUAD | SPI_RX_QUAD;
787
+
ctlr->max_speed_hz = 1000 * 1000 * 100;
788
+
ctlr->min_speed_hz = 1000 * 10;
789
+
ctlr->setup = aml_spisg_setup;
790
+
ctlr->cleanup = aml_spisg_cleanup;
791
+
ctlr->prepare_message = aml_spisg_prepare_message;
792
+
ctlr->transfer_one_message = aml_spisg_transfer_one_message;
793
+
ctlr->target_abort = aml_spisg_target_abort;
794
+
ctlr->can_dma = aml_spisg_can_dma;
795
+
ctlr->max_dma_len = SPISG_BLOCK_MAX;
796
+
ctlr->auto_runtime_pm = true;
797
+
798
+
dma_set_max_seg_size(&pdev->dev, SPISG_BLOCK_MAX);
799
+
800
+
ret = devm_request_irq(&pdev->dev, irq, aml_spisg_irq, 0, NULL, spisg);
801
+
if (ret) {
802
+
dev_err(&pdev->dev, "irq request failed\n");
803
+
goto out_clk;
804
+
}
805
+
806
+
ret = devm_spi_register_controller(dev, ctlr);
807
+
if (ret) {
808
+
dev_err(&pdev->dev, "spi controller registration failed\n");
809
+
goto out_clk;
810
+
}
811
+
812
+
init_completion(&spisg->completion);
813
+
814
+
pm_runtime_put(&spisg->pdev->dev);
815
+
816
+
return 0;
817
+
out_clk:
818
+
if (spisg->core)
819
+
clk_disable_unprepare(spisg->core);
820
+
clk_disable_unprepare(spisg->pclk);
821
+
out_controller:
822
+
spi_controller_put(ctlr);
823
+
824
+
return ret;
825
+
}
826
+
827
+
static void aml_spisg_remove(struct platform_device *pdev)
828
+
{
829
+
struct spisg_device *spisg = platform_get_drvdata(pdev);
830
+
831
+
if (!pm_runtime_suspended(&pdev->dev)) {
832
+
pinctrl_pm_select_sleep_state(&spisg->pdev->dev);
833
+
clk_disable_unprepare(spisg->core);
834
+
clk_disable_unprepare(spisg->pclk);
835
+
}
836
+
}
837
+
838
+
static int spisg_suspend_runtime(struct device *dev)
839
+
{
840
+
struct spisg_device *spisg = dev_get_drvdata(dev);
841
+
842
+
pinctrl_pm_select_sleep_state(&spisg->pdev->dev);
843
+
clk_disable_unprepare(spisg->sclk);
844
+
clk_disable_unprepare(spisg->core);
845
+
846
+
return 0;
847
+
}
848
+
849
+
static int spisg_resume_runtime(struct device *dev)
850
+
{
851
+
struct spisg_device *spisg = dev_get_drvdata(dev);
852
+
853
+
clk_prepare_enable(spisg->core);
854
+
clk_prepare_enable(spisg->sclk);
855
+
pinctrl_pm_select_default_state(&spisg->pdev->dev);
856
+
857
+
return 0;
858
+
}
859
+
860
+
static const struct dev_pm_ops amlogic_spisg_pm_ops = {
861
+
.runtime_suspend = spisg_suspend_runtime,
862
+
.runtime_resume = spisg_resume_runtime,
863
+
};
864
+
865
+
static const struct of_device_id amlogic_spisg_of_match[] = {
866
+
{
867
+
.compatible = "amlogic,a4-spisg",
868
+
},
869
+
870
+
{ /* sentinel */ }
871
+
};
872
+
MODULE_DEVICE_TABLE(of, amlogic_spisg_of_match);
873
+
874
+
static struct platform_driver amlogic_spisg_driver = {
875
+
.probe = aml_spisg_probe,
876
+
.remove = aml_spisg_remove,
877
+
.driver = {
878
+
.name = "amlogic-spisg",
879
+
.of_match_table = amlogic_spisg_of_match,
880
+
.pm = &amlogic_spisg_pm_ops,
881
+
},
882
+
};
883
+
884
+
module_platform_driver(amlogic_spisg_driver);
885
+
886
+
MODULE_DESCRIPTION("Amlogic SPI Scatter-Gather Controller driver");
887
+
MODULE_AUTHOR("Sunny Luo <sunny.luo@amlogic.com>");
888
+
MODULE_LICENSE("GPL");
-2
drivers/spi/spi-cadence-quadspi.c
-2
drivers/spi/spi-cadence-quadspi.c
···
1469
1469
1470
1470
ret = cqspi_mem_process(mem, op);
1471
1471
1472
-
pm_runtime_mark_last_busy(dev);
1473
1472
pm_runtime_put_autosuspend(dev);
1474
1473
1475
1474
if (ret)
···
1969
1970
goto probe_setup_failed;
1970
1971
}
1971
1972
1972
-
pm_runtime_mark_last_busy(dev);
1973
1973
pm_runtime_put_autosuspend(dev);
1974
1974
1975
1975
return 0;
-1
drivers/spi/spi-cadence.c
-1
drivers/spi/spi-cadence.c
+3
-2
drivers/spi/spi-falcon.c
+3
-2
drivers/spi/spi-falcon.c
···
94
94
struct spi_controller *host;
95
95
};
96
96
97
-
int falcon_sflash_xfer(struct spi_device *spi, struct spi_transfer *t,
98
-
unsigned long flags)
97
+
static int
98
+
falcon_sflash_xfer(struct spi_device *spi, struct spi_transfer *t,
99
+
unsigned long flags)
99
100
{
100
101
struct device *dev = &spi->dev;
101
102
struct falcon_sflash *priv = spi_controller_get_devdata(spi->controller);
+233
-123
drivers/spi/spi-fsl-dspi.c
+233
-123
drivers/spi/spi-fsl-dspi.c
···
24
24
25
25
#define SPI_MCR 0x00
26
26
#define SPI_MCR_HOST BIT(31)
27
+
#define SPI_MCR_MTFE BIT(26)
27
28
#define SPI_MCR_PCSIS(x) ((x) << 16)
28
29
#define SPI_MCR_CLR_TXF BIT(11)
29
30
#define SPI_MCR_CLR_RXF BIT(10)
···
36
35
#define SPI_TCR 0x08
37
36
#define SPI_TCR_GET_TCNT(x) (((x) & GENMASK(31, 16)) >> 16)
38
37
39
-
#define SPI_CTAR(x) (0x0c + (((x) & GENMASK(1, 0)) * 4))
38
+
#define SPI_CTAR(x) (0x0c + (((x) & GENMASK(2, 0)) * 4))
40
39
#define SPI_CTAR_FMSZ(x) (((x) << 27) & GENMASK(30, 27))
40
+
#define SPI_CTAR_DBR BIT(31)
41
41
#define SPI_CTAR_CPOL BIT(26)
42
42
#define SPI_CTAR_CPHA BIT(25)
43
43
#define SPI_CTAR_LSBFE BIT(24)
···
95
93
#define SPI_TXFR1 0x40
96
94
#define SPI_TXFR2 0x44
97
95
#define SPI_TXFR3 0x48
96
+
#define SPI_TXFR4 0x4C
98
97
#define SPI_RXFR0 0x7c
99
98
#define SPI_RXFR1 0x80
100
99
#define SPI_RXFR2 0x84
101
100
#define SPI_RXFR3 0x88
101
+
#define SPI_RXFR4 0x8C
102
102
103
-
#define SPI_CTARE(x) (0x11c + (((x) & GENMASK(1, 0)) * 4))
103
+
#define SPI_CTARE(x) (0x11c + (((x) & GENMASK(2, 0)) * 4))
104
104
#define SPI_CTARE_FMSZE(x) (((x) & 0x1) << 16)
105
105
#define SPI_CTARE_DTCP(x) ((x) & 0x7ff)
106
106
···
112
108
#define SPI_FRAME_EBITS(bits) SPI_CTARE_FMSZE(((bits) - 1) >> 4)
113
109
114
110
#define DMA_COMPLETION_TIMEOUT msecs_to_jiffies(3000)
111
+
112
+
#define SPI_25MHZ 25000000
115
113
116
114
struct chip_data {
117
115
u32 ctar_val;
···
128
122
enum dspi_trans_mode trans_mode;
129
123
u8 max_clock_factor;
130
124
int fifo_size;
125
+
const struct regmap_config *regmap;
131
126
};
132
127
133
128
enum {
···
142
135
LX2160A,
143
136
MCF5441X,
144
137
VF610,
138
+
S32G,
139
+
S32G_TARGET,
140
+
};
141
+
142
+
static const struct regmap_range dspi_yes_ranges[] = {
143
+
regmap_reg_range(SPI_MCR, SPI_MCR),
144
+
regmap_reg_range(SPI_TCR, SPI_CTAR(3)),
145
+
regmap_reg_range(SPI_SR, SPI_TXFR3),
146
+
regmap_reg_range(SPI_RXFR0, SPI_RXFR3),
147
+
regmap_reg_range(SPI_CTARE(0), SPI_CTARE(3)),
148
+
regmap_reg_range(SPI_SREX, SPI_SREX),
149
+
};
150
+
151
+
static const struct regmap_range s32g_dspi_yes_ranges[] = {
152
+
regmap_reg_range(SPI_MCR, SPI_MCR),
153
+
regmap_reg_range(SPI_TCR, SPI_CTAR(5)),
154
+
regmap_reg_range(SPI_SR, SPI_TXFR4),
155
+
regmap_reg_range(SPI_RXFR0, SPI_RXFR4),
156
+
regmap_reg_range(SPI_CTARE(0), SPI_CTARE(5)),
157
+
regmap_reg_range(SPI_SREX, SPI_SREX),
158
+
};
159
+
160
+
static const struct regmap_access_table dspi_access_table = {
161
+
.yes_ranges = dspi_yes_ranges,
162
+
.n_yes_ranges = ARRAY_SIZE(dspi_yes_ranges),
163
+
};
164
+
165
+
static const struct regmap_access_table s32g_dspi_access_table = {
166
+
.yes_ranges = s32g_dspi_yes_ranges,
167
+
.n_yes_ranges = ARRAY_SIZE(s32g_dspi_yes_ranges),
168
+
};
169
+
170
+
static const struct regmap_range dspi_volatile_ranges[] = {
171
+
regmap_reg_range(SPI_MCR, SPI_TCR),
172
+
regmap_reg_range(SPI_SR, SPI_SR),
173
+
regmap_reg_range(SPI_PUSHR, SPI_RXFR4),
174
+
regmap_reg_range(SPI_SREX, SPI_SREX),
175
+
};
176
+
177
+
static const struct regmap_access_table dspi_volatile_table = {
178
+
.yes_ranges = dspi_volatile_ranges,
179
+
.n_yes_ranges = ARRAY_SIZE(dspi_volatile_ranges),
180
+
};
181
+
182
+
enum {
183
+
DSPI_REGMAP,
184
+
S32G_DSPI_REGMAP,
185
+
DSPI_XSPI_REGMAP,
186
+
S32G_DSPI_XSPI_REGMAP,
187
+
DSPI_PUSHR,
188
+
};
189
+
190
+
static const struct regmap_config dspi_regmap_config[] = {
191
+
[DSPI_REGMAP] = {
192
+
.reg_bits = 32,
193
+
.val_bits = 32,
194
+
.reg_stride = 4,
195
+
.max_register = SPI_RXFR3,
196
+
.volatile_table = &dspi_volatile_table,
197
+
.rd_table = &dspi_access_table,
198
+
.wr_table = &dspi_access_table,
199
+
},
200
+
[S32G_DSPI_REGMAP] = {
201
+
.reg_bits = 32,
202
+
.val_bits = 32,
203
+
.reg_stride = 4,
204
+
.max_register = SPI_RXFR4,
205
+
.volatile_table = &dspi_volatile_table,
206
+
.wr_table = &s32g_dspi_access_table,
207
+
.rd_table = &s32g_dspi_access_table,
208
+
},
209
+
[DSPI_XSPI_REGMAP] = {
210
+
.reg_bits = 32,
211
+
.val_bits = 32,
212
+
.reg_stride = 4,
213
+
.max_register = SPI_SREX,
214
+
.volatile_table = &dspi_volatile_table,
215
+
.rd_table = &dspi_access_table,
216
+
.wr_table = &dspi_access_table,
217
+
},
218
+
[S32G_DSPI_XSPI_REGMAP] = {
219
+
.reg_bits = 32,
220
+
.val_bits = 32,
221
+
.reg_stride = 4,
222
+
.max_register = SPI_SREX,
223
+
.volatile_table = &dspi_volatile_table,
224
+
.wr_table = &s32g_dspi_access_table,
225
+
.rd_table = &s32g_dspi_access_table,
226
+
},
227
+
[DSPI_PUSHR] = {
228
+
.name = "pushr",
229
+
.reg_bits = 16,
230
+
.val_bits = 16,
231
+
.reg_stride = 2,
232
+
.max_register = 0x2,
233
+
},
145
234
};
146
235
147
236
static const struct fsl_dspi_devtype_data devtype_data[] = {
···
245
142
.trans_mode = DSPI_DMA_MODE,
246
143
.max_clock_factor = 2,
247
144
.fifo_size = 4,
145
+
.regmap = &dspi_regmap_config[DSPI_REGMAP],
248
146
},
249
147
[LS1021A] = {
250
148
/* Has A-011218 DMA erratum */
251
149
.trans_mode = DSPI_XSPI_MODE,
252
150
.max_clock_factor = 8,
253
151
.fifo_size = 4,
152
+
.regmap = &dspi_regmap_config[DSPI_XSPI_REGMAP],
254
153
},
255
154
[LS1012A] = {
256
155
/* Has A-011218 DMA erratum */
257
156
.trans_mode = DSPI_XSPI_MODE,
258
157
.max_clock_factor = 8,
259
158
.fifo_size = 16,
159
+
.regmap = &dspi_regmap_config[DSPI_XSPI_REGMAP],
260
160
},
261
161
[LS1028A] = {
262
162
.trans_mode = DSPI_XSPI_MODE,
263
163
.max_clock_factor = 8,
264
164
.fifo_size = 4,
165
+
.regmap = &dspi_regmap_config[DSPI_XSPI_REGMAP],
265
166
},
266
167
[LS1043A] = {
267
168
/* Has A-011218 DMA erratum */
268
169
.trans_mode = DSPI_XSPI_MODE,
269
170
.max_clock_factor = 8,
270
171
.fifo_size = 16,
172
+
.regmap = &dspi_regmap_config[DSPI_XSPI_REGMAP],
271
173
},
272
174
[LS1046A] = {
273
175
/* Has A-011218 DMA erratum */
274
176
.trans_mode = DSPI_XSPI_MODE,
275
177
.max_clock_factor = 8,
276
178
.fifo_size = 16,
179
+
.regmap = &dspi_regmap_config[DSPI_XSPI_REGMAP],
277
180
},
278
181
[LS2080A] = {
279
182
.trans_mode = DSPI_XSPI_MODE,
280
183
.max_clock_factor = 8,
281
184
.fifo_size = 4,
185
+
.regmap = &dspi_regmap_config[DSPI_XSPI_REGMAP],
282
186
},
283
187
[LS2085A] = {
284
188
.trans_mode = DSPI_XSPI_MODE,
285
189
.max_clock_factor = 8,
286
190
.fifo_size = 4,
191
+
.regmap = &dspi_regmap_config[DSPI_XSPI_REGMAP],
287
192
},
288
193
[LX2160A] = {
289
194
.trans_mode = DSPI_XSPI_MODE,
290
195
.max_clock_factor = 8,
291
196
.fifo_size = 4,
197
+
.regmap = &dspi_regmap_config[DSPI_XSPI_REGMAP],
292
198
},
293
199
[MCF5441X] = {
294
200
.trans_mode = DSPI_DMA_MODE,
295
201
.max_clock_factor = 8,
296
202
.fifo_size = 16,
203
+
.regmap = &dspi_regmap_config[DSPI_REGMAP],
204
+
},
205
+
[S32G] = {
206
+
.trans_mode = DSPI_XSPI_MODE,
207
+
.max_clock_factor = 1,
208
+
.fifo_size = 5,
209
+
.regmap = &dspi_regmap_config[S32G_DSPI_XSPI_REGMAP],
210
+
},
211
+
[S32G_TARGET] = {
212
+
.trans_mode = DSPI_DMA_MODE,
213
+
.max_clock_factor = 1,
214
+
.fifo_size = 5,
215
+
.regmap = &dspi_regmap_config[S32G_DSPI_REGMAP],
297
216
},
298
217
};
299
218
···
350
225
const void *tx;
351
226
void *rx;
352
227
u16 tx_cmd;
228
+
bool mtf_enabled;
353
229
const struct fsl_dspi_devtype_data *devtype_data;
354
230
355
231
struct completion xfer_done;
···
372
246
void (*host_to_dev)(struct fsl_dspi *dspi, u32 *txdata);
373
247
void (*dev_to_host)(struct fsl_dspi *dspi, u32 rxdata);
374
248
};
249
+
250
+
static bool is_s32g_dspi(struct fsl_dspi *data)
251
+
{
252
+
return data->devtype_data == &devtype_data[S32G] ||
253
+
data->devtype_data == &devtype_data[S32G_TARGET];
254
+
}
375
255
376
256
static void dspi_native_host_to_dev(struct fsl_dspi *dspi, u32 *txdata)
377
257
{
···
727
595
}
728
596
729
597
static void hz_to_spi_baud(char *pbr, char *br, int speed_hz,
730
-
unsigned long clkrate)
598
+
unsigned long clkrate, bool mtf_enabled)
731
599
{
732
600
/* Valid baud rate pre-scaler values */
733
601
int pbr_tbl[4] = {2, 3, 5, 7};
···
744
612
745
613
for (i = 0; i < ARRAY_SIZE(brs); i++)
746
614
for (j = 0; j < ARRAY_SIZE(pbr_tbl); j++) {
747
-
scale = brs[i] * pbr_tbl[j];
615
+
if (mtf_enabled) {
616
+
/* In MTF mode DBR=1 so frequency is doubled */
617
+
scale = (brs[i] * pbr_tbl[j]) / 2;
618
+
} else {
619
+
scale = brs[i] * pbr_tbl[j];
620
+
}
621
+
748
622
if (scale >= scale_needed) {
749
623
if (scale < minscale) {
750
624
minscale = scale;
···
884
746
struct spi_transfer *xfer = dspi->cur_transfer;
885
747
bool odd = !!(dspi->len & 1);
886
748
887
-
/* No accel for frames not multiple of 8 bits at the moment */
888
-
if (xfer->bits_per_word % 8)
749
+
/*
750
+
* No accel for DMA transfers or frames not multiples of 8 bits at the
751
+
* moment.
752
+
*/
753
+
if (dspi->devtype_data->trans_mode == DSPI_DMA_MODE ||
754
+
xfer->bits_per_word % 8)
889
755
goto no_accel;
890
756
891
757
if (!odd && dspi->len <= dspi->devtype_data->fifo_size * 2) {
···
898
756
dspi->oper_bits_per_word = 8;
899
757
} else {
900
758
/* Start off with maximum supported by hardware */
901
-
if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE)
902
-
dspi->oper_bits_per_word = 32;
903
-
else
904
-
dspi->oper_bits_per_word = 16;
759
+
dspi->oper_bits_per_word = 32;
905
760
906
761
/*
907
762
* And go down only if the buffer can't be sent with
···
1166
1027
return status;
1167
1028
}
1168
1029
1030
+
static int dspi_set_mtf(struct fsl_dspi *dspi)
1031
+
{
1032
+
if (spi_controller_is_target(dspi->ctlr))
1033
+
return 0;
1034
+
1035
+
if (dspi->mtf_enabled)
1036
+
regmap_update_bits(dspi->regmap, SPI_MCR, SPI_MCR_MTFE,
1037
+
SPI_MCR_MTFE);
1038
+
else
1039
+
regmap_update_bits(dspi->regmap, SPI_MCR, SPI_MCR_MTFE, 0);
1040
+
1041
+
return 0;
1042
+
}
1043
+
1169
1044
static int dspi_setup(struct spi_device *spi)
1170
1045
{
1171
1046
struct fsl_dspi *dspi = spi_controller_get_devdata(spi->controller);
···
1238
1085
cs_sck_delay, sck_cs_delay);
1239
1086
1240
1087
clkrate = clk_get_rate(dspi->clk);
1241
-
hz_to_spi_baud(&pbr, &br, spi->max_speed_hz, clkrate);
1088
+
1089
+
if (is_s32g_dspi(dspi) && spi->max_speed_hz > SPI_25MHZ)
1090
+
dspi->mtf_enabled = true;
1091
+
else
1092
+
dspi->mtf_enabled = false;
1093
+
1094
+
dspi_set_mtf(dspi);
1095
+
1096
+
hz_to_spi_baud(&pbr, &br, spi->max_speed_hz, clkrate,
1097
+
dspi->mtf_enabled);
1242
1098
1243
1099
/* Set PCS to SCK delay scale values */
1244
1100
ns_delay_scale(&pcssck, &cssck, cs_sck_delay, clkrate);
···
1268
1106
SPI_CTAR_ASC(asc) |
1269
1107
SPI_CTAR_PBR(pbr) |
1270
1108
SPI_CTAR_BR(br);
1109
+
1110
+
if (dspi->mtf_enabled)
1111
+
chip->ctar_val |= SPI_CTAR_DBR;
1271
1112
1272
1113
if (spi->mode & SPI_LSB_FIRST)
1273
1114
chip->ctar_val |= SPI_CTAR_LSBFE;
···
1325
1160
}, {
1326
1161
.compatible = "fsl,lx2160a-dspi",
1327
1162
.data = &devtype_data[LX2160A],
1163
+
}, {
1164
+
.compatible = "nxp,s32g2-dspi",
1165
+
.data = &devtype_data[S32G],
1328
1166
},
1329
1167
{ /* sentinel */ }
1330
1168
};
1331
1169
MODULE_DEVICE_TABLE(of, fsl_dspi_dt_ids);
1332
-
1333
-
#ifdef CONFIG_PM_SLEEP
1334
-
static int dspi_suspend(struct device *dev)
1335
-
{
1336
-
struct fsl_dspi *dspi = dev_get_drvdata(dev);
1337
-
1338
-
if (dspi->irq)
1339
-
disable_irq(dspi->irq);
1340
-
spi_controller_suspend(dspi->ctlr);
1341
-
clk_disable_unprepare(dspi->clk);
1342
-
1343
-
pinctrl_pm_select_sleep_state(dev);
1344
-
1345
-
return 0;
1346
-
}
1347
-
1348
-
static int dspi_resume(struct device *dev)
1349
-
{
1350
-
struct fsl_dspi *dspi = dev_get_drvdata(dev);
1351
-
int ret;
1352
-
1353
-
pinctrl_pm_select_default_state(dev);
1354
-
1355
-
ret = clk_prepare_enable(dspi->clk);
1356
-
if (ret)
1357
-
return ret;
1358
-
spi_controller_resume(dspi->ctlr);
1359
-
if (dspi->irq)
1360
-
enable_irq(dspi->irq);
1361
-
1362
-
return 0;
1363
-
}
1364
-
#endif /* CONFIG_PM_SLEEP */
1365
-
1366
-
static SIMPLE_DEV_PM_OPS(dspi_pm, dspi_suspend, dspi_resume);
1367
-
1368
-
static const struct regmap_range dspi_yes_ranges[] = {
1369
-
regmap_reg_range(SPI_MCR, SPI_MCR),
1370
-
regmap_reg_range(SPI_TCR, SPI_CTAR(3)),
1371
-
regmap_reg_range(SPI_SR, SPI_TXFR3),
1372
-
regmap_reg_range(SPI_RXFR0, SPI_RXFR3),
1373
-
regmap_reg_range(SPI_CTARE(0), SPI_CTARE(3)),
1374
-
regmap_reg_range(SPI_SREX, SPI_SREX),
1375
-
};
1376
-
1377
-
static const struct regmap_access_table dspi_access_table = {
1378
-
.yes_ranges = dspi_yes_ranges,
1379
-
.n_yes_ranges = ARRAY_SIZE(dspi_yes_ranges),
1380
-
};
1381
-
1382
-
static const struct regmap_range dspi_volatile_ranges[] = {
1383
-
regmap_reg_range(SPI_MCR, SPI_TCR),
1384
-
regmap_reg_range(SPI_SR, SPI_SR),
1385
-
regmap_reg_range(SPI_PUSHR, SPI_RXFR3),
1386
-
};
1387
-
1388
-
static const struct regmap_access_table dspi_volatile_table = {
1389
-
.yes_ranges = dspi_volatile_ranges,
1390
-
.n_yes_ranges = ARRAY_SIZE(dspi_volatile_ranges),
1391
-
};
1392
-
1393
-
static const struct regmap_config dspi_regmap_config = {
1394
-
.reg_bits = 32,
1395
-
.val_bits = 32,
1396
-
.reg_stride = 4,
1397
-
.max_register = 0x88,
1398
-
.volatile_table = &dspi_volatile_table,
1399
-
.rd_table = &dspi_access_table,
1400
-
.wr_table = &dspi_access_table,
1401
-
};
1402
-
1403
-
static const struct regmap_range dspi_xspi_volatile_ranges[] = {
1404
-
regmap_reg_range(SPI_MCR, SPI_TCR),
1405
-
regmap_reg_range(SPI_SR, SPI_SR),
1406
-
regmap_reg_range(SPI_PUSHR, SPI_RXFR3),
1407
-
regmap_reg_range(SPI_SREX, SPI_SREX),
1408
-
};
1409
-
1410
-
static const struct regmap_access_table dspi_xspi_volatile_table = {
1411
-
.yes_ranges = dspi_xspi_volatile_ranges,
1412
-
.n_yes_ranges = ARRAY_SIZE(dspi_xspi_volatile_ranges),
1413
-
};
1414
-
1415
-
static const struct regmap_config dspi_xspi_regmap_config[] = {
1416
-
{
1417
-
.reg_bits = 32,
1418
-
.val_bits = 32,
1419
-
.reg_stride = 4,
1420
-
.max_register = 0x13c,
1421
-
.volatile_table = &dspi_xspi_volatile_table,
1422
-
.rd_table = &dspi_access_table,
1423
-
.wr_table = &dspi_access_table,
1424
-
},
1425
-
{
1426
-
.name = "pushr",
1427
-
.reg_bits = 16,
1428
-
.val_bits = 16,
1429
-
.reg_stride = 2,
1430
-
.max_register = 0x2,
1431
-
},
1432
-
};
1433
1170
1434
1171
static int dspi_init(struct fsl_dspi *dspi)
1435
1172
{
···
1368
1301
return 0;
1369
1302
}
1370
1303
1304
+
#ifdef CONFIG_PM_SLEEP
1305
+
static int dspi_suspend(struct device *dev)
1306
+
{
1307
+
struct fsl_dspi *dspi = dev_get_drvdata(dev);
1308
+
1309
+
if (dspi->irq)
1310
+
disable_irq(dspi->irq);
1311
+
spi_controller_suspend(dspi->ctlr);
1312
+
clk_disable_unprepare(dspi->clk);
1313
+
1314
+
pinctrl_pm_select_sleep_state(dev);
1315
+
1316
+
return 0;
1317
+
}
1318
+
1319
+
static int dspi_resume(struct device *dev)
1320
+
{
1321
+
struct fsl_dspi *dspi = dev_get_drvdata(dev);
1322
+
int ret;
1323
+
1324
+
pinctrl_pm_select_default_state(dev);
1325
+
1326
+
ret = clk_prepare_enable(dspi->clk);
1327
+
if (ret)
1328
+
return ret;
1329
+
spi_controller_resume(dspi->ctlr);
1330
+
1331
+
ret = dspi_init(dspi);
1332
+
if (ret) {
1333
+
dev_err(dev, "failed to initialize dspi during resume\n");
1334
+
return ret;
1335
+
}
1336
+
1337
+
dspi_set_mtf(dspi);
1338
+
1339
+
if (dspi->irq)
1340
+
enable_irq(dspi->irq);
1341
+
1342
+
return 0;
1343
+
}
1344
+
#endif /* CONFIG_PM_SLEEP */
1345
+
1346
+
static SIMPLE_DEV_PM_OPS(dspi_pm, dspi_suspend, dspi_resume);
1347
+
1371
1348
static int dspi_target_abort(struct spi_controller *host)
1372
1349
{
1373
1350
struct fsl_dspi *dspi = spi_controller_get_devdata(host);
···
1436
1325
static int dspi_probe(struct platform_device *pdev)
1437
1326
{
1438
1327
struct device_node *np = pdev->dev.of_node;
1439
-
const struct regmap_config *regmap_config;
1440
1328
struct fsl_dspi_platform_data *pdata;
1441
1329
struct spi_controller *ctlr;
1442
1330
int ret, cs_num, bus_num = -1;
···
1448
1338
if (!dspi)
1449
1339
return -ENOMEM;
1450
1340
1451
-
ctlr = spi_alloc_host(&pdev->dev, 0);
1341
+
if (of_property_read_bool(np, "spi-slave"))
1342
+
ctlr = spi_alloc_target(&pdev->dev, 0);
1343
+
else
1344
+
ctlr = spi_alloc_host(&pdev->dev, 0);
1452
1345
if (!ctlr)
1453
1346
return -ENOMEM;
1454
1347
···
1490
1377
of_property_read_u32(np, "bus-num", &bus_num);
1491
1378
ctlr->bus_num = bus_num;
1492
1379
1493
-
if (of_property_read_bool(np, "spi-slave"))
1494
-
ctlr->target = true;
1495
-
1496
1380
dspi->devtype_data = of_device_get_match_data(&pdev->dev);
1497
1381
if (!dspi->devtype_data) {
1498
1382
dev_err(&pdev->dev, "can't get devtype_data\n");
···
1507
1397
dspi->pushr_tx = 0;
1508
1398
}
1509
1399
1400
+
if (spi_controller_is_target(ctlr) && is_s32g_dspi(dspi))
1401
+
dspi->devtype_data = &devtype_data[S32G_TARGET];
1402
+
1510
1403
if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE)
1511
1404
ctlr->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1512
1405
else
···
1521
1408
goto out_ctlr_put;
1522
1409
}
1523
1410
1524
-
if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE)
1525
-
regmap_config = &dspi_xspi_regmap_config[0];
1526
-
else
1527
-
regmap_config = &dspi_regmap_config;
1528
-
dspi->regmap = devm_regmap_init_mmio(&pdev->dev, base, regmap_config);
1411
+
dspi->regmap = devm_regmap_init_mmio(&pdev->dev, base,
1412
+
dspi->devtype_data->regmap);
1529
1413
if (IS_ERR(dspi->regmap)) {
1530
1414
dev_err(&pdev->dev, "failed to init regmap: %ld\n",
1531
1415
PTR_ERR(dspi->regmap));
···
1533
1423
if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE) {
1534
1424
dspi->regmap_pushr = devm_regmap_init_mmio(
1535
1425
&pdev->dev, base + SPI_PUSHR,
1536
-
&dspi_xspi_regmap_config[1]);
1426
+
&dspi_regmap_config[DSPI_PUSHR]);
1537
1427
if (IS_ERR(dspi->regmap_pushr)) {
1538
1428
dev_err(&pdev->dev,
1539
1429
"failed to init pushr regmap: %ld\n",
-2
drivers/spi/spi-fsl-espi.c
-2
drivers/spi/spi-fsl-espi.c
···
513
513
514
514
fsl_espi_setup_transfer(spi, NULL);
515
515
516
-
pm_runtime_mark_last_busy(espi->dev);
517
516
pm_runtime_put_autosuspend(espi->dev);
518
517
519
518
return 0;
···
725
726
726
727
dev_info(dev, "irq = %u\n", irq);
727
728
728
-
pm_runtime_mark_last_busy(dev);
729
729
pm_runtime_put_autosuspend(dev);
730
730
731
731
return 0;
-2
drivers/spi/spi-fsl-lpspi.c
-2
drivers/spi/spi-fsl-lpspi.c
···
233
233
struct fsl_lpspi_data *fsl_lpspi =
234
234
spi_controller_get_devdata(controller);
235
235
236
-
pm_runtime_mark_last_busy(fsl_lpspi->dev);
237
236
pm_runtime_put_autosuspend(fsl_lpspi->dev);
238
237
239
238
return 0;
···
965
966
goto free_dma;
966
967
}
967
968
968
-
pm_runtime_mark_last_busy(fsl_lpspi->dev);
969
969
pm_runtime_put_autosuspend(fsl_lpspi->dev);
970
970
971
971
return 0;
+8
-8
drivers/spi/spi-gpio.c
+8
-8
drivers/spi/spi-gpio.c
···
104
104
*/
105
105
106
106
static u32 spi_gpio_txrx_word_mode0(struct spi_device *spi,
107
-
unsigned nsecs, u32 word, u8 bits, unsigned flags)
107
+
unsigned int nsecs, u32 word, u8 bits, unsigned int flags)
108
108
{
109
109
if (unlikely(spi->mode & SPI_LSB_FIRST))
110
110
return bitbang_txrx_le_cpha0(spi, nsecs, 0, flags, word, bits);
···
113
113
}
114
114
115
115
static u32 spi_gpio_txrx_word_mode1(struct spi_device *spi,
116
-
unsigned nsecs, u32 word, u8 bits, unsigned flags)
116
+
unsigned int nsecs, u32 word, u8 bits, unsigned int flags)
117
117
{
118
118
if (unlikely(spi->mode & SPI_LSB_FIRST))
119
119
return bitbang_txrx_le_cpha1(spi, nsecs, 0, flags, word, bits);
···
122
122
}
123
123
124
124
static u32 spi_gpio_txrx_word_mode2(struct spi_device *spi,
125
-
unsigned nsecs, u32 word, u8 bits, unsigned flags)
125
+
unsigned int nsecs, u32 word, u8 bits, unsigned int flags)
126
126
{
127
127
if (unlikely(spi->mode & SPI_LSB_FIRST))
128
128
return bitbang_txrx_le_cpha0(spi, nsecs, 1, flags, word, bits);
···
131
131
}
132
132
133
133
static u32 spi_gpio_txrx_word_mode3(struct spi_device *spi,
134
-
unsigned nsecs, u32 word, u8 bits, unsigned flags)
134
+
unsigned int nsecs, u32 word, u8 bits, unsigned int flags)
135
135
{
136
136
if (unlikely(spi->mode & SPI_LSB_FIRST))
137
137
return bitbang_txrx_le_cpha1(spi, nsecs, 1, flags, word, bits);
···
150
150
*/
151
151
152
152
static u32 spi_gpio_spec_txrx_word_mode0(struct spi_device *spi,
153
-
unsigned nsecs, u32 word, u8 bits, unsigned flags)
153
+
unsigned int nsecs, u32 word, u8 bits, unsigned int flags)
154
154
{
155
155
flags = spi->controller->flags;
156
156
if (unlikely(spi->mode & SPI_LSB_FIRST))
···
160
160
}
161
161
162
162
static u32 spi_gpio_spec_txrx_word_mode1(struct spi_device *spi,
163
-
unsigned nsecs, u32 word, u8 bits, unsigned flags)
163
+
unsigned int nsecs, u32 word, u8 bits, unsigned int flags)
164
164
{
165
165
flags = spi->controller->flags;
166
166
if (unlikely(spi->mode & SPI_LSB_FIRST))
···
170
170
}
171
171
172
172
static u32 spi_gpio_spec_txrx_word_mode2(struct spi_device *spi,
173
-
unsigned nsecs, u32 word, u8 bits, unsigned flags)
173
+
unsigned int nsecs, u32 word, u8 bits, unsigned int flags)
174
174
{
175
175
flags = spi->controller->flags;
176
176
if (unlikely(spi->mode & SPI_LSB_FIRST))
···
180
180
}
181
181
182
182
static u32 spi_gpio_spec_txrx_word_mode3(struct spi_device *spi,
183
-
unsigned nsecs, u32 word, u8 bits, unsigned flags)
183
+
unsigned int nsecs, u32 word, u8 bits, unsigned int flags)
184
184
{
185
185
flags = spi->controller->flags;
186
186
if (unlikely(spi->mode & SPI_LSB_FIRST))
-3
drivers/spi/spi-imx.c
-3
drivers/spi/spi-imx.c
···
1748
1748
1749
1749
ret = spi_imx->devtype_data->prepare_message(spi_imx, msg);
1750
1750
if (ret) {
1751
-
pm_runtime_mark_last_busy(spi_imx->dev);
1752
1751
pm_runtime_put_autosuspend(spi_imx->dev);
1753
1752
}
1754
1753
···
1759
1760
{
1760
1761
struct spi_imx_data *spi_imx = spi_controller_get_devdata(controller);
1761
1762
1762
-
pm_runtime_mark_last_busy(spi_imx->dev);
1763
1763
pm_runtime_put_autosuspend(spi_imx->dev);
1764
1764
return 0;
1765
1765
}
···
1931
1933
goto out_register_controller;
1932
1934
}
1933
1935
1934
-
pm_runtime_mark_last_busy(spi_imx->dev);
1935
1936
pm_runtime_put_autosuspend(spi_imx->dev);
1936
1937
1937
1938
return ret;
+10
-3
drivers/spi/spi-intel.c
+10
-3
drivers/spi/spi-intel.c
···
189
189
static bool writeable;
190
190
module_param(writeable, bool, 0);
191
191
MODULE_PARM_DESC(writeable, "Enable write access to SPI flash chip (default=0)");
192
+
static bool ignore_protection_status;
193
+
module_param(ignore_protection_status, bool, 0);
194
+
MODULE_PARM_DESC(
195
+
ignore_protection_status,
196
+
"Do not block SPI flash chip write access even if it is write-protected (default=0)");
192
197
193
198
static void intel_spi_dump_regs(struct intel_spi *ispi)
194
199
{
···
1253
1248
continue;
1254
1249
1255
1250
/*
1256
-
* If any of the regions have protection bits set, make the
1257
-
* whole partition read-only to be on the safe side.
1251
+
* If any of the regions have protection bits set and
1252
+
* the ignore protection status parameter is not set,
1253
+
* make the whole partition read-only to be on the safe side.
1258
1254
*
1259
1255
* Also if the user did not ask the chip to be writeable
1260
1256
* mask the bit too.
1261
1257
*/
1262
-
if (!writeable || intel_spi_is_protected(ispi, base, limit)) {
1258
+
if (!writeable || (!ignore_protection_status &&
1259
+
intel_spi_is_protected(ispi, base, limit))) {
1263
1260
part->mask_flags |= MTD_WRITEABLE;
1264
1261
ispi->protected = true;
1265
1262
}
+204
-22
drivers/spi/spi-microchip-core-qspi.c
+204
-22
drivers/spi/spi-microchip-core-qspi.c
···
194
194
}
195
195
}
196
196
197
-
static inline void mchp_coreqspi_write_op(struct mchp_coreqspi *qspi, bool word)
197
+
static inline void mchp_coreqspi_write_op(struct mchp_coreqspi *qspi)
198
198
{
199
199
u32 control, data;
200
200
···
219
219
;
220
220
data = *qspi->txbuf++;
221
221
writel_relaxed(data, qspi->regs + REG_TX_DATA);
222
+
}
223
+
}
224
+
225
+
static inline void mchp_coreqspi_write_read_op(struct mchp_coreqspi *qspi)
226
+
{
227
+
u32 control, data;
228
+
229
+
qspi->rx_len = qspi->tx_len;
230
+
231
+
control = readl_relaxed(qspi->regs + REG_CONTROL);
232
+
control |= CONTROL_FLAGSX4;
233
+
writel_relaxed(control, qspi->regs + REG_CONTROL);
234
+
235
+
while (qspi->tx_len >= 4) {
236
+
while (readl_relaxed(qspi->regs + REG_STATUS) & STATUS_TXFIFOFULL)
237
+
;
238
+
239
+
data = qspi->txbuf ? *((u32 *)qspi->txbuf) : 0xaa;
240
+
if (qspi->txbuf)
241
+
qspi->txbuf += 4;
242
+
qspi->tx_len -= 4;
243
+
writel_relaxed(data, qspi->regs + REG_X4_TX_DATA);
244
+
245
+
/*
246
+
* The rx FIFO is twice the size of the tx FIFO, so there is
247
+
* no requirement to block transmission if receive data is not
248
+
* ready, and it is fine to let the tx FIFO completely fill
249
+
* without reading anything from the rx FIFO. Once the tx FIFO
250
+
* has been filled and becomes non-full due to a transmission
251
+
* occurring there will always be something to receive.
252
+
* IOW, this is safe as TX_FIFO_SIZE + 4 < 2 * TX_FIFO_SIZE
253
+
*/
254
+
if (qspi->rx_len >= 4) {
255
+
if (readl_relaxed(qspi->regs + REG_STATUS) & STATUS_RXAVAILABLE) {
256
+
data = readl_relaxed(qspi->regs + REG_X4_RX_DATA);
257
+
*(u32 *)qspi->rxbuf = data;
258
+
qspi->rxbuf += 4;
259
+
qspi->rx_len -= 4;
260
+
}
261
+
}
262
+
}
263
+
264
+
/*
265
+
* Since transmission is not being blocked by clearing the rx FIFO,
266
+
* loop here until all received data "leaked" by the loop above has
267
+
* been dealt with.
268
+
*/
269
+
while (qspi->rx_len >= 4) {
270
+
while (readl_relaxed(qspi->regs + REG_STATUS) & STATUS_RXFIFOEMPTY)
271
+
;
272
+
data = readl_relaxed(qspi->regs + REG_X4_RX_DATA);
273
+
*(u32 *)qspi->rxbuf = data;
274
+
qspi->rxbuf += 4;
275
+
qspi->rx_len -= 4;
276
+
}
277
+
278
+
/*
279
+
* Since rx_len and tx_len must be < 4 bytes at this point, there's no
280
+
* concern about overflowing the rx or tx FIFOs any longer. It's
281
+
* therefore safe to loop over the remainder of the transmit data before
282
+
* handling the remaining receive data.
283
+
*/
284
+
if (!qspi->tx_len)
285
+
return;
286
+
287
+
control &= ~CONTROL_FLAGSX4;
288
+
writel_relaxed(control, qspi->regs + REG_CONTROL);
289
+
290
+
while (qspi->tx_len--) {
291
+
while (readl_relaxed(qspi->regs + REG_STATUS) & STATUS_TXFIFOFULL)
292
+
;
293
+
data = qspi->txbuf ? *qspi->txbuf : 0xaa;
294
+
qspi->txbuf++;
295
+
writel_relaxed(data, qspi->regs + REG_TX_DATA);
296
+
}
297
+
298
+
while (qspi->rx_len--) {
299
+
while (readl_relaxed(qspi->regs + REG_STATUS) & STATUS_RXFIFOEMPTY)
300
+
;
301
+
data = readl_relaxed(qspi->regs + REG_RX_DATA);
302
+
*qspi->rxbuf++ = (data & 0xFF);
222
303
}
223
304
}
224
305
···
347
266
}
348
267
349
268
static int mchp_coreqspi_setup_clock(struct mchp_coreqspi *qspi, struct spi_device *spi,
350
-
const struct spi_mem_op *op)
269
+
u32 max_freq)
351
270
{
352
271
unsigned long clk_hz;
353
272
u32 control, baud_rate_val = 0;
···
356
275
if (!clk_hz)
357
276
return -EINVAL;
358
277
359
-
baud_rate_val = DIV_ROUND_UP(clk_hz, 2 * op->max_freq);
278
+
baud_rate_val = DIV_ROUND_UP(clk_hz, 2 * max_freq);
360
279
if (baud_rate_val > MAX_DIVIDER || baud_rate_val < MIN_DIVIDER) {
361
280
dev_err(&spi->dev,
362
281
"could not configure the clock for spi clock %d Hz & system clock %ld Hz\n",
363
-
op->max_freq, clk_hz);
282
+
max_freq, clk_hz);
364
283
return -EINVAL;
365
284
}
366
285
···
448
367
writel_relaxed(frames, qspi->regs + REG_FRAMES);
449
368
}
450
369
451
-
static int mchp_qspi_wait_for_ready(struct spi_mem *mem)
370
+
static int mchp_coreqspi_wait_for_ready(struct mchp_coreqspi *qspi)
452
371
{
453
-
struct mchp_coreqspi *qspi = spi_controller_get_devdata
454
-
(mem->spi->controller);
455
372
u32 status;
456
-
int ret;
457
373
458
-
ret = readl_poll_timeout(qspi->regs + REG_STATUS, status,
374
+
return readl_poll_timeout(qspi->regs + REG_STATUS, status,
459
375
(status & STATUS_READY), 0,
460
376
TIMEOUT_MS);
461
-
if (ret) {
462
-
dev_err(&mem->spi->dev,
463
-
"Timeout waiting on QSPI ready.\n");
464
-
return -ETIMEDOUT;
465
-
}
466
-
467
-
return ret;
468
377
}
469
378
470
379
static int mchp_coreqspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
···
467
396
int err, i;
468
397
469
398
mutex_lock(&qspi->op_lock);
470
-
err = mchp_qspi_wait_for_ready(mem);
471
-
if (err)
399
+
err = mchp_coreqspi_wait_for_ready(qspi);
400
+
if (err) {
401
+
dev_err(&mem->spi->dev, "Timeout waiting on QSPI ready.\n");
472
402
goto error;
403
+
}
473
404
474
-
err = mchp_coreqspi_setup_clock(qspi, mem->spi, op);
405
+
err = mchp_coreqspi_setup_clock(qspi, mem->spi, op->max_freq);
475
406
if (err)
476
407
goto error;
477
408
···
488
415
qspi->rxbuf = NULL;
489
416
qspi->tx_len = op->cmd.nbytes;
490
417
qspi->rx_len = 0;
491
-
mchp_coreqspi_write_op(qspi, false);
418
+
mchp_coreqspi_write_op(qspi);
492
419
}
493
420
494
421
qspi->txbuf = &opaddr[0];
···
499
426
qspi->rxbuf = NULL;
500
427
qspi->tx_len = op->addr.nbytes;
501
428
qspi->rx_len = 0;
502
-
mchp_coreqspi_write_op(qspi, false);
429
+
mchp_coreqspi_write_op(qspi);
503
430
}
504
431
505
432
if (op->data.nbytes) {
···
508
435
qspi->rxbuf = NULL;
509
436
qspi->rx_len = 0;
510
437
qspi->tx_len = op->data.nbytes;
511
-
mchp_coreqspi_write_op(qspi, true);
438
+
mchp_coreqspi_write_op(qspi);
512
439
} else {
513
440
qspi->txbuf = NULL;
514
441
qspi->rxbuf = (u8 *)op->data.buf.in;
···
588
515
.per_op_freq = true,
589
516
};
590
517
518
+
static int mchp_coreqspi_unprepare_message(struct spi_controller *ctlr, struct spi_message *m)
519
+
{
520
+
struct mchp_coreqspi *qspi = spi_controller_get_devdata(ctlr);
521
+
522
+
/*
523
+
* This delay is required for the driver to function correctly,
524
+
* but no explanation has been determined for why it is required.
525
+
*/
526
+
udelay(750);
527
+
528
+
mutex_unlock(&qspi->op_lock);
529
+
530
+
return 0;
531
+
}
532
+
533
+
static int mchp_coreqspi_prepare_message(struct spi_controller *ctlr, struct spi_message *m)
534
+
{
535
+
struct mchp_coreqspi *qspi = spi_controller_get_devdata(ctlr);
536
+
struct spi_transfer *t = NULL;
537
+
u32 control, frames;
538
+
u32 total_bytes = 0, cmd_bytes = 0, idle_cycles = 0;
539
+
int ret;
540
+
bool quad = false, dual = false;
541
+
542
+
mutex_lock(&qspi->op_lock);
543
+
ret = mchp_coreqspi_wait_for_ready(qspi);
544
+
if (ret) {
545
+
mutex_unlock(&qspi->op_lock);
546
+
dev_err(&ctlr->dev, "Timeout waiting on QSPI ready.\n");
547
+
return ret;
548
+
}
549
+
550
+
ret = mchp_coreqspi_setup_clock(qspi, m->spi, m->spi->max_speed_hz);
551
+
if (ret) {
552
+
mutex_unlock(&qspi->op_lock);
553
+
return ret;
554
+
}
555
+
556
+
control = readl_relaxed(qspi->regs + REG_CONTROL);
557
+
control &= ~(CONTROL_MODE12_MASK | CONTROL_MODE0);
558
+
writel_relaxed(control, qspi->regs + REG_CONTROL);
559
+
560
+
reinit_completion(&qspi->data_completion);
561
+
562
+
list_for_each_entry(t, &m->transfers, transfer_list) {
563
+
total_bytes += t->len;
564
+
if (!cmd_bytes && !(t->tx_buf && t->rx_buf))
565
+
cmd_bytes = t->len;
566
+
if (!t->rx_buf)
567
+
cmd_bytes = total_bytes;
568
+
if (t->tx_nbits == SPI_NBITS_QUAD || t->rx_nbits == SPI_NBITS_QUAD)
569
+
quad = true;
570
+
else if (t->tx_nbits == SPI_NBITS_DUAL || t->rx_nbits == SPI_NBITS_DUAL)
571
+
dual = true;
572
+
}
573
+
574
+
control = readl_relaxed(qspi->regs + REG_CONTROL);
575
+
if (quad) {
576
+
control |= (CONTROL_MODE0 | CONTROL_MODE12_EX_RW);
577
+
} else if (dual) {
578
+
control &= ~CONTROL_MODE0;
579
+
control |= CONTROL_MODE12_FULL;
580
+
} else {
581
+
control &= ~(CONTROL_MODE12_MASK | CONTROL_MODE0);
582
+
}
583
+
writel_relaxed(control, qspi->regs + REG_CONTROL);
584
+
585
+
frames = total_bytes & BYTESUPPER_MASK;
586
+
writel_relaxed(frames, qspi->regs + REG_FRAMESUP);
587
+
frames = total_bytes & BYTESLOWER_MASK;
588
+
frames |= cmd_bytes << FRAMES_CMDBYTES_SHIFT;
589
+
frames |= idle_cycles << FRAMES_IDLE_SHIFT;
590
+
control = readl_relaxed(qspi->regs + REG_CONTROL);
591
+
if (control & CONTROL_MODE12_MASK)
592
+
frames |= (1 << FRAMES_SHIFT);
593
+
594
+
frames |= FRAMES_FLAGWORD;
595
+
writel_relaxed(frames, qspi->regs + REG_FRAMES);
596
+
597
+
return 0;
598
+
};
599
+
600
+
static int mchp_coreqspi_transfer_one(struct spi_controller *ctlr, struct spi_device *spi,
601
+
struct spi_transfer *t)
602
+
{
603
+
struct mchp_coreqspi *qspi = spi_controller_get_devdata(ctlr);
604
+
605
+
qspi->tx_len = t->len;
606
+
607
+
if (t->tx_buf)
608
+
qspi->txbuf = (u8 *)t->tx_buf;
609
+
610
+
if (!t->rx_buf) {
611
+
mchp_coreqspi_write_op(qspi);
612
+
} else {
613
+
qspi->rxbuf = (u8 *)t->rx_buf;
614
+
qspi->rx_len = t->len;
615
+
mchp_coreqspi_write_read_op(qspi);
616
+
}
617
+
618
+
return 0;
619
+
}
620
+
591
621
static int mchp_coreqspi_probe(struct platform_device *pdev)
592
622
{
593
623
struct spi_controller *ctlr;
···
738
562
ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD |
739
563
SPI_TX_DUAL | SPI_TX_QUAD;
740
564
ctlr->dev.of_node = np;
565
+
ctlr->min_speed_hz = clk_get_rate(qspi->clk) / 30;
566
+
ctlr->prepare_message = mchp_coreqspi_prepare_message;
567
+
ctlr->unprepare_message = mchp_coreqspi_unprepare_message;
568
+
ctlr->transfer_one = mchp_coreqspi_transfer_one;
569
+
ctlr->num_chipselect = 2;
570
+
ctlr->use_gpio_descriptors = true;
741
571
742
572
ret = devm_spi_register_controller(&pdev->dev, ctlr);
743
573
if (ret)
+11
drivers/spi/spi-mt65xx.c
+11
drivers/spi/spi-mt65xx.c
···
220
220
.no_need_unprepare = true,
221
221
};
222
222
223
+
static const struct mtk_spi_compatible mt6991_compat = {
224
+
.need_pad_sel = true,
225
+
.must_tx = true,
226
+
.enhance_timing = true,
227
+
.dma_ext = true,
228
+
.ipm_design = true,
229
+
};
230
+
223
231
/*
224
232
* A piece of default chip info unless the platform
225
233
* supplies it.
···
252
244
},
253
245
{ .compatible = "mediatek,mt6765-spi",
254
246
.data = (void *)&mt6765_compat,
247
+
},
248
+
{ .compatible = "mediatek,mt6991-spi",
249
+
.data = (void *)&mt6991_compat,
255
250
},
256
251
{ .compatible = "mediatek,mt7622-spi",
257
252
.data = (void *)&mt7622_compat,
-1
drivers/spi/spi-mtk-nor.c
-1
drivers/spi/spi-mtk-nor.c
-1
drivers/spi/spi-nxp-fspi.c
-1
drivers/spi/spi-nxp-fspi.c
+59
drivers/spi/spi-offload-trigger-adi-util-sigma-delta.c
+59
drivers/spi/spi-offload-trigger-adi-util-sigma-delta.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (C) 2025 Analog Devices Inc.
4
+
* Copyright (C) 2025 BayLibre, SAS
5
+
*/
6
+
7
+
#include <linux/clk.h>
8
+
#include <linux/device.h>
9
+
#include <linux/mod_devicetable.h>
10
+
#include <linux/module.h>
11
+
#include <linux/platform_device.h>
12
+
#include <linux/property.h>
13
+
#include <linux/spi/offload/provider.h>
14
+
15
+
static bool adi_util_sigma_delta_match(struct spi_offload_trigger *trigger,
16
+
enum spi_offload_trigger_type type,
17
+
u64 *args, u32 nargs)
18
+
{
19
+
return type == SPI_OFFLOAD_TRIGGER_DATA_READY && nargs == 0;
20
+
}
21
+
22
+
static const struct spi_offload_trigger_ops adi_util_sigma_delta_ops = {
23
+
.match = adi_util_sigma_delta_match,
24
+
};
25
+
26
+
static int adi_util_sigma_delta_probe(struct platform_device *pdev)
27
+
{
28
+
struct device *dev = &pdev->dev;
29
+
struct spi_offload_trigger_info info = {
30
+
.fwnode = dev_fwnode(dev),
31
+
.ops = &adi_util_sigma_delta_ops,
32
+
};
33
+
struct clk *clk;
34
+
35
+
clk = devm_clk_get_enabled(dev, NULL);
36
+
if (IS_ERR(clk))
37
+
return dev_err_probe(dev, PTR_ERR(clk), "Failed to get clock\n");
38
+
39
+
return devm_spi_offload_trigger_register(dev, &info);
40
+
}
41
+
42
+
static const struct of_device_id adi_util_sigma_delta_of_match_table[] = {
43
+
{ .compatible = "adi,util-sigma-delta-spi", },
44
+
{ }
45
+
};
46
+
MODULE_DEVICE_TABLE(of, adi_util_sigma_delta_of_match_table);
47
+
48
+
static struct platform_driver adi_util_sigma_delta_driver = {
49
+
.probe = adi_util_sigma_delta_probe,
50
+
.driver = {
51
+
.name = "adi-util-sigma-delta-spi",
52
+
.of_match_table = adi_util_sigma_delta_of_match_table,
53
+
},
54
+
};
55
+
module_platform_driver(adi_util_sigma_delta_driver);
56
+
57
+
MODULE_AUTHOR("David Lechner <dlechner@baylibre.com>");
58
+
MODULE_DESCRIPTION("ADI Sigma-Delta SPI offload trigger utility driver");
59
+
MODULE_LICENSE("GPL");
-3
drivers/spi/spi-omap2-mcspi.c
-3
drivers/spi/spi-omap2-mcspi.c
···
272
272
273
273
mcspi_write_chconf0(spi, l);
274
274
275
-
pm_runtime_mark_last_busy(mcspi->dev);
276
275
pm_runtime_put_autosuspend(mcspi->dev);
277
276
}
278
277
}
···
1101
1102
if (ret && initial_setup)
1102
1103
omap2_mcspi_cleanup(spi);
1103
1104
1104
-
pm_runtime_mark_last_busy(mcspi->dev);
1105
1105
pm_runtime_put_autosuspend(mcspi->dev);
1106
1106
1107
1107
return ret;
···
1377
1379
ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
1378
1380
1379
1381
omap2_mcspi_set_mode(ctlr);
1380
-
pm_runtime_mark_last_busy(mcspi->dev);
1381
1382
pm_runtime_put_autosuspend(mcspi->dev);
1382
1383
return 0;
1383
1384
}
+188
-97
drivers/spi/spi-pci1xxxx.c
+188
-97
drivers/spi/spi-pci1xxxx.c
···
23
23
#define SYS_FREQ_DEFAULT (62500000)
24
24
25
25
#define PCI1XXXX_SPI_MAX_CLOCK_HZ (30000000)
26
+
#define PCI1XXXX_SPI_CLK_25MHZ (25000000)
26
27
#define PCI1XXXX_SPI_CLK_20MHZ (20000000)
27
28
#define PCI1XXXX_SPI_CLK_15MHZ (15000000)
28
29
#define PCI1XXXX_SPI_CLK_12MHZ (12000000)
···
97
96
#define SPI_DMA_CH1_DONE_INT BIT(1)
98
97
#define SPI_DMA_CH0_ABORT_INT BIT(16)
99
98
#define SPI_DMA_CH1_ABORT_INT BIT(17)
100
-
#define SPI_DMA_DONE_INT_MASK (SPI_DMA_CH0_DONE_INT | SPI_DMA_CH1_DONE_INT)
101
-
#define SPI_DMA_ABORT_INT_MASK (SPI_DMA_CH0_ABORT_INT | SPI_DMA_CH1_ABORT_INT)
99
+
#define SPI_DMA_DONE_INT_MASK(x) (1 << (x))
100
+
#define SPI_DMA_ABORT_INT_MASK(x) (1 << (16 + (x)))
102
101
#define DMA_CH_CONTROL_LIE BIT(3)
103
102
#define DMA_CH_CONTROL_RIE BIT(4)
104
103
#define DMA_INTR_EN (DMA_CH_CONTROL_RIE | DMA_CH_CONTROL_LIE)
···
132
131
#define SPI_SUSPEND_CONFIG 0x101
133
132
#define SPI_RESUME_CONFIG 0x203
134
133
134
+
#define NUM_VEC_PER_INST 3
135
+
135
136
struct pci1xxxx_spi_internal {
136
137
u8 hw_inst;
137
138
u8 clkdiv;
138
-
int irq;
139
+
int irq[NUM_VEC_PER_INST];
139
140
int mode;
140
141
bool spi_xfer_in_progress;
142
+
atomic_t dma_completion_count;
141
143
void *rx_buf;
142
144
bool dma_aborted_rd;
143
145
u32 bytes_recvd;
···
164
160
u8 dev_rev;
165
161
void __iomem *reg_base;
166
162
void __iomem *dma_offset_bar;
167
-
/* lock to safely access the DMA registers in isr */
168
-
spinlock_t dma_reg_lock;
163
+
/* lock to safely access the DMA RD registers in isr */
164
+
spinlock_t dma_rd_reg_lock;
165
+
/* lock to safely access the DMA RD registers in isr */
166
+
spinlock_t dma_wr_reg_lock;
169
167
bool can_dma;
170
168
struct pci1xxxx_spi_internal *spi_int[] __counted_by(total_hw_instances);
171
169
};
···
198
192
199
193
MODULE_DEVICE_TABLE(pci, pci1xxxx_spi_pci_id_table);
200
194
195
+
static irqreturn_t pci1xxxx_spi_isr_dma_rd(int irq, void *dev);
196
+
static irqreturn_t pci1xxxx_spi_isr_dma_wr(int irq, void *dev);
197
+
201
198
static int pci1xxxx_set_sys_lock(struct pci1xxxx_spi *par)
202
199
{
203
200
writel(SPI_SYSLOCK, par->reg_base + SPI_SYSLOCK_REG);
···
221
212
writel(0x0, par->reg_base + SPI_SYSLOCK_REG);
222
213
}
223
214
224
-
static int pci1xxxx_check_spi_can_dma(struct pci1xxxx_spi *spi_bus, int irq)
215
+
static int pci1xxxx_check_spi_can_dma(struct pci1xxxx_spi *spi_bus, int hw_inst, int num_vector)
225
216
{
226
217
struct pci_dev *pdev = spi_bus->dev;
227
218
u32 pf_num;
228
219
u32 regval;
229
220
int ret;
221
+
222
+
if (num_vector != hw_inst * NUM_VEC_PER_INST)
223
+
return -EOPNOTSUPP;
230
224
231
225
/*
232
226
* DEV REV Registers is a system register, HW Syslock bit
···
258
246
if (spi_bus->dev_rev < 0xC0 || pf_num)
259
247
return -EOPNOTSUPP;
260
248
261
-
/*
262
-
* DMA Supported only with MSI Interrupts
263
-
* One of the SPI instance's MSI vector address and data
264
-
* is used for DMA Interrupt
265
-
*/
266
-
if (!irq_get_msi_desc(irq)) {
267
-
dev_warn(&pdev->dev, "Error MSI Interrupt not supported, will operate in PIO mode\n");
268
-
return -EOPNOTSUPP;
269
-
}
270
-
271
249
spi_bus->dma_offset_bar = pcim_iomap(pdev, 2, pci_resource_len(pdev, 2));
272
250
if (!spi_bus->dma_offset_bar) {
273
251
dev_warn(&pdev->dev, "Error failed to map dma bar, will operate in PIO mode\n");
···
274
272
return 0;
275
273
}
276
274
277
-
static int pci1xxxx_spi_dma_init(struct pci1xxxx_spi *spi_bus, int irq)
275
+
static void pci1xxxx_spi_dma_config(struct pci1xxxx_spi *spi_bus)
278
276
{
277
+
struct pci1xxxx_spi_internal *spi_sub_ptr;
278
+
u8 iter, irq_index;
279
279
struct msi_msg msi;
280
+
u32 regval;
281
+
u16 data;
282
+
283
+
irq_index = spi_bus->total_hw_instances;
284
+
for (iter = 0; iter < spi_bus->total_hw_instances; iter++) {
285
+
spi_sub_ptr = spi_bus->spi_int[iter];
286
+
get_cached_msi_msg(spi_sub_ptr->irq[1], &msi);
287
+
if (iter == 0) {
288
+
writel(msi.address_hi, spi_bus->dma_offset_bar +
289
+
SPI_DMA_INTR_IMWR_WDONE_HIGH);
290
+
writel(msi.address_hi, spi_bus->dma_offset_bar +
291
+
SPI_DMA_INTR_IMWR_WABORT_HIGH);
292
+
writel(msi.address_hi, spi_bus->dma_offset_bar +
293
+
SPI_DMA_INTR_IMWR_RDONE_HIGH);
294
+
writel(msi.address_hi, spi_bus->dma_offset_bar +
295
+
SPI_DMA_INTR_IMWR_RABORT_HIGH);
296
+
writel(msi.address_lo, spi_bus->dma_offset_bar +
297
+
SPI_DMA_INTR_IMWR_WDONE_LOW);
298
+
writel(msi.address_lo, spi_bus->dma_offset_bar +
299
+
SPI_DMA_INTR_IMWR_WABORT_LOW);
300
+
writel(msi.address_lo, spi_bus->dma_offset_bar +
301
+
SPI_DMA_INTR_IMWR_RDONE_LOW);
302
+
writel(msi.address_lo, spi_bus->dma_offset_bar +
303
+
SPI_DMA_INTR_IMWR_RABORT_LOW);
304
+
writel(0, spi_bus->dma_offset_bar + SPI_DMA_INTR_WR_IMWR_DATA);
305
+
writel(0, spi_bus->dma_offset_bar + SPI_DMA_INTR_RD_IMWR_DATA);
306
+
}
307
+
regval = readl(spi_bus->dma_offset_bar + SPI_DMA_INTR_WR_IMWR_DATA);
308
+
data = msi.data + irq_index;
309
+
writel((regval | (data << (iter * 16))), spi_bus->dma_offset_bar +
310
+
SPI_DMA_INTR_WR_IMWR_DATA);
311
+
regval = readl(spi_bus->dma_offset_bar + SPI_DMA_INTR_WR_IMWR_DATA);
312
+
irq_index++;
313
+
314
+
data = msi.data + irq_index;
315
+
regval = readl(spi_bus->dma_offset_bar + SPI_DMA_INTR_RD_IMWR_DATA);
316
+
writel(regval | (data << (iter * 16)), spi_bus->dma_offset_bar +
317
+
SPI_DMA_INTR_RD_IMWR_DATA);
318
+
regval = readl(spi_bus->dma_offset_bar + SPI_DMA_INTR_RD_IMWR_DATA);
319
+
irq_index++;
320
+
}
321
+
}
322
+
323
+
static int pci1xxxx_spi_dma_init(struct pci1xxxx_spi *spi_bus, int hw_inst, int num_vector)
324
+
{
325
+
struct pci1xxxx_spi_internal *spi_sub_ptr;
326
+
u8 iter, irq_index;
280
327
int ret;
281
328
282
-
ret = pci1xxxx_check_spi_can_dma(spi_bus, irq);
329
+
irq_index = hw_inst;
330
+
ret = pci1xxxx_check_spi_can_dma(spi_bus, hw_inst, num_vector);
283
331
if (ret)
284
332
return ret;
285
333
286
-
spin_lock_init(&spi_bus->dma_reg_lock);
287
-
get_cached_msi_msg(irq, &msi);
334
+
spin_lock_init(&spi_bus->dma_rd_reg_lock);
335
+
spin_lock_init(&spi_bus->dma_wr_reg_lock);
288
336
writel(SPI_DMA_ENGINE_EN, spi_bus->dma_offset_bar + SPI_DMA_GLOBAL_WR_ENGINE_EN);
289
337
writel(SPI_DMA_ENGINE_EN, spi_bus->dma_offset_bar + SPI_DMA_GLOBAL_RD_ENGINE_EN);
290
-
writel(msi.address_hi, spi_bus->dma_offset_bar + SPI_DMA_INTR_IMWR_WDONE_HIGH);
291
-
writel(msi.address_hi, spi_bus->dma_offset_bar + SPI_DMA_INTR_IMWR_WABORT_HIGH);
292
-
writel(msi.address_hi, spi_bus->dma_offset_bar + SPI_DMA_INTR_IMWR_RDONE_HIGH);
293
-
writel(msi.address_hi, spi_bus->dma_offset_bar + SPI_DMA_INTR_IMWR_RABORT_HIGH);
294
-
writel(msi.address_lo, spi_bus->dma_offset_bar + SPI_DMA_INTR_IMWR_WDONE_LOW);
295
-
writel(msi.address_lo, spi_bus->dma_offset_bar + SPI_DMA_INTR_IMWR_WABORT_LOW);
296
-
writel(msi.address_lo, spi_bus->dma_offset_bar + SPI_DMA_INTR_IMWR_RDONE_LOW);
297
-
writel(msi.address_lo, spi_bus->dma_offset_bar + SPI_DMA_INTR_IMWR_RABORT_LOW);
298
-
writel(msi.data, spi_bus->dma_offset_bar + SPI_DMA_INTR_WR_IMWR_DATA);
299
-
writel(msi.data, spi_bus->dma_offset_bar + SPI_DMA_INTR_RD_IMWR_DATA);
338
+
339
+
for (iter = 0; iter < hw_inst; iter++) {
340
+
spi_sub_ptr = spi_bus->spi_int[iter];
341
+
spi_sub_ptr->irq[1] = pci_irq_vector(spi_bus->dev, irq_index);
342
+
ret = devm_request_irq(&spi_bus->dev->dev, spi_sub_ptr->irq[1],
343
+
pci1xxxx_spi_isr_dma_wr, PCI1XXXX_IRQ_FLAGS,
344
+
pci_name(spi_bus->dev), spi_sub_ptr);
345
+
if (ret < 0)
346
+
return ret;
347
+
348
+
irq_index++;
349
+
350
+
spi_sub_ptr->irq[2] = pci_irq_vector(spi_bus->dev, irq_index);
351
+
ret = devm_request_irq(&spi_bus->dev->dev, spi_sub_ptr->irq[2],
352
+
pci1xxxx_spi_isr_dma_rd, PCI1XXXX_IRQ_FLAGS,
353
+
pci_name(spi_bus->dev), spi_sub_ptr);
354
+
if (ret < 0)
355
+
return ret;
356
+
357
+
irq_index++;
358
+
}
359
+
pci1xxxx_spi_dma_config(spi_bus);
300
360
dma_set_max_seg_size(&spi_bus->dev->dev, PCI1XXXX_SPI_BUFFER_SIZE);
301
361
spi_bus->can_dma = true;
302
362
return 0;
···
382
318
writel(regval, par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst));
383
319
}
384
320
385
-
static u8 pci1xxxx_get_clock_div(u32 hz)
321
+
static u8 pci1xxxx_get_clock_div(struct pci1xxxx_spi *par, u32 hz)
386
322
{
387
323
u8 val = 0;
388
324
389
325
if (hz >= PCI1XXXX_SPI_MAX_CLOCK_HZ)
390
326
val = 2;
327
+
else if (par->dev_rev >= 0xC0 && hz >= PCI1XXXX_SPI_CLK_25MHZ)
328
+
val = 1;
391
329
else if ((hz < PCI1XXXX_SPI_MAX_CLOCK_HZ) && (hz >= PCI1XXXX_SPI_CLK_20MHZ))
392
330
val = 3;
393
331
else if ((hz < PCI1XXXX_SPI_CLK_20MHZ) && (hz >= PCI1XXXX_SPI_CLK_15MHZ))
···
464
398
writel(regval, par->reg_base + SPI_MST_CTL_REG_OFFSET(hw_inst));
465
399
}
466
400
467
-
static void pci1xxxx_start_spi_xfer(struct pci1xxxx_spi_internal *p, u8 hw_inst)
401
+
static void pci1xxxx_start_spi_xfer(struct pci1xxxx_spi_internal *p)
468
402
{
469
403
u32 regval;
470
404
471
-
regval = readl(p->parent->reg_base + SPI_MST_CTL_REG_OFFSET(hw_inst));
405
+
atomic_set(&p->dma_completion_count, 0);
406
+
regval = readl(p->parent->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst));
472
407
regval |= SPI_MST_CTL_GO;
473
-
writel(regval, p->parent->reg_base + SPI_MST_CTL_REG_OFFSET(hw_inst));
408
+
writel(regval, p->parent->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst));
474
409
}
475
410
476
411
static int pci1xxxx_spi_transfer_with_io(struct spi_controller *spi_ctlr,
···
490
423
491
424
p->spi_xfer_in_progress = true;
492
425
p->bytes_recvd = 0;
493
-
clkdiv = pci1xxxx_get_clock_div(xfer->speed_hz);
426
+
clkdiv = pci1xxxx_get_clock_div(par, xfer->speed_hz);
494
427
tx_buf = xfer->tx_buf;
495
428
rx_buf = xfer->rx_buf;
496
429
transfer_len = xfer->len;
···
515
448
&tx_buf[bytes_transfered], len);
516
449
bytes_transfered += len;
517
450
pci1xxxx_spi_setup(par, p->hw_inst, spi->mode, clkdiv, len);
518
-
pci1xxxx_start_spi_xfer(p, p->hw_inst);
451
+
pci1xxxx_start_spi_xfer(p);
519
452
520
453
/* Wait for DMA_TERM interrupt */
521
454
result = wait_for_completion_timeout(&p->spi_xfer_done,
···
541
474
{
542
475
struct pci1xxxx_spi_internal *p = spi_controller_get_devdata(spi_ctlr);
543
476
struct pci1xxxx_spi *par = p->parent;
544
-
dma_addr_t rx_dma_addr = 0;
545
477
dma_addr_t tx_dma_addr = 0;
546
478
int ret = 0;
547
479
u32 regval;
···
549
483
p->tx_sgl = xfer->tx_sg.sgl;
550
484
p->rx_sgl = xfer->rx_sg.sgl;
551
485
p->rx_buf = xfer->rx_buf;
486
+
atomic_set(&p->dma_completion_count, 1);
552
487
regval = readl(par->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst));
553
488
writel(regval, par->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst));
554
489
···
559
492
}
560
493
p->xfer = xfer;
561
494
p->mode = spi->mode;
562
-
p->clkdiv = pci1xxxx_get_clock_div(xfer->speed_hz);
495
+
p->clkdiv = pci1xxxx_get_clock_div(par, xfer->speed_hz);
563
496
p->bytes_recvd = 0;
564
497
p->rx_buf = xfer->rx_buf;
565
498
regval = readl(par->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst));
566
499
writel(regval, par->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst));
567
500
568
501
tx_dma_addr = sg_dma_address(p->tx_sgl);
569
-
rx_dma_addr = sg_dma_address(p->rx_sgl);
570
502
p->tx_sgl_len = sg_dma_len(p->tx_sgl);
571
-
p->rx_sgl_len = sg_dma_len(p->rx_sgl);
572
503
pci1xxxx_spi_setup(par, p->hw_inst, p->mode, p->clkdiv, p->tx_sgl_len);
573
504
pci1xxxx_spi_setup_dma_to_io(p, (tx_dma_addr), p->tx_sgl_len);
574
-
if (rx_dma_addr)
575
-
pci1xxxx_spi_setup_dma_from_io(p, rx_dma_addr, p->rx_sgl_len);
576
505
writel(p->hw_inst, par->dma_offset_bar + SPI_DMA_RD_DOORBELL_REG);
577
506
578
507
reinit_completion(&p->spi_xfer_done);
···
658
595
return spi_int_fired;
659
596
}
660
597
661
-
static void pci1xxxx_spi_setup_next_dma_transfer(struct pci1xxxx_spi_internal *p)
598
+
static void pci1xxxx_spi_setup_next_dma_to_io_transfer(struct pci1xxxx_spi_internal *p)
662
599
{
663
600
dma_addr_t tx_dma_addr = 0;
664
-
dma_addr_t rx_dma_addr = 0;
665
601
u32 prev_len;
666
602
667
603
p->tx_sgl = sg_next(p->tx_sgl);
668
-
if (p->rx_sgl)
669
-
p->rx_sgl = sg_next(p->rx_sgl);
670
-
if (!p->tx_sgl) {
671
-
/* Clear xfer_done */
672
-
complete(&p->spi_xfer_done);
673
-
} else {
604
+
if (p->tx_sgl) {
674
605
tx_dma_addr = sg_dma_address(p->tx_sgl);
675
606
prev_len = p->tx_sgl_len;
676
607
p->tx_sgl_len = sg_dma_len(p->tx_sgl);
608
+
pci1xxxx_spi_setup_dma_to_io(p, tx_dma_addr, p->tx_sgl_len);
609
+
writel(p->hw_inst, p->parent->dma_offset_bar + SPI_DMA_RD_DOORBELL_REG);
677
610
if (prev_len != p->tx_sgl_len)
678
611
pci1xxxx_spi_setup(p->parent,
679
612
p->hw_inst, p->mode, p->clkdiv, p->tx_sgl_len);
680
-
pci1xxxx_spi_setup_dma_to_io(p, tx_dma_addr, p->tx_sgl_len);
681
-
if (p->rx_sgl) {
682
-
rx_dma_addr = sg_dma_address(p->rx_sgl);
683
-
p->rx_sgl_len = sg_dma_len(p->rx_sgl);
684
-
pci1xxxx_spi_setup_dma_from_io(p, rx_dma_addr, p->rx_sgl_len);
685
-
}
686
-
writel(p->hw_inst, p->parent->dma_offset_bar + SPI_DMA_RD_DOORBELL_REG);
687
613
}
688
614
}
689
615
690
-
static irqreturn_t pci1xxxx_spi_isr_dma(int irq, void *dev)
616
+
static void pci1xxxx_spi_setup_next_dma_from_io_transfer(struct pci1xxxx_spi_internal *p)
617
+
{
618
+
dma_addr_t rx_dma_addr = 0;
619
+
620
+
if (p->rx_sgl) {
621
+
rx_dma_addr = sg_dma_address(p->rx_sgl);
622
+
p->rx_sgl_len = sg_dma_len(p->rx_sgl);
623
+
pci1xxxx_spi_setup_dma_from_io(p, rx_dma_addr, p->rx_sgl_len);
624
+
writel(p->hw_inst, p->parent->dma_offset_bar + SPI_DMA_WR_DOORBELL_REG);
625
+
}
626
+
}
627
+
628
+
static irqreturn_t pci1xxxx_spi_isr_dma_rd(int irq, void *dev)
691
629
{
692
630
struct pci1xxxx_spi_internal *p = dev;
693
631
irqreturn_t spi_int_fired = IRQ_NONE;
694
632
unsigned long flags;
695
633
u32 regval;
696
634
697
-
spin_lock_irqsave(&p->parent->dma_reg_lock, flags);
698
635
/* Clear the DMA RD INT and start spi xfer*/
699
636
regval = readl(p->parent->dma_offset_bar + SPI_DMA_INTR_RD_STS);
700
-
if (regval & SPI_DMA_DONE_INT_MASK) {
701
-
if (regval & SPI_DMA_CH0_DONE_INT)
702
-
pci1xxxx_start_spi_xfer(p, SPI0);
703
-
if (regval & SPI_DMA_CH1_DONE_INT)
704
-
pci1xxxx_start_spi_xfer(p, SPI1);
705
-
spi_int_fired = IRQ_HANDLED;
637
+
if (regval) {
638
+
if (regval & SPI_DMA_DONE_INT_MASK(p->hw_inst)) {
639
+
/* Start the SPI transfer only if both DMA read and write are completed */
640
+
if (atomic_inc_return(&p->dma_completion_count) == 2)
641
+
pci1xxxx_start_spi_xfer(p);
642
+
spi_int_fired = IRQ_HANDLED;
643
+
}
644
+
if (regval & SPI_DMA_ABORT_INT_MASK(p->hw_inst)) {
645
+
p->dma_aborted_rd = true;
646
+
spi_int_fired = IRQ_HANDLED;
647
+
}
648
+
spin_lock_irqsave(&p->parent->dma_rd_reg_lock, flags);
649
+
writel((SPI_DMA_DONE_INT_MASK(p->hw_inst) | SPI_DMA_ABORT_INT_MASK(p->hw_inst)),
650
+
p->parent->dma_offset_bar + SPI_DMA_INTR_RD_CLR);
651
+
spin_unlock_irqrestore(&p->parent->dma_rd_reg_lock, flags);
706
652
}
707
-
if (regval & SPI_DMA_ABORT_INT_MASK) {
708
-
p->dma_aborted_rd = true;
709
-
spi_int_fired = IRQ_HANDLED;
710
-
}
711
-
writel(regval, p->parent->dma_offset_bar + SPI_DMA_INTR_RD_CLR);
653
+
return spi_int_fired;
654
+
}
655
+
656
+
static irqreturn_t pci1xxxx_spi_isr_dma_wr(int irq, void *dev)
657
+
{
658
+
struct pci1xxxx_spi_internal *p = dev;
659
+
irqreturn_t spi_int_fired = IRQ_NONE;
660
+
unsigned long flags;
661
+
u32 regval;
712
662
713
663
/* Clear the DMA WR INT */
714
664
regval = readl(p->parent->dma_offset_bar + SPI_DMA_INTR_WR_STS);
715
-
if (regval & SPI_DMA_DONE_INT_MASK) {
716
-
if (regval & SPI_DMA_CH0_DONE_INT)
717
-
pci1xxxx_spi_setup_next_dma_transfer(p->parent->spi_int[SPI0]);
665
+
if (regval) {
666
+
if (regval & SPI_DMA_DONE_INT_MASK(p->hw_inst)) {
667
+
spi_int_fired = IRQ_HANDLED;
668
+
if (sg_is_last(p->rx_sgl)) {
669
+
complete(&p->spi_xfer_done);
670
+
} else {
671
+
p->rx_sgl = sg_next(p->rx_sgl);
672
+
if (atomic_inc_return(&p->dma_completion_count) == 2)
673
+
pci1xxxx_start_spi_xfer(p);
674
+
}
718
675
719
-
if (regval & SPI_DMA_CH1_DONE_INT)
720
-
pci1xxxx_spi_setup_next_dma_transfer(p->parent->spi_int[SPI1]);
676
+
}
677
+
if (regval & SPI_DMA_ABORT_INT_MASK(p->hw_inst)) {
678
+
p->dma_aborted_wr = true;
679
+
spi_int_fired = IRQ_HANDLED;
680
+
}
681
+
spin_lock_irqsave(&p->parent->dma_wr_reg_lock, flags);
682
+
writel((SPI_DMA_DONE_INT_MASK(p->hw_inst) | SPI_DMA_ABORT_INT_MASK(p->hw_inst)),
683
+
p->parent->dma_offset_bar + SPI_DMA_INTR_WR_CLR);
684
+
spin_unlock_irqrestore(&p->parent->dma_wr_reg_lock, flags);
685
+
}
686
+
return spi_int_fired;
687
+
}
721
688
722
-
spi_int_fired = IRQ_HANDLED;
723
-
}
724
-
if (regval & SPI_DMA_ABORT_INT_MASK) {
725
-
p->dma_aborted_wr = true;
726
-
spi_int_fired = IRQ_HANDLED;
727
-
}
728
-
writel(regval, p->parent->dma_offset_bar + SPI_DMA_INTR_WR_CLR);
729
-
spin_unlock_irqrestore(&p->parent->dma_reg_lock, flags);
689
+
static irqreturn_t pci1xxxx_spi_isr_dma(int irq, void *dev)
690
+
{
691
+
struct pci1xxxx_spi_internal *p = dev;
692
+
irqreturn_t spi_int_fired = IRQ_NONE;
693
+
u32 regval;
730
694
731
695
/* Clear the SPI GO_BIT Interrupt */
732
696
regval = readl(p->parent->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst));
733
697
if (regval & SPI_INTR) {
734
-
writel(p->hw_inst, p->parent->dma_offset_bar + SPI_DMA_WR_DOORBELL_REG);
698
+
pci1xxxx_spi_setup_next_dma_from_io_transfer(p);
699
+
pci1xxxx_spi_setup_next_dma_to_io_transfer(p);
735
700
spi_int_fired = IRQ_HANDLED;
701
+
writel(regval, p->parent->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst));
736
702
}
737
-
writel(regval, p->parent->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst));
738
703
return spi_int_fired;
739
704
}
740
705
···
852
761
if (!spi_bus->reg_base)
853
762
return -EINVAL;
854
763
855
-
num_vector = pci_alloc_irq_vectors(pdev, 1, hw_inst_cnt,
764
+
num_vector = pci_alloc_irq_vectors(pdev, 1, hw_inst_cnt * NUM_VEC_PER_INST,
856
765
PCI_IRQ_INTX | PCI_IRQ_MSI);
857
766
if (num_vector < 0) {
858
767
dev_err(&pdev->dev, "Error allocating MSI vectors\n");
···
866
775
regval &= ~SPI_INTR;
867
776
writel(regval, spi_bus->reg_base +
868
777
SPI_MST_EVENT_MASK_REG_OFFSET(spi_sub_ptr->hw_inst));
869
-
spi_sub_ptr->irq = pci_irq_vector(pdev, 0);
778
+
spi_sub_ptr->irq[0] = pci_irq_vector(pdev, 0);
870
779
871
780
if (num_vector >= hw_inst_cnt)
872
-
ret = devm_request_irq(&pdev->dev, spi_sub_ptr->irq,
781
+
ret = devm_request_irq(&pdev->dev, spi_sub_ptr->irq[0],
873
782
pci1xxxx_spi_isr, PCI1XXXX_IRQ_FLAGS,
874
783
pci_name(pdev), spi_sub_ptr);
875
784
else
876
-
ret = devm_request_irq(&pdev->dev, spi_sub_ptr->irq,
785
+
ret = devm_request_irq(&pdev->dev, spi_sub_ptr->irq[0],
877
786
pci1xxxx_spi_shared_isr,
878
787
PCI1XXXX_IRQ_FLAGS | IRQF_SHARED,
879
788
pci_name(pdev), spi_bus);
880
789
if (ret < 0) {
881
790
dev_err(&pdev->dev, "Unable to request irq : %d",
882
-
spi_sub_ptr->irq);
791
+
spi_sub_ptr->irq[0]);
883
792
return -ENODEV;
884
793
}
885
-
886
-
ret = pci1xxxx_spi_dma_init(spi_bus, spi_sub_ptr->irq);
887
-
if (ret && ret != -EOPNOTSUPP)
888
-
return ret;
889
794
890
795
/* This register is only applicable for 1st instance */
891
796
regval = readl(spi_bus->reg_base + SPI_PCI_CTRL_REG_OFFSET(0));
···
904
817
writel(regval, spi_bus->reg_base +
905
818
SPI_MST_EVENT_MASK_REG_OFFSET(spi_sub_ptr->hw_inst));
906
819
if (num_vector >= hw_inst_cnt) {
907
-
spi_sub_ptr->irq = pci_irq_vector(pdev, iter);
908
-
ret = devm_request_irq(&pdev->dev, spi_sub_ptr->irq,
820
+
spi_sub_ptr->irq[0] = pci_irq_vector(pdev, iter);
821
+
ret = devm_request_irq(&pdev->dev, spi_sub_ptr->irq[0],
909
822
pci1xxxx_spi_isr, PCI1XXXX_IRQ_FLAGS,
910
823
pci_name(pdev), spi_sub_ptr);
911
824
if (ret < 0) {
912
825
dev_err(&pdev->dev, "Unable to request irq : %d",
913
-
spi_sub_ptr->irq);
826
+
spi_sub_ptr->irq[0]);
914
827
return -ENODEV;
915
828
}
916
829
}
···
933
846
if (ret)
934
847
return ret;
935
848
}
849
+
ret = pci1xxxx_spi_dma_init(spi_bus, hw_inst_cnt, num_vector);
850
+
if (ret && ret != -EOPNOTSUPP)
851
+
return ret;
852
+
936
853
pci_set_drvdata(pdev, spi_bus);
937
854
938
855
return 0;
+36
-36
drivers/spi/spi-qpic-snand.c
+36
-36
drivers/spi/spi-qpic-snand.c
···
59
59
#define OOB_BUF_SIZE 128
60
60
#define ecceng_to_qspi(eng) container_of(eng, struct qpic_spi_nand, ecc_eng)
61
61
62
-
struct qpic_snand_op {
63
-
u32 cmd_reg;
64
-
u32 addr1_reg;
65
-
u32 addr2_reg;
66
-
};
67
-
68
62
struct snandc_read_status {
69
63
__le32 snandc_flash;
70
64
__le32 snandc_buffer;
···
277
283
goto err_free_ecc_cfg;
278
284
}
279
285
280
-
if (ecc_cfg->strength != 4) {
286
+
switch (ecc_cfg->strength) {
287
+
case 4:
288
+
ecc_cfg->ecc_mode = ECC_MODE_4BIT;
289
+
ecc_cfg->ecc_bytes_hw = 7;
290
+
ecc_cfg->spare_bytes = 4;
291
+
break;
292
+
293
+
case 8:
294
+
ecc_cfg->ecc_mode = ECC_MODE_8BIT;
295
+
ecc_cfg->ecc_bytes_hw = 13;
296
+
ecc_cfg->spare_bytes = 2;
297
+
break;
298
+
299
+
default:
281
300
dev_err(snandc->dev,
282
-
"only 4 bits ECC strength is supported\n");
301
+
"only 4 or 8 bits ECC strength is supported\n");
283
302
ret = -EOPNOTSUPP;
284
303
goto err_free_ecc_cfg;
285
304
}
···
309
302
nand->ecc.ctx.priv = ecc_cfg;
310
303
snandc->qspi->mtd = mtd;
311
304
312
-
ecc_cfg->ecc_bytes_hw = 7;
313
-
ecc_cfg->spare_bytes = 4;
314
305
ecc_cfg->bbm_size = 1;
315
306
ecc_cfg->bch_enabled = true;
316
307
ecc_cfg->bytes = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes + ecc_cfg->bbm_size;
···
370
365
FIELD_PREP(ECC_SW_RESET, 0) |
371
366
FIELD_PREP(ECC_NUM_DATA_BYTES_MASK, ecc_cfg->cw_data) |
372
367
FIELD_PREP(ECC_FORCE_CLK_OPEN, 1) |
373
-
FIELD_PREP(ECC_MODE_MASK, 0) |
368
+
FIELD_PREP(ECC_MODE_MASK, ecc_cfg->ecc_mode) |
374
369
FIELD_PREP(ECC_PARITY_SIZE_BYTES_BCH_MASK, ecc_cfg->ecc_bytes_hw);
375
370
376
371
ecc_cfg->ecc_buf_cfg = FIELD_PREP(NUM_STEPS_MASK, 0x203);
···
613
608
614
609
bbpos = mtd->writesize - ecc_cfg->cw_size * (num_cw - 1);
615
610
616
-
if (snandc->data_buffer[bbpos] == 0xff)
617
-
snandc->data_buffer[bbpos + 1] = 0xff;
618
-
if (snandc->data_buffer[bbpos] != 0xff)
619
-
snandc->data_buffer[bbpos + 1] = snandc->data_buffer[bbpos];
611
+
/*
612
+
* TODO: The SPINAND code expects two bad block marker bytes
613
+
* at the beginning of the OOB area, but the OOB layout used by
614
+
* the driver has only one. Duplicate that for now in order to
615
+
* avoid certain blocks to be marked as bad.
616
+
*
617
+
* This can be removed once single-byte bad block marker support
618
+
* gets implemented in the SPINAND code.
619
+
*/
620
+
snandc->data_buffer[bbpos + 1] = snandc->data_buffer[bbpos];
620
621
621
622
memcpy(op->data.buf.in, snandc->data_buffer + bbpos, op->data.nbytes);
622
623
···
862
851
int data_size, oob_size;
863
852
864
853
if (i == (num_cw - 1)) {
865
-
data_size = 512 - ((num_cw - 1) << 2);
854
+
data_size = NANDC_STEP_SIZE - ((num_cw - 1) << 2);
866
855
oob_size = (num_cw << 2) + ecc_cfg->ecc_bytes_hw +
867
856
ecc_cfg->spare_bytes;
868
857
} else {
···
1321
1310
static int qcom_spi_send_cmdaddr(struct qcom_nand_controller *snandc,
1322
1311
const struct spi_mem_op *op)
1323
1312
{
1324
-
struct qpic_snand_op s_op = {};
1325
1313
u32 cmd;
1326
1314
int ret, opcode;
1327
1315
···
1328
1318
if (ret < 0)
1329
1319
return ret;
1330
1320
1331
-
s_op.cmd_reg = cmd;
1332
-
s_op.addr1_reg = op->addr.val;
1333
-
s_op.addr2_reg = 0;
1334
-
1335
1321
opcode = op->cmd.opcode;
1336
1322
1337
1323
switch (opcode) {
1338
1324
case SPINAND_WRITE_EN:
1339
1325
return 0;
1340
1326
case SPINAND_PROGRAM_EXECUTE:
1341
-
s_op.addr1_reg = op->addr.val << 16;
1342
-
s_op.addr2_reg = op->addr.val >> 16 & 0xff;
1343
-
snandc->qspi->addr1 = cpu_to_le32(s_op.addr1_reg);
1344
-
snandc->qspi->addr2 = cpu_to_le32(s_op.addr2_reg);
1327
+
snandc->qspi->addr1 = cpu_to_le32(op->addr.val << 16);
1328
+
snandc->qspi->addr2 = cpu_to_le32(op->addr.val >> 16 & 0xff);
1345
1329
snandc->qspi->cmd = cpu_to_le32(cmd);
1346
1330
return qcom_spi_program_execute(snandc, op);
1347
1331
case SPINAND_READ:
1348
-
s_op.addr1_reg = (op->addr.val << 16);
1349
-
s_op.addr2_reg = op->addr.val >> 16 & 0xff;
1350
-
snandc->qspi->addr1 = cpu_to_le32(s_op.addr1_reg);
1351
-
snandc->qspi->addr2 = cpu_to_le32(s_op.addr2_reg);
1332
+
snandc->qspi->addr1 = cpu_to_le32(op->addr.val << 16);
1333
+
snandc->qspi->addr2 = cpu_to_le32(op->addr.val >> 16 & 0xff);
1352
1334
snandc->qspi->cmd = cpu_to_le32(cmd);
1353
1335
return 0;
1354
1336
case SPINAND_ERASE:
1355
-
s_op.addr2_reg = (op->addr.val >> 16) & 0xffff;
1356
-
s_op.addr1_reg = op->addr.val;
1357
-
snandc->qspi->addr1 = cpu_to_le32(s_op.addr1_reg << 16);
1358
-
snandc->qspi->addr2 = cpu_to_le32(s_op.addr2_reg);
1337
+
snandc->qspi->addr1 = cpu_to_le32(op->addr.val << 16);
1338
+
snandc->qspi->addr2 = cpu_to_le32(op->addr.val >> 16 & 0xffff);
1359
1339
snandc->qspi->cmd = cpu_to_le32(cmd);
1360
1340
return qcom_spi_block_erase(snandc);
1361
1341
default:
···
1357
1357
qcom_clear_read_regs(snandc);
1358
1358
qcom_clear_bam_transaction(snandc);
1359
1359
1360
-
snandc->regs->cmd = cpu_to_le32(s_op.cmd_reg);
1360
+
snandc->regs->cmd = cpu_to_le32(cmd);
1361
1361
snandc->regs->exec = cpu_to_le32(1);
1362
-
snandc->regs->addr0 = cpu_to_le32(s_op.addr1_reg);
1363
-
snandc->regs->addr1 = cpu_to_le32(s_op.addr2_reg);
1362
+
snandc->regs->addr0 = cpu_to_le32(op->addr.val);
1363
+
snandc->regs->addr1 = cpu_to_le32(0);
1364
1364
1365
1365
qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 3, NAND_BAM_NEXT_SGL);
1366
1366
qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
-3
drivers/spi/spi-rockchip-sfc.c
-3
drivers/spi/spi-rockchip-sfc.c
···
565
565
566
566
ret = rockchip_sfc_xfer_done(sfc, 100000);
567
567
out:
568
-
pm_runtime_mark_last_busy(sfc->dev);
569
568
pm_runtime_put_autosuspend(sfc->dev);
570
569
571
570
return ret;
···
711
712
if (ret)
712
713
goto err_register;
713
714
714
-
pm_runtime_mark_last_busy(dev);
715
715
pm_runtime_put_autosuspend(dev);
716
716
717
717
return 0;
···
797
799
798
800
rockchip_sfc_init(sfc);
799
801
800
-
pm_runtime_mark_last_busy(dev);
801
802
pm_runtime_put_autosuspend(dev);
802
803
803
804
return 0;
+2
-7
drivers/spi/spi-rspi.c
+2
-7
drivers/spi/spi-rspi.c
···
1404
1404
1405
1405
MODULE_DEVICE_TABLE(platform, spi_driver_ids);
1406
1406
1407
-
#ifdef CONFIG_PM_SLEEP
1408
1407
static int rspi_suspend(struct device *dev)
1409
1408
{
1410
1409
struct rspi_data *rspi = dev_get_drvdata(dev);
···
1418
1419
return spi_controller_resume(rspi->ctlr);
1419
1420
}
1420
1421
1421
-
static SIMPLE_DEV_PM_OPS(rspi_pm_ops, rspi_suspend, rspi_resume);
1422
-
#define DEV_PM_OPS &rspi_pm_ops
1423
-
#else
1424
-
#define DEV_PM_OPS NULL
1425
-
#endif /* CONFIG_PM_SLEEP */
1422
+
static DEFINE_SIMPLE_DEV_PM_OPS(rspi_pm_ops, rspi_suspend, rspi_resume);
1426
1423
1427
1424
static struct platform_driver rspi_driver = {
1428
1425
.probe = rspi_probe,
···
1426
1431
.id_table = spi_driver_ids,
1427
1432
.driver = {
1428
1433
.name = "renesas_spi",
1429
-
.pm = DEV_PM_OPS,
1434
+
.pm = pm_sleep_ptr(&rspi_pm_ops),
1430
1435
.of_match_table = of_match_ptr(rspi_of_match),
1431
1436
},
1432
1437
};
+466
drivers/spi/spi-rzv2h-rspi.c
+466
drivers/spi/spi-rzv2h-rspi.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-or-later
2
+
/*
3
+
* Renesas RZ/V2H Renesas Serial Peripheral Interface (RSPI)
4
+
*
5
+
* Copyright (C) 2025 Renesas Electronics Corporation
6
+
*/
7
+
8
+
#include <linux/bitfield.h>
9
+
#include <linux/bitops.h>
10
+
#include <linux/bits.h>
11
+
#include <linux/clk.h>
12
+
#include <linux/interrupt.h>
13
+
#include <linux/io.h>
14
+
#include <linux/limits.h>
15
+
#include <linux/log2.h>
16
+
#include <linux/math.h>
17
+
#include <linux/of.h>
18
+
#include <linux/platform_device.h>
19
+
#include <linux/property.h>
20
+
#include <linux/reset.h>
21
+
#include <linux/spi/spi.h>
22
+
#include <linux/wait.h>
23
+
24
+
/* Registers */
25
+
#define RSPI_SPDR 0x00
26
+
#define RSPI_SPCR 0x08
27
+
#define RSPI_SSLP 0x10
28
+
#define RSPI_SPBR 0x11
29
+
#define RSPI_SPSCR 0x13
30
+
#define RSPI_SPCMD 0x14
31
+
#define RSPI_SPDCR2 0x44
32
+
#define RSPI_SPSR 0x52
33
+
#define RSPI_SPSRC 0x6a
34
+
#define RSPI_SPFCR 0x6c
35
+
36
+
/* Register SPCR */
37
+
#define RSPI_SPCR_MSTR BIT(30)
38
+
#define RSPI_SPCR_SPRIE BIT(17)
39
+
#define RSPI_SPCR_SCKASE BIT(12)
40
+
#define RSPI_SPCR_SPE BIT(0)
41
+
42
+
/* Register SPBR */
43
+
#define RSPI_SPBR_SPR_MIN 0
44
+
#define RSPI_SPBR_SPR_MAX 255
45
+
46
+
/* Register SPCMD */
47
+
#define RSPI_SPCMD_SSLA GENMASK(25, 24)
48
+
#define RSPI_SPCMD_SPB GENMASK(20, 16)
49
+
#define RSPI_SPCMD_LSBF BIT(12)
50
+
#define RSPI_SPCMD_SSLKP BIT(7)
51
+
#define RSPI_SPCMD_BRDV GENMASK(3, 2)
52
+
#define RSPI_SPCMD_CPOL BIT(1)
53
+
#define RSPI_SPCMD_CPHA BIT(0)
54
+
55
+
#define RSPI_SPCMD_BRDV_MIN 0
56
+
#define RSPI_SPCMD_BRDV_MAX 3
57
+
58
+
/* Register SPDCR2 */
59
+
#define RSPI_SPDCR2_TTRG GENMASK(11, 8)
60
+
#define RSPI_SPDCR2_RTRG GENMASK(3, 0)
61
+
#define RSPI_FIFO_SIZE 16
62
+
63
+
/* Register SPSR */
64
+
#define RSPI_SPSR_SPRF BIT(15)
65
+
66
+
/* Register RSPI_SPSRC */
67
+
#define RSPI_SPSRC_CLEAR 0xfd80
68
+
69
+
#define RSPI_RESET_NUM 2
70
+
#define RSPI_CLK_NUM 3
71
+
72
+
struct rzv2h_rspi_priv {
73
+
struct reset_control_bulk_data resets[RSPI_RESET_NUM];
74
+
struct spi_controller *controller;
75
+
void __iomem *base;
76
+
struct clk *tclk;
77
+
wait_queue_head_t wait;
78
+
unsigned int bytes_per_word;
79
+
u32 freq;
80
+
u16 status;
81
+
};
82
+
83
+
#define RZV2H_RSPI_TX(func, type) \
84
+
static inline void rzv2h_rspi_tx_##type(struct rzv2h_rspi_priv *rspi, \
85
+
const void *txbuf, \
86
+
unsigned int index) { \
87
+
type buf = 0; \
88
+
\
89
+
if (txbuf) \
90
+
buf = ((type *)txbuf)[index]; \
91
+
\
92
+
func(buf, rspi->base + RSPI_SPDR); \
93
+
}
94
+
95
+
#define RZV2H_RSPI_RX(func, type) \
96
+
static inline void rzv2h_rspi_rx_##type(struct rzv2h_rspi_priv *rspi, \
97
+
void *rxbuf, \
98
+
unsigned int index) { \
99
+
type buf = func(rspi->base + RSPI_SPDR); \
100
+
\
101
+
if (rxbuf) \
102
+
((type *)rxbuf)[index] = buf; \
103
+
}
104
+
105
+
RZV2H_RSPI_TX(writel, u32)
106
+
RZV2H_RSPI_TX(writew, u16)
107
+
RZV2H_RSPI_TX(writeb, u8)
108
+
RZV2H_RSPI_RX(readl, u32)
109
+
RZV2H_RSPI_RX(readw, u16)
110
+
RZV2H_RSPI_RX(readl, u8)
111
+
112
+
static void rzv2h_rspi_reg_rmw(const struct rzv2h_rspi_priv *rspi,
113
+
int reg_offs, u32 bit_mask, u32 value)
114
+
{
115
+
u32 tmp;
116
+
117
+
value <<= __ffs(bit_mask);
118
+
tmp = (readl(rspi->base + reg_offs) & ~bit_mask) | value;
119
+
writel(tmp, rspi->base + reg_offs);
120
+
}
121
+
122
+
static inline void rzv2h_rspi_spe_disable(const struct rzv2h_rspi_priv *rspi)
123
+
{
124
+
rzv2h_rspi_reg_rmw(rspi, RSPI_SPCR, RSPI_SPCR_SPE, 0);
125
+
}
126
+
127
+
static inline void rzv2h_rspi_spe_enable(const struct rzv2h_rspi_priv *rspi)
128
+
{
129
+
rzv2h_rspi_reg_rmw(rspi, RSPI_SPCR, RSPI_SPCR_SPE, 1);
130
+
}
131
+
132
+
static inline void rzv2h_rspi_clear_fifos(const struct rzv2h_rspi_priv *rspi)
133
+
{
134
+
writeb(1, rspi->base + RSPI_SPFCR);
135
+
}
136
+
137
+
static inline void rzv2h_rspi_clear_all_irqs(struct rzv2h_rspi_priv *rspi)
138
+
{
139
+
writew(RSPI_SPSRC_CLEAR, rspi->base + RSPI_SPSRC);
140
+
rspi->status = 0;
141
+
}
142
+
143
+
static irqreturn_t rzv2h_rx_irq_handler(int irq, void *data)
144
+
{
145
+
struct rzv2h_rspi_priv *rspi = data;
146
+
147
+
rspi->status = readw(rspi->base + RSPI_SPSR);
148
+
wake_up(&rspi->wait);
149
+
150
+
return IRQ_HANDLED;
151
+
}
152
+
153
+
static inline int rzv2h_rspi_wait_for_interrupt(struct rzv2h_rspi_priv *rspi,
154
+
u32 wait_mask)
155
+
{
156
+
return wait_event_timeout(rspi->wait, (rspi->status & wait_mask),
157
+
HZ) == 0 ? -ETIMEDOUT : 0;
158
+
}
159
+
160
+
static void rzv2h_rspi_send(struct rzv2h_rspi_priv *rspi, const void *txbuf,
161
+
unsigned int index)
162
+
{
163
+
switch (rspi->bytes_per_word) {
164
+
case 4:
165
+
rzv2h_rspi_tx_u32(rspi, txbuf, index);
166
+
break;
167
+
case 2:
168
+
rzv2h_rspi_tx_u16(rspi, txbuf, index);
169
+
break;
170
+
default:
171
+
rzv2h_rspi_tx_u8(rspi, txbuf, index);
172
+
}
173
+
}
174
+
175
+
static int rzv2h_rspi_receive(struct rzv2h_rspi_priv *rspi, void *rxbuf,
176
+
unsigned int index)
177
+
{
178
+
int ret;
179
+
180
+
ret = rzv2h_rspi_wait_for_interrupt(rspi, RSPI_SPSR_SPRF);
181
+
if (ret)
182
+
return ret;
183
+
184
+
switch (rspi->bytes_per_word) {
185
+
case 4:
186
+
rzv2h_rspi_rx_u32(rspi, rxbuf, index);
187
+
break;
188
+
case 2:
189
+
rzv2h_rspi_rx_u16(rspi, rxbuf, index);
190
+
break;
191
+
default:
192
+
rzv2h_rspi_rx_u8(rspi, rxbuf, index);
193
+
}
194
+
195
+
return 0;
196
+
}
197
+
198
+
static int rzv2h_rspi_transfer_one(struct spi_controller *controller,
199
+
struct spi_device *spi,
200
+
struct spi_transfer *transfer)
201
+
{
202
+
struct rzv2h_rspi_priv *rspi = spi_controller_get_devdata(controller);
203
+
unsigned int words_to_transfer, i;
204
+
int ret = 0;
205
+
206
+
transfer->effective_speed_hz = rspi->freq;
207
+
words_to_transfer = transfer->len / rspi->bytes_per_word;
208
+
209
+
for (i = 0; i < words_to_transfer; i++) {
210
+
rzv2h_rspi_clear_all_irqs(rspi);
211
+
212
+
rzv2h_rspi_send(rspi, transfer->tx_buf, i);
213
+
214
+
ret = rzv2h_rspi_receive(rspi, transfer->rx_buf, i);
215
+
if (ret)
216
+
break;
217
+
}
218
+
219
+
rzv2h_rspi_clear_all_irqs(rspi);
220
+
221
+
if (ret)
222
+
transfer->error = SPI_TRANS_FAIL_IO;
223
+
224
+
spi_finalize_current_transfer(controller);
225
+
226
+
return ret;
227
+
}
228
+
229
+
static inline u32 rzv2h_rspi_calc_bitrate(unsigned long tclk_rate, u8 spr,
230
+
u8 brdv)
231
+
{
232
+
return DIV_ROUND_UP(tclk_rate, (2 * (spr + 1) * (1 << brdv)));
233
+
}
234
+
235
+
static u32 rzv2h_rspi_setup_clock(struct rzv2h_rspi_priv *rspi, u32 hz)
236
+
{
237
+
unsigned long tclk_rate;
238
+
int spr;
239
+
u8 brdv;
240
+
241
+
/*
242
+
* From the manual:
243
+
* Bit rate = f(RSPI_n_TCLK)/(2*(n+1)*2^(N))
244
+
*
245
+
* Where:
246
+
* * RSPI_n_TCLK is fixed to 200MHz on V2H
247
+
* * n = SPR - is RSPI_SPBR.SPR (from 0 to 255)
248
+
* * N = BRDV - is RSPI_SPCMD.BRDV (from 0 to 3)
249
+
*/
250
+
tclk_rate = clk_get_rate(rspi->tclk);
251
+
for (brdv = RSPI_SPCMD_BRDV_MIN; brdv <= RSPI_SPCMD_BRDV_MAX; brdv++) {
252
+
spr = DIV_ROUND_UP(tclk_rate, hz * (1 << (brdv + 1)));
253
+
spr--;
254
+
if (spr >= RSPI_SPBR_SPR_MIN && spr <= RSPI_SPBR_SPR_MAX)
255
+
goto clock_found;
256
+
}
257
+
258
+
return 0;
259
+
260
+
clock_found:
261
+
rzv2h_rspi_reg_rmw(rspi, RSPI_SPCMD, RSPI_SPCMD_BRDV, brdv);
262
+
writeb(spr, rspi->base + RSPI_SPBR);
263
+
264
+
return rzv2h_rspi_calc_bitrate(tclk_rate, spr, brdv);
265
+
}
266
+
267
+
static int rzv2h_rspi_prepare_message(struct spi_controller *ctlr,
268
+
struct spi_message *message)
269
+
{
270
+
struct rzv2h_rspi_priv *rspi = spi_controller_get_devdata(ctlr);
271
+
const struct spi_device *spi = message->spi;
272
+
struct spi_transfer *xfer;
273
+
u32 speed_hz = U32_MAX;
274
+
u8 bits_per_word;
275
+
u32 conf32;
276
+
u16 conf16;
277
+
278
+
/* Make sure SPCR.SPE is 0 before amending the configuration */
279
+
rzv2h_rspi_spe_disable(rspi);
280
+
281
+
/* Configure the device to work in "host" mode */
282
+
conf32 = RSPI_SPCR_MSTR;
283
+
284
+
/* Auto-stop function */
285
+
conf32 |= RSPI_SPCR_SCKASE;
286
+
287
+
/* SPI receive buffer full interrupt enable */
288
+
conf32 |= RSPI_SPCR_SPRIE;
289
+
290
+
writel(conf32, rspi->base + RSPI_SPCR);
291
+
292
+
/* Use SPCMD0 only */
293
+
writeb(0x0, rspi->base + RSPI_SPSCR);
294
+
295
+
/* Setup mode */
296
+
conf32 = FIELD_PREP(RSPI_SPCMD_CPOL, !!(spi->mode & SPI_CPOL));
297
+
conf32 |= FIELD_PREP(RSPI_SPCMD_CPHA, !!(spi->mode & SPI_CPHA));
298
+
conf32 |= FIELD_PREP(RSPI_SPCMD_LSBF, !!(spi->mode & SPI_LSB_FIRST));
299
+
conf32 |= FIELD_PREP(RSPI_SPCMD_SSLKP, 1);
300
+
conf32 |= FIELD_PREP(RSPI_SPCMD_SSLA, spi_get_chipselect(spi, 0));
301
+
writel(conf32, rspi->base + RSPI_SPCMD);
302
+
if (spi->mode & SPI_CS_HIGH)
303
+
writeb(BIT(spi_get_chipselect(spi, 0)), rspi->base + RSPI_SSLP);
304
+
else
305
+
writeb(0, rspi->base + RSPI_SSLP);
306
+
307
+
/* Setup FIFO thresholds */
308
+
conf16 = FIELD_PREP(RSPI_SPDCR2_TTRG, RSPI_FIFO_SIZE - 1);
309
+
conf16 |= FIELD_PREP(RSPI_SPDCR2_RTRG, 0);
310
+
writew(conf16, rspi->base + RSPI_SPDCR2);
311
+
312
+
rzv2h_rspi_clear_fifos(rspi);
313
+
314
+
list_for_each_entry(xfer, &message->transfers, transfer_list) {
315
+
if (!xfer->speed_hz)
316
+
continue;
317
+
318
+
speed_hz = min(xfer->speed_hz, speed_hz);
319
+
bits_per_word = xfer->bits_per_word;
320
+
}
321
+
322
+
if (speed_hz == U32_MAX)
323
+
return -EINVAL;
324
+
325
+
rspi->bytes_per_word = roundup_pow_of_two(BITS_TO_BYTES(bits_per_word));
326
+
rzv2h_rspi_reg_rmw(rspi, RSPI_SPCMD, RSPI_SPCMD_SPB, bits_per_word - 1);
327
+
328
+
rspi->freq = rzv2h_rspi_setup_clock(rspi, speed_hz);
329
+
if (!rspi->freq)
330
+
return -EINVAL;
331
+
332
+
rzv2h_rspi_spe_enable(rspi);
333
+
334
+
return 0;
335
+
}
336
+
337
+
static int rzv2h_rspi_unprepare_message(struct spi_controller *ctlr,
338
+
struct spi_message *message)
339
+
{
340
+
struct rzv2h_rspi_priv *rspi = spi_controller_get_devdata(ctlr);
341
+
342
+
rzv2h_rspi_spe_disable(rspi);
343
+
344
+
return 0;
345
+
}
346
+
347
+
static int rzv2h_rspi_probe(struct platform_device *pdev)
348
+
{
349
+
struct spi_controller *controller;
350
+
struct device *dev = &pdev->dev;
351
+
struct rzv2h_rspi_priv *rspi;
352
+
struct clk_bulk_data *clks;
353
+
unsigned long tclk_rate;
354
+
int irq_rx, ret, i;
355
+
356
+
controller = devm_spi_alloc_host(dev, sizeof(*rspi));
357
+
if (!controller)
358
+
return -ENOMEM;
359
+
360
+
rspi = spi_controller_get_devdata(controller);
361
+
platform_set_drvdata(pdev, rspi);
362
+
363
+
rspi->controller = controller;
364
+
365
+
rspi->base = devm_platform_ioremap_resource(pdev, 0);
366
+
if (IS_ERR(rspi->base))
367
+
return PTR_ERR(rspi->base);
368
+
369
+
ret = devm_clk_bulk_get_all_enabled(dev, &clks);
370
+
if (ret != RSPI_CLK_NUM)
371
+
return dev_err_probe(dev, ret >= 0 ? -EINVAL : ret,
372
+
"cannot get clocks\n");
373
+
for (i = 0; i < RSPI_CLK_NUM; i++) {
374
+
if (!strcmp(clks[i].id, "tclk")) {
375
+
rspi->tclk = clks[i].clk;
376
+
break;
377
+
}
378
+
}
379
+
380
+
if (!rspi->tclk)
381
+
return dev_err_probe(dev, -EINVAL, "Failed to get tclk\n");
382
+
383
+
tclk_rate = clk_get_rate(rspi->tclk);
384
+
385
+
rspi->resets[0].id = "presetn";
386
+
rspi->resets[1].id = "tresetn";
387
+
ret = devm_reset_control_bulk_get_exclusive(dev, RSPI_RESET_NUM,
388
+
rspi->resets);
389
+
if (ret)
390
+
return dev_err_probe(dev, ret, "cannot get resets\n");
391
+
392
+
irq_rx = platform_get_irq_byname(pdev, "rx");
393
+
if (irq_rx < 0)
394
+
return dev_err_probe(dev, irq_rx, "cannot get IRQ 'rx'\n");
395
+
396
+
ret = reset_control_bulk_deassert(RSPI_RESET_NUM, rspi->resets);
397
+
if (ret)
398
+
return dev_err_probe(dev, ret, "failed to deassert resets\n");
399
+
400
+
init_waitqueue_head(&rspi->wait);
401
+
402
+
ret = devm_request_irq(dev, irq_rx, rzv2h_rx_irq_handler, 0,
403
+
dev_name(dev), rspi);
404
+
if (ret) {
405
+
dev_err(dev, "cannot request `rx` IRQ\n");
406
+
goto quit_resets;
407
+
}
408
+
409
+
controller->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH |
410
+
SPI_LSB_FIRST;
411
+
controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
412
+
controller->prepare_message = rzv2h_rspi_prepare_message;
413
+
controller->unprepare_message = rzv2h_rspi_unprepare_message;
414
+
controller->num_chipselect = 4;
415
+
controller->transfer_one = rzv2h_rspi_transfer_one;
416
+
controller->min_speed_hz = rzv2h_rspi_calc_bitrate(tclk_rate,
417
+
RSPI_SPBR_SPR_MAX,
418
+
RSPI_SPCMD_BRDV_MAX);
419
+
controller->max_speed_hz = rzv2h_rspi_calc_bitrate(tclk_rate,
420
+
RSPI_SPBR_SPR_MIN,
421
+
RSPI_SPCMD_BRDV_MIN);
422
+
423
+
device_set_node(&controller->dev, dev_fwnode(dev));
424
+
425
+
ret = spi_register_controller(controller);
426
+
if (ret) {
427
+
dev_err(dev, "register controller failed\n");
428
+
goto quit_resets;
429
+
}
430
+
431
+
return 0;
432
+
433
+
quit_resets:
434
+
reset_control_bulk_assert(RSPI_RESET_NUM, rspi->resets);
435
+
436
+
return ret;
437
+
}
438
+
439
+
static void rzv2h_rspi_remove(struct platform_device *pdev)
440
+
{
441
+
struct rzv2h_rspi_priv *rspi = platform_get_drvdata(pdev);
442
+
443
+
spi_unregister_controller(rspi->controller);
444
+
445
+
reset_control_bulk_assert(RSPI_RESET_NUM, rspi->resets);
446
+
}
447
+
448
+
static const struct of_device_id rzv2h_rspi_match[] = {
449
+
{ .compatible = "renesas,r9a09g057-rspi" },
450
+
{ /* sentinel */ }
451
+
};
452
+
MODULE_DEVICE_TABLE(of, rzv2h_rspi_match);
453
+
454
+
static struct platform_driver rzv2h_rspi_drv = {
455
+
.probe = rzv2h_rspi_probe,
456
+
.remove = rzv2h_rspi_remove,
457
+
.driver = {
458
+
.name = "rzv2h_rspi",
459
+
.of_match_table = rzv2h_rspi_match,
460
+
},
461
+
};
462
+
module_platform_driver(rzv2h_rspi_drv);
463
+
464
+
MODULE_LICENSE("GPL");
465
+
MODULE_AUTHOR("Fabrizio Castro <fabrizio.castro.jz@renesas.com>");
466
+
MODULE_DESCRIPTION("Renesas RZ/V2H(P) Serial Peripheral Interface Driver");
-3
drivers/spi/spi-s3c64xx.c
-3
drivers/spi/spi-s3c64xx.c
···
1045
1045
}
1046
1046
}
1047
1047
1048
-
pm_runtime_mark_last_busy(&sdd->pdev->dev);
1049
1048
pm_runtime_put_autosuspend(&sdd->pdev->dev);
1050
1049
s3c64xx_spi_set_cs(spi, false);
1051
1050
1052
1051
return 0;
1053
1052
1054
1053
setup_exit:
1055
-
pm_runtime_mark_last_busy(&sdd->pdev->dev);
1056
1054
pm_runtime_put_autosuspend(&sdd->pdev->dev);
1057
1055
/* setup() returns with device de-selected */
1058
1056
s3c64xx_spi_set_cs(spi, false);
···
1382
1384
dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tFIFO %dbytes\n",
1383
1385
mem_res, sdd->fifo_depth);
1384
1386
1385
-
pm_runtime_mark_last_busy(&pdev->dev);
1386
1387
pm_runtime_put_autosuspend(&pdev->dev);
1387
1388
1388
1389
return 0;
+26
-3
drivers/spi/spi-sg2044-nor.c
+26
-3
drivers/spi/spi-sg2044-nor.c
···
84
84
85
85
#define SPIFMC_MAX_READ_SIZE 0x10000
86
86
87
+
struct sg204x_spifmc_chip_info {
88
+
bool has_opt_reg;
89
+
u32 rd_fifo_int_trigger_level;
90
+
};
91
+
87
92
struct sg2044_spifmc {
88
93
struct spi_controller *ctrl;
89
94
void __iomem *io_base;
90
95
struct device *dev;
91
96
struct mutex lock;
92
97
struct clk *clk;
98
+
const struct sg204x_spifmc_chip_info *chip_info;
93
99
};
94
100
95
101
static int sg2044_spifmc_wait_int(struct sg2044_spifmc *spifmc, u8 int_type)
···
145
139
146
140
reg = sg2044_spifmc_init_reg(spifmc);
147
141
reg |= (op->addr.nbytes + op->dummy.nbytes) << SPIFMC_TRAN_CSR_ADDR_BYTES_SHIFT;
148
-
reg |= SPIFMC_TRAN_CSR_FIFO_TRG_LVL_8_BYTE;
142
+
reg |= spifmc->chip_info->rd_fifo_int_trigger_level;
149
143
reg |= SPIFMC_TRAN_CSR_WITH_CMD;
150
144
reg |= SPIFMC_TRAN_CSR_TRAN_MODE_RX;
151
145
···
341
335
reg |= SPIFMC_TRAN_CSR_TRAN_MODE_RX;
342
336
reg |= SPIFMC_TRAN_CSR_TRAN_MODE_TX;
343
337
344
-
writel(SPIFMC_OPT_DISABLE_FIFO_FLUSH, spifmc->io_base + SPIFMC_OPT);
338
+
if (spifmc->chip_info->has_opt_reg)
339
+
writel(SPIFMC_OPT_DISABLE_FIFO_FLUSH, spifmc->io_base + SPIFMC_OPT);
345
340
} else {
346
341
/*
347
342
* If write values to the Status Register,
···
464
457
ret = devm_mutex_init(dev, &spifmc->lock);
465
458
if (ret)
466
459
return ret;
460
+
spifmc->chip_info = device_get_match_data(&pdev->dev);
461
+
if (!spifmc->chip_info) {
462
+
dev_err(&pdev->dev, "Failed to get specific chip info\n");
463
+
return -EINVAL;
464
+
}
467
465
468
466
sg2044_spifmc_init(spifmc);
469
467
sg2044_spifmc_init_reg(spifmc);
···
480
468
return 0;
481
469
}
482
470
471
+
static const struct sg204x_spifmc_chip_info sg2044_chip_info = {
472
+
.has_opt_reg = true,
473
+
.rd_fifo_int_trigger_level = SPIFMC_TRAN_CSR_FIFO_TRG_LVL_8_BYTE,
474
+
};
475
+
476
+
static const struct sg204x_spifmc_chip_info sg2042_chip_info = {
477
+
.has_opt_reg = false,
478
+
.rd_fifo_int_trigger_level = SPIFMC_TRAN_CSR_FIFO_TRG_LVL_1_BYTE,
479
+
};
480
+
483
481
static const struct of_device_id sg2044_spifmc_match[] = {
484
-
{ .compatible = "sophgo,sg2044-spifmc-nor" },
482
+
{ .compatible = "sophgo,sg2044-spifmc-nor", .data = &sg2044_chip_info },
483
+
{ .compatible = "sophgo,sg2042-spifmc-nor", .data = &sg2042_chip_info },
485
484
{ /* sentinel */ }
486
485
};
487
486
MODULE_DEVICE_TABLE(of, sg2044_spifmc_match);
+3
-8
drivers/spi/spi-sh-msiof.c
+3
-8
drivers/spi/spi-sh-msiof.c
···
1320
1320
};
1321
1321
MODULE_DEVICE_TABLE(platform, spi_driver_ids);
1322
1322
1323
-
#ifdef CONFIG_PM_SLEEP
1324
1323
static int sh_msiof_spi_suspend(struct device *dev)
1325
1324
{
1326
1325
struct sh_msiof_spi_priv *p = dev_get_drvdata(dev);
···
1334
1335
return spi_controller_resume(p->ctlr);
1335
1336
}
1336
1337
1337
-
static SIMPLE_DEV_PM_OPS(sh_msiof_spi_pm_ops, sh_msiof_spi_suspend,
1338
-
sh_msiof_spi_resume);
1339
-
#define DEV_PM_OPS (&sh_msiof_spi_pm_ops)
1340
-
#else
1341
-
#define DEV_PM_OPS NULL
1342
-
#endif /* CONFIG_PM_SLEEP */
1338
+
static DEFINE_SIMPLE_DEV_PM_OPS(sh_msiof_spi_pm_ops, sh_msiof_spi_suspend,
1339
+
sh_msiof_spi_resume);
1343
1340
1344
1341
static struct platform_driver sh_msiof_spi_drv = {
1345
1342
.probe = sh_msiof_spi_probe,
···
1343
1348
.id_table = spi_driver_ids,
1344
1349
.driver = {
1345
1350
.name = "spi_sh_msiof",
1346
-
.pm = DEV_PM_OPS,
1351
+
.pm = pm_sleep_ptr(&sh_msiof_spi_pm_ops),
1347
1352
.of_match_table = of_match_ptr(sh_msiof_match),
1348
1353
},
1349
1354
};
-1
drivers/spi/spi-sprd.c
-1
drivers/spi/spi-sprd.c
+5
-9
drivers/spi/spi-st-ssc4.c
+5
-9
drivers/spi/spi-st-ssc4.c
···
378
378
pinctrl_pm_select_sleep_state(&pdev->dev);
379
379
}
380
380
381
-
#ifdef CONFIG_PM
382
-
static int spi_st_runtime_suspend(struct device *dev)
381
+
static int __maybe_unused spi_st_runtime_suspend(struct device *dev)
383
382
{
384
383
struct spi_controller *host = dev_get_drvdata(dev);
385
384
struct spi_st *spi_st = spi_controller_get_devdata(host);
···
391
392
return 0;
392
393
}
393
394
394
-
static int spi_st_runtime_resume(struct device *dev)
395
+
static int __maybe_unused spi_st_runtime_resume(struct device *dev)
395
396
{
396
397
struct spi_controller *host = dev_get_drvdata(dev);
397
398
struct spi_st *spi_st = spi_controller_get_devdata(host);
···
402
403
403
404
return ret;
404
405
}
405
-
#endif
406
406
407
-
#ifdef CONFIG_PM_SLEEP
408
-
static int spi_st_suspend(struct device *dev)
407
+
static int __maybe_unused spi_st_suspend(struct device *dev)
409
408
{
410
409
struct spi_controller *host = dev_get_drvdata(dev);
411
410
int ret;
···
415
418
return pm_runtime_force_suspend(dev);
416
419
}
417
420
418
-
static int spi_st_resume(struct device *dev)
421
+
static int __maybe_unused spi_st_resume(struct device *dev)
419
422
{
420
423
struct spi_controller *host = dev_get_drvdata(dev);
421
424
int ret;
···
426
429
427
430
return pm_runtime_force_resume(dev);
428
431
}
429
-
#endif
430
432
431
433
static const struct dev_pm_ops spi_st_pm = {
432
434
SET_SYSTEM_SLEEP_PM_OPS(spi_st_suspend, spi_st_resume)
···
441
445
static struct platform_driver spi_st_driver = {
442
446
.driver = {
443
447
.name = "spi-st",
444
-
.pm = &spi_st_pm,
448
+
.pm = pm_sleep_ptr(&spi_st_pm),
445
449
.of_match_table = of_match_ptr(stm_spi_match),
446
450
},
447
451
.probe = spi_st_probe,
+9
-22
drivers/spi/spi-stm32-ospi.c
+9
-22
drivers/spi/spi-stm32-ospi.c
···
547
547
ret = stm32_ospi_send(mem->spi, op);
548
548
mutex_unlock(&ospi->lock);
549
549
550
-
pm_runtime_mark_last_busy(ospi->dev);
551
550
pm_runtime_put_autosuspend(ospi->dev);
552
551
553
552
return ret;
···
570
571
ret = stm32_ospi_send(mem->spi, op);
571
572
mutex_unlock(&ospi->lock);
572
573
573
-
pm_runtime_mark_last_busy(ospi->dev);
574
574
pm_runtime_put_autosuspend(ospi->dev);
575
575
576
576
return ret;
···
626
628
ret = stm32_ospi_send(desc->mem->spi, &op);
627
629
mutex_unlock(&ospi->lock);
628
630
629
-
pm_runtime_mark_last_busy(ospi->dev);
630
631
pm_runtime_put_autosuspend(ospi->dev);
631
632
632
633
return ret ?: len;
···
710
713
msg->status = ret;
711
714
spi_finalize_current_message(ctrl);
712
715
713
-
pm_runtime_mark_last_busy(ospi->dev);
714
716
pm_runtime_put_autosuspend(ospi->dev);
715
717
716
718
return ret;
···
746
750
747
751
mutex_unlock(&ospi->lock);
748
752
749
-
pm_runtime_mark_last_busy(ospi->dev);
750
753
pm_runtime_put_autosuspend(ospi->dev);
751
754
752
755
return 0;
···
766
771
{
767
772
struct device *dev = &pdev->dev;
768
773
struct stm32_ospi *ospi = platform_get_drvdata(pdev);
769
-
struct resource *res;
770
-
struct reserved_mem *rmem = NULL;
771
-
struct device_node *node;
774
+
struct resource *res, _res;
772
775
int ret;
773
776
774
777
ospi->regs_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
···
818
825
goto err_dma;
819
826
}
820
827
821
-
node = of_parse_phandle(dev->of_node, "memory-region", 0);
822
-
if (node)
823
-
rmem = of_reserved_mem_lookup(node);
824
-
of_node_put(node);
825
-
826
-
if (rmem) {
827
-
ospi->mm_size = rmem->size;
828
-
ospi->mm_base = devm_ioremap(dev, rmem->base, rmem->size);
829
-
if (!ospi->mm_base) {
830
-
dev_err(dev, "unable to map memory region: %pa+%pa\n",
831
-
&rmem->base, &rmem->size);
832
-
ret = -ENOMEM;
828
+
res = &_res;
829
+
ret = of_reserved_mem_region_to_resource(dev->of_node, 0, res);
830
+
if (!ret) {
831
+
ospi->mm_size = resource_size(res);
832
+
ospi->mm_base = devm_ioremap_resource(dev, res);
833
+
if (IS_ERR(ospi->mm_base)) {
834
+
dev_err(dev, "unable to map memory region: %pR\n", res);
835
+
ret = PTR_ERR(ospi->mm_base);
833
836
goto err_dma;
834
837
}
835
838
···
942
953
goto err_pm_resume;
943
954
}
944
955
945
-
pm_runtime_mark_last_busy(ospi->dev);
946
956
pm_runtime_put_autosuspend(ospi->dev);
947
957
948
958
return 0;
···
1020
1032
1021
1033
writel_relaxed(ospi->cr_reg, regs_base + OSPI_CR);
1022
1034
writel_relaxed(ospi->dcr_reg, regs_base + OSPI_DCR1);
1023
-
pm_runtime_mark_last_busy(ospi->dev);
1024
1035
pm_runtime_put_autosuspend(ospi->dev);
1025
1036
1026
1037
return 0;
-7
drivers/spi/spi-stm32-qspi.c
-7
drivers/spi/spi-stm32-qspi.c
···
463
463
ret = stm32_qspi_send(mem->spi, op);
464
464
mutex_unlock(&qspi->lock);
465
465
466
-
pm_runtime_mark_last_busy(qspi->dev);
467
466
pm_runtime_put_autosuspend(qspi->dev);
468
467
469
468
return ret;
···
486
487
ret = stm32_qspi_send(mem->spi, op);
487
488
mutex_unlock(&qspi->lock);
488
489
489
-
pm_runtime_mark_last_busy(qspi->dev);
490
490
pm_runtime_put_autosuspend(qspi->dev);
491
491
492
492
return ret;
···
541
543
ret = stm32_qspi_send(desc->mem->spi, &op);
542
544
mutex_unlock(&qspi->lock);
543
545
544
-
pm_runtime_mark_last_busy(qspi->dev);
545
546
pm_runtime_put_autosuspend(qspi->dev);
546
547
547
548
return ret ?: len;
···
624
627
msg->status = ret;
625
628
spi_finalize_current_message(ctrl);
626
629
627
-
pm_runtime_mark_last_busy(qspi->dev);
628
630
pm_runtime_put_autosuspend(qspi->dev);
629
631
630
632
return ret;
···
680
684
writel_relaxed(qspi->dcr_reg, qspi->io_base + QSPI_DCR);
681
685
mutex_unlock(&qspi->lock);
682
686
683
-
pm_runtime_mark_last_busy(qspi->dev);
684
687
pm_runtime_put_autosuspend(qspi->dev);
685
688
686
689
return 0;
···
853
858
if (ret)
854
859
goto err_pm_runtime_free;
855
860
856
-
pm_runtime_mark_last_busy(dev);
857
861
pm_runtime_put_autosuspend(dev);
858
862
859
863
return 0;
···
932
938
writel_relaxed(qspi->cr_reg, qspi->io_base + QSPI_CR);
933
939
writel_relaxed(qspi->dcr_reg, qspi->io_base + QSPI_DCR);
934
940
935
-
pm_runtime_mark_last_busy(dev);
936
941
pm_runtime_put_autosuspend(dev);
937
942
938
943
return 0;
+282
-34
drivers/spi/spi-stm32.c
+282
-34
drivers/spi/spi-stm32.c
···
9
9
#include <linux/debugfs.h>
10
10
#include <linux/clk.h>
11
11
#include <linux/delay.h>
12
+
#include <linux/dma-mapping.h>
12
13
#include <linux/dmaengine.h>
14
+
#include <linux/genalloc.h>
13
15
#include <linux/interrupt.h>
14
16
#include <linux/iopoll.h>
15
17
#include <linux/module.h>
···
156
154
/* STM32H7_SPI_I2SCFGR bit fields */
157
155
#define STM32H7_SPI_I2SCFGR_I2SMOD BIT(0)
158
156
157
+
/* STM32MP25_SPICFG2 bit fields */
158
+
#define STM32MP25_SPI_CFG2_RDIOM BIT(13)
159
+
159
160
/* STM32MP25 SPI registers bit fields */
160
161
#define STM32MP25_SPI_HWCFGR1 0x3F0
161
162
···
227
222
* @rx: SPI RX data register
228
223
* @tx: SPI TX data register
229
224
* @fullcfg: SPI full or limited feature set register
225
+
* @rdy_en: SPI ready feature register
230
226
*/
231
227
struct stm32_spi_regspec {
232
228
const struct stm32_spi_reg en;
···
241
235
const struct stm32_spi_reg rx;
242
236
const struct stm32_spi_reg tx;
243
237
const struct stm32_spi_reg fullcfg;
238
+
const struct stm32_spi_reg rdy_en;
244
239
};
245
240
246
241
struct stm32_spi;
···
283
276
int (*config)(struct stm32_spi *spi);
284
277
void (*set_bpw)(struct stm32_spi *spi);
285
278
int (*set_mode)(struct stm32_spi *spi, unsigned int comm_type);
286
-
void (*set_data_idleness)(struct stm32_spi *spi, u32 length);
279
+
void (*set_data_idleness)(struct stm32_spi *spi, struct spi_transfer *xfer);
287
280
int (*set_number_of_data)(struct stm32_spi *spi, u32 length);
288
281
void (*write_tx)(struct stm32_spi *spi);
289
282
void (*read_rx)(struct stm32_spi *spi);
···
330
323
* @dma_rx: dma channel for RX transfer
331
324
* @phys_addr: SPI registers physical base address
332
325
* @device_mode: the controller is configured as SPI device
326
+
* @sram_pool: SRAM pool for DMA transfers
327
+
* @sram_rx_buf_size: size of SRAM buffer for RX transfer
328
+
* @sram_rx_buf: SRAM buffer for RX transfer
329
+
* @sram_dma_rx_buf: SRAM buffer physical address for RX transfer
330
+
* @mdma_rx: MDMA channel for RX transfer
333
331
*/
334
332
struct stm32_spi {
335
333
struct device *dev;
···
369
357
dma_addr_t phys_addr;
370
358
371
359
bool device_mode;
360
+
361
+
struct gen_pool *sram_pool;
362
+
size_t sram_rx_buf_size;
363
+
void *sram_rx_buf;
364
+
dma_addr_t sram_dma_rx_buf;
365
+
struct dma_chan *mdma_rx;
372
366
};
373
367
374
368
static const struct stm32_spi_regspec stm32fx_spi_regspec = {
···
433
415
.tx = { STM32H7_SPI_TXDR },
434
416
435
417
.fullcfg = { STM32MP25_SPI_HWCFGR1, STM32MP25_SPI_HWCFGR1_FULLCFG },
418
+
419
+
.rdy_en = { STM32H7_SPI_CFG2, STM32MP25_SPI_CFG2_RDIOM },
436
420
};
437
421
438
422
static inline void stm32_spi_set_bits(struct stm32_spi *spi,
···
898
878
899
879
if (spi->cur_usedma && spi->dma_tx)
900
880
dmaengine_terminate_async(spi->dma_tx);
901
-
if (spi->cur_usedma && spi->dma_rx)
881
+
if (spi->cur_usedma && spi->dma_rx) {
902
882
dmaengine_terminate_async(spi->dma_rx);
883
+
if (spi->mdma_rx)
884
+
dmaengine_terminate_async(spi->mdma_rx);
885
+
}
903
886
904
887
stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
905
888
···
1114
1091
}
1115
1092
1116
1093
if (sr & STM32H7_SPI_SR_EOT) {
1094
+
dev_dbg(spi->dev, "End of transfer\n");
1117
1095
if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
1118
1096
stm32h7_spi_read_rxfifo(spi);
1119
1097
if (!spi->cur_usedma ||
1120
-
(spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX))
1098
+
(spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) ||
1099
+
(spi->mdma_rx && (spi->cur_comm == SPI_SIMPLEX_RX ||
1100
+
spi->cur_comm == SPI_FULL_DUPLEX)))
1121
1101
end = true;
1122
1102
}
1123
1103
···
1137
1111
spin_unlock_irqrestore(&spi->lock, flags);
1138
1112
1139
1113
if (end) {
1114
+
if (spi->cur_usedma && spi->mdma_rx) {
1115
+
dmaengine_pause(spi->dma_rx);
1116
+
/* Wait for callback */
1117
+
return IRQ_HANDLED;
1118
+
}
1140
1119
stm32h7_spi_disable(spi);
1141
1120
spi_finalize_current_transfer(ctrl);
1142
1121
}
···
1203
1172
else
1204
1173
clrb |= spi->cfg->regs->cs_high.mask;
1205
1174
1206
-
dev_dbg(spi->dev, "cpol=%d cpha=%d lsb_first=%d cs_high=%d\n",
1175
+
if (spi_dev->mode & SPI_READY)
1176
+
setb |= spi->cfg->regs->rdy_en.mask;
1177
+
else
1178
+
clrb |= spi->cfg->regs->rdy_en.mask;
1179
+
1180
+
dev_dbg(spi->dev, "cpol=%d cpha=%d lsb_first=%d cs_high=%d rdy=%d\n",
1207
1181
!!(spi_dev->mode & SPI_CPOL),
1208
1182
!!(spi_dev->mode & SPI_CPHA),
1209
1183
!!(spi_dev->mode & SPI_LSB_FIRST),
1210
-
!!(spi_dev->mode & SPI_CS_HIGH));
1184
+
!!(spi_dev->mode & SPI_CS_HIGH),
1185
+
!!(spi_dev->mode & SPI_READY));
1211
1186
1212
1187
spin_lock_irqsave(&spi->lock, flags);
1213
1188
1214
-
/* CPOL, CPHA and LSB FIRST bits have common register */
1189
+
/* CPOL, CPHA, LSB FIRST, CS_HIGH and RDY_EN bits have common register */
1215
1190
if (clrb || setb)
1216
1191
writel_relaxed(
1217
1192
(readl_relaxed(spi->base + spi->cfg->regs->cpol.reg) &
···
1447
1410
/* Enable the interrupts */
1448
1411
if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX)
1449
1412
ier |= STM32H7_SPI_IER_EOTIE | STM32H7_SPI_IER_TXTFIE;
1413
+
if (spi->mdma_rx && (spi->cur_comm == SPI_SIMPLEX_RX || spi->cur_comm == SPI_FULL_DUPLEX))
1414
+
ier |= STM32H7_SPI_IER_EOTIE;
1450
1415
1451
1416
stm32_spi_set_bits(spi, STM32H7_SPI_IER, ier);
1452
1417
···
1456
1417
1457
1418
if (STM32_SPI_HOST_MODE(spi))
1458
1419
stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART);
1420
+
}
1421
+
1422
+
/**
1423
+
* stm32_spi_prepare_rx_dma_mdma_chaining - Prepare RX DMA and MDMA chaining
1424
+
* @spi: pointer to the spi controller data structure
1425
+
* @xfer: pointer to the spi transfer
1426
+
* @rx_dma_conf: pointer to the DMA configuration for RX channel
1427
+
* @rx_dma_desc: pointer to the RX DMA descriptor
1428
+
* @rx_mdma_desc: pointer to the RX MDMA descriptor
1429
+
*
1430
+
* It must return 0 if the chaining is possible or an error code if not.
1431
+
*/
1432
+
static int stm32_spi_prepare_rx_dma_mdma_chaining(struct stm32_spi *spi,
1433
+
struct spi_transfer *xfer,
1434
+
struct dma_slave_config *rx_dma_conf,
1435
+
struct dma_async_tx_descriptor **rx_dma_desc,
1436
+
struct dma_async_tx_descriptor **rx_mdma_desc)
1437
+
{
1438
+
struct dma_async_tx_descriptor *_mdma_desc = *rx_mdma_desc;
1439
+
struct dma_async_tx_descriptor *_dma_desc = *rx_dma_desc;
1440
+
struct dma_slave_config rx_mdma_conf = {0};
1441
+
u32 sram_period, nents = 0, spi_s_len;
1442
+
struct sg_table dma_sgt, mdma_sgt;
1443
+
struct scatterlist *spi_s, *s;
1444
+
dma_addr_t dma_buf;
1445
+
int i, ret;
1446
+
1447
+
sram_period = spi->sram_rx_buf_size / 2;
1448
+
1449
+
/* Configure MDMA RX channel */
1450
+
rx_mdma_conf.direction = rx_dma_conf->direction;
1451
+
rx_mdma_conf.src_addr = spi->sram_dma_rx_buf;
1452
+
rx_mdma_conf.peripheral_config = rx_dma_conf->peripheral_config;
1453
+
rx_mdma_conf.peripheral_size = rx_dma_conf->peripheral_size;
1454
+
dmaengine_slave_config(spi->mdma_rx, &rx_mdma_conf);
1455
+
1456
+
/* Count the number of entries needed */
1457
+
for_each_sg(xfer->rx_sg.sgl, spi_s, xfer->rx_sg.nents, i)
1458
+
if (sg_dma_len(spi_s) > sram_period)
1459
+
nents += DIV_ROUND_UP(sg_dma_len(spi_s), sram_period);
1460
+
else
1461
+
nents++;
1462
+
1463
+
/* Prepare DMA slave_sg DBM transfer DEV_TO_MEM (RX>MEM=SRAM) */
1464
+
ret = sg_alloc_table(&dma_sgt, nents, GFP_ATOMIC);
1465
+
if (ret)
1466
+
return ret;
1467
+
1468
+
spi_s = xfer->rx_sg.sgl;
1469
+
spi_s_len = sg_dma_len(spi_s);
1470
+
dma_buf = spi->sram_dma_rx_buf;
1471
+
for_each_sg(dma_sgt.sgl, s, dma_sgt.nents, i) {
1472
+
size_t bytes = min_t(size_t, spi_s_len, sram_period);
1473
+
1474
+
sg_dma_len(s) = bytes;
1475
+
sg_dma_address(s) = dma_buf;
1476
+
spi_s_len -= bytes;
1477
+
1478
+
if (!spi_s_len && sg_next(spi_s)) {
1479
+
spi_s = sg_next(spi_s);
1480
+
spi_s_len = sg_dma_len(spi_s);
1481
+
dma_buf = spi->sram_dma_rx_buf;
1482
+
} else { /* DMA configured in DBM: it will swap between the SRAM periods */
1483
+
if (i & 1)
1484
+
dma_buf += sram_period;
1485
+
else
1486
+
dma_buf = spi->sram_dma_rx_buf;
1487
+
}
1488
+
}
1489
+
1490
+
_dma_desc = dmaengine_prep_slave_sg(spi->dma_rx, dma_sgt.sgl,
1491
+
dma_sgt.nents, rx_dma_conf->direction,
1492
+
DMA_PREP_INTERRUPT);
1493
+
sg_free_table(&dma_sgt);
1494
+
1495
+
if (!_dma_desc)
1496
+
return -EINVAL;
1497
+
1498
+
/* Prepare MDMA slave_sg transfer MEM_TO_MEM (SRAM>DDR) */
1499
+
ret = sg_alloc_table(&mdma_sgt, nents, GFP_ATOMIC);
1500
+
if (ret) {
1501
+
_dma_desc = NULL;
1502
+
return ret;
1503
+
}
1504
+
1505
+
spi_s = xfer->rx_sg.sgl;
1506
+
spi_s_len = sg_dma_len(spi_s);
1507
+
dma_buf = sg_dma_address(spi_s);
1508
+
for_each_sg(mdma_sgt.sgl, s, mdma_sgt.nents, i) {
1509
+
size_t bytes = min_t(size_t, spi_s_len, sram_period);
1510
+
1511
+
sg_dma_len(s) = bytes;
1512
+
sg_dma_address(s) = dma_buf;
1513
+
spi_s_len -= bytes;
1514
+
1515
+
if (!spi_s_len && sg_next(spi_s)) {
1516
+
spi_s = sg_next(spi_s);
1517
+
spi_s_len = sg_dma_len(spi_s);
1518
+
dma_buf = sg_dma_address(spi_s);
1519
+
} else {
1520
+
dma_buf += bytes;
1521
+
}
1522
+
}
1523
+
1524
+
_mdma_desc = dmaengine_prep_slave_sg(spi->mdma_rx, mdma_sgt.sgl,
1525
+
mdma_sgt.nents, rx_mdma_conf.direction,
1526
+
DMA_PREP_INTERRUPT);
1527
+
sg_free_table(&mdma_sgt);
1528
+
1529
+
if (!_mdma_desc) {
1530
+
_dma_desc = NULL;
1531
+
return -EINVAL;
1532
+
}
1533
+
1534
+
return 0;
1459
1535
}
1460
1536
1461
1537
/**
···
1584
1430
static int stm32_spi_transfer_one_dma(struct stm32_spi *spi,
1585
1431
struct spi_transfer *xfer)
1586
1432
{
1433
+
struct dma_async_tx_descriptor *rx_mdma_desc = NULL, *rx_dma_desc = NULL;
1434
+
struct dma_async_tx_descriptor *tx_dma_desc = NULL;
1587
1435
struct dma_slave_config tx_dma_conf, rx_dma_conf;
1588
-
struct dma_async_tx_descriptor *tx_dma_desc, *rx_dma_desc;
1589
1436
unsigned long flags;
1437
+
int ret = 0;
1590
1438
1591
1439
spin_lock_irqsave(&spi->lock, flags);
1592
1440
1593
-
rx_dma_desc = NULL;
1594
1441
if (spi->rx_buf && spi->dma_rx) {
1595
1442
stm32_spi_dma_config(spi, spi->dma_rx, &rx_dma_conf, DMA_DEV_TO_MEM);
1596
-
dmaengine_slave_config(spi->dma_rx, &rx_dma_conf);
1443
+
if (spi->mdma_rx) {
1444
+
rx_dma_conf.peripheral_size = 1;
1445
+
dmaengine_slave_config(spi->dma_rx, &rx_dma_conf);
1597
1446
1598
-
/* Enable Rx DMA request */
1599
-
stm32_spi_set_bits(spi, spi->cfg->regs->dma_rx_en.reg,
1600
-
spi->cfg->regs->dma_rx_en.mask);
1601
-
1602
-
rx_dma_desc = dmaengine_prep_slave_sg(
1603
-
spi->dma_rx, xfer->rx_sg.sgl,
1604
-
xfer->rx_sg.nents,
1605
-
rx_dma_conf.direction,
1606
-
DMA_PREP_INTERRUPT);
1447
+
ret = stm32_spi_prepare_rx_dma_mdma_chaining(spi, xfer, &rx_dma_conf,
1448
+
&rx_dma_desc, &rx_mdma_desc);
1449
+
if (ret) { /* RX DMA MDMA chaining not possible, fallback to DMA only */
1450
+
rx_dma_conf.peripheral_config = 0;
1451
+
rx_dma_desc = NULL;
1452
+
}
1453
+
}
1454
+
if (!rx_dma_desc) {
1455
+
dmaengine_slave_config(spi->dma_rx, &rx_dma_conf);
1456
+
rx_dma_desc = dmaengine_prep_slave_sg(spi->dma_rx, xfer->rx_sg.sgl,
1457
+
xfer->rx_sg.nents,
1458
+
rx_dma_conf.direction,
1459
+
DMA_PREP_INTERRUPT);
1460
+
}
1607
1461
}
1608
1462
1609
-
tx_dma_desc = NULL;
1610
1463
if (spi->tx_buf && spi->dma_tx) {
1611
1464
stm32_spi_dma_config(spi, spi->dma_tx, &tx_dma_conf, DMA_MEM_TO_DEV);
1612
1465
dmaengine_slave_config(spi->dma_tx, &tx_dma_conf);
1613
-
1614
-
tx_dma_desc = dmaengine_prep_slave_sg(
1615
-
spi->dma_tx, xfer->tx_sg.sgl,
1616
-
xfer->tx_sg.nents,
1617
-
tx_dma_conf.direction,
1618
-
DMA_PREP_INTERRUPT);
1466
+
tx_dma_desc = dmaengine_prep_slave_sg(spi->dma_tx, xfer->tx_sg.sgl,
1467
+
xfer->tx_sg.nents,
1468
+
tx_dma_conf.direction,
1469
+
DMA_PREP_INTERRUPT);
1619
1470
}
1620
1471
1621
1472
if ((spi->tx_buf && spi->dma_tx && !tx_dma_desc) ||
···
1631
1472
goto dma_desc_error;
1632
1473
1633
1474
if (rx_dma_desc) {
1634
-
rx_dma_desc->callback = spi->cfg->dma_rx_cb;
1635
-
rx_dma_desc->callback_param = spi;
1475
+
if (rx_mdma_desc) {
1476
+
rx_mdma_desc->callback = spi->cfg->dma_rx_cb;
1477
+
rx_mdma_desc->callback_param = spi;
1478
+
} else {
1479
+
rx_dma_desc->callback = spi->cfg->dma_rx_cb;
1480
+
rx_dma_desc->callback_param = spi;
1481
+
}
1636
1482
1483
+
/* Enable Rx DMA request */
1484
+
stm32_spi_set_bits(spi, spi->cfg->regs->dma_rx_en.reg,
1485
+
spi->cfg->regs->dma_rx_en.mask);
1486
+
if (rx_mdma_desc) {
1487
+
if (dma_submit_error(dmaengine_submit(rx_mdma_desc))) {
1488
+
dev_err(spi->dev, "Rx MDMA submit failed\n");
1489
+
goto dma_desc_error;
1490
+
}
1491
+
/* Enable Rx MDMA channel */
1492
+
dma_async_issue_pending(spi->mdma_rx);
1493
+
}
1637
1494
if (dma_submit_error(dmaengine_submit(rx_dma_desc))) {
1638
1495
dev_err(spi->dev, "Rx DMA submit failed\n");
1639
1496
goto dma_desc_error;
···
1684
1509
return 1;
1685
1510
1686
1511
dma_submit_error:
1512
+
if (spi->mdma_rx)
1513
+
dmaengine_terminate_sync(spi->mdma_rx);
1687
1514
if (spi->dma_rx)
1688
1515
dmaengine_terminate_sync(spi->dma_rx);
1689
1516
···
1696
1519
spin_unlock_irqrestore(&spi->lock, flags);
1697
1520
1698
1521
dev_info(spi->dev, "DMA issue: fall back to irq transfer\n");
1522
+
1523
+
if (spi->sram_rx_buf)
1524
+
memset(spi->sram_rx_buf, 0, spi->sram_rx_buf_size);
1699
1525
1700
1526
spi->cur_usedma = false;
1701
1527
return spi->cfg->transfer_one_irq(spi);
···
1882
1702
* stm32h7_spi_data_idleness - configure minimum time delay inserted between two
1883
1703
* consecutive data frames in host mode
1884
1704
* @spi: pointer to the spi controller data structure
1885
-
* @len: transfer len
1705
+
* @xfer: pointer to spi transfer
1886
1706
*/
1887
-
static void stm32h7_spi_data_idleness(struct stm32_spi *spi, u32 len)
1707
+
static void stm32h7_spi_data_idleness(struct stm32_spi *spi, struct spi_transfer *xfer)
1888
1708
{
1889
1709
u32 cfg2_clrb = 0, cfg2_setb = 0;
1710
+
u32 len = xfer->len;
1711
+
u32 spi_delay_ns;
1712
+
1713
+
spi_delay_ns = spi_delay_to_ns(&xfer->word_delay, xfer);
1714
+
1715
+
if (spi->cur_midi != 0) {
1716
+
dev_warn(spi->dev, "st,spi-midi-ns DT property is deprecated\n");
1717
+
if (spi_delay_ns) {
1718
+
dev_warn(spi->dev, "Overriding st,spi-midi-ns with word_delay_ns %d\n",
1719
+
spi_delay_ns);
1720
+
spi->cur_midi = spi_delay_ns;
1721
+
}
1722
+
} else {
1723
+
spi->cur_midi = spi_delay_ns;
1724
+
}
1890
1725
1891
1726
cfg2_clrb |= STM32H7_SPI_CFG2_MIDI;
1892
1727
if ((len > 1) && (spi->cur_midi > 0)) {
···
1963
1768
spi->cur_bpw = transfer->bits_per_word;
1964
1769
spi->cfg->set_bpw(spi);
1965
1770
1771
+
if (spi_dev->mode & SPI_READY && spi->cur_bpw < 8) {
1772
+
writel_relaxed(readl_relaxed(spi->base + spi->cfg->regs->rdy_en.reg) &
1773
+
~spi->cfg->regs->rdy_en.mask,
1774
+
spi->base + spi->cfg->regs->rdy_en.reg);
1775
+
dev_dbg(spi->dev, "RDY logic disabled as bits per word < 8\n");
1776
+
}
1777
+
1966
1778
/* Update spi->cur_speed with real clock speed */
1967
1779
if (STM32_SPI_HOST_MODE(spi)) {
1968
1780
mbr = stm32_spi_prepare_mbr(spi, transfer->speed_hz,
···
1992
1790
spi->cur_comm = comm_type;
1993
1791
1994
1792
if (STM32_SPI_HOST_MODE(spi) && spi->cfg->set_data_idleness)
1995
-
spi->cfg->set_data_idleness(spi, transfer->len);
1793
+
spi->cfg->set_data_idleness(spi, transfer);
1996
1794
1997
1795
if (spi->cur_bpw <= 8)
1998
1796
nb_words = transfer->len;
···
2072
1870
struct stm32_spi *spi = spi_controller_get_devdata(ctrl);
2073
1871
2074
1872
spi->cfg->disable(spi);
1873
+
1874
+
if (spi->sram_rx_buf)
1875
+
memset(spi->sram_rx_buf, 0, spi->sram_rx_buf_size);
2075
1876
2076
1877
return 0;
2077
1878
}
···
2274
2069
struct resource *res;
2275
2070
struct reset_control *rst;
2276
2071
struct device_node *np = pdev->dev.of_node;
2072
+
const struct stm32_spi_cfg *cfg;
2277
2073
bool device_mode;
2278
2074
int ret;
2279
-
const struct stm32_spi_cfg *cfg = of_device_get_match_data(&pdev->dev);
2075
+
2076
+
cfg = of_device_get_match_data(&pdev->dev);
2077
+
if (!cfg) {
2078
+
dev_err(&pdev->dev, "Failed to get match data for platform\n");
2079
+
return -ENODEV;
2080
+
}
2280
2081
2281
2082
device_mode = of_property_read_bool(np, "spi-slave");
2282
2083
if (!cfg->has_device_mode && device_mode) {
···
2390
2179
ctrl->auto_runtime_pm = true;
2391
2180
ctrl->bus_num = pdev->id;
2392
2181
ctrl->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST |
2393
-
SPI_3WIRE;
2182
+
SPI_3WIRE | SPI_READY;
2394
2183
ctrl->bits_per_word_mask = spi->cfg->get_bpw_mask(spi);
2395
2184
ctrl->max_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_min;
2396
2185
ctrl->min_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_max;
···
2430
2219
if (spi->dma_tx || spi->dma_rx)
2431
2220
ctrl->can_dma = stm32_spi_can_dma;
2432
2221
2222
+
spi->sram_pool = of_gen_pool_get(pdev->dev.of_node, "sram", 0);
2223
+
if (spi->sram_pool) {
2224
+
spi->sram_rx_buf_size = gen_pool_size(spi->sram_pool);
2225
+
dev_info(&pdev->dev, "SRAM pool: %zu KiB for RX DMA/MDMA chaining\n",
2226
+
spi->sram_rx_buf_size / 1024);
2227
+
spi->sram_rx_buf = gen_pool_dma_zalloc(spi->sram_pool, spi->sram_rx_buf_size,
2228
+
&spi->sram_dma_rx_buf);
2229
+
if (!spi->sram_rx_buf) {
2230
+
dev_err(&pdev->dev, "failed to allocate SRAM buffer\n");
2231
+
} else {
2232
+
spi->mdma_rx = dma_request_chan(spi->dev, "rxm2m");
2233
+
if (IS_ERR(spi->mdma_rx)) {
2234
+
ret = PTR_ERR(spi->mdma_rx);
2235
+
spi->mdma_rx = NULL;
2236
+
if (ret == -EPROBE_DEFER) {
2237
+
goto err_pool_free;
2238
+
} else {
2239
+
gen_pool_free(spi->sram_pool,
2240
+
(unsigned long)spi->sram_rx_buf,
2241
+
spi->sram_rx_buf_size);
2242
+
dev_warn(&pdev->dev,
2243
+
"failed to request rx mdma channel, DMA only\n");
2244
+
}
2245
+
}
2246
+
}
2247
+
}
2248
+
2433
2249
pm_runtime_set_autosuspend_delay(&pdev->dev,
2434
2250
STM32_SPI_AUTOSUSPEND_DELAY);
2435
2251
pm_runtime_use_autosuspend(&pdev->dev);
···
2471
2233
goto err_pm_disable;
2472
2234
}
2473
2235
2474
-
pm_runtime_mark_last_busy(&pdev->dev);
2475
2236
pm_runtime_put_autosuspend(&pdev->dev);
2476
2237
2477
2238
dev_info(&pdev->dev, "driver initialized (%s mode)\n",
···
2483
2246
pm_runtime_put_noidle(&pdev->dev);
2484
2247
pm_runtime_set_suspended(&pdev->dev);
2485
2248
pm_runtime_dont_use_autosuspend(&pdev->dev);
2249
+
2250
+
if (spi->mdma_rx)
2251
+
dma_release_channel(spi->mdma_rx);
2252
+
err_pool_free:
2253
+
if (spi->sram_pool)
2254
+
gen_pool_free(spi->sram_pool, (unsigned long)spi->sram_rx_buf,
2255
+
spi->sram_rx_buf_size);
2486
2256
err_dma_release:
2487
2257
if (spi->dma_tx)
2488
2258
dma_release_channel(spi->dma_tx);
···
2520
2276
dma_release_channel(ctrl->dma_tx);
2521
2277
if (ctrl->dma_rx)
2522
2278
dma_release_channel(ctrl->dma_rx);
2279
+
if (spi->mdma_rx)
2280
+
dma_release_channel(spi->mdma_rx);
2281
+
if (spi->sram_rx_buf)
2282
+
gen_pool_free(spi->sram_pool, (unsigned long)spi->sram_rx_buf,
2283
+
spi->sram_rx_buf_size);
2523
2284
2524
2285
clk_disable_unprepare(spi->clk);
2525
2286
···
2591
2342
2592
2343
spi->cfg->config(spi);
2593
2344
2594
-
pm_runtime_mark_last_busy(dev);
2595
2345
pm_runtime_put_autosuspend(dev);
2596
2346
2597
2347
return 0;
-2
drivers/spi/spi-ti-qspi.c
-2
drivers/spi/spi-ti-qspi.c
···
158
158
return ret;
159
159
}
160
160
161
-
pm_runtime_mark_last_busy(qspi->dev);
162
161
ret = pm_runtime_put_autosuspend(qspi->dev);
163
162
if (ret < 0) {
164
163
dev_err(qspi->dev, "pm_runtime_put_autosuspend() failed\n");
···
194
195
ctx_reg->clkctrl = clk_ctrl_new;
195
196
}
196
197
197
-
pm_runtime_mark_last_busy(qspi->dev);
198
198
pm_runtime_put_autosuspend(qspi->dev);
199
199
}
200
200
+3
-2
drivers/spi/spi-xilinx.c
+3
-2
drivers/spi/spi-xilinx.c
···
89
89
u8 bytes_per_word;
90
90
int buffer_size; /* buffer size in words */
91
91
u32 cs_inactive; /* Level of the CS pins when inactive*/
92
-
unsigned int (*read_fn)(void __iomem *);
93
-
void (*write_fn)(u32, void __iomem *);
92
+
unsigned int (*read_fn)(void __iomem *addr);
93
+
void (*write_fn)(u32 val, void __iomem *addr);
94
94
};
95
95
96
96
static void xspi_write32(u32 val, void __iomem *addr)
···
251
251
if (xspi->irq >= 0 &&
252
252
(xspi->force_irq || remaining_words > xspi->buffer_size)) {
253
253
u32 isr;
254
+
254
255
use_irq = true;
255
256
/* Inhibit irq to avoid spurious irqs on tx_empty*/
256
257
cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET);
-1
drivers/spi/spi-zynqmp-gqspi.c
-1
drivers/spi/spi-zynqmp-gqspi.c
-3
drivers/spi/spi.c
-3
drivers/spi/spi.c
···
1723
1723
static void spi_idle_runtime_pm(struct spi_controller *ctlr)
1724
1724
{
1725
1725
if (ctlr->auto_runtime_pm) {
1726
-
pm_runtime_mark_last_busy(ctlr->dev.parent);
1727
1726
pm_runtime_put_autosuspend(ctlr->dev.parent);
1728
1727
}
1729
1728
}
···
3855
3856
}
3856
3857
3857
3858
status = spi->controller->set_cs_timing(spi);
3858
-
pm_runtime_mark_last_busy(parent);
3859
3859
pm_runtime_put_autosuspend(parent);
3860
3860
} else {
3861
3861
status = spi->controller->set_cs_timing(spi);
···
3989
3991
status = 0;
3990
3992
3991
3993
spi_set_cs(spi, false, true);
3992
-
pm_runtime_mark_last_busy(spi->controller->dev.parent);
3993
3994
pm_runtime_put_autosuspend(spi->controller->dev.parent);
3994
3995
} else {
3995
3996
spi_set_cs(spi, false, true);
+2
drivers/spi/spidev.c
+2
drivers/spi/spidev.c
···
703
703
* spidev_dt_ids array below. Both arrays are kept in the same ordering.
704
704
*/
705
705
static const struct spi_device_id spidev_spi_ids[] = {
706
+
{ .name = /* abb */ "spi-sensor" },
706
707
{ .name = /* cisco */ "spi-petra" },
707
708
{ .name = /* dh */ "dhcom-board" },
708
709
{ .name = /* elgin */ "jg10309-01" },
···
736
735
}
737
736
738
737
static const struct of_device_id spidev_dt_ids[] = {
738
+
{ .compatible = "abb,spi-sensor", .data = &spidev_of_check },
739
739
{ .compatible = "cisco,spi-petra", .data = &spidev_of_check },
740
740
{ .compatible = "dh,dhcom-board", .data = &spidev_of_check },
741
741
{ .compatible = "elgin,jg10309-01", .data = &spidev_of_check },
+7
include/linux/dmaengine.h
+7
include/linux/dmaengine.h
···
1524
1524
1525
1525
struct dma_chan *dma_request_chan(struct device *dev, const char *name);
1526
1526
struct dma_chan *dma_request_chan_by_mask(const dma_cap_mask_t *mask);
1527
+
struct dma_chan *devm_dma_request_chan(struct device *dev, const char *name);
1527
1528
1528
1529
void dma_release_channel(struct dma_chan *chan);
1529
1530
int dma_get_slave_caps(struct dma_chan *chan, struct dma_slave_caps *caps);
···
1561
1560
{
1562
1561
return ERR_PTR(-ENODEV);
1563
1562
}
1563
+
1564
+
static inline struct dma_chan *devm_dma_request_chan(struct device *dev, const char *name)
1565
+
{
1566
+
return ERR_PTR(-ENODEV);
1567
+
}
1568
+
1564
1569
static inline void dma_release_channel(struct dma_chan *chan)
1565
1570
{
1566
1571
}
+2
include/linux/mtd/nand-qpic-common.h
+2
include/linux/mtd/nand-qpic-common.h
···
101
101
#define ECC_SW_RESET BIT(1)
102
102
#define ECC_MODE 4
103
103
#define ECC_MODE_MASK GENMASK(5, 4)
104
+
#define ECC_MODE_4BIT 0
105
+
#define ECC_MODE_8BIT 1
104
106
#define ECC_PARITY_SIZE_BYTES_BCH 8
105
107
#define ECC_PARITY_SIZE_BYTES_BCH_MASK GENMASK(12, 8)
106
108
#define ECC_NUM_DATA_BYTES 16