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powerpc/perf: Fix the PMU group constraints for threshold events in power10

The PMU group constraints mask for threshold events covers
all thresholding bits which includes threshold control value
(start/stop), select value as well as thresh_cmp value (MMCRA[9:18].
In power9, thresh_cmp bits were part of the event code. But in case
of power10, thresh_cmp bits are not part of event code due to
inclusion of MMCR3 bits. Hence thresh_cmp is not valid for
group constraints for power10.

Fix the PMU group constraints checking for threshold events in
power10 by using constraint mask and value for only threshold control
and select bits.

Fixes: a64e697cef23 ("powerpc/perf: power10 Performance Monitoring support")
Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/1606409684-1589-4-git-send-email-atrajeev@linux.vnet.ibm.com

authored by

Athira Rajeev and committed by
Michael Ellerman 0263bbb3 e924be7b

+9 -1
+6 -1
arch/powerpc/perf/isa207-common.c
··· 351 351 value |= CNST_SAMPLE_VAL(event >> EVENT_SAMPLE_SHIFT); 352 352 } 353 353 354 - if (cpu_has_feature(CPU_FTR_ARCH_300)) { 354 + if (cpu_has_feature(CPU_FTR_ARCH_31)) { 355 + if (event_is_threshold(event)) { 356 + mask |= CNST_THRESH_CTL_SEL_MASK; 357 + value |= CNST_THRESH_CTL_SEL_VAL(event >> EVENT_THRESH_SHIFT); 358 + } 359 + } else if (cpu_has_feature(CPU_FTR_ARCH_300)) { 355 360 if (event_is_threshold(event) && is_thresh_cmp_valid(event)) { 356 361 mask |= CNST_THRESH_MASK; 357 362 value |= CNST_THRESH_VAL(event >> EVENT_THRESH_SHIFT);
+3
arch/powerpc/perf/isa207-common.h
··· 149 149 #define CNST_THRESH_VAL(v) (((v) & EVENT_THRESH_MASK) << 32) 150 150 #define CNST_THRESH_MASK CNST_THRESH_VAL(EVENT_THRESH_MASK) 151 151 152 + #define CNST_THRESH_CTL_SEL_VAL(v) (((v) & 0x7ffull) << 32) 153 + #define CNST_THRESH_CTL_SEL_MASK CNST_THRESH_CTL_SEL_VAL(0x7ff) 154 + 152 155 #define CNST_EBB_VAL(v) (((v) & EVENT_EBB_MASK) << 24) 153 156 #define CNST_EBB_MASK CNST_EBB_VAL(EVENT_EBB_MASK) 154 157