tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'drm-fixes-2022-04-15' of git://anongit.freedesktop.org/drm/drm

Pull drm fixes from Dave Airlie:
"Eggs season holidays are among us, and I think I'd expect some smaller
pulls for two weeks then.

This seems eerily quiet. One i915 fix, amdgpu has a bunch and msm. I
didn't see a misc pull this week, so I expect that will catch up next
week.

i915:
- Correct legacy mmap disabling to use GRAPHICS_VER_FULL

msm:
- system suspend fix
- kzalloc return checks
- misc display fix
- iommu_present removal

amdgpu:
- Fix for alpha properly in pre-multiplied mode
- Fix VCN 3.1.2 firmware name
- Suspend/resume fix
- Add a gfxoff quirk for Mac vega20 board
- DCN 3.1.6 spread spectrum fix"

* tag 'drm-fixes-2022-04-15' of git://anongit.freedesktop.org/drm/drm:
drm/amd/display: remove dtbclk_ss compensation for dcn316
drm/amdgpu: Enable gfxoff quirk on MacBook Pro
drm/amdgpu: Ensure HDA function is suspended before ASIC reset
drm/amdgpu: fix VCN 3.1.2 firmware name
drm/amd/display: don't ignore alpha property on pre-multiplied mode
drm/msm/gpu: Avoid -Wunused-function with !CONFIG_PM_SLEEP
drm/msm/dp: add fail safe mode outside of event_mutex context
drm/msm/dsi: Use connector directly in msm_dsi_manager_connector_init()
drm/msm: Stop using iommu_present()
drm/msm/mdp5: check the return of kzalloc()
drm/msm: Fix range size vs end confusion
drm/i915: Sunset igpu legacy mmap support based on GRAPHICS_VER_FULL
drm/msm/dpu: Use indexed array initializer to prevent mismatches
drm/msm/disp: check the return value of kzalloc()
dt-bindings: display/msm: another fix for the dpu-qcm2290 example
drm/msm: Add missing put_task_struct() in debugfs path
drm/msm/gpu: Remove mutex from wait_event condition
drm/msm/gpu: Park scheduler threads for system suspend
drm/msm/gpu: Rename runtime suspend/resume functions

Linus Torvalds 028192fe 38a5e3fb

+154 -77
+2 -2
Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml
··· 160 160 mdss: mdss@5e00000 { 161 161 #address-cells = <1>; 162 162 #size-cells = <1>; 163 - compatible = "qcom,qcm2290-mdss", "qcom,mdss"; 163 + compatible = "qcom,qcm2290-mdss"; 164 164 reg = <0x05e00000 0x1000>; 165 165 reg-names = "mdss"; 166 166 power-domains = <&dispcc MDSS_GDSC>; ··· 180 180 <&apps_smmu 0x421 0x0>; 181 181 ranges; 182 182 183 - mdss_mdp: mdp@5e01000 { 183 + mdss_mdp: display-controller@5e01000 { 184 184 compatible = "qcom,qcm2290-dpu"; 185 185 reg = <0x05e01000 0x8f000>, 186 186 <0x05eb0000 0x2008>;
+12 -6
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
··· 2323 2323 { 2324 2324 struct drm_device *drm_dev = dev_get_drvdata(dev); 2325 2325 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2326 - int r; 2327 2326 2328 2327 if (amdgpu_acpi_is_s0ix_active(adev)) 2329 2328 adev->in_s0ix = true; 2330 2329 else 2331 2330 adev->in_s3 = true; 2332 - r = amdgpu_device_suspend(drm_dev, true); 2333 - if (r) 2334 - return r; 2331 + return amdgpu_device_suspend(drm_dev, true); 2332 + } 2333 + 2334 + static int amdgpu_pmops_suspend_noirq(struct device *dev) 2335 + { 2336 + struct drm_device *drm_dev = dev_get_drvdata(dev); 2337 + struct amdgpu_device *adev = drm_to_adev(drm_dev); 2338 + 2335 2339 if (!adev->in_s0ix) 2336 - r = amdgpu_asic_reset(adev); 2337 - return r; 2340 + return amdgpu_asic_reset(adev); 2341 + 2342 + return 0; 2338 2343 } 2339 2344 2340 2345 static int amdgpu_pmops_resume(struct device *dev) ··· 2580 2575 .prepare = amdgpu_pmops_prepare, 2581 2576 .complete = amdgpu_pmops_complete, 2582 2577 .suspend = amdgpu_pmops_suspend, 2578 + .suspend_noirq = amdgpu_pmops_suspend_noirq, 2583 2579 .resume = amdgpu_pmops_resume, 2584 2580 .freeze = amdgpu_pmops_freeze, 2585 2581 .thaw = amdgpu_pmops_thaw,
+1 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
··· 52 52 #define FIRMWARE_ALDEBARAN "amdgpu/aldebaran_vcn.bin" 53 53 #define FIRMWARE_BEIGE_GOBY "amdgpu/beige_goby_vcn.bin" 54 54 #define FIRMWARE_YELLOW_CARP "amdgpu/yellow_carp_vcn.bin" 55 - #define FIRMWARE_VCN_3_1_2 "amdgpu/vcn_3_1_2_vcn.bin" 55 + #define FIRMWARE_VCN_3_1_2 "amdgpu/vcn_3_1_2.bin" 56 56 57 57 MODULE_FIRMWARE(FIRMWARE_RAVEN); 58 58 MODULE_FIRMWARE(FIRMWARE_PICASSO);
+2
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
··· 1205 1205 { 0x1002, 0x15dd, 0x103c, 0x83e7, 0xd3 }, 1206 1206 /* GFXOFF is unstable on C6 parts with a VBIOS 113-RAVEN-114 */ 1207 1207 { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc6 }, 1208 + /* Apple MacBook Pro (15-inch, 2019) Radeon Pro Vega 20 4 GB */ 1209 + { 0x1002, 0x69af, 0x106b, 0x019a, 0xc0 }, 1208 1210 { 0, 0, 0, 0, 0 }, 1209 1211 }; 1210 1212
+1 -1
drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
··· 374 374 clk_mgr_dce->dprefclk_ss_percentage = 375 375 info.spread_spectrum_percentage; 376 376 } 377 - if (clk_mgr_dce->base.ctx->dc->debug.ignore_dpref_ss) 377 + if (clk_mgr_dce->base.ctx->dc->config.ignore_dpref_ss) 378 378 clk_mgr_dce->dprefclk_ss_percentage = 0; 379 379 } 380 380 }
+2 -2
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
··· 686 686 clk_mgr->base.base.dprefclk_khz = dcn316_smu_get_dpref_clk(&clk_mgr->base); 687 687 clk_mgr->base.dccg->ref_dtbclk_khz = clk_mgr->base.base.dprefclk_khz; 688 688 dce_clock_read_ss_info(&clk_mgr->base); 689 - clk_mgr->base.dccg->ref_dtbclk_khz = 690 - dce_adjust_dp_ref_freq_for_ss(&clk_mgr->base, clk_mgr->base.base.dprefclk_khz); 689 + /*clk_mgr->base.dccg->ref_dtbclk_khz = 690 + dce_adjust_dp_ref_freq_for_ss(&clk_mgr->base, clk_mgr->base.base.dprefclk_khz);*/ 691 691 692 692 clk_mgr->base.base.bw_params = &dcn316_bw_params; 693 693
+1 -1
drivers/gpu/drm/amd/display/dc/dc.h
··· 340 340 bool is_asymmetric_memory; 341 341 bool is_single_rank_dimm; 342 342 bool use_pipe_ctx_sync_logic; 343 + bool ignore_dpref_ss; 343 344 }; 344 345 345 346 enum visual_confirm { ··· 730 729 bool apply_vendor_specific_lttpr_wa; 731 730 bool extended_blank_optimization; 732 731 union aux_wake_wa_options aux_wake_wa; 733 - bool ignore_dpref_ss; 734 732 uint8_t psr_power_use_phy_fsm; 735 733 }; 736 734
+9 -5
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
··· 2522 2522 struct mpc *mpc = dc->res_pool->mpc; 2523 2523 struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params); 2524 2524 2525 - if (per_pixel_alpha) 2526 - blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA; 2527 - else 2528 - blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA; 2529 - 2530 2525 blnd_cfg.overlap_only = false; 2531 2526 blnd_cfg.global_gain = 0xff; 2527 + 2528 + if (per_pixel_alpha && pipe_ctx->plane_state->global_alpha) { 2529 + blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN; 2530 + blnd_cfg.global_gain = pipe_ctx->plane_state->global_alpha_value; 2531 + } else if (per_pixel_alpha) { 2532 + blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA; 2533 + } else { 2534 + blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA; 2535 + } 2532 2536 2533 2537 if (pipe_ctx->plane_state->global_alpha) 2534 2538 blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value;
+9 -5
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
··· 2344 2344 struct mpc *mpc = dc->res_pool->mpc; 2345 2345 struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params); 2346 2346 2347 - if (per_pixel_alpha) 2348 - blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA; 2349 - else 2350 - blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA; 2351 - 2352 2347 blnd_cfg.overlap_only = false; 2353 2348 blnd_cfg.global_gain = 0xff; 2349 + 2350 + if (per_pixel_alpha && pipe_ctx->plane_state->global_alpha) { 2351 + blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN; 2352 + blnd_cfg.global_gain = pipe_ctx->plane_state->global_alpha_value; 2353 + } else if (per_pixel_alpha) { 2354 + blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA; 2355 + } else { 2356 + blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA; 2357 + } 2354 2358 2355 2359 if (pipe_ctx->plane_state->global_alpha) 2356 2360 blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value;
+1 -1
drivers/gpu/drm/i915/gem/i915_gem_mman.c
··· 70 70 * mmap ioctl is disallowed for all discrete platforms, 71 71 * and for all platforms with GRAPHICS_VER > 12. 72 72 */ 73 - if (IS_DGFX(i915) || GRAPHICS_VER(i915) > 12) 73 + if (IS_DGFX(i915) || GRAPHICS_VER_FULL(i915) > IP_VER(12, 0)) 74 74 return -EOPNOTSUPP; 75 75 76 76 if (args->flags & ~(I915_MMAP_WC))
+1 -1
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
··· 1742 1742 return ERR_CAST(mmu); 1743 1743 1744 1744 return msm_gem_address_space_create(mmu, 1745 - "gpu", 0x100000000ULL, 0x1ffffffffULL); 1745 + "gpu", 0x100000000ULL, SZ_4G); 1746 1746 } 1747 1747 1748 1748 static uint32_t a6xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
+71 -23
drivers/gpu/drm/msm/adreno/adreno_device.c
··· 599 599 {} 600 600 }; 601 601 602 - #ifdef CONFIG_PM 603 - static int adreno_resume(struct device *dev) 602 + static int adreno_runtime_resume(struct device *dev) 604 603 { 605 604 struct msm_gpu *gpu = dev_to_gpu(dev); 606 605 607 606 return gpu->funcs->pm_resume(gpu); 608 607 } 609 608 610 - static int active_submits(struct msm_gpu *gpu) 611 - { 612 - int active_submits; 613 - mutex_lock(&gpu->active_lock); 614 - active_submits = gpu->active_submits; 615 - mutex_unlock(&gpu->active_lock); 616 - return active_submits; 617 - } 618 - 619 - static int adreno_suspend(struct device *dev) 609 + static int adreno_runtime_suspend(struct device *dev) 620 610 { 621 611 struct msm_gpu *gpu = dev_to_gpu(dev); 622 - int remaining; 623 612 624 - remaining = wait_event_timeout(gpu->retire_event, 625 - active_submits(gpu) == 0, 626 - msecs_to_jiffies(1000)); 627 - if (remaining == 0) { 628 - dev_err(dev, "Timeout waiting for GPU to suspend\n"); 629 - return -EBUSY; 630 - } 613 + /* 614 + * We should be holding a runpm ref, which will prevent 615 + * runtime suspend. In the system suspend path, we've 616 + * already waited for active jobs to complete. 617 + */ 618 + WARN_ON_ONCE(gpu->active_submits); 631 619 632 620 return gpu->funcs->pm_suspend(gpu); 633 621 } 634 - #endif 622 + 623 + static void suspend_scheduler(struct msm_gpu *gpu) 624 + { 625 + int i; 626 + 627 + /* 628 + * Shut down the scheduler before we force suspend, so that 629 + * suspend isn't racing with scheduler kthread feeding us 630 + * more work. 631 + * 632 + * Note, we just want to park the thread, and let any jobs 633 + * that are already on the hw queue complete normally, as 634 + * opposed to the drm_sched_stop() path used for handling 635 + * faulting/timed-out jobs. We can't really cancel any jobs 636 + * already on the hw queue without racing with the GPU. 637 + */ 638 + for (i = 0; i < gpu->nr_rings; i++) { 639 + struct drm_gpu_scheduler *sched = &gpu->rb[i]->sched; 640 + kthread_park(sched->thread); 641 + } 642 + } 643 + 644 + static void resume_scheduler(struct msm_gpu *gpu) 645 + { 646 + int i; 647 + 648 + for (i = 0; i < gpu->nr_rings; i++) { 649 + struct drm_gpu_scheduler *sched = &gpu->rb[i]->sched; 650 + kthread_unpark(sched->thread); 651 + } 652 + } 653 + 654 + static int adreno_system_suspend(struct device *dev) 655 + { 656 + struct msm_gpu *gpu = dev_to_gpu(dev); 657 + int remaining, ret; 658 + 659 + suspend_scheduler(gpu); 660 + 661 + remaining = wait_event_timeout(gpu->retire_event, 662 + gpu->active_submits == 0, 663 + msecs_to_jiffies(1000)); 664 + if (remaining == 0) { 665 + dev_err(dev, "Timeout waiting for GPU to suspend\n"); 666 + ret = -EBUSY; 667 + goto out; 668 + } 669 + 670 + ret = pm_runtime_force_suspend(dev); 671 + out: 672 + if (ret) 673 + resume_scheduler(gpu); 674 + 675 + return ret; 676 + } 677 + 678 + static int adreno_system_resume(struct device *dev) 679 + { 680 + resume_scheduler(dev_to_gpu(dev)); 681 + return pm_runtime_force_resume(dev); 682 + } 635 683 636 684 static const struct dev_pm_ops adreno_pm_ops = { 637 - SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) 638 - SET_RUNTIME_PM_OPS(adreno_suspend, adreno_resume, NULL) 685 + SYSTEM_SLEEP_PM_OPS(adreno_system_suspend, adreno_system_resume) 686 + RUNTIME_PM_OPS(adreno_runtime_suspend, adreno_runtime_resume, NULL) 639 687 }; 640 688 641 689 static struct platform_driver adreno_driver = {
+17 -17
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
··· 54 54 * When making changes be sure to sync with dpu_hw_intr_reg 55 55 */ 56 56 static const struct dpu_intr_reg dpu_intr_set[] = { 57 - { 57 + [MDP_SSPP_TOP0_INTR] = { 58 58 MDP_SSPP_TOP0_OFF+INTR_CLEAR, 59 59 MDP_SSPP_TOP0_OFF+INTR_EN, 60 60 MDP_SSPP_TOP0_OFF+INTR_STATUS 61 61 }, 62 - { 62 + [MDP_SSPP_TOP0_INTR2] = { 63 63 MDP_SSPP_TOP0_OFF+INTR2_CLEAR, 64 64 MDP_SSPP_TOP0_OFF+INTR2_EN, 65 65 MDP_SSPP_TOP0_OFF+INTR2_STATUS 66 66 }, 67 - { 67 + [MDP_SSPP_TOP0_HIST_INTR] = { 68 68 MDP_SSPP_TOP0_OFF+HIST_INTR_CLEAR, 69 69 MDP_SSPP_TOP0_OFF+HIST_INTR_EN, 70 70 MDP_SSPP_TOP0_OFF+HIST_INTR_STATUS 71 71 }, 72 - { 72 + [MDP_INTF0_INTR] = { 73 73 MDP_INTF_0_OFF+INTF_INTR_CLEAR, 74 74 MDP_INTF_0_OFF+INTF_INTR_EN, 75 75 MDP_INTF_0_OFF+INTF_INTR_STATUS 76 76 }, 77 - { 77 + [MDP_INTF1_INTR] = { 78 78 MDP_INTF_1_OFF+INTF_INTR_CLEAR, 79 79 MDP_INTF_1_OFF+INTF_INTR_EN, 80 80 MDP_INTF_1_OFF+INTF_INTR_STATUS 81 81 }, 82 - { 82 + [MDP_INTF2_INTR] = { 83 83 MDP_INTF_2_OFF+INTF_INTR_CLEAR, 84 84 MDP_INTF_2_OFF+INTF_INTR_EN, 85 85 MDP_INTF_2_OFF+INTF_INTR_STATUS 86 86 }, 87 - { 87 + [MDP_INTF3_INTR] = { 88 88 MDP_INTF_3_OFF+INTF_INTR_CLEAR, 89 89 MDP_INTF_3_OFF+INTF_INTR_EN, 90 90 MDP_INTF_3_OFF+INTF_INTR_STATUS 91 91 }, 92 - { 92 + [MDP_INTF4_INTR] = { 93 93 MDP_INTF_4_OFF+INTF_INTR_CLEAR, 94 94 MDP_INTF_4_OFF+INTF_INTR_EN, 95 95 MDP_INTF_4_OFF+INTF_INTR_STATUS 96 96 }, 97 - { 97 + [MDP_INTF5_INTR] = { 98 98 MDP_INTF_5_OFF+INTF_INTR_CLEAR, 99 99 MDP_INTF_5_OFF+INTF_INTR_EN, 100 100 MDP_INTF_5_OFF+INTF_INTR_STATUS 101 101 }, 102 - { 102 + [MDP_AD4_0_INTR] = { 103 103 MDP_AD4_0_OFF + MDP_AD4_INTR_CLEAR_OFF, 104 104 MDP_AD4_0_OFF + MDP_AD4_INTR_EN_OFF, 105 105 MDP_AD4_0_OFF + MDP_AD4_INTR_STATUS_OFF, 106 106 }, 107 - { 107 + [MDP_AD4_1_INTR] = { 108 108 MDP_AD4_1_OFF + MDP_AD4_INTR_CLEAR_OFF, 109 109 MDP_AD4_1_OFF + MDP_AD4_INTR_EN_OFF, 110 110 MDP_AD4_1_OFF + MDP_AD4_INTR_STATUS_OFF, 111 111 }, 112 - { 112 + [MDP_INTF0_7xxx_INTR] = { 113 113 MDP_INTF_0_OFF_REV_7xxx+INTF_INTR_CLEAR, 114 114 MDP_INTF_0_OFF_REV_7xxx+INTF_INTR_EN, 115 115 MDP_INTF_0_OFF_REV_7xxx+INTF_INTR_STATUS 116 116 }, 117 - { 117 + [MDP_INTF1_7xxx_INTR] = { 118 118 MDP_INTF_1_OFF_REV_7xxx+INTF_INTR_CLEAR, 119 119 MDP_INTF_1_OFF_REV_7xxx+INTF_INTR_EN, 120 120 MDP_INTF_1_OFF_REV_7xxx+INTF_INTR_STATUS 121 121 }, 122 - { 122 + [MDP_INTF2_7xxx_INTR] = { 123 123 MDP_INTF_2_OFF_REV_7xxx+INTF_INTR_CLEAR, 124 124 MDP_INTF_2_OFF_REV_7xxx+INTF_INTR_EN, 125 125 MDP_INTF_2_OFF_REV_7xxx+INTF_INTR_STATUS 126 126 }, 127 - { 127 + [MDP_INTF3_7xxx_INTR] = { 128 128 MDP_INTF_3_OFF_REV_7xxx+INTF_INTR_CLEAR, 129 129 MDP_INTF_3_OFF_REV_7xxx+INTF_INTR_EN, 130 130 MDP_INTF_3_OFF_REV_7xxx+INTF_INTR_STATUS 131 131 }, 132 - { 132 + [MDP_INTF4_7xxx_INTR] = { 133 133 MDP_INTF_4_OFF_REV_7xxx+INTF_INTR_CLEAR, 134 134 MDP_INTF_4_OFF_REV_7xxx+INTF_INTR_EN, 135 135 MDP_INTF_4_OFF_REV_7xxx+INTF_INTR_STATUS 136 136 }, 137 - { 137 + [MDP_INTF5_7xxx_INTR] = { 138 138 MDP_INTF_5_OFF_REV_7xxx+INTF_INTR_CLEAR, 139 139 MDP_INTF_5_OFF_REV_7xxx+INTF_INTR_EN, 140 140 MDP_INTF_5_OFF_REV_7xxx+INTF_INTR_STATUS
+3
drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
··· 98 98 __drm_atomic_helper_plane_destroy_state(plane->state); 99 99 100 100 kfree(to_mdp5_plane_state(plane->state)); 101 + plane->state = NULL; 101 102 mdp5_state = kzalloc(sizeof(*mdp5_state), GFP_KERNEL); 103 + if (!mdp5_state) 104 + return; 102 105 __drm_atomic_helper_plane_reset(plane, &mdp5_state->base); 103 106 } 104 107
+2
drivers/gpu/drm/msm/disp/msm_disp_snapshot_util.c
··· 176 176 va_list va; 177 177 178 178 new_blk = kzalloc(sizeof(struct msm_disp_state_block), GFP_KERNEL); 179 + if (!new_blk) 180 + return; 179 181 180 182 va_start(va, fmt); 181 183
+6
drivers/gpu/drm/msm/dp/dp_display.c
··· 580 580 dp->dp_display.connector_type, state); 581 581 mutex_unlock(&dp->event_mutex); 582 582 583 + /* 584 + * add fail safe mode outside event_mutex scope 585 + * to avoid potiential circular lock with drm thread 586 + */ 587 + dp_panel_add_fail_safe_mode(dp->dp_display.connector); 588 + 583 589 /* uevent will complete connection part */ 584 590 return 0; 585 591 };
+10 -10
drivers/gpu/drm/msm/dp/dp_panel.c
··· 151 151 return rc; 152 152 } 153 153 154 + void dp_panel_add_fail_safe_mode(struct drm_connector *connector) 155 + { 156 + /* fail safe edid */ 157 + mutex_lock(&connector->dev->mode_config.mutex); 158 + if (drm_add_modes_noedid(connector, 640, 480)) 159 + drm_set_preferred_mode(connector, 640, 480); 160 + mutex_unlock(&connector->dev->mode_config.mutex); 161 + } 162 + 154 163 int dp_panel_read_sink_caps(struct dp_panel *dp_panel, 155 164 struct drm_connector *connector) 156 165 { ··· 216 207 goto end; 217 208 } 218 209 219 - /* fail safe edid */ 220 - mutex_lock(&connector->dev->mode_config.mutex); 221 - if (drm_add_modes_noedid(connector, 640, 480)) 222 - drm_set_preferred_mode(connector, 640, 480); 223 - mutex_unlock(&connector->dev->mode_config.mutex); 224 - } else { 225 - /* always add fail-safe mode as backup mode */ 226 - mutex_lock(&connector->dev->mode_config.mutex); 227 - drm_add_modes_noedid(connector, 640, 480); 228 - mutex_unlock(&connector->dev->mode_config.mutex); 210 + dp_panel_add_fail_safe_mode(connector); 229 211 } 230 212 231 213 if (panel->aux_cfg_update_done) {
+1
drivers/gpu/drm/msm/dp/dp_panel.h
··· 59 59 int dp_panel_deinit(struct dp_panel *dp_panel); 60 60 int dp_panel_timing_cfg(struct dp_panel *dp_panel); 61 61 void dp_panel_dump_regs(struct dp_panel *dp_panel); 62 + void dp_panel_add_fail_safe_mode(struct drm_connector *connector); 62 63 int dp_panel_read_sink_caps(struct dp_panel *dp_panel, 63 64 struct drm_connector *connector); 64 65 u32 dp_panel_get_mode_bpp(struct dp_panel *dp_panel, u32 mode_max_bpp,
+1 -1
drivers/gpu/drm/msm/dsi/dsi_manager.c
··· 638 638 return connector; 639 639 640 640 fail: 641 - connector->funcs->destroy(msm_dsi->connector); 641 + connector->funcs->destroy(connector); 642 642 return ERR_PTR(ret); 643 643 } 644 644
+1 -1
drivers/gpu/drm/msm/msm_drv.c
··· 274 274 struct msm_drm_private *priv = dev->dev_private; 275 275 276 276 /* a2xx comes with its own MMU */ 277 - return priv->is_a2xx || iommu_present(&platform_bus_type); 277 + return priv->is_a2xx || device_iommu_mapped(dev->dev); 278 278 } 279 279 280 280 static int msm_init_vram(struct drm_device *dev)
+1
drivers/gpu/drm/msm/msm_gem.c
··· 926 926 get_pid_task(aspace->pid, PIDTYPE_PID); 927 927 if (task) { 928 928 comm = kstrdup(task->comm, GFP_KERNEL); 929 + put_task_struct(task); 929 930 } else { 930 931 comm = NULL; 931 932 }