tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'tegra-for-6.2-arm64-dt-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt

arm64: tegra: Device tree changes for v6.2-rc1

This contains many new additions, primarily for Tegra234, as well as a
slew of cleanups for issues flagged by the DT validation tools.

* tag 'tegra-for-6.2-arm64-dt-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (30 commits)
arm64: tegra: Remove unneeded clock-names for Tegra132 PWM
arm64: tegra: Fix up compatible string for SDMMC1 on Tegra234
arm64: tegra: Remove unused reset-names for QSPI
arm64: tegra: Fixup pinmux node names
arm64: tegra: Remove reset-names for QSPI
arm64: tegra: Use correct compatible string for Tegra234 HDA
arm64: tegra: Use correct compatible string for Tegra194 HDA
arm64: tegra: Use vbus-gpios property
arm64: tegra: Restructure Tegra210 PMC pinmux nodes
arm64: tegra: Update cache properties
arm64: tegra: Remove 'enable-active-low'
arm64: tegra: Add dma-channel-mask in GPCDMA node
arm64: tegra: Fix non-prefetchable aperture of PCIe C3 controller
arm64: tegra: Add missing compatible string to Ethernet USB device
arm64: tegra: Separate AON pinmux from main pinmux on Tegra194
arm64: tegra: Add ECAM aperture info for all the PCIe controllers
arm64: tegra: Remove clock-names from PWM nodes
arm64: tegra: Enable GTE nodes
arm64: tegra: Update console for Jetson Xavier and Orin
arm64: tegra: Enable PWM users on Jetson AGX Orin
...

Link: https://lore.kernel.org/r/20221121171239.2041835-7-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Arnd Bergmann 02946788 83cbe78a

+576 -296
+1 -1
arch/arm64/boot/dts/nvidia/tegra132-norrin.dts
··· 62 62 pinctrl-names = "default"; 63 63 pinctrl-0 = <&pinmux_default>; 64 64 65 - pinmux_default: pinmux@0 { 65 + pinmux_default: pinmux { 66 66 dap_mclk1_pw4 { 67 67 nvidia,pins = "dap_mclk1_pw4"; 68 68 nvidia,function = "extperiph1";
-1
arch/arm64/boot/dts/nvidia/tegra132.dtsi
··· 393 393 reg = <0x0 0x7000a000 0x0 0x100>; 394 394 #pwm-cells = <2>; 395 395 clocks = <&tegra_car TEGRA124_CLK_PWM>; 396 - clock-names = "pwm"; 397 396 resets = <&tegra_car 17>; 398 397 reset-names = "pwm"; 399 398 status = "disabled";
+3 -9
arch/arm64/boot/dts/nvidia/tegra186.dtsi
··· 78 78 reg = <0x0 0x2600000 0x0 0x210000>; 79 79 resets = <&bpmp TEGRA186_RESET_GPCDMA>; 80 80 reset-names = "gpcdma"; 81 - interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 81 + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 82 + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 82 83 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 83 84 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 84 85 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, ··· 113 112 #dma-cells = <1>; 114 113 iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 115 114 dma-coherent; 115 + dma-channel-mask = <0xfffffffe>; 116 116 status = "okay"; 117 117 }; 118 118 ··· 792 790 compatible = "nvidia,tegra186-pwm"; 793 791 reg = <0x0 0x3280000 0x0 0x10000>; 794 792 clocks = <&bpmp TEGRA186_CLK_PWM1>; 795 - clock-names = "pwm"; 796 793 resets = <&bpmp TEGRA186_RESET_PWM1>; 797 794 reset-names = "pwm"; 798 795 status = "disabled"; ··· 802 801 compatible = "nvidia,tegra186-pwm"; 803 802 reg = <0x0 0x3290000 0x0 0x10000>; 804 803 clocks = <&bpmp TEGRA186_CLK_PWM2>; 805 - clock-names = "pwm"; 806 804 resets = <&bpmp TEGRA186_RESET_PWM2>; 807 805 reset-names = "pwm"; 808 806 status = "disabled"; ··· 812 812 compatible = "nvidia,tegra186-pwm"; 813 813 reg = <0x0 0x32a0000 0x0 0x10000>; 814 814 clocks = <&bpmp TEGRA186_CLK_PWM3>; 815 - clock-names = "pwm"; 816 815 resets = <&bpmp TEGRA186_RESET_PWM3>; 817 816 reset-names = "pwm"; 818 817 status = "disabled"; ··· 822 823 compatible = "nvidia,tegra186-pwm"; 823 824 reg = <0x0 0x32c0000 0x0 0x10000>; 824 825 clocks = <&bpmp TEGRA186_CLK_PWM5>; 825 - clock-names = "pwm"; 826 826 resets = <&bpmp TEGRA186_RESET_PWM5>; 827 827 reset-names = "pwm"; 828 828 status = "disabled"; ··· 832 834 compatible = "nvidia,tegra186-pwm"; 833 835 reg = <0x0 0x32d0000 0x0 0x10000>; 834 836 clocks = <&bpmp TEGRA186_CLK_PWM6>; 835 - clock-names = "pwm"; 836 837 resets = <&bpmp TEGRA186_RESET_PWM6>; 837 838 reset-names = "pwm"; 838 839 status = "disabled"; ··· 842 845 compatible = "nvidia,tegra186-pwm"; 843 846 reg = <0x0 0x32e0000 0x0 0x10000>; 844 847 clocks = <&bpmp TEGRA186_CLK_PWM7>; 845 - clock-names = "pwm"; 846 848 resets = <&bpmp TEGRA186_RESET_PWM7>; 847 849 reset-names = "pwm"; 848 850 status = "disabled"; ··· 852 856 compatible = "nvidia,tegra186-pwm"; 853 857 reg = <0x0 0x32f0000 0x0 0x10000>; 854 858 clocks = <&bpmp TEGRA186_CLK_PWM8>; 855 - clock-names = "pwm"; 856 859 resets = <&bpmp TEGRA186_RESET_PWM8>; 857 860 reset-names = "pwm"; 858 861 status = "disabled"; ··· 1269 1274 compatible = "nvidia,tegra186-pwm"; 1270 1275 reg = <0x0 0xc340000 0x0 0x10000>; 1271 1276 clocks = <&bpmp TEGRA186_CLK_PWM4>; 1272 - clock-names = "pwm"; 1273 1277 resets = <&bpmp TEGRA186_RESET_PWM4>; 1274 1278 reset-names = "pwm"; 1275 1279 status = "disabled";
+1 -1
arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
··· 23 23 }; 24 24 25 25 chosen { 26 - bootargs = "console=ttyS0,115200n8"; 26 + bootargs = "console=ttyTCU0,115200n8"; 27 27 stdout-path = "serial0:115200n8"; 28 28 }; 29 29
+2 -2
arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi
··· 2117 2117 "usb-b-connector"; 2118 2118 label = "micro-USB"; 2119 2119 type = "micro"; 2120 - vbus-gpio = <&gpio TEGRA194_MAIN_GPIO(Z, 1) 2121 - GPIO_ACTIVE_LOW>; 2120 + vbus-gpios = <&gpio TEGRA194_MAIN_GPIO(Z, 1) 2121 + GPIO_ACTIVE_LOW>; 2122 2122 }; 2123 2123 }; 2124 2124
+1 -1
arch/arm64/boot/dts/nvidia/tegra194-p3668.dtsi
··· 20 20 }; 21 21 22 22 chosen { 23 - bootargs = "console=ttyS0,115200n8"; 23 + bootargs = "console=ttyTCU0,115200n8"; 24 24 stdout-path = "serial0:115200n8"; 25 25 }; 26 26
+52 -18
arch/arm64/boot/dts/nvidia/tegra194.dtsi
··· 86 86 interrupt-controller; 87 87 #gpio-cells = <2>; 88 88 gpio-controller; 89 + gpio-ranges = <&pinmux 0 0 169>; 89 90 }; 90 91 91 92 cbb-noc@2300000 { ··· 143 142 reg = <0x2600000 0x210000>; 144 143 resets = <&bpmp TEGRA194_RESET_GPCDMA>; 145 144 reset-names = "gpcdma"; 146 - interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 145 + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 146 + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 147 147 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 148 148 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 149 149 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, ··· 178 176 #dma-cells = <1>; 179 177 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 180 178 dma-coherent; 179 + dma-channel-mask = <0xfffffffe>; 181 180 status = "okay"; 182 181 }; 183 182 ··· 629 626 630 627 pinmux: pinmux@2430000 { 631 628 compatible = "nvidia,tegra194-pinmux"; 632 - reg = <0x2430000 0x17000>, 633 - <0xc300000 0x4000>; 634 - 629 + reg = <0x2430000 0x17000>; 635 630 status = "okay"; 636 631 637 - pex_rst_c5_out_state: pex_rst_c5_out { 632 + pex_rst_c5_out_state: pinmux-pex-rst-c5-out { 638 633 pex_rst { 639 634 nvidia,pins = "pex_l5_rst_n_pgg1"; 640 635 nvidia,schmitt = <TEGRA_PIN_DISABLE>; ··· 643 642 }; 644 643 }; 645 644 646 - clkreq_c5_bi_dir_state: clkreq_c5_bi_dir { 645 + clkreq_c5_bi_dir_state: pinmux-clkreq-c5-bi-dir { 647 646 clkreq { 648 647 nvidia,pins = "pex_l5_clkreq_n_pgg0"; 649 648 nvidia,schmitt = <TEGRA_PIN_DISABLE>; ··· 936 935 <&bpmp TEGRA194_CLK_QSPI0_PM>; 937 936 clock-names = "qspi", "qspi_out"; 938 937 resets = <&bpmp TEGRA194_RESET_QSPI0>; 939 - reset-names = "qspi"; 940 938 status = "disabled"; 941 939 }; 942 940 ··· 949 949 <&bpmp TEGRA194_CLK_QSPI1_PM>; 950 950 clock-names = "qspi", "qspi_out"; 951 951 resets = <&bpmp TEGRA194_RESET_QSPI1>; 952 - reset-names = "qspi"; 953 952 status = "disabled"; 954 953 }; 955 954 ··· 957 958 "nvidia,tegra186-pwm"; 958 959 reg = <0x3280000 0x10000>; 959 960 clocks = <&bpmp TEGRA194_CLK_PWM1>; 960 - clock-names = "pwm"; 961 961 resets = <&bpmp TEGRA194_RESET_PWM1>; 962 962 reset-names = "pwm"; 963 963 status = "disabled"; ··· 968 970 "nvidia,tegra186-pwm"; 969 971 reg = <0x3290000 0x10000>; 970 972 clocks = <&bpmp TEGRA194_CLK_PWM2>; 971 - clock-names = "pwm"; 972 973 resets = <&bpmp TEGRA194_RESET_PWM2>; 973 974 reset-names = "pwm"; 974 975 status = "disabled"; ··· 979 982 "nvidia,tegra186-pwm"; 980 983 reg = <0x32a0000 0x10000>; 981 984 clocks = <&bpmp TEGRA194_CLK_PWM3>; 982 - clock-names = "pwm"; 983 985 resets = <&bpmp TEGRA194_RESET_PWM3>; 984 986 reset-names = "pwm"; 985 987 status = "disabled"; ··· 990 994 "nvidia,tegra186-pwm"; 991 995 reg = <0x32c0000 0x10000>; 992 996 clocks = <&bpmp TEGRA194_CLK_PWM5>; 993 - clock-names = "pwm"; 994 997 resets = <&bpmp TEGRA194_RESET_PWM5>; 995 998 reset-names = "pwm"; 996 999 status = "disabled"; ··· 1001 1006 "nvidia,tegra186-pwm"; 1002 1007 reg = <0x32d0000 0x10000>; 1003 1008 clocks = <&bpmp TEGRA194_CLK_PWM6>; 1004 - clock-names = "pwm"; 1005 1009 resets = <&bpmp TEGRA194_RESET_PWM6>; 1006 1010 reset-names = "pwm"; 1007 1011 status = "disabled"; ··· 1012 1018 "nvidia,tegra186-pwm"; 1013 1019 reg = <0x32e0000 0x10000>; 1014 1020 clocks = <&bpmp TEGRA194_CLK_PWM7>; 1015 - clock-names = "pwm"; 1016 1021 resets = <&bpmp TEGRA194_RESET_PWM7>; 1017 1022 reset-names = "pwm"; 1018 1023 status = "disabled"; ··· 1023 1030 "nvidia,tegra186-pwm"; 1024 1031 reg = <0x32f0000 0x10000>; 1025 1032 clocks = <&bpmp TEGRA194_CLK_PWM8>; 1026 - clock-names = "pwm"; 1027 1033 resets = <&bpmp TEGRA194_RESET_PWM8>; 1028 1034 reset-names = "pwm"; 1029 1035 status = "disabled"; ··· 1146 1154 }; 1147 1155 1148 1156 hda@3510000 { 1149 - compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda"; 1157 + compatible = "nvidia,tegra194-hda"; 1150 1158 reg = <0x3510000 0x10000>; 1151 1159 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 1152 1160 clocks = <&bpmp TEGRA194_CLK_HDA>, ··· 1356 1364 clocks = <&bpmp TEGRA194_CLK_CEC>; 1357 1365 clock-names = "cec"; 1358 1366 status = "disabled"; 1367 + }; 1368 + 1369 + hte_lic: hardware-timestamp@3aa0000 { 1370 + compatible = "nvidia,tegra194-gte-lic"; 1371 + reg = <0x3aa0000 0x10000>; 1372 + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1373 + nvidia,int-threshold = <1>; 1374 + nvidia,slices = <11>; 1375 + #timestamp-cells = <1>; 1376 + status = "okay"; 1359 1377 }; 1360 1378 1361 1379 hsp_top0: hsp@3c00000 { ··· 1581 1579 #mbox-cells = <2>; 1582 1580 }; 1583 1581 1582 + hte_aon: hardware-timestamp@c1e0000 { 1583 + compatible = "nvidia,tegra194-gte-aon"; 1584 + reg = <0xc1e0000 0x10000>; 1585 + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1586 + nvidia,int-threshold = <1>; 1587 + nvidia,slices = <3>; 1588 + #timestamp-cells = <1>; 1589 + status = "okay"; 1590 + }; 1591 + 1584 1592 gen2_i2c: i2c@c240000 { 1585 1593 compatible = "nvidia,tegra194-i2c"; 1586 1594 reg = <0x0c240000 0x10000>; ··· 1672 1660 #gpio-cells = <2>; 1673 1661 interrupt-controller; 1674 1662 #interrupt-cells = <2>; 1663 + gpio-range = <&pinmux_aon 0 0 30>; 1664 + }; 1665 + 1666 + pinmux_aon: pinmux@c300000 { 1667 + compatible = "nvidia,tegra194-pinmux-aon"; 1668 + reg = <0xc300000 0x4000>; 1669 + 1670 + status = "okay"; 1675 1671 }; 1676 1672 1677 1673 pwm4: pwm@c340000 { ··· 1687 1667 "nvidia,tegra186-pwm"; 1688 1668 reg = <0xc340000 0x10000>; 1689 1669 clocks = <&bpmp TEGRA194_CLK_PWM4>; 1690 - clock-names = "pwm"; 1691 1670 resets = <&bpmp TEGRA194_RESET_PWM4>; 1692 1671 reset-names = "pwm"; 1693 1672 status = "disabled"; ··· 1914 1895 #address-cells = <1>; 1915 1896 #size-cells = <1>; 1916 1897 1917 - ranges = <0x15000000 0x15000000 0x01000000>; 1898 + ranges = <0x14800000 0x14800000 0x02800000>; 1918 1899 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>; 1919 1900 interconnect-names = "dma-mem"; 1920 1901 iommus = <&smmu TEGRA194_SID_HOST1X>; ··· 3048 3029 }; 3049 3030 3050 3031 l2c_0: l2-cache0 { 3032 + compatible = "cache"; 3033 + cache-unified; 3051 3034 cache-size = <2097152>; 3052 3035 cache-line-size = <64>; 3053 3036 cache-sets = <2048>; 3037 + cache-level = <2>; 3054 3038 next-level-cache = <&l3c>; 3055 3039 }; 3056 3040 3057 3041 l2c_1: l2-cache1 { 3042 + compatible = "cache"; 3043 + cache-unified; 3058 3044 cache-size = <2097152>; 3059 3045 cache-line-size = <64>; 3060 3046 cache-sets = <2048>; 3047 + cache-level = <2>; 3061 3048 next-level-cache = <&l3c>; 3062 3049 }; 3063 3050 3064 3051 l2c_2: l2-cache2 { 3052 + compatible = "cache"; 3053 + cache-unified; 3065 3054 cache-size = <2097152>; 3066 3055 cache-line-size = <64>; 3067 3056 cache-sets = <2048>; 3057 + cache-level = <2>; 3068 3058 next-level-cache = <&l3c>; 3069 3059 }; 3070 3060 3071 3061 l2c_3: l2-cache3 { 3062 + compatible = "cache"; 3063 + cache-unified; 3072 3064 cache-size = <2097152>; 3073 3065 cache-line-size = <64>; 3074 3066 cache-sets = <2048>; 3067 + cache-level = <2>; 3075 3068 next-level-cache = <&l3c>; 3076 3069 }; 3077 3070 3078 3071 l3c: l3-cache { 3072 + compatible = "cache"; 3073 + cache-unified; 3079 3074 cache-size = <4194304>; 3080 3075 cache-line-size = <64>; 3076 + cache-level = <3>; 3081 3077 cache-sets = <4096>; 3082 3078 }; 3083 3079 };
+3 -2
arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
··· 1293 1293 }; 1294 1294 }; 1295 1295 1296 - dvfs_pwm_active_state: dvfs_pwm_active { 1296 + dvfs_pwm_active_state: pinmux-dvfs-pwm-active { 1297 1297 dvfs_pwm_pbb1 { 1298 1298 nvidia,pins = "dvfs_pwm_pbb1"; 1299 1299 nvidia,tristate = <TEGRA_PIN_DISABLE>; 1300 1300 }; 1301 1301 }; 1302 1302 1303 - dvfs_pwm_inactive_state: dvfs_pwm_inactive { 1303 + dvfs_pwm_inactive_state: pinmux-dvfs-pwm-inactive { 1304 1304 dvfs_pwm_pbb1 { 1305 1305 nvidia,pins = "dvfs_pwm_pbb1"; 1306 1306 nvidia,tristate = <TEGRA_PIN_ENABLE>; ··· 1368 1368 #size-cells = <0>; 1369 1369 1370 1370 ethernet@1 { 1371 + compatible = "usb955,9ff"; 1371 1372 reg = <1>; 1372 1373 }; 1373 1374 };
+2 -2
arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts
··· 109 109 }; 110 110 111 111 pinmux@700008d4 { 112 - dvfs_pwm_active_state: dvfs_pwm_active { 112 + dvfs_pwm_active_state: pinmux-dvfs-pwm-active { 113 113 dvfs_pwm_pbb1 { 114 114 nvidia,pins = "dvfs_pwm_pbb1"; 115 115 nvidia,tristate = <TEGRA_PIN_DISABLE>; 116 116 }; 117 117 }; 118 118 119 - dvfs_pwm_inactive_state: dvfs_pwm_inactive { 119 + dvfs_pwm_inactive_state: pinmux-dvfs-pwm-inactive { 120 120 dvfs_pwm_pbb1 { 121 121 nvidia,pins = "dvfs_pwm_pbb1"; 122 122 nvidia,tristate = <TEGRA_PIN_ENABLE>;
+32 -29
arch/arm64/boot/dts/nvidia/tegra210.dtsi
··· 554 554 compatible = "nvidia,tegra210-pinmux"; 555 555 reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */ 556 556 <0x0 0x70003000 0x0 0x294>; /* Mux registers */ 557 - sdmmc1_3v3_drv: sdmmc1-3v3-drv { 557 + 558 + sdmmc1_3v3_drv: pinmux-sdmmc1-3v3-drv { 558 559 sdmmc1 { 559 560 nvidia,pins = "drive_sdmmc1"; 560 561 nvidia,pull-down-strength = <0x8>; 561 562 nvidia,pull-up-strength = <0x8>; 562 563 }; 563 564 }; 564 - sdmmc1_1v8_drv: sdmmc1-1v8-drv { 565 + 566 + sdmmc1_1v8_drv: pinmux-sdmmc1-1v8-drv { 565 567 sdmmc1 { 566 568 nvidia,pins = "drive_sdmmc1"; 567 569 nvidia,pull-down-strength = <0x4>; 568 570 nvidia,pull-up-strength = <0x3>; 569 571 }; 570 572 }; 571 - sdmmc2_1v8_drv: sdmmc2-1v8-drv { 573 + 574 + sdmmc2_1v8_drv: pinmux-sdmmc2-1v8-drv { 572 575 sdmmc2 { 573 576 nvidia,pins = "drive_sdmmc2"; 574 577 nvidia,pull-down-strength = <0x10>; 575 578 nvidia,pull-up-strength = <0x10>; 576 579 }; 577 580 }; 578 - sdmmc3_3v3_drv: sdmmc3-3v3-drv { 581 + 582 + sdmmc3_3v3_drv: pinmux-sdmmc3-3v3-drv { 579 583 sdmmc3 { 580 584 nvidia,pins = "drive_sdmmc3"; 581 585 nvidia,pull-down-strength = <0x8>; 582 586 nvidia,pull-up-strength = <0x8>; 583 587 }; 584 588 }; 585 - sdmmc3_1v8_drv: sdmmc3-1v8-drv { 589 + 590 + sdmmc3_1v8_drv: pinmux-sdmmc3-1v8-drv { 586 591 sdmmc3 { 587 592 nvidia,pins = "drive_sdmmc3"; 588 593 nvidia,pull-down-strength = <0x4>; 589 594 nvidia,pull-up-strength = <0x3>; 590 595 }; 591 596 }; 592 - sdmmc4_1v8_drv: sdmmc4-1v8-drv { 597 + 598 + sdmmc4_1v8_drv: pinmux-sdmmc4-1v8-drv { 593 599 sdmmc4 { 594 600 nvidia,pins = "drive_sdmmc4"; 595 601 nvidia,pull-down-strength = <0x10>; ··· 673 667 reg = <0x0 0x7000a000 0x0 0x100>; 674 668 #pwm-cells = <2>; 675 669 clocks = <&tegra_car TEGRA210_CLK_PWM>; 676 - clock-names = "pwm"; 677 670 resets = <&tegra_car 17>; 678 671 reset-names = "pwm"; 679 672 status = "disabled"; ··· 917 912 }; 918 913 }; 919 914 920 - sdmmc1_3v3: sdmmc1-3v3 { 921 - pins = "sdmmc1"; 922 - power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 923 - }; 915 + pinmux { 916 + sdmmc1_3v3: sdmmc1-3v3 { 917 + pins = "sdmmc1"; 918 + power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 919 + }; 924 920 925 - sdmmc1_1v8: sdmmc1-1v8 { 926 - pins = "sdmmc1"; 927 - power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 928 - }; 921 + sdmmc1_1v8: sdmmc1-1v8 { 922 + pins = "sdmmc1"; 923 + power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 924 + }; 929 925 930 - sdmmc3_3v3: sdmmc3-3v3 { 931 - pins = "sdmmc3"; 932 - power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 933 - }; 926 + sdmmc3_3v3: sdmmc3-3v3 { 927 + pins = "sdmmc3"; 928 + power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 929 + }; 934 930 935 - sdmmc3_1v8: sdmmc3-1v8 { 936 - pins = "sdmmc3"; 937 - power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 938 - }; 931 + sdmmc3_1v8: sdmmc3-1v8 { 932 + pins = "sdmmc3"; 933 + power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 934 + }; 939 935 940 - pex_dpd_disable: pex_en { 941 - pex-dpd-disable { 936 + pex_dpd_disable: pex-dpd-disable { 942 937 pins = "pex-bias", "pex-clk1", "pex-clk2"; 943 938 low-power-disable; 944 939 }; 945 - }; 946 940 947 - pex_dpd_enable: pex_dis { 948 - pex-dpd-enable { 941 + pex_dpd_enable: pex-dpd-enable { 949 942 pins = "pex-bias", "pex-clk1", "pex-clk2"; 950 943 low-power-enable; 951 944 }; ··· 1868 1865 <&tegra_car TEGRA210_CLK_QSPI_PM>; 1869 1866 clock-names = "qspi", "qspi_out"; 1870 1867 resets = <&tegra_car 211>; 1871 - reset-names = "qspi"; 1872 1868 dmas = <&apbdma 5>, <&apbdma 5>; 1873 1869 dma-names = "rx", "tx"; 1874 1870 status = "disabled"; ··· 2007 2005 2008 2006 L2: l2-cache { 2009 2007 compatible = "cache"; 2008 + cache-level = <2>; 2010 2009 }; 2011 2010 }; 2012 2011
+7 -1
arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi
··· 39 39 regulator-max-microvolt = <12000000>; 40 40 gpio = <&gpio TEGRA234_MAIN_GPIO(A, 1) GPIO_ACTIVE_LOW>; 41 41 regulator-boot-on; 42 - enable-active-low; 43 42 }; 44 43 45 44 bus@0 { ··· 52 53 spi-tx-bus-width = <4>; 53 54 spi-rx-bus-width = <4>; 54 55 }; 56 + }; 57 + 58 + mmc@3400000 { 59 + status = "okay"; 60 + bus-width = <4>; 61 + cd-gpios = <&gpio TEGRA234_MAIN_GPIO(G, 7) GPIO_ACTIVE_LOW>; 62 + disable-wp; 55 63 }; 56 64 57 65 mmc@3460000 {
+20 -1
arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts
··· 2007 2007 status = "okay"; 2008 2008 }; 2009 2009 2010 + serial@31d0000 { 2011 + current-speed = <115200>; 2012 + status = "okay"; 2013 + }; 2014 + 2015 + pwm@32a0000 { 2016 + assigned-clocks = <&bpmp TEGRA234_CLK_PWM3>; 2017 + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 2018 + status = "okay"; 2019 + }; 2020 + 2010 2021 hda@3510000 { 2011 2022 nvidia,model = "NVIDIA Jetson AGX Orin HDA"; 2012 2023 status = "okay"; ··· 2025 2014 }; 2026 2015 2027 2016 chosen { 2028 - bootargs = "console=ttyS0,115200n8"; 2017 + bootargs = "console=ttyTCU0,115200n8"; 2029 2018 stdout-path = "serial0:115200n8"; 2030 2019 }; 2031 2020 ··· 2194 2183 <&p2u_nvhs_6>, <&p2u_nvhs_7>; 2195 2184 phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", 2196 2185 "p2u-5", "p2u-6", "p2u-7"; 2186 + }; 2187 + 2188 + pwm-fan { 2189 + compatible = "pwm-fan"; 2190 + pwms = <&pwm3 0 45334>; 2191 + 2192 + cooling-levels = <0 95 178 255>; 2193 + #cooling-cells = <2>; 2197 2194 }; 2198 2195 };
+14
arch/arm64/boot/dts/nvidia/tegra234-p3737-0000.dtsi
··· 2 2 3 3 / { 4 4 compatible = "nvidia,p3737-0000"; 5 + 6 + bus@0 { 7 + pwm@3280000 { 8 + status = "okay"; 9 + }; 10 + 11 + pwm@32c0000 { 12 + status = "okay"; 13 + }; 14 + 15 + pwm@32f0000 { 16 + status = "okay"; 17 + }; 18 + }; 5 19 };
+438 -228
arch/arm64/boot/dts/nvidia/tegra234.dtsi
··· 7 7 #include <dt-bindings/memory/tegra234-mc.h> 8 8 #include <dt-bindings/power/tegra234-powergate.h> 9 9 #include <dt-bindings/reset/tegra234-reset.h> 10 + #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 10 11 11 12 / { 12 13 compatible = "nvidia,tegra234"; ··· 28 27 reg = <0x2600000 0x210000>; 29 28 resets = <&bpmp TEGRA234_RESET_GPCDMA>; 30 29 reset-names = "gpcdma"; 31 - interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 30 + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 31 + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 32 32 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 33 33 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 34 34 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, ··· 62 60 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 63 61 #dma-cells = <1>; 64 62 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 63 + dma-channel-mask = <0xfffffffe>; 65 64 dma-coherent; 66 65 }; 67 66 ··· 567 564 #address-cells = <1>; 568 565 #size-cells = <1>; 569 566 570 - ranges = <0x15000000 0x15000000 0x01000000>; 567 + ranges = <0x14800000 0x14800000 0x02000000>; 571 568 interconnects = <&mc TEGRA234_MEMORY_CLIENT_HOST1XDMAR &emc>; 572 569 interconnect-names = "dma-mem"; 573 570 iommus = <&smmu_niso1 TEGRA234_SID_HOST1X>; ··· 605 602 interconnect-names = "dma-mem", "write"; 606 603 iommus = <&smmu_niso1 TEGRA234_SID_VIC>; 607 604 dma-coherent; 605 + }; 606 + 607 + nvdec@15480000 { 608 + compatible = "nvidia,tegra234-nvdec"; 609 + reg = <0x15480000 0x00040000>; 610 + clocks = <&bpmp TEGRA234_CLK_NVDEC>, 611 + <&bpmp TEGRA234_CLK_FUSE>, 612 + <&bpmp TEGRA234_CLK_TSEC_PKA>; 613 + clock-names = "nvdec", "fuse", "tsec_pka"; 614 + resets = <&bpmp TEGRA234_RESET_NVDEC>; 615 + reset-names = "nvdec"; 616 + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVDEC>; 617 + interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDECSRD &emc>, 618 + <&mc TEGRA234_MEMORY_CLIENT_NVDECSWR &emc>; 619 + interconnect-names = "dma-mem", "write"; 620 + iommus = <&smmu_niso1 TEGRA234_SID_NVDEC>; 621 + dma-coherent; 622 + 623 + nvidia,memory-controller = <&mc>; 624 + 625 + /* 626 + * Placeholder values that firmware needs to update with the real 627 + * offsets parsed from the microcode headers. 628 + */ 629 + nvidia,bl-manifest-offset = <0>; 630 + nvidia,bl-data-offset = <0>; 631 + nvidia,bl-code-offset = <0>; 632 + nvidia,os-manifest-offset = <0>; 633 + nvidia,os-data-offset = <0>; 634 + nvidia,os-code-offset = <0>; 635 + 636 + /* 637 + * Firmware needs to set this to "okay" once the above values have 638 + * been updated. 639 + */ 640 + status = "disabled"; 608 641 }; 609 642 }; 610 643 ··· 875 836 dma-names = "rx", "tx"; 876 837 }; 877 838 839 + uarti: serial@31d0000 { 840 + compatible = "arm,sbsa-uart"; 841 + reg = <0x31d0000 0x10000>; 842 + interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; 843 + status = "disabled"; 844 + }; 845 + 878 846 dp_aux_ch3_i2c: i2c@31e0000 { 879 847 compatible = "nvidia,tegra194-i2c"; 880 848 reg = <0x31e0000 0x100>; ··· 911 865 <&bpmp TEGRA234_CLK_QSPI0_PM>; 912 866 clock-names = "qspi", "qspi_out"; 913 867 resets = <&bpmp TEGRA234_RESET_QSPI0>; 914 - reset-names = "qspi"; 915 868 status = "disabled"; 916 869 }; 917 870 918 871 pwm1: pwm@3280000 { 919 - compatible = "nvidia,tegra194-pwm", 920 - "nvidia,tegra186-pwm"; 872 + compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 921 873 reg = <0x3280000 0x10000>; 922 874 clocks = <&bpmp TEGRA234_CLK_PWM1>; 923 - clock-names = "pwm"; 924 875 resets = <&bpmp TEGRA234_RESET_PWM1>; 876 + reset-names = "pwm"; 877 + status = "disabled"; 878 + #pwm-cells = <2>; 879 + }; 880 + 881 + pwm2: pwm@3290000 { 882 + compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 883 + reg = <0x3290000 0x10000>; 884 + clocks = <&bpmp TEGRA234_CLK_PWM2>; 885 + resets = <&bpmp TEGRA234_RESET_PWM2>; 886 + reset-names = "pwm"; 887 + status = "disabled"; 888 + #pwm-cells = <2>; 889 + }; 890 + 891 + pwm3: pwm@32a0000 { 892 + compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 893 + reg = <0x32a0000 0x10000>; 894 + clocks = <&bpmp TEGRA234_CLK_PWM3>; 895 + resets = <&bpmp TEGRA234_RESET_PWM3>; 896 + reset-names = "pwm"; 897 + status = "disabled"; 898 + #pwm-cells = <2>; 899 + }; 900 + 901 + pwm5: pwm@32c0000 { 902 + compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 903 + reg = <0x32c0000 0x10000>; 904 + clocks = <&bpmp TEGRA234_CLK_PWM5>; 905 + resets = <&bpmp TEGRA234_RESET_PWM5>; 906 + reset-names = "pwm"; 907 + status = "disabled"; 908 + #pwm-cells = <2>; 909 + }; 910 + 911 + pwm6: pwm@32d0000 { 912 + compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 913 + reg = <0x32d0000 0x10000>; 914 + clocks = <&bpmp TEGRA234_CLK_PWM6>; 915 + resets = <&bpmp TEGRA234_RESET_PWM6>; 916 + reset-names = "pwm"; 917 + status = "disabled"; 918 + #pwm-cells = <2>; 919 + }; 920 + 921 + pwm7: pwm@32e0000 { 922 + compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 923 + reg = <0x32e0000 0x10000>; 924 + clocks = <&bpmp TEGRA234_CLK_PWM7>; 925 + resets = <&bpmp TEGRA234_RESET_PWM7>; 926 + reset-names = "pwm"; 927 + status = "disabled"; 928 + #pwm-cells = <2>; 929 + }; 930 + 931 + pwm8: pwm@32f0000 { 932 + compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 933 + reg = <0x32f0000 0x10000>; 934 + clocks = <&bpmp TEGRA234_CLK_PWM8>; 935 + resets = <&bpmp TEGRA234_RESET_PWM8>; 925 936 reset-names = "pwm"; 926 937 status = "disabled"; 927 938 #pwm-cells = <2>; ··· 994 891 <&bpmp TEGRA234_CLK_QSPI1_PM>; 995 892 clock-names = "qspi", "qspi_out"; 996 893 resets = <&bpmp TEGRA234_RESET_QSPI1>; 997 - reset-names = "qspi"; 894 + status = "disabled"; 895 + }; 896 + 897 + mmc@3400000 { 898 + compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; 899 + reg = <0x03400000 0x20000>; 900 + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 901 + clocks = <&bpmp TEGRA234_CLK_SDMMC1>, 902 + <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; 903 + clock-names = "sdhci", "tmclk"; 904 + assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC1>, 905 + <&bpmp TEGRA234_CLK_PLLC4_MUXED>; 906 + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4_MUXED>, 907 + <&bpmp TEGRA234_CLK_PLLC4_VCO_DIV2>; 908 + resets = <&bpmp TEGRA234_RESET_SDMMC1>; 909 + reset-names = "sdhci"; 910 + interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRA &emc>, 911 + <&mc TEGRA234_MEMORY_CLIENT_SDMMCWA &emc>; 912 + interconnect-names = "dma-mem", "write"; 913 + iommus = <&smmu_niso1 TEGRA234_SID_SDMMC1A>; 914 + pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 915 + pinctrl-0 = <&sdmmc1_3v3>; 916 + pinctrl-1 = <&sdmmc1_1v8>; 917 + nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 918 + nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x07>; 919 + nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 920 + nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 921 + nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 922 + nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 923 + nvidia,default-tap = <14>; 924 + nvidia,default-trim = <0x8>; 925 + sd-uhs-sdr25; 926 + sd-uhs-sdr50; 927 + sd-uhs-ddr50; 928 + sd-uhs-sdr104; 998 929 status = "disabled"; 999 930 }; 1000 931 ··· 1062 925 }; 1063 926 1064 927 hda@3510000 { 1065 - compatible = "nvidia,tegra234-hda", "nvidia,tegra30-hda"; 928 + compatible = "nvidia,tegra234-hda"; 1066 929 reg = <0x3510000 0x10000>; 1067 930 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 1068 931 clocks = <&bpmp TEGRA234_CLK_AZA_BIT>, ··· 1102 965 "shared3", "shared4", "shared5", "shared6", 1103 966 "shared7"; 1104 967 #mbox-cells = <2>; 968 + }; 969 + 970 + p2u_hsio_0: phy@3e00000 { 971 + compatible = "nvidia,tegra234-p2u"; 972 + reg = <0x03e00000 0x10000>; 973 + reg-names = "ctl"; 974 + 975 + #phy-cells = <0>; 976 + }; 977 + 978 + p2u_hsio_1: phy@3e10000 { 979 + compatible = "nvidia,tegra234-p2u"; 980 + reg = <0x03e10000 0x10000>; 981 + reg-names = "ctl"; 982 + 983 + #phy-cells = <0>; 984 + }; 985 + 986 + p2u_hsio_2: phy@3e20000 { 987 + compatible = "nvidia,tegra234-p2u"; 988 + reg = <0x03e20000 0x10000>; 989 + reg-names = "ctl"; 990 + 991 + #phy-cells = <0>; 992 + }; 993 + 994 + p2u_hsio_3: phy@3e30000 { 995 + compatible = "nvidia,tegra234-p2u"; 996 + reg = <0x03e30000 0x10000>; 997 + reg-names = "ctl"; 998 + 999 + #phy-cells = <0>; 1000 + }; 1001 + 1002 + p2u_hsio_4: phy@3e40000 { 1003 + compatible = "nvidia,tegra234-p2u"; 1004 + reg = <0x03e40000 0x10000>; 1005 + reg-names = "ctl"; 1006 + 1007 + #phy-cells = <0>; 1008 + }; 1009 + 1010 + p2u_hsio_5: phy@3e50000 { 1011 + compatible = "nvidia,tegra234-p2u"; 1012 + reg = <0x03e50000 0x10000>; 1013 + reg-names = "ctl"; 1014 + 1015 + #phy-cells = <0>; 1016 + }; 1017 + 1018 + p2u_hsio_6: phy@3e60000 { 1019 + compatible = "nvidia,tegra234-p2u"; 1020 + reg = <0x03e60000 0x10000>; 1021 + reg-names = "ctl"; 1022 + 1023 + #phy-cells = <0>; 1024 + }; 1025 + 1026 + p2u_hsio_7: phy@3e70000 { 1027 + compatible = "nvidia,tegra234-p2u"; 1028 + reg = <0x03e70000 0x10000>; 1029 + reg-names = "ctl"; 1030 + 1031 + #phy-cells = <0>; 1032 + }; 1033 + 1034 + p2u_nvhs_0: phy@3e90000 { 1035 + compatible = "nvidia,tegra234-p2u"; 1036 + reg = <0x03e90000 0x10000>; 1037 + reg-names = "ctl"; 1038 + 1039 + #phy-cells = <0>; 1040 + }; 1041 + 1042 + p2u_nvhs_1: phy@3ea0000 { 1043 + compatible = "nvidia,tegra234-p2u"; 1044 + reg = <0x03ea0000 0x10000>; 1045 + reg-names = "ctl"; 1046 + 1047 + #phy-cells = <0>; 1048 + }; 1049 + 1050 + p2u_nvhs_2: phy@3eb0000 { 1051 + compatible = "nvidia,tegra234-p2u"; 1052 + reg = <0x03eb0000 0x10000>; 1053 + reg-names = "ctl"; 1054 + 1055 + #phy-cells = <0>; 1056 + }; 1057 + 1058 + p2u_nvhs_3: phy@3ec0000 { 1059 + compatible = "nvidia,tegra234-p2u"; 1060 + reg = <0x03ec0000 0x10000>; 1061 + reg-names = "ctl"; 1062 + 1063 + #phy-cells = <0>; 1064 + }; 1065 + 1066 + p2u_nvhs_4: phy@3ed0000 { 1067 + compatible = "nvidia,tegra234-p2u"; 1068 + reg = <0x03ed0000 0x10000>; 1069 + reg-names = "ctl"; 1070 + 1071 + #phy-cells = <0>; 1072 + }; 1073 + 1074 + p2u_nvhs_5: phy@3ee0000 { 1075 + compatible = "nvidia,tegra234-p2u"; 1076 + reg = <0x03ee0000 0x10000>; 1077 + reg-names = "ctl"; 1078 + 1079 + #phy-cells = <0>; 1080 + }; 1081 + 1082 + p2u_nvhs_6: phy@3ef0000 { 1083 + compatible = "nvidia,tegra234-p2u"; 1084 + reg = <0x03ef0000 0x10000>; 1085 + reg-names = "ctl"; 1086 + 1087 + #phy-cells = <0>; 1088 + }; 1089 + 1090 + p2u_nvhs_7: phy@3f00000 { 1091 + compatible = "nvidia,tegra234-p2u"; 1092 + reg = <0x03f00000 0x10000>; 1093 + reg-names = "ctl"; 1094 + 1095 + #phy-cells = <0>; 1096 + }; 1097 + 1098 + p2u_gbe_0: phy@3f20000 { 1099 + compatible = "nvidia,tegra234-p2u"; 1100 + reg = <0x03f20000 0x10000>; 1101 + reg-names = "ctl"; 1102 + 1103 + #phy-cells = <0>; 1104 + }; 1105 + 1106 + p2u_gbe_1: phy@3f30000 { 1107 + compatible = "nvidia,tegra234-p2u"; 1108 + reg = <0x03f30000 0x10000>; 1109 + reg-names = "ctl"; 1110 + 1111 + #phy-cells = <0>; 1112 + }; 1113 + 1114 + p2u_gbe_2: phy@3f40000 { 1115 + compatible = "nvidia,tegra234-p2u"; 1116 + reg = <0x03f40000 0x10000>; 1117 + reg-names = "ctl"; 1118 + 1119 + #phy-cells = <0>; 1120 + }; 1121 + 1122 + p2u_gbe_3: phy@3f50000 { 1123 + compatible = "nvidia,tegra234-p2u"; 1124 + reg = <0x03f50000 0x10000>; 1125 + reg-names = "ctl"; 1126 + 1127 + #phy-cells = <0>; 1128 + }; 1129 + 1130 + p2u_gbe_4: phy@3f60000 { 1131 + compatible = "nvidia,tegra234-p2u"; 1132 + reg = <0x03f60000 0x10000>; 1133 + reg-names = "ctl"; 1134 + 1135 + #phy-cells = <0>; 1136 + }; 1137 + 1138 + p2u_gbe_5: phy@3f70000 { 1139 + compatible = "nvidia,tegra234-p2u"; 1140 + reg = <0x03f70000 0x10000>; 1141 + reg-names = "ctl"; 1142 + 1143 + #phy-cells = <0>; 1144 + }; 1145 + 1146 + p2u_gbe_6: phy@3f80000 { 1147 + compatible = "nvidia,tegra234-p2u"; 1148 + reg = <0x03f80000 0x10000>; 1149 + reg-names = "ctl"; 1150 + 1151 + #phy-cells = <0>; 1152 + }; 1153 + 1154 + p2u_gbe_7: phy@3f90000 { 1155 + compatible = "nvidia,tegra234-p2u"; 1156 + reg = <0x03f90000 0x10000>; 1157 + reg-names = "ctl"; 1158 + 1159 + #phy-cells = <0>; 1105 1160 }; 1106 1161 1107 1162 ethernet@6800000 { ··· 1588 1259 status = "okay"; 1589 1260 }; 1590 1261 1591 - p2u_hsio_0: phy@3e00000 { 1592 - compatible = "nvidia,tegra234-p2u"; 1593 - reg = <0x03e00000 0x10000>; 1594 - reg-names = "ctl"; 1595 - 1596 - #phy-cells = <0>; 1597 - }; 1598 - 1599 - p2u_hsio_1: phy@3e10000 { 1600 - compatible = "nvidia,tegra234-p2u"; 1601 - reg = <0x03e10000 0x10000>; 1602 - reg-names = "ctl"; 1603 - 1604 - #phy-cells = <0>; 1605 - }; 1606 - 1607 - p2u_hsio_2: phy@3e20000 { 1608 - compatible = "nvidia,tegra234-p2u"; 1609 - reg = <0x03e20000 0x10000>; 1610 - reg-names = "ctl"; 1611 - 1612 - #phy-cells = <0>; 1613 - }; 1614 - 1615 - p2u_hsio_3: phy@3e30000 { 1616 - compatible = "nvidia,tegra234-p2u"; 1617 - reg = <0x03e30000 0x10000>; 1618 - reg-names = "ctl"; 1619 - 1620 - #phy-cells = <0>; 1621 - }; 1622 - 1623 - p2u_hsio_4: phy@3e40000 { 1624 - compatible = "nvidia,tegra234-p2u"; 1625 - reg = <0x03e40000 0x10000>; 1626 - reg-names = "ctl"; 1627 - 1628 - #phy-cells = <0>; 1629 - }; 1630 - 1631 - p2u_hsio_5: phy@3e50000 { 1632 - compatible = "nvidia,tegra234-p2u"; 1633 - reg = <0x03e50000 0x10000>; 1634 - reg-names = "ctl"; 1635 - 1636 - #phy-cells = <0>; 1637 - }; 1638 - 1639 - p2u_hsio_6: phy@3e60000 { 1640 - compatible = "nvidia,tegra234-p2u"; 1641 - reg = <0x03e60000 0x10000>; 1642 - reg-names = "ctl"; 1643 - 1644 - #phy-cells = <0>; 1645 - }; 1646 - 1647 - p2u_hsio_7: phy@3e70000 { 1648 - compatible = "nvidia,tegra234-p2u"; 1649 - reg = <0x03e70000 0x10000>; 1650 - reg-names = "ctl"; 1651 - 1652 - #phy-cells = <0>; 1653 - }; 1654 - 1655 - p2u_nvhs_0: phy@3e90000 { 1656 - compatible = "nvidia,tegra234-p2u"; 1657 - reg = <0x03e90000 0x10000>; 1658 - reg-names = "ctl"; 1659 - 1660 - #phy-cells = <0>; 1661 - }; 1662 - 1663 - p2u_nvhs_1: phy@3ea0000 { 1664 - compatible = "nvidia,tegra234-p2u"; 1665 - reg = <0x03ea0000 0x10000>; 1666 - reg-names = "ctl"; 1667 - 1668 - #phy-cells = <0>; 1669 - }; 1670 - 1671 - p2u_nvhs_2: phy@3eb0000 { 1672 - compatible = "nvidia,tegra234-p2u"; 1673 - reg = <0x03eb0000 0x10000>; 1674 - reg-names = "ctl"; 1675 - 1676 - #phy-cells = <0>; 1677 - }; 1678 - 1679 - p2u_nvhs_3: phy@3ec0000 { 1680 - compatible = "nvidia,tegra234-p2u"; 1681 - reg = <0x03ec0000 0x10000>; 1682 - reg-names = "ctl"; 1683 - 1684 - #phy-cells = <0>; 1685 - }; 1686 - 1687 - p2u_nvhs_4: phy@3ed0000 { 1688 - compatible = "nvidia,tegra234-p2u"; 1689 - reg = <0x03ed0000 0x10000>; 1690 - reg-names = "ctl"; 1691 - 1692 - #phy-cells = <0>; 1693 - }; 1694 - 1695 - p2u_nvhs_5: phy@3ee0000 { 1696 - compatible = "nvidia,tegra234-p2u"; 1697 - reg = <0x03ee0000 0x10000>; 1698 - reg-names = "ctl"; 1699 - 1700 - #phy-cells = <0>; 1701 - }; 1702 - 1703 - p2u_nvhs_6: phy@3ef0000 { 1704 - compatible = "nvidia,tegra234-p2u"; 1705 - reg = <0x03ef0000 0x10000>; 1706 - reg-names = "ctl"; 1707 - 1708 - #phy-cells = <0>; 1709 - }; 1710 - 1711 - p2u_nvhs_7: phy@3f00000 { 1712 - compatible = "nvidia,tegra234-p2u"; 1713 - reg = <0x03f00000 0x10000>; 1714 - reg-names = "ctl"; 1715 - 1716 - #phy-cells = <0>; 1717 - }; 1718 - 1719 - p2u_gbe_0: phy@3f20000 { 1720 - compatible = "nvidia,tegra234-p2u"; 1721 - reg = <0x03f20000 0x10000>; 1722 - reg-names = "ctl"; 1723 - 1724 - #phy-cells = <0>; 1725 - }; 1726 - 1727 - p2u_gbe_1: phy@3f30000 { 1728 - compatible = "nvidia,tegra234-p2u"; 1729 - reg = <0x03f30000 0x10000>; 1730 - reg-names = "ctl"; 1731 - 1732 - #phy-cells = <0>; 1733 - }; 1734 - 1735 - p2u_gbe_2: phy@3f40000 { 1736 - compatible = "nvidia,tegra234-p2u"; 1737 - reg = <0x03f40000 0x10000>; 1738 - reg-names = "ctl"; 1739 - 1740 - #phy-cells = <0>; 1741 - }; 1742 - 1743 - p2u_gbe_3: phy@3f50000 { 1744 - compatible = "nvidia,tegra234-p2u"; 1745 - reg = <0x03f50000 0x10000>; 1746 - reg-names = "ctl"; 1747 - 1748 - #phy-cells = <0>; 1749 - }; 1750 - 1751 - p2u_gbe_4: phy@3f60000 { 1752 - compatible = "nvidia,tegra234-p2u"; 1753 - reg = <0x03f60000 0x10000>; 1754 - reg-names = "ctl"; 1755 - 1756 - #phy-cells = <0>; 1757 - }; 1758 - 1759 - p2u_gbe_5: phy@3f70000 { 1760 - compatible = "nvidia,tegra234-p2u"; 1761 - reg = <0x03f70000 0x10000>; 1762 - reg-names = "ctl"; 1763 - 1764 - #phy-cells = <0>; 1765 - }; 1766 - 1767 - p2u_gbe_6: phy@3f80000 { 1768 - compatible = "nvidia,tegra234-p2u"; 1769 - reg = <0x03f80000 0x10000>; 1770 - reg-names = "ctl"; 1771 - 1772 - #phy-cells = <0>; 1773 - }; 1774 - 1775 - p2u_gbe_7: phy@3f90000 { 1776 - compatible = "nvidia,tegra234-p2u"; 1777 - reg = <0x03f90000 0x10000>; 1778 - reg-names = "ctl"; 1779 - 1780 - #phy-cells = <0>; 1781 - }; 1782 - 1783 1262 hsp_aon: hsp@c150000 { 1784 1263 compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 1785 1264 reg = <0x0c150000 0x90000>; ··· 1625 1488 gen8_i2c: i2c@c250000 { 1626 1489 compatible = "nvidia,tegra194-i2c"; 1627 1490 reg = <0xc250000 0x100>; 1628 - nvidia,hw-instance-id = <0x7>; 1629 1491 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1630 1492 status = "disabled"; 1631 1493 clock-frequency = <400000>; ··· 1666 1530 gpio-controller; 1667 1531 }; 1668 1532 1533 + pwm4: pwm@c340000 { 1534 + compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 1535 + reg = <0xc340000 0x10000>; 1536 + clocks = <&bpmp TEGRA234_CLK_PWM4>; 1537 + resets = <&bpmp TEGRA234_RESET_PWM4>; 1538 + reset-names = "pwm"; 1539 + status = "disabled"; 1540 + #pwm-cells = <2>; 1541 + }; 1542 + 1669 1543 pmc: pmc@c360000 { 1670 1544 compatible = "nvidia,tegra234-pmc"; 1671 1545 reg = <0x0c360000 0x10000>, ··· 1687 1541 1688 1542 #interrupt-cells = <2>; 1689 1543 interrupt-controller; 1544 + 1545 + sdmmc1_3v3: sdmmc1-3v3 { 1546 + pins = "sdmmc1-hv"; 1547 + power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1548 + }; 1549 + 1550 + sdmmc1_1v8: sdmmc1-1v8 { 1551 + pins = "sdmmc1-hv"; 1552 + power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1553 + }; 1554 + 1555 + sdmmc3_3v3: sdmmc3-3v3 { 1556 + pins = "sdmmc3-hv"; 1557 + power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1558 + }; 1559 + 1560 + sdmmc3_1v8: sdmmc3-1v8 { 1561 + pins = "sdmmc3-hv"; 1562 + power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1563 + }; 1690 1564 }; 1691 1565 1692 1566 aon-fabric@c600000 { ··· 1742 1576 interrupt-controller; 1743 1577 }; 1744 1578 1745 - smmu_iso: iommu@10000000{ 1579 + smmu_iso: iommu@10000000 { 1746 1580 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 1747 1581 reg = <0x10000000 0x1000000>; 1748 1582 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, ··· 2045 1879 reg = <0x00 0x140a0000 0x0 0x00020000>, /* appl registers (128K) */ 2046 1880 <0x00 0x2a000000 0x0 0x00040000>, /* configuration space (256K) */ 2047 1881 <0x00 0x2a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2048 - <0x00 0x2a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2049 - reg-names = "appl", "config", "atu_dma", "dbi"; 1882 + <0x00 0x2a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 1883 + <0x35 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 1884 + reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2050 1885 2051 1886 #address-cells = <3>; 2052 1887 #size-cells = <2>; ··· 2099 1932 reg = <0x00 0x140c0000 0x0 0x00020000>, /* appl registers (128K) */ 2100 1933 <0x00 0x2c000000 0x0 0x00040000>, /* configuration space (256K) */ 2101 1934 <0x00 0x2c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2102 - <0x00 0x2c080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2103 - reg-names = "appl", "config", "atu_dma", "dbi"; 1935 + <0x00 0x2c080000 0x0 0x00040000>, /* DBI reg space (256K) */ 1936 + <0x38 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 1937 + reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2104 1938 2105 1939 #address-cells = <3>; 2106 1940 #size-cells = <2>; ··· 2133 1965 2134 1966 bus-range = <0x0 0xff>; 2135 1967 2136 - ranges = <0x43000000 0x35 0x40000000 0x35 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 1968 + ranges = <0x43000000 0x35 0x40000000 0x35 0x40000000 0x2 0xc0000000>, /* prefetchable memory (11264 MB) */ 2137 1969 <0x02000000 0x0 0x40000000 0x38 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2138 1970 <0x01000000 0x0 0x2c100000 0x00 0x2c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2139 1971 ··· 2153 1985 reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */ 2154 1986 <0x00 0x2e000000 0x0 0x00040000>, /* configuration space (256K) */ 2155 1987 <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2156 - <0x00 0x2e080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2157 - reg-names = "appl", "config", "atu_dma", "dbi"; 1988 + <0x00 0x2e080000 0x0 0x00040000>, /* DBI reg space (256K) */ 1989 + <0x3b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 1990 + reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2158 1991 2159 1992 #address-cells = <3>; 2160 1993 #size-cells = <2>; ··· 2207 2038 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 2208 2039 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 2209 2040 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2210 - <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2211 - reg-names = "appl", "config", "atu_dma", "dbi"; 2041 + <0x00 0x30080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2042 + <0x20 0xb0000000 0x0 0x10000000>; /* ECAM (256MB) */ 2043 + reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2212 2044 2213 2045 #address-cells = <3>; 2214 2046 #size-cells = <2>; ··· 2261 2091 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 2262 2092 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 2263 2093 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2264 - <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2265 - reg-names = "appl", "config", "atu_dma", "dbi"; 2094 + <0x00 0x32080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2095 + <0x20 0xf0000000 0x0 0x10000000>; /* ECAM (256MB) */ 2096 + reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2266 2097 2267 2098 #address-cells = <3>; 2268 2099 #size-cells = <2>; ··· 2315 2144 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 2316 2145 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 2317 2146 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2318 - <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2319 - reg-names = "appl", "config", "atu_dma", "dbi"; 2147 + <0x00 0x34080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2148 + <0x21 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2149 + reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2320 2150 2321 2151 #address-cells = <3>; 2322 2152 #size-cells = <2>; ··· 2350 2178 bus-range = <0x0 0xff>; 2351 2179 2352 2180 ranges = <0x43000000 0x21 0x00000000 0x21 0x00000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 2353 - <0x02000000 0x0 0x40000000 0x21 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2181 + <0x02000000 0x0 0x40000000 0x21 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2354 2182 <0x01000000 0x0 0x34100000 0x00 0x34100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2355 2183 2356 2184 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE3R &emc>, ··· 2369 2197 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2370 2198 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 2371 2199 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2372 - <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2373 - reg-names = "appl", "config", "atu_dma", "dbi"; 2200 + <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2201 + <0x24 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2202 + reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2374 2203 2375 2204 #address-cells = <3>; 2376 2205 #size-cells = <2>; ··· 2423 2250 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2424 2251 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 2425 2252 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2426 - <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2427 - reg-names = "appl", "config", "atu_dma", "dbi"; 2253 + <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2254 + <0x27 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2255 + reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2428 2256 2429 2257 #address-cells = <3>; 2430 2258 #size-cells = <2>; ··· 2477 2303 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2478 2304 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 2479 2305 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2480 - <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2481 - reg-names = "appl", "config", "atu_dma", "dbi"; 2306 + <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2307 + <0x2b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2308 + reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2482 2309 2483 2310 #address-cells = <3>; 2484 2311 #size-cells = <2>; ··· 2511 2336 2512 2337 bus-range = <0x0 0xff>; 2513 2338 2514 - ranges = <0x43000000 0x27 0x40000000 0x27 0x40000000 0x3 0xe8000000>, /* prefetchable memory (16000 MB) */ 2339 + ranges = <0x43000000 0x28 0x00000000 0x28 0x00000000 0x3 0x28000000>, /* prefetchable memory (12928 MB) */ 2515 2340 <0x02000000 0x0 0x40000000 0x2b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2516 2341 <0x01000000 0x0 0x3a100000 0x00 0x3a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2517 2342 ··· 2531 2356 reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */ 2532 2357 <0x00 0x3c000000 0x0 0x00040000>, /* configuration space (256K) */ 2533 2358 <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2534 - <0x00 0x3c080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2535 - reg-names = "appl", "config", "atu_dma", "dbi"; 2359 + <0x00 0x3c080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2360 + <0x2e 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2361 + reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2536 2362 2537 2363 #address-cells = <3>; 2538 2364 #size-cells = <2>; ··· 2585 2409 reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */ 2586 2410 <0x00 0x3e000000 0x0 0x00040000>, /* configuration space (256K) */ 2587 2411 <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2588 - <0x00 0x3e080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2589 - reg-names = "appl", "config", "atu_dma", "dbi"; 2412 + <0x00 0x3e080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2413 + <0x32 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2414 + reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2590 2415 2591 2416 #address-cells = <3>; 2592 2417 #size-cells = <2>; ··· 2619 2442 2620 2443 bus-range = <0x0 0xff>; 2621 2444 2622 - ranges = <0x43000000 0x2e 0x40000000 0x2e 0x40000000 0x3 0xe8000000>, /* prefetchable memory (16000 MB) */ 2445 + ranges = <0x43000000 0x30 0x00000000 0x30 0x00000000 0x2 0x28000000>, /* prefetchable memory (8832 MB) */ 2623 2446 <0x02000000 0x0 0x40000000 0x32 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2624 2447 <0x01000000 0x0 0x3e100000 0x00 0x3e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2625 2448 ··· 3082 2905 }; 3083 2906 3084 2907 l2c0_0: l2-cache00 { 2908 + compatible = "cache"; 3085 2909 cache-size = <262144>; 3086 2910 cache-line-size = <64>; 3087 2911 cache-sets = <512>; 3088 2912 cache-unified; 2913 + cache-level = <2>; 3089 2914 next-level-cache = <&l3c0>; 3090 2915 }; 3091 2916 3092 2917 l2c0_1: l2-cache01 { 2918 + compatible = "cache"; 3093 2919 cache-size = <262144>; 3094 2920 cache-line-size = <64>; 3095 2921 cache-sets = <512>; 3096 2922 cache-unified; 2923 + cache-level = <2>; 3097 2924 next-level-cache = <&l3c0>; 3098 2925 }; 3099 2926 3100 2927 l2c0_2: l2-cache02 { 2928 + compatible = "cache"; 3101 2929 cache-size = <262144>; 3102 2930 cache-line-size = <64>; 3103 2931 cache-sets = <512>; 3104 2932 cache-unified; 2933 + cache-level = <2>; 3105 2934 next-level-cache = <&l3c0>; 3106 2935 }; 3107 2936 3108 2937 l2c0_3: l2-cache03 { 2938 + compatible = "cache"; 3109 2939 cache-size = <262144>; 3110 2940 cache-line-size = <64>; 3111 2941 cache-sets = <512>; 3112 2942 cache-unified; 2943 + cache-level = <2>; 3113 2944 next-level-cache = <&l3c0>; 3114 2945 }; 3115 2946 3116 2947 l2c1_0: l2-cache10 { 2948 + compatible = "cache"; 3117 2949 cache-size = <262144>; 3118 2950 cache-line-size = <64>; 3119 2951 cache-sets = <512>; 3120 2952 cache-unified; 2953 + cache-level = <2>; 3121 2954 next-level-cache = <&l3c1>; 3122 2955 }; 3123 2956 3124 2957 l2c1_1: l2-cache11 { 2958 + compatible = "cache"; 3125 2959 cache-size = <262144>; 3126 2960 cache-line-size = <64>; 3127 2961 cache-sets = <512>; 3128 2962 cache-unified; 2963 + cache-level = <2>; 3129 2964 next-level-cache = <&l3c1>; 3130 2965 }; 3131 2966 3132 2967 l2c1_2: l2-cache12 { 2968 + compatible = "cache"; 3133 2969 cache-size = <262144>; 3134 2970 cache-line-size = <64>; 3135 2971 cache-sets = <512>; 3136 2972 cache-unified; 2973 + cache-level = <2>; 3137 2974 next-level-cache = <&l3c1>; 3138 2975 }; 3139 2976 3140 2977 l2c1_3: l2-cache13 { 2978 + compatible = "cache"; 3141 2979 cache-size = <262144>; 3142 2980 cache-line-size = <64>; 3143 2981 cache-sets = <512>; 3144 2982 cache-unified; 2983 + cache-level = <2>; 3145 2984 next-level-cache = <&l3c1>; 3146 2985 }; 3147 2986 3148 2987 l2c2_0: l2-cache20 { 2988 + compatible = "cache"; 3149 2989 cache-size = <262144>; 3150 2990 cache-line-size = <64>; 3151 2991 cache-sets = <512>; 3152 2992 cache-unified; 2993 + cache-level = <2>; 3153 2994 next-level-cache = <&l3c2>; 3154 2995 }; 3155 2996 3156 2997 l2c2_1: l2-cache21 { 2998 + compatible = "cache"; 3157 2999 cache-size = <262144>; 3158 3000 cache-line-size = <64>; 3159 3001 cache-sets = <512>; 3160 3002 cache-unified; 3003 + cache-level = <2>; 3161 3004 next-level-cache = <&l3c2>; 3162 3005 }; 3163 3006 3164 3007 l2c2_2: l2-cache22 { 3008 + compatible = "cache"; 3165 3009 cache-size = <262144>; 3166 3010 cache-line-size = <64>; 3167 3011 cache-sets = <512>; 3168 3012 cache-unified; 3013 + cache-level = <2>; 3169 3014 next-level-cache = <&l3c2>; 3170 3015 }; 3171 3016 3172 3017 l2c2_3: l2-cache23 { 3018 + compatible = "cache"; 3173 3019 cache-size = <262144>; 3174 3020 cache-line-size = <64>; 3175 3021 cache-sets = <512>; 3176 3022 cache-unified; 3023 + cache-level = <2>; 3177 3024 next-level-cache = <&l3c2>; 3178 3025 }; 3179 3026 3180 3027 l3c0: l3-cache0 { 3028 + compatible = "cache"; 3029 + cache-unified; 3181 3030 cache-size = <2097152>; 3182 3031 cache-line-size = <64>; 3183 3032 cache-sets = <2048>; 3033 + cache-level = <3>; 3184 3034 }; 3185 3035 3186 3036 l3c1: l3-cache1 { 3037 + compatible = "cache"; 3038 + cache-unified; 3187 3039 cache-size = <2097152>; 3188 3040 cache-line-size = <64>; 3189 3041 cache-sets = <2048>; 3042 + cache-level = <3>; 3190 3043 }; 3191 3044 3192 3045 l3c2: l3-cache2 { 3046 + compatible = "cache"; 3047 + cache-unified; 3193 3048 cache-size = <2097152>; 3194 3049 cache-line-size = <64>; 3195 3050 cache-sets = <2048>; 3051 + cache-level = <3>; 3196 3052 }; 3197 3053 }; 3198 3054