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drm/amdgpu: add some comments in DCE6

Add some comments.

Signed-off-by: Alexandre Demers <alexandre.f.demers@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Alexandre Demers and committed by
Alex Deucher
029ab8ca fb92daa3

+16 -2
+16 -2
drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
··· 206 206 /* update the scanout addresses */ 207 207 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 208 208 upper_32_bits(crtc_base)); 209 + /* writing to the low address triggers the update */ 209 210 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 210 211 (u32)crtc_base); 211 - 212 212 /* post the write */ 213 213 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); 214 214 } ··· 218 218 { 219 219 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) 220 220 return -EINVAL; 221 + 221 222 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); 222 223 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); 223 224 224 225 return 0; 225 - 226 226 } 227 227 228 228 /** ··· 1006 1006 } 1007 1007 1008 1008 /* watermark setup */ 1009 + /** 1010 + * dce_v6_0_line_buffer_adjust - Set up the line buffer 1011 + * 1012 + * @adev: amdgpu_device pointer 1013 + * @amdgpu_crtc: the selected display controller 1014 + * @mode: the current display mode on the selected display 1015 + * controller 1016 + * 1017 + * Setup up the line buffer allocation for 1018 + * the selected display controller (CIK). 1019 + * Returns the line buffer size in pixels. 1020 + */ 1009 1021 static u32 dce_v6_0_line_buffer_adjust(struct amdgpu_device *adev, 1010 1022 struct amdgpu_crtc *amdgpu_crtc, 1011 1023 struct drm_display_mode *mode, ··· 1398 1386 adev->mode_info.audio.pin[i].connected = false; 1399 1387 adev->mode_info.audio.pin[i].offset = pin_offsets[i]; 1400 1388 adev->mode_info.audio.pin[i].id = i; 1389 + /* disable audio. it will be set up later */ 1390 + /* XXX remove once we switch to ip funcs */ 1401 1391 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 1402 1392 } 1403 1393