···206206 /* update the scanout addresses */207207 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,208208 upper_32_bits(crtc_base));209209+ /* writing to the low address triggers the update */209210 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,210211 (u32)crtc_base);211211-212212 /* post the write */213213 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);214214}···218218{219219 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))220220 return -EINVAL;221221+221222 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);222223 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);223224224225 return 0;225225-226226}227227228228/**···10061006}1007100710081008/* watermark setup */10091009+/**10101010+ * dce_v6_0_line_buffer_adjust - Set up the line buffer10111011+ *10121012+ * @adev: amdgpu_device pointer10131013+ * @amdgpu_crtc: the selected display controller10141014+ * @mode: the current display mode on the selected display10151015+ * controller10161016+ *10171017+ * Setup up the line buffer allocation for10181018+ * the selected display controller (CIK).10191019+ * Returns the line buffer size in pixels.10201020+ */10091021static u32 dce_v6_0_line_buffer_adjust(struct amdgpu_device *adev,10101022 struct amdgpu_crtc *amdgpu_crtc,10111023 struct drm_display_mode *mode,···13981386 adev->mode_info.audio.pin[i].connected = false;13991387 adev->mode_info.audio.pin[i].offset = pin_offsets[i];14001388 adev->mode_info.audio.pin[i].id = i;13891389+ /* disable audio. it will be set up later */13901390+ /* XXX remove once we switch to ip funcs */14011391 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);14021392 }14031393