tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'iommu-fixes-v5.10-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu

Pull iommu fixes from Joerg Roedel:

- Fix a NULL-ptr dereference in the Intel VT-d driver

- Two fixes for Intel SVM support

- Increase IRQ remapping table size in the AMD IOMMU driver. The old
number of 128 turned out to be too low for some recent devices.

- Fix a mask check in generic IOMMU code

* tag 'iommu-fixes-v5.10-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu:
iommu: Fix a check in iommu_check_bind_data()
iommu/vt-d: Fix a bug for PDP check in prq_event_thread
iommu/vt-d: Fix sid not set issue in intel_svm_bind_gpasid()
iommu/vt-d: Fix kernel NULL pointer dereference in find_domain()
iommu/amd: Increase interrupt remapping table limit to 512 entries

Linus Torvalds 02a2aa35 1669ecf9

+16 -3
+5 -1
drivers/iommu/amd/amd_iommu_types.h
··· 409 409 /* Only true if all IOMMUs support device IOTLBs */ 410 410 extern bool amd_iommu_iotlb_sup; 411 411 412 - #define MAX_IRQS_PER_TABLE 256 412 + /* 413 + * AMD IOMMU hardware only support 512 IRTEs despite 414 + * the architectural limitation of 2048 entries. 415 + */ 416 + #define MAX_IRQS_PER_TABLE 512 413 417 #define IRQ_TABLE_ALIGNMENT 128 414 418 415 419 struct irq_remap_table {
+3
drivers/iommu/intel/iommu.c
··· 2525 2525 { 2526 2526 struct device_domain_info *info; 2527 2527 2528 + if (unlikely(!dev || !dev->iommu)) 2529 + return NULL; 2530 + 2528 2531 if (unlikely(attach_deferred(dev))) 2529 2532 return NULL; 2530 2533
+7 -1
drivers/iommu/intel/svm.c
··· 279 279 struct intel_iommu *iommu = device_to_iommu(dev, NULL, NULL); 280 280 struct intel_svm_dev *sdev = NULL; 281 281 struct dmar_domain *dmar_domain; 282 + struct device_domain_info *info; 282 283 struct intel_svm *svm = NULL; 283 284 int ret = 0; 284 285 ··· 309 308 * guest PASID range. 310 309 */ 311 310 if (data->hpasid <= 0 || data->hpasid >= PASID_MAX) 311 + return -EINVAL; 312 + 313 + info = get_domain_info(dev); 314 + if (!info) 312 315 return -EINVAL; 313 316 314 317 dmar_domain = to_dmar_domain(domain); ··· 362 357 goto out; 363 358 } 364 359 sdev->dev = dev; 360 + sdev->sid = PCI_DEVID(info->bus, info->devfn); 365 361 366 362 /* Only count users if device has aux domains */ 367 363 if (iommu_dev_feature_enabled(dev, IOMMU_DEV_FEAT_AUX)) ··· 1035 1029 resp.qw0 = QI_PGRP_PASID(req->pasid) | 1036 1030 QI_PGRP_DID(req->rid) | 1037 1031 QI_PGRP_PASID_P(req->pasid_present) | 1038 - QI_PGRP_PDP(req->pasid_present) | 1032 + QI_PGRP_PDP(req->priv_data_present) | 1039 1033 QI_PGRP_RESP_CODE(result) | 1040 1034 QI_PGRP_RESP_TYPE; 1041 1035 resp.qw1 = QI_PGRP_IDX(req->prg_index) |
+1 -1
drivers/iommu/iommu.c
··· 2071 2071 2072 2072 static int iommu_check_bind_data(struct iommu_gpasid_bind_data *data) 2073 2073 { 2074 - u32 mask; 2074 + u64 mask; 2075 2075 int i; 2076 2076 2077 2077 if (data->version != IOMMU_GPASID_BIND_VERSION_1)