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phy: exynos5-usbdrd: support HS phy for ExynosAutov920

Enable UTMI+ phy support for this SoC which is very similar to what
the existing Exynos850 supports.

Add required change in phy driver to support HS phy for this SoC.

Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Pritam Manohar Sutar <pritam.sutar@samsung.com>
Link: https://patch.msgid.link/20251124110453.2887437-3-pritam.sutar@samsung.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Pritam Manohar Sutar and committed by
Vinod Koul
031314bd 28810c0d

+125
+123
drivers/phy/samsung/phy-exynos5-usbdrd.c
··· 2054 2054 .n_regulators = ARRAY_SIZE(exynos5_regulator_names), 2055 2055 }; 2056 2056 2057 + static int exynosautov920_usbdrd_phy_init(struct phy *phy) 2058 + { 2059 + struct phy_usb_instance *inst = phy_get_drvdata(phy); 2060 + struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst); 2061 + int ret; 2062 + 2063 + ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks); 2064 + if (ret) 2065 + return ret; 2066 + 2067 + /* Bypass PHY isol */ 2068 + inst->phy_cfg->phy_isol(inst, false); 2069 + 2070 + /* UTMI or PIPE3 specific init */ 2071 + inst->phy_cfg->phy_init(phy_drd); 2072 + 2073 + clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks); 2074 + 2075 + return 0; 2076 + } 2077 + 2078 + static int exynosautov920_usbdrd_phy_exit(struct phy *phy) 2079 + { 2080 + struct phy_usb_instance *inst = phy_get_drvdata(phy); 2081 + struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst); 2082 + int ret; 2083 + 2084 + ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks); 2085 + if (ret) 2086 + return ret; 2087 + 2088 + exynos850_usbdrd_phy_exit(phy); 2089 + 2090 + /* enable PHY isol */ 2091 + inst->phy_cfg->phy_isol(inst, true); 2092 + 2093 + clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks); 2094 + 2095 + return 0; 2096 + } 2097 + 2098 + static int exynosautov920_usbdrd_phy_power_on(struct phy *phy) 2099 + { 2100 + struct phy_usb_instance *inst = phy_get_drvdata(phy); 2101 + struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst); 2102 + int ret; 2103 + 2104 + dev_dbg(phy_drd->dev, "Request to power_on usbdrd_phy phy\n"); 2105 + 2106 + ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_core_clks, 2107 + phy_drd->core_clks); 2108 + if (ret) 2109 + return ret; 2110 + 2111 + /* Enable supply */ 2112 + ret = regulator_bulk_enable(phy_drd->drv_data->n_regulators, 2113 + phy_drd->regulators); 2114 + if (ret) { 2115 + dev_err(phy_drd->dev, "Failed to enable PHY regulator(s)\n"); 2116 + goto fail_supply; 2117 + } 2118 + 2119 + return 0; 2120 + 2121 + fail_supply: 2122 + clk_bulk_disable_unprepare(phy_drd->drv_data->n_core_clks, 2123 + phy_drd->core_clks); 2124 + 2125 + return ret; 2126 + } 2127 + 2128 + static int exynosautov920_usbdrd_phy_power_off(struct phy *phy) 2129 + { 2130 + struct phy_usb_instance *inst = phy_get_drvdata(phy); 2131 + struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst); 2132 + 2133 + dev_dbg(phy_drd->dev, "Request to power_off usbdrd_phy phy\n"); 2134 + 2135 + /* Disable supply */ 2136 + regulator_bulk_disable(phy_drd->drv_data->n_regulators, 2137 + phy_drd->regulators); 2138 + 2139 + clk_bulk_disable_unprepare(phy_drd->drv_data->n_core_clks, 2140 + phy_drd->core_clks); 2141 + 2142 + return 0; 2143 + } 2144 + 2145 + static const char * const exynosautov920_usb20_regulators[] = { 2146 + "dvdd", "vdd18", "vdd33", 2147 + }; 2148 + 2149 + static const struct phy_ops exynosautov920_usbdrd_phy_ops = { 2150 + .init = exynosautov920_usbdrd_phy_init, 2151 + .exit = exynosautov920_usbdrd_phy_exit, 2152 + .power_on = exynosautov920_usbdrd_phy_power_on, 2153 + .power_off = exynosautov920_usbdrd_phy_power_off, 2154 + .owner = THIS_MODULE, 2155 + }; 2156 + 2157 + static const struct exynos5_usbdrd_phy_config phy_cfg_exynosautov920[] = { 2158 + { 2159 + .id = EXYNOS5_DRDPHY_UTMI, 2160 + .phy_isol = exynos5_usbdrd_phy_isol, 2161 + .phy_init = exynos850_usbdrd_utmi_init, 2162 + }, 2163 + }; 2164 + 2165 + static const struct exynos5_usbdrd_phy_drvdata exynosautov920_usbdrd_phy = { 2166 + .phy_cfg = phy_cfg_exynosautov920, 2167 + .phy_ops = &exynosautov920_usbdrd_phy_ops, 2168 + .pmu_offset_usbdrd0_phy = EXYNOSAUTOV920_PHY_CTRL_USB20, 2169 + .clk_names = exynos5_clk_names, 2170 + .n_clks = ARRAY_SIZE(exynos5_clk_names), 2171 + .core_clk_names = exynos5_core_clk_names, 2172 + .n_core_clks = ARRAY_SIZE(exynos5_core_clk_names), 2173 + .regulator_names = exynosautov920_usb20_regulators, 2174 + .n_regulators = ARRAY_SIZE(exynosautov920_usb20_regulators), 2175 + }; 2176 + 2057 2177 static const struct exynos5_usbdrd_phy_config phy_cfg_gs101[] = { 2058 2178 { 2059 2179 .id = EXYNOS5_DRDPHY_UTMI, ··· 2380 2260 }, { 2381 2261 .compatible = "samsung,exynos990-usbdrd-phy", 2382 2262 .data = &exynos990_usbdrd_phy 2263 + }, { 2264 + .compatible = "samsung,exynosautov920-usbdrd-phy", 2265 + .data = &exynosautov920_usbdrd_phy 2383 2266 }, 2384 2267 { }, 2385 2268 };
+2
include/linux/soc/samsung/exynos-regs-pmu.h
··· 1015 1015 #define GS101_GRP2_INTR_BID_UPEND (0x0208) 1016 1016 #define GS101_GRP2_INTR_BID_CLEAR (0x020c) 1017 1017 1018 + /* exynosautov920 */ 1019 + #define EXYNOSAUTOV920_PHY_CTRL_USB20 (0x0710) 1018 1020 #endif /* __LINUX_SOC_EXYNOS_REGS_PMU_H */