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irqchip/gic-v5: Enable GICv5 SMP booting

Set up IPIs by allocating IPI IRQs for all cpus and call into
arm64 core code to initialise IPIs IRQ descriptors and
request the related IRQ.

Implement hotplug callback to enable interrupts on a cpu
and register the cpu with an IRS.

Co-developed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com>
Co-developed-by: Timothy Hayes <timothy.hayes@arm.com>
Signed-off-by: Timothy Hayes <timothy.hayes@arm.com>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20250703-gicv5-host-v7-23-12e71f1b3528@kernel.org
Signed-off-by: Marc Zyngier <maz@kernel.org>

authored by

Lorenzo Pieralisi and committed by
Marc Zyngier 03a28dc3 0f010132

+21
+21
drivers/irqchip/irq-gic-v5.c
··· 5 5 6 6 #define pr_fmt(fmt) "GICv5: " fmt 7 7 8 + #include <linux/cpuhotplug.h> 8 9 #include <linux/idr.h> 9 10 #include <linux/irqdomain.h> 10 11 #include <linux/slab.h> ··· 919 918 write_sysreg_s(cr0, SYS_ICC_CR0_EL1); 920 919 } 921 920 921 + static int base_ipi_virq; 922 + 922 923 static int gicv5_starting_cpu(unsigned int cpu) 923 924 { 924 925 if (WARN(!gicv5_cpuif_has_gcie(), ··· 930 927 gicv5_cpu_enable_interrupts(); 931 928 932 929 return gicv5_irs_register_cpu(cpu); 930 + } 931 + 932 + static void __init gicv5_smp_init(void) 933 + { 934 + unsigned int num_ipis = GICV5_IPIS_PER_CPU * nr_cpu_ids; 935 + 936 + cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING, 937 + "irqchip/arm/gicv5:starting", 938 + gicv5_starting_cpu, NULL); 939 + 940 + base_ipi_virq = irq_domain_alloc_irqs(gicv5_global_data.ipi_domain, 941 + num_ipis, NUMA_NO_NODE, NULL); 942 + if (WARN(base_ipi_virq <= 0, "IPI IRQ allocation was not successful")) 943 + return; 944 + 945 + set_smp_ipi_range_percpu(base_ipi_virq, GICV5_IPIS_PER_CPU, nr_cpu_ids); 933 946 } 934 947 935 948 static void __init gicv5_free_domains(void) ··· 1068 1049 ret = gicv5_irs_enable(); 1069 1050 if (ret) 1070 1051 goto out_int; 1052 + 1053 + gicv5_smp_init(); 1071 1054 1072 1055 return 0; 1073 1056