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Documentation/gpu: Add more information about GC

This commit introduces set of information that details the different
sets of schedulers available in the SE.

Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian König <christian.koenig@amd.com>
Cc: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Rodrigo Siqueira and committed by
Alex Deucher 03a48f07 d68ba530

+13 -11
+13 -11
Documentation/gpu/amdgpu/gc/index.rst
··· 7 7 The relationship between the CPU and GPU can be described as the 8 8 producer-consumer problem, where the CPU fills out a buffer with operations 9 9 (producer) to be executed by the GPU (consumer). The requested operations in 10 - the buffer are called Command Packets, which can be summarized as a compressed 11 - way of transmitting command information to the graphics controller. 10 + the buffer are called **Command Packets**, which can be summarized as a 11 + compressed way of transmitting command information to the graphics controller. 12 12 13 13 The component that acts as the front end between the CPU and the GPU is called 14 - the Command Processor (CP). This component is responsible for providing greater 15 - flexibility to the GC since CP makes it possible to program various aspects of 16 - the GPU pipeline. CP also coordinates the communication between the CPU and GPU 17 - via a mechanism named **Ring Buffers**, where the CPU appends information to 18 - the buffer while the GPU removes operations. It is relevant to highlight that a 19 - CPU can add a pointer to the Ring Buffer that points to another region of 20 - memory outside the Ring Buffer, and CP can handle it; this mechanism is called 21 - **Indirect Buffer (IB)**. CP receives and parses the Command Streams (CS), and 22 - writes the operations to the correct hardware blocks. 14 + **Command Processor (CP)**. This component is responsible for providing greater 15 + flexibility to the **Graphics and Compute (GC)** since CP makes it possible to 16 + program various aspects of the GPU pipeline. CP also coordinates the 17 + communication between the CPU and GPU via a mechanism named **Ring Buffers**, 18 + where the CPU appends information to the buffer while the GPU removes 19 + operations. CP is also responsible for handling **Indirect Buffers (IB)**. 20 + 21 + For reference, internally the CP consists of several sub-blocks (CPC - CP 22 + compute, CPG - CP graphics, and CPF - CP fetcher). Some of these acronyms 23 + appear in register names, but this is more of an implementation detail and not 24 + something that directly impacts driver programming or debugging. 23 25 24 26 Graphics (GFX) and Compute Microcontrollers 25 27 -------------------------------------------