Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull drm intel and exynos fixes from Dave Airlie:
"A bunch of fixes for Intel and exynos, nothing too major, a new intel
PCI ID, and a fix for CRT detection."
* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux:
drm/i915: pch_irq_handler -> {ibx, cpt}_irq_handler
char/agp: add another Ironlake host bridge
drm/i915: fix up ivb plane 3 pageflips
drm/exynos: fixed blending for hdmi graphic layer
drm/exynos: Remove dummy encoder get_crtc operation implementation
drm/exynos: Keep a reference to frame buffer GEM objects
drm/exynos: Don't cast GEM object to Exynos GEM object when not needed
drm/exynos: DRIVER_BUS_PLATFORM is not a driver feature
drm/exynos: fixed size type.
drm/exynos: Use DRM_FORMAT_{NV12, YUV420} instead of DRM_FORMAT_{NV12M, YUV420M}
drm/i915: hold forcewake around ring hw init
drm/i915: Mark the ringbuffers as being in the GTT domain
drm/i915/crt: Do not rely upon the HPD presence pin
drm/i915: Reset last_retired_head when resetting ring
+161
-45
+1
drivers/char/agp/intel-agp.c
+1
drivers/char/agp/intel-agp.c
···
898
898
ID(PCI_DEVICE_ID_INTEL_B43_HB),
899
899
ID(PCI_DEVICE_ID_INTEL_B43_1_HB),
900
900
ID(PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB),
901
+
ID(PCI_DEVICE_ID_INTEL_IRONLAKE_D2_HB),
901
902
ID(PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB),
902
903
ID(PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB),
903
904
ID(PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB),
+1
drivers/char/agp/intel-agp.h
+1
drivers/char/agp/intel-agp.h
···
212
212
#define PCI_DEVICE_ID_INTEL_G41_HB 0x2E30
213
213
#define PCI_DEVICE_ID_INTEL_G41_IG 0x2E32
214
214
#define PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB 0x0040
215
+
#define PCI_DEVICE_ID_INTEL_IRONLAKE_D2_HB 0x0069
215
216
#define PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG 0x0042
216
217
#define PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB 0x0044
217
218
#define PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB 0x0062
+2
-2
drivers/gpu/drm/exynos/exynos_drm_drv.c
+2
-2
drivers/gpu/drm/exynos/exynos_drm_drv.c
···
244
244
};
245
245
246
246
static struct drm_driver exynos_drm_driver = {
247
-
.driver_features = DRIVER_HAVE_IRQ | DRIVER_BUS_PLATFORM |
248
-
DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME,
247
+
.driver_features = DRIVER_HAVE_IRQ | DRIVER_MODESET |
248
+
DRIVER_GEM | DRIVER_PRIME,
249
249
.load = exynos_drm_load,
250
250
.unload = exynos_drm_unload,
251
251
.open = exynos_drm_open,
-7
drivers/gpu/drm/exynos/exynos_drm_encoder.c
-7
drivers/gpu/drm/exynos/exynos_drm_encoder.c
···
172
172
manager_ops->commit(manager->dev);
173
173
}
174
174
175
-
static struct drm_crtc *
176
-
exynos_drm_encoder_get_crtc(struct drm_encoder *encoder)
177
-
{
178
-
return encoder->crtc;
179
-
}
180
-
181
175
static struct drm_encoder_helper_funcs exynos_encoder_helper_funcs = {
182
176
.dpms = exynos_drm_encoder_dpms,
183
177
.mode_fixup = exynos_drm_encoder_mode_fixup,
184
178
.mode_set = exynos_drm_encoder_mode_set,
185
179
.prepare = exynos_drm_encoder_prepare,
186
180
.commit = exynos_drm_encoder_commit,
187
-
.get_crtc = exynos_drm_encoder_get_crtc,
188
181
};
189
182
190
183
static void exynos_drm_encoder_destroy(struct drm_encoder *encoder)
+14
-5
drivers/gpu/drm/exynos/exynos_drm_fb.c
+14
-5
drivers/gpu/drm/exynos/exynos_drm_fb.c
···
51
51
static void exynos_drm_fb_destroy(struct drm_framebuffer *fb)
52
52
{
53
53
struct exynos_drm_fb *exynos_fb = to_exynos_fb(fb);
54
+
unsigned int i;
54
55
55
56
DRM_DEBUG_KMS("%s\n", __FILE__);
56
57
57
58
drm_framebuffer_cleanup(fb);
59
+
60
+
for (i = 0; i < ARRAY_SIZE(exynos_fb->exynos_gem_obj); i++) {
61
+
struct drm_gem_object *obj;
62
+
63
+
if (exynos_fb->exynos_gem_obj[i] == NULL)
64
+
continue;
65
+
66
+
obj = &exynos_fb->exynos_gem_obj[i]->base;
67
+
drm_gem_object_unreference_unlocked(obj);
68
+
}
58
69
59
70
kfree(exynos_fb);
60
71
exynos_fb = NULL;
···
145
134
return ERR_PTR(-ENOENT);
146
135
}
147
136
148
-
drm_gem_object_unreference_unlocked(obj);
149
-
150
137
fb = exynos_drm_framebuffer_init(dev, mode_cmd, obj);
151
-
if (IS_ERR(fb))
138
+
if (IS_ERR(fb)) {
139
+
drm_gem_object_unreference_unlocked(obj);
152
140
return fb;
141
+
}
153
142
154
143
exynos_fb = to_exynos_fb(fb);
155
144
nr = exynos_drm_format_num_buffers(fb->pixel_format);
···
162
151
exynos_drm_fb_destroy(fb);
163
152
return ERR_PTR(-ENOENT);
164
153
}
165
-
166
-
drm_gem_object_unreference_unlocked(obj);
167
154
168
155
exynos_fb->exynos_gem_obj[i] = to_exynos_gem_obj(obj);
169
156
}
+2
-2
drivers/gpu/drm/exynos/exynos_drm_fb.h
+2
-2
drivers/gpu/drm/exynos/exynos_drm_fb.h
···
31
31
static inline int exynos_drm_format_num_buffers(uint32_t format)
32
32
{
33
33
switch (format) {
34
-
case DRM_FORMAT_NV12M:
34
+
case DRM_FORMAT_NV12:
35
35
case DRM_FORMAT_NV12MT:
36
36
return 2;
37
-
case DRM_FORMAT_YUV420M:
37
+
case DRM_FORMAT_YUV420:
38
38
return 3;
39
39
default:
40
40
return 1;
+3
-6
drivers/gpu/drm/exynos/exynos_drm_gem.c
+3
-6
drivers/gpu/drm/exynos/exynos_drm_gem.c
···
689
689
struct drm_device *dev, uint32_t handle,
690
690
uint64_t *offset)
691
691
{
692
-
struct exynos_drm_gem_obj *exynos_gem_obj;
693
692
struct drm_gem_object *obj;
694
693
int ret = 0;
695
694
···
709
710
goto unlock;
710
711
}
711
712
712
-
exynos_gem_obj = to_exynos_gem_obj(obj);
713
-
714
-
if (!exynos_gem_obj->base.map_list.map) {
715
-
ret = drm_gem_create_mmap_offset(&exynos_gem_obj->base);
713
+
if (!obj->map_list.map) {
714
+
ret = drm_gem_create_mmap_offset(obj);
716
715
if (ret)
717
716
goto out;
718
717
}
719
718
720
-
*offset = (u64)exynos_gem_obj->base.map_list.hash.key << PAGE_SHIFT;
719
+
*offset = (u64)obj->map_list.hash.key << PAGE_SHIFT;
721
720
DRM_DEBUG_KMS("offset = 0x%lx\n", (unsigned long)*offset);
722
721
723
722
out:
+7
-5
drivers/gpu/drm/exynos/exynos_mixer.c
+7
-5
drivers/gpu/drm/exynos/exynos_mixer.c
···
365
365
switch (win_data->pixel_format) {
366
366
case DRM_FORMAT_NV12MT:
367
367
tiled_mode = true;
368
-
case DRM_FORMAT_NV12M:
368
+
case DRM_FORMAT_NV12:
369
369
crcb_mode = false;
370
370
buf_num = 2;
371
371
break;
···
601
601
mixer_reg_write(res, MXR_BG_COLOR2, 0x008080);
602
602
603
603
/* setting graphical layers */
604
-
605
604
val = MXR_GRP_CFG_COLOR_KEY_DISABLE; /* no blank key */
606
605
val |= MXR_GRP_CFG_WIN_BLEND_EN;
606
+
val |= MXR_GRP_CFG_BLEND_PRE_MUL;
607
+
val |= MXR_GRP_CFG_PIXEL_BLEND_EN;
607
608
val |= MXR_GRP_CFG_ALPHA_VAL(0xff); /* non-transparent alpha */
608
609
609
610
/* the same configuration for both layers */
610
611
mixer_reg_write(res, MXR_GRAPHIC_CFG(0), val);
611
-
612
-
val |= MXR_GRP_CFG_BLEND_PRE_MUL;
613
-
val |= MXR_GRP_CFG_PIXEL_BLEND_EN;
614
612
mixer_reg_write(res, MXR_GRAPHIC_CFG(1), val);
613
+
614
+
/* setting video layers */
615
+
val = MXR_GRP_CFG_ALPHA_VAL(0);
616
+
mixer_reg_write(res, MXR_VIDEO_CFG, val);
615
617
616
618
/* configuration of Video Processor Registers */
617
619
vp_win_reset(ctx);
+9
-4
drivers/gpu/drm/i915/i915_drv.c
+9
-4
drivers/gpu/drm/i915/i915_drv.c
···
233
233
.has_blt_ring = 1,
234
234
.has_llc = 1,
235
235
.has_pch_split = 1,
236
+
.has_force_wake = 1,
236
237
};
237
238
238
239
static const struct intel_device_info intel_sandybridge_m_info = {
···
244
243
.has_blt_ring = 1,
245
244
.has_llc = 1,
246
245
.has_pch_split = 1,
246
+
.has_force_wake = 1,
247
247
};
248
248
249
249
static const struct intel_device_info intel_ivybridge_d_info = {
···
254
252
.has_blt_ring = 1,
255
253
.has_llc = 1,
256
254
.has_pch_split = 1,
255
+
.has_force_wake = 1,
257
256
};
258
257
259
258
static const struct intel_device_info intel_ivybridge_m_info = {
···
265
262
.has_blt_ring = 1,
266
263
.has_llc = 1,
267
264
.has_pch_split = 1,
265
+
.has_force_wake = 1,
268
266
};
269
267
270
268
static const struct intel_device_info intel_valleyview_m_info = {
···
293
289
.has_blt_ring = 1,
294
290
.has_llc = 1,
295
291
.has_pch_split = 1,
292
+
.has_force_wake = 1,
296
293
};
297
294
298
295
static const struct intel_device_info intel_haswell_m_info = {
···
303
298
.has_blt_ring = 1,
304
299
.has_llc = 1,
305
300
.has_pch_split = 1,
301
+
.has_force_wake = 1,
306
302
};
307
303
308
304
static const struct pci_device_id pciidlist[] = { /* aka */
···
1145
1139
1146
1140
/* We give fast paths for the really cool registers */
1147
1141
#define NEEDS_FORCE_WAKE(dev_priv, reg) \
1148
-
(((dev_priv)->info->gen >= 6) && \
1149
-
((reg) < 0x40000) && \
1150
-
((reg) != FORCEWAKE)) && \
1151
-
(!IS_VALLEYVIEW((dev_priv)->dev))
1142
+
((HAS_FORCE_WAKE((dev_priv)->dev)) && \
1143
+
((reg) < 0x40000) && \
1144
+
((reg) != FORCEWAKE))
1152
1145
1153
1146
#define __i915_read(x, y) \
1154
1147
u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
+3
drivers/gpu/drm/i915/i915_drv.h
+3
drivers/gpu/drm/i915/i915_drv.h
···
285
285
u8 is_ivybridge:1;
286
286
u8 is_valleyview:1;
287
287
u8 has_pch_split:1;
288
+
u8 has_force_wake:1;
288
289
u8 is_haswell:1;
289
290
u8 has_fbc:1;
290
291
u8 has_pipe_cxsr:1;
···
1101
1100
#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
1102
1101
#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1103
1102
#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1103
+
1104
+
#define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
1104
1105
1105
1106
#include "i915_trace.h"
1106
1107
+35
-3
drivers/gpu/drm/i915/i915_irq.c
+35
-3
drivers/gpu/drm/i915/i915_irq.c
···
510
510
return ret;
511
511
}
512
512
513
-
static void pch_irq_handler(struct drm_device *dev, u32 pch_iir)
513
+
static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
514
514
{
515
515
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
516
516
int pipe;
···
548
548
DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
549
549
if (pch_iir & SDE_TRANSA_FIFO_UNDER)
550
550
DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
551
+
}
552
+
553
+
static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
554
+
{
555
+
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
556
+
int pipe;
557
+
558
+
if (pch_iir & SDE_AUDIO_POWER_MASK_CPT)
559
+
DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
560
+
(pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
561
+
SDE_AUDIO_POWER_SHIFT_CPT);
562
+
563
+
if (pch_iir & SDE_AUX_MASK_CPT)
564
+
DRM_DEBUG_DRIVER("AUX channel interrupt\n");
565
+
566
+
if (pch_iir & SDE_GMBUS_CPT)
567
+
DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
568
+
569
+
if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
570
+
DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
571
+
572
+
if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
573
+
DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
574
+
575
+
if (pch_iir & SDE_FDI_MASK_CPT)
576
+
for_each_pipe(pipe)
577
+
DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
578
+
pipe_name(pipe),
579
+
I915_READ(FDI_RX_IIR(pipe)));
551
580
}
552
581
553
582
static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)
···
620
591
621
592
if (pch_iir & SDE_HOTPLUG_MASK_CPT)
622
593
queue_work(dev_priv->wq, &dev_priv->hotplug_work);
623
-
pch_irq_handler(dev, pch_iir);
594
+
cpt_irq_handler(dev, pch_iir);
624
595
625
596
/* clear PCH hotplug event before clear CPU irq */
626
597
I915_WRITE(SDEIIR, pch_iir);
···
713
684
if (de_iir & DE_PCH_EVENT) {
714
685
if (pch_iir & hotplug_mask)
715
686
queue_work(dev_priv->wq, &dev_priv->hotplug_work);
716
-
pch_irq_handler(dev, pch_iir);
687
+
if (HAS_PCH_CPT(dev))
688
+
cpt_irq_handler(dev, pch_iir);
689
+
else
690
+
ibx_irq_handler(dev, pch_iir);
717
691
}
718
692
719
693
if (de_iir & DE_PCU_EVENT) {
+40
-3
drivers/gpu/drm/i915/i915_reg.h
+40
-3
drivers/gpu/drm/i915/i915_reg.h
···
210
210
#define MI_DISPLAY_FLIP MI_INSTR(0x14, 2)
211
211
#define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1)
212
212
#define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
213
+
/* IVB has funny definitions for which plane to flip. */
214
+
#define MI_DISPLAY_FLIP_IVB_PLANE_A (0 << 19)
215
+
#define MI_DISPLAY_FLIP_IVB_PLANE_B (1 << 19)
216
+
#define MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19)
217
+
#define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19)
218
+
#define MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19)
219
+
#define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19)
220
+
213
221
#define MI_SET_CONTEXT MI_INSTR(0x18, 0)
214
222
#define MI_MM_SPACE_GTT (1<<8)
215
223
#define MI_MM_SPACE_PHYSICAL (0<<8)
···
3321
3313
3322
3314
/* PCH */
3323
3315
3324
-
/* south display engine interrupt */
3316
+
/* south display engine interrupt: IBX */
3325
3317
#define SDE_AUDIO_POWER_D (1 << 27)
3326
3318
#define SDE_AUDIO_POWER_C (1 << 26)
3327
3319
#define SDE_AUDIO_POWER_B (1 << 25)
···
3357
3349
#define SDE_TRANSA_CRC_ERR (1 << 1)
3358
3350
#define SDE_TRANSA_FIFO_UNDER (1 << 0)
3359
3351
#define SDE_TRANS_MASK (0x3f)
3360
-
/* CPT */
3361
-
#define SDE_CRT_HOTPLUG_CPT (1 << 19)
3352
+
3353
+
/* south display engine interrupt: CPT/PPT */
3354
+
#define SDE_AUDIO_POWER_D_CPT (1 << 31)
3355
+
#define SDE_AUDIO_POWER_C_CPT (1 << 30)
3356
+
#define SDE_AUDIO_POWER_B_CPT (1 << 29)
3357
+
#define SDE_AUDIO_POWER_SHIFT_CPT 29
3358
+
#define SDE_AUDIO_POWER_MASK_CPT (7 << 29)
3359
+
#define SDE_AUXD_CPT (1 << 27)
3360
+
#define SDE_AUXC_CPT (1 << 26)
3361
+
#define SDE_AUXB_CPT (1 << 25)
3362
+
#define SDE_AUX_MASK_CPT (7 << 25)
3362
3363
#define SDE_PORTD_HOTPLUG_CPT (1 << 23)
3363
3364
#define SDE_PORTC_HOTPLUG_CPT (1 << 22)
3364
3365
#define SDE_PORTB_HOTPLUG_CPT (1 << 21)
3366
+
#define SDE_CRT_HOTPLUG_CPT (1 << 19)
3365
3367
#define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \
3366
3368
SDE_PORTD_HOTPLUG_CPT | \
3367
3369
SDE_PORTC_HOTPLUG_CPT | \
3368
3370
SDE_PORTB_HOTPLUG_CPT)
3371
+
#define SDE_GMBUS_CPT (1 << 17)
3372
+
#define SDE_AUDIO_CP_REQ_C_CPT (1 << 10)
3373
+
#define SDE_AUDIO_CP_CHG_C_CPT (1 << 9)
3374
+
#define SDE_FDI_RXC_CPT (1 << 8)
3375
+
#define SDE_AUDIO_CP_REQ_B_CPT (1 << 6)
3376
+
#define SDE_AUDIO_CP_CHG_B_CPT (1 << 5)
3377
+
#define SDE_FDI_RXB_CPT (1 << 4)
3378
+
#define SDE_AUDIO_CP_REQ_A_CPT (1 << 2)
3379
+
#define SDE_AUDIO_CP_CHG_A_CPT (1 << 1)
3380
+
#define SDE_FDI_RXA_CPT (1 << 0)
3381
+
#define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \
3382
+
SDE_AUDIO_CP_REQ_B_CPT | \
3383
+
SDE_AUDIO_CP_REQ_A_CPT)
3384
+
#define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \
3385
+
SDE_AUDIO_CP_CHG_B_CPT | \
3386
+
SDE_AUDIO_CP_CHG_A_CPT)
3387
+
#define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \
3388
+
SDE_FDI_RXB_CPT | \
3389
+
SDE_FDI_RXA_CPT)
3369
3390
3370
3391
#define SDEISR 0xc4000
3371
3392
#define SDEIMR 0xc4004
+5
-3
drivers/gpu/drm/i915/intel_crt.c
+5
-3
drivers/gpu/drm/i915/intel_crt.c
···
453
453
struct intel_load_detect_pipe tmp;
454
454
455
455
if (I915_HAS_HOTPLUG(dev)) {
456
+
/* We can not rely on the HPD pin always being correctly wired
457
+
* up, for example many KVM do not pass it through, and so
458
+
* only trust an assertion that the monitor is connected.
459
+
*/
456
460
if (intel_crt_detect_hotplug(connector)) {
457
461
DRM_DEBUG_KMS("CRT detected via hotplug\n");
458
462
return connector_status_connected;
459
-
} else {
463
+
} else
460
464
DRM_DEBUG_KMS("CRT not detected via hotplug\n");
461
-
return connector_status_disconnected;
462
-
}
463
465
}
464
466
465
467
if (intel_crt_detect_ddc(connector))
+18
-1
drivers/gpu/drm/i915/intel_display.c
+18
-1
drivers/gpu/drm/i915/intel_display.c
···
6158
6158
struct drm_i915_private *dev_priv = dev->dev_private;
6159
6159
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6160
6160
struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6161
+
uint32_t plane_bit = 0;
6161
6162
int ret;
6162
6163
6163
6164
ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6164
6165
if (ret)
6165
6166
goto err;
6166
6167
6168
+
switch(intel_crtc->plane) {
6169
+
case PLANE_A:
6170
+
plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
6171
+
break;
6172
+
case PLANE_B:
6173
+
plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
6174
+
break;
6175
+
case PLANE_C:
6176
+
plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
6177
+
break;
6178
+
default:
6179
+
WARN_ONCE(1, "unknown plane in flip command\n");
6180
+
ret = -ENODEV;
6181
+
goto err;
6182
+
}
6183
+
6167
6184
ret = intel_ring_begin(ring, 4);
6168
6185
if (ret)
6169
6186
goto err_unpin;
6170
6187
6171
-
intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
6188
+
intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
6172
6189
intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
6173
6190
intel_ring_emit(ring, (obj->gtt_offset));
6174
6191
intel_ring_emit(ring, (MI_NOOP));
+18
-3
drivers/gpu/drm/i915/intel_ringbuffer.c
+18
-3
drivers/gpu/drm/i915/intel_ringbuffer.c
···
266
266
267
267
static int init_ring_common(struct intel_ring_buffer *ring)
268
268
{
269
-
drm_i915_private_t *dev_priv = ring->dev->dev_private;
269
+
struct drm_device *dev = ring->dev;
270
+
drm_i915_private_t *dev_priv = dev->dev_private;
270
271
struct drm_i915_gem_object *obj = ring->obj;
272
+
int ret = 0;
271
273
u32 head;
274
+
275
+
if (HAS_FORCE_WAKE(dev))
276
+
gen6_gt_force_wake_get(dev_priv);
272
277
273
278
/* Stop the ring if it's running. */
274
279
I915_WRITE_CTL(ring, 0);
···
322
317
I915_READ_HEAD(ring),
323
318
I915_READ_TAIL(ring),
324
319
I915_READ_START(ring));
325
-
return -EIO;
320
+
ret = -EIO;
321
+
goto out;
326
322
}
327
323
328
324
if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
···
332
326
ring->head = I915_READ_HEAD(ring);
333
327
ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
334
328
ring->space = ring_space(ring);
329
+
ring->last_retired_head = -1;
335
330
}
336
331
337
-
return 0;
332
+
out:
333
+
if (HAS_FORCE_WAKE(dev))
334
+
gen6_gt_force_wake_put(dev_priv);
335
+
336
+
return ret;
338
337
}
339
338
340
339
static int
···
997
986
ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
998
987
if (ret)
999
988
goto err_unref;
989
+
990
+
ret = i915_gem_object_set_to_gtt_domain(obj, true);
991
+
if (ret)
992
+
goto err_unpin;
1000
993
1001
994
ring->virtual_start = ioremap_wc(dev->agp->base + obj->gtt_offset,
1002
995
ring->size);
+3
-1
include/drm/exynos_drm.h
+3
-1
include/drm/exynos_drm.h
···
64
64
* A structure for mapping buffer.
65
65
*
66
66
* @handle: a handle to gem object created.
67
+
* @pad: just padding to be 64-bit aligned.
67
68
* @size: memory size to be mapped.
68
69
* @mapped: having user virtual address mmaped.
69
70
* - this variable would be filled by exynos gem module
···
73
72
*/
74
73
struct drm_exynos_gem_mmap {
75
74
unsigned int handle;
76
-
unsigned int size;
75
+
unsigned int pad;
76
+
uint64_t size;
77
77
uint64_t mapped;
78
78
};
79
79