Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux
Pull arm64 fixes from Catalin Marinas:
- Expand the speculative SSBS errata workaround to more CPUs
- Ensure jump label changes are visible to all CPUs with a
kick_all_cpus_sync() (and also enable jump label batching as part of
the fix)
- The shadow call stack sanitiser is currently incompatible with Rust,
make CONFIG_RUST conditional on !CONFIG_SHADOW_CALL_STACK
* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
arm64: jump_label: Ensure patched jump_labels are visible to all CPUs
rust: SHADOW_CALL_STACK is incompatible with Rust
arm64: errata: Expand speculative SSBS workaround (again)
arm64: cputype: Add Cortex-A725 definitions
arm64: cputype: Add Cortex-X1C definitions
+59
-9
+18
Documentation/arch/arm64/silicon-errata.rst
+18
Documentation/arch/arm64/silicon-errata.rst
···
122
122
+----------------+-----------------+-----------------+-----------------------------+
123
123
| ARM | Cortex-A76 | #1490853 | N/A |
124
124
+----------------+-----------------+-----------------+-----------------------------+
125
+
| ARM | Cortex-A76 | #3324349 | ARM64_ERRATUM_3194386 |
126
+
+----------------+-----------------+-----------------+-----------------------------+
125
127
| ARM | Cortex-A77 | #1491015 | N/A |
126
128
+----------------+-----------------+-----------------+-----------------------------+
127
129
| ARM | Cortex-A77 | #1508412 | ARM64_ERRATUM_1508412 |
130
+
+----------------+-----------------+-----------------+-----------------------------+
131
+
| ARM | Cortex-A77 | #3324348 | ARM64_ERRATUM_3194386 |
132
+
+----------------+-----------------+-----------------+-----------------------------+
133
+
| ARM | Cortex-A78 | #3324344 | ARM64_ERRATUM_3194386 |
134
+
+----------------+-----------------+-----------------+-----------------------------+
135
+
| ARM | Cortex-A78C | #3324346,3324347| ARM64_ERRATUM_3194386 |
128
136
+----------------+-----------------+-----------------+-----------------------------+
129
137
| ARM | Cortex-A710 | #2119858 | ARM64_ERRATUM_2119858 |
130
138
+----------------+-----------------+-----------------+-----------------------------+
···
146
138
+----------------+-----------------+-----------------+-----------------------------+
147
139
| ARM | Cortex-A720 | #3456091 | ARM64_ERRATUM_3194386 |
148
140
+----------------+-----------------+-----------------+-----------------------------+
141
+
| ARM | Cortex-A725 | #3456106 | ARM64_ERRATUM_3194386 |
142
+
+----------------+-----------------+-----------------+-----------------------------+
149
143
| ARM | Cortex-X1 | #1502854 | N/A |
144
+
+----------------+-----------------+-----------------+-----------------------------+
145
+
| ARM | Cortex-X1 | #3324344 | ARM64_ERRATUM_3194386 |
146
+
+----------------+-----------------+-----------------+-----------------------------+
147
+
| ARM | Cortex-X1C | #3324346 | ARM64_ERRATUM_3194386 |
150
148
+----------------+-----------------+-----------------+-----------------------------+
151
149
| ARM | Cortex-X2 | #2119858 | ARM64_ERRATUM_2119858 |
152
150
+----------------+-----------------+-----------------+-----------------------------+
···
174
160
+----------------+-----------------+-----------------+-----------------------------+
175
161
| ARM | Neoverse-N1 | #1542419 | ARM64_ERRATUM_1542419 |
176
162
+----------------+-----------------+-----------------+-----------------------------+
163
+
| ARM | Neoverse-N1 | #3324349 | ARM64_ERRATUM_3194386 |
164
+
+----------------+-----------------+-----------------+-----------------------------+
177
165
| ARM | Neoverse-N2 | #2139208 | ARM64_ERRATUM_2139208 |
178
166
+----------------+-----------------+-----------------+-----------------------------+
179
167
| ARM | Neoverse-N2 | #2067961 | ARM64_ERRATUM_2067961 |
···
185
169
| ARM | Neoverse-N2 | #3324339 | ARM64_ERRATUM_3194386 |
186
170
+----------------+-----------------+-----------------+-----------------------------+
187
171
| ARM | Neoverse-V1 | #1619801 | N/A |
172
+
+----------------+-----------------+-----------------+-----------------------------+
173
+
| ARM | Neoverse-V1 | #3324341 | ARM64_ERRATUM_3194386 |
188
174
+----------------+-----------------+-----------------+-----------------------------+
189
175
| ARM | Neoverse-V2 | #3324336 | ARM64_ERRATUM_3194386 |
190
176
+----------------+-----------------+-----------------+-----------------------------+
+16
-6
arch/arm64/Kconfig
+16
-6
arch/arm64/Kconfig
···
1069
1069
If unsure, say Y.
1070
1070
1071
1071
config ARM64_ERRATUM_3194386
1072
-
bool "Cortex-{A720,X4,X925}/Neoverse-V3: workaround for MSR SSBS not self-synchronizing"
1072
+
bool "Cortex-*/Neoverse-*: workaround for MSR SSBS not self-synchronizing"
1073
1073
default y
1074
1074
help
1075
1075
This option adds the workaround for the following errata:
1076
1076
1077
+
* ARM Cortex-A76 erratum 3324349
1078
+
* ARM Cortex-A77 erratum 3324348
1079
+
* ARM Cortex-A78 erratum 3324344
1080
+
* ARM Cortex-A78C erratum 3324346
1081
+
* ARM Cortex-A78C erratum 3324347
1077
1082
* ARM Cortex-A710 erratam 3324338
1078
1083
* ARM Cortex-A720 erratum 3456091
1084
+
* ARM Cortex-A725 erratum 3456106
1085
+
* ARM Cortex-X1 erratum 3324344
1086
+
* ARM Cortex-X1C erratum 3324346
1079
1087
* ARM Cortex-X2 erratum 3324338
1080
1088
* ARM Cortex-X3 erratum 3324335
1081
1089
* ARM Cortex-X4 erratum 3194386
1082
1090
* ARM Cortex-X925 erratum 3324334
1091
+
* ARM Neoverse-N1 erratum 3324349
1083
1092
* ARM Neoverse N2 erratum 3324339
1093
+
* ARM Neoverse-V1 erratum 3324341
1084
1094
* ARM Neoverse V2 erratum 3324336
1085
1095
* ARM Neoverse-V3 erratum 3312417
1086
1096
···
1098
1088
subsequent speculative instructions, which may permit unexepected
1099
1089
speculative store bypassing.
1100
1090
1101
-
Work around this problem by placing a speculation barrier after
1102
-
kernel changes to SSBS. The presence of the SSBS special-purpose
1103
-
register is hidden from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such
1104
-
that userspace will use the PR_SPEC_STORE_BYPASS prctl to change
1105
-
SSBS.
1091
+
Work around this problem by placing a Speculation Barrier (SB) or
1092
+
Instruction Synchronization Barrier (ISB) after kernel changes to
1093
+
SSBS. The presence of the SSBS special-purpose register is hidden
1094
+
from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such that userspace
1095
+
will use the PR_SPEC_STORE_BYPASS prctl to change SSBS.
1106
1096
1107
1097
If unsure, say Y.
1108
1098
+4
arch/arm64/include/asm/cputype.h
+4
arch/arm64/include/asm/cputype.h
···
86
86
#define ARM_CPU_PART_CORTEX_X2 0xD48
87
87
#define ARM_CPU_PART_NEOVERSE_N2 0xD49
88
88
#define ARM_CPU_PART_CORTEX_A78C 0xD4B
89
+
#define ARM_CPU_PART_CORTEX_X1C 0xD4C
89
90
#define ARM_CPU_PART_CORTEX_X3 0xD4E
90
91
#define ARM_CPU_PART_NEOVERSE_V2 0xD4F
91
92
#define ARM_CPU_PART_CORTEX_A720 0xD81
92
93
#define ARM_CPU_PART_CORTEX_X4 0xD82
93
94
#define ARM_CPU_PART_NEOVERSE_V3 0xD84
94
95
#define ARM_CPU_PART_CORTEX_X925 0xD85
96
+
#define ARM_CPU_PART_CORTEX_A725 0xD87
95
97
96
98
#define APM_CPU_PART_XGENE 0x000
97
99
#define APM_CPU_VAR_POTENZA 0x00
···
167
165
#define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2)
168
166
#define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2)
169
167
#define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C)
168
+
#define MIDR_CORTEX_X1C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1C)
170
169
#define MIDR_CORTEX_X3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X3)
171
170
#define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2)
172
171
#define MIDR_CORTEX_A720 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720)
173
172
#define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4)
174
173
#define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3)
175
174
#define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925)
175
+
#define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725)
176
176
#define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
177
177
#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
178
178
#define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)
+1
arch/arm64/include/asm/jump_label.h
+1
arch/arm64/include/asm/jump_label.h
+10
-1
arch/arm64/kernel/cpu_errata.c
+10
-1
arch/arm64/kernel/cpu_errata.c
···
434
434
435
435
#ifdef CONFIG_ARM64_ERRATUM_3194386
436
436
static const struct midr_range erratum_spec_ssbs_list[] = {
437
+
MIDR_ALL_VERSIONS(MIDR_CORTEX_A76),
438
+
MIDR_ALL_VERSIONS(MIDR_CORTEX_A77),
439
+
MIDR_ALL_VERSIONS(MIDR_CORTEX_A78),
440
+
MIDR_ALL_VERSIONS(MIDR_CORTEX_A78C),
437
441
MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
438
442
MIDR_ALL_VERSIONS(MIDR_CORTEX_A720),
443
+
MIDR_ALL_VERSIONS(MIDR_CORTEX_A725),
444
+
MIDR_ALL_VERSIONS(MIDR_CORTEX_X1),
445
+
MIDR_ALL_VERSIONS(MIDR_CORTEX_X1C),
439
446
MIDR_ALL_VERSIONS(MIDR_CORTEX_X2),
440
447
MIDR_ALL_VERSIONS(MIDR_CORTEX_X3),
441
448
MIDR_ALL_VERSIONS(MIDR_CORTEX_X4),
442
449
MIDR_ALL_VERSIONS(MIDR_CORTEX_X925),
450
+
MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1),
443
451
MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
444
-
MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3),
452
+
MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1),
445
453
MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V2),
454
+
MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3),
446
455
{}
447
456
};
448
457
#endif
+9
-2
arch/arm64/kernel/jump_label.c
+9
-2
arch/arm64/kernel/jump_label.c
···
7
7
*/
8
8
#include <linux/kernel.h>
9
9
#include <linux/jump_label.h>
10
+
#include <linux/smp.h>
10
11
#include <asm/insn.h>
11
12
#include <asm/patching.h>
12
13
13
-
void arch_jump_label_transform(struct jump_entry *entry,
14
-
enum jump_label_type type)
14
+
bool arch_jump_label_transform_queue(struct jump_entry *entry,
15
+
enum jump_label_type type)
15
16
{
16
17
void *addr = (void *)jump_entry_code(entry);
17
18
u32 insn;
···
26
25
}
27
26
28
27
aarch64_insn_patch_text_nosync(addr, insn);
28
+
return true;
29
+
}
30
+
31
+
void arch_jump_label_transform_apply(void)
32
+
{
33
+
kick_all_cpus_sync();
29
34
}