Merge tag 'ntb-4.20' of git://github.com/jonmason/ntb

+4 -26

drivers/net/ntb_netdev.c

··· 71 71 static unsigned int tx_stop = 5; 72 72 73 73 struct ntb_netdev { 74 - struct list_head list; 75 74 struct pci_dev *pdev; 76 75 struct net_device *ndev; 77 76 struct ntb_transport_qp *qp; ··· 79 80 80 81 #define NTB_TX_TIMEOUT_MS 1000 81 82 #define NTB_RXQ_SIZE 100 82 - 83 - static LIST_HEAD(dev_list); 84 83 85 84 static void ntb_netdev_event_handler(void *data, int link_is_up) 86 85 { ··· 233 236 struct net_device *ndev = dev->ndev; 234 237 235 238 if (ntb_transport_tx_free_entry(dev->qp) < tx_stop) { 236 - mod_timer(&dev->tx_timer, jiffies + msecs_to_jiffies(tx_time)); 239 + mod_timer(&dev->tx_timer, jiffies + usecs_to_jiffies(tx_time)); 237 240 } else { 238 241 /* Make sure anybody stopping the queue after this sees the new 239 242 * value of ntb_transport_tx_free_entry() ··· 449 452 if (rc) 450 453 goto err1; 451 454 452 - list_add(&dev->list, &dev_list); 455 + dev_set_drvdata(client_dev, ndev); 453 456 dev_info(&pdev->dev, "%s created\n", ndev->name); 454 457 return 0; 455 458 ··· 462 465 463 466 static void ntb_netdev_remove(struct device *client_dev) 464 467 { 465 - struct ntb_dev *ntb; 466 - struct net_device *ndev; 467 - struct pci_dev *pdev; 468 - struct ntb_netdev *dev; 469 - bool found = false; 470 - 471 - ntb = dev_ntb(client_dev->parent); 472 - pdev = ntb->pdev; 473 - 474 - list_for_each_entry(dev, &dev_list, list) { 475 - if (dev->pdev == pdev) { 476 - found = true; 477 - break; 478 - } 479 - } 480 - if (!found) 481 - return; 482 - 483 - list_del(&dev->list); 484 - 485 - ndev = dev->ndev; 468 + struct net_device *ndev = dev_get_drvdata(client_dev); 469 + struct ntb_netdev *dev = netdev_priv(ndev); 486 470 487 471 unregister_netdev(ndev); 488 472 ntb_transport_free_queue(dev->qp);

+2 -3

drivers/ntb/hw/idt/Kconfig

··· 1 1 config NTB_IDT 2 2 tristate "IDT PCIe-switch Non-Transparent Bridge support" 3 3 depends on PCI 4 + select HWMON 4 5 help 5 6 This driver supports NTB of cappable IDT PCIe-switches. 6 7 ··· 24 23 BAR settings of peer NT-functions, the BAR setups can't be done over 25 24 kernel PCI fixups. That's why the alternative pre-initialization 26 25 techniques like BIOS using SMBus interface or EEPROM should be 27 - utilized. Additionally if one needs to have temperature sensor 28 - information printed to system log, the corresponding registers must 29 - be initialized within BIOS/EEPROM as well. 26 + utilized. 30 27 31 28 If unsure, say N. 32 29

+279 -56

drivers/ntb/hw/idt/ntb_hw_idt.c

··· 4 4 * 5 5 * GPL LICENSE SUMMARY 6 6 * 7 - * Copyright (C) 2016 T-Platforms All Rights Reserved. 7 + * Copyright (C) 2016-2018 T-Platforms JSC All Rights Reserved. 8 8 * 9 9 * This program is free software; you can redistribute it and/or modify it 10 10 * under the terms and conditions of the GNU General Public License, ··· 49 49 #include <linux/init.h> 50 50 #include <linux/interrupt.h> 51 51 #include <linux/spinlock.h> 52 + #include <linux/mutex.h> 52 53 #include <linux/pci.h> 53 54 #include <linux/aer.h> 54 55 #include <linux/slab.h> 55 56 #include <linux/list.h> 56 57 #include <linux/debugfs.h> 58 + #include <linux/hwmon.h> 59 + #include <linux/hwmon-sysfs.h> 57 60 #include <linux/ntb.h> 58 61 59 62 #include "ntb_hw_idt.h" ··· 1108 1105 } 1109 1106 1110 1107 /* Allocate memory for memory window descriptors */ 1111 - ret_mws = devm_kcalloc(&ndev->ntb.pdev->dev, *mw_cnt, 1112 - sizeof(*ret_mws), GFP_KERNEL); 1113 - if (IS_ERR_OR_NULL(ret_mws)) 1108 + ret_mws = devm_kcalloc(&ndev->ntb.pdev->dev, *mw_cnt, sizeof(*ret_mws), 1109 + GFP_KERNEL); 1110 + if (!ret_mws) 1114 1111 return ERR_PTR(-ENOMEM); 1115 1112 1116 1113 /* Copy the info of detected memory windows */ ··· 1323 1320 idt_nt_write(ndev, bar->ltbase, (u32)addr); 1324 1321 idt_nt_write(ndev, bar->utbase, (u32)(addr >> 32)); 1325 1322 /* Set the custom BAR aperture limit */ 1326 - limit = pci_resource_start(ntb->pdev, mw_cfg->bar) + size; 1323 + limit = pci_bus_address(ntb->pdev, mw_cfg->bar) + size; 1327 1324 idt_nt_write(ndev, bar->limit, (u32)limit); 1328 1325 if (IS_FLD_SET(BARSETUP_TYPE, data, 64)) 1329 1326 idt_nt_write(ndev, (bar + 1)->limit, (limit >> 32)); ··· 1824 1821 * 7. Temperature sensor operations 1825 1822 * 1826 1823 * IDT PCIe-switch has an embedded temperature sensor, which can be used to 1827 - * warn a user-space of possible chip overheating. Since workload temperature 1828 - * can be different on different platforms, temperature thresholds as well as 1829 - * general sensor settings must be setup in the framework of BIOS/EEPROM 1830 - * initializations. It includes the actual sensor enabling as well. 1824 + * check current chip core temperature. Since a workload environment can be 1825 + * different on different platforms, an offset and ADC/filter settings can be 1826 + * specified. Although the offset configuration is only exposed to the sysfs 1827 + * hwmon interface at the moment. The rest of the settings can be adjusted 1828 + * for instance by the BIOS/EEPROM firmware. 1831 1829 *============================================================================= 1832 1830 */ 1833 1831 1834 1832 /* 1835 - * idt_read_temp() - read temperature from chip sensor 1836 - * @ntb: NTB device context. 1837 - * @val: OUT - integer value of temperature 1838 - * @frac: OUT - fraction 1833 + * idt_get_deg() - convert millidegree Celsius value to just degree 1834 + * @mdegC: IN - millidegree Celsius value 1835 + * 1836 + * Return: Degree corresponding to the passed millidegree value 1839 1837 */ 1840 - static void idt_read_temp(struct idt_ntb_dev *ndev, unsigned char *val, 1841 - unsigned char *frac) 1838 + static inline s8 idt_get_deg(long mdegC) 1842 1839 { 1843 - u32 data; 1844 - 1845 - /* Read the data from TEMP field of the TMPSTS register */ 1846 - data = idt_sw_read(ndev, IDT_SW_TMPSTS); 1847 - data = GET_FIELD(TMPSTS_TEMP, data); 1848 - /* TEMP field has one fractional bit and seven integer bits */ 1849 - *val = data >> 1; 1850 - *frac = ((data & 0x1) ? 5 : 0); 1840 + return mdegC / 1000; 1851 1841 } 1852 1842 1853 1843 /* 1854 - * idt_temp_isr() - temperature sensor alarm events ISR 1855 - * @ndev: IDT NTB hardware driver descriptor 1856 - * @ntint_sts: NT-function interrupt status 1844 + * idt_get_frac() - retrieve 0/0.5 fraction of the millidegree Celsius value 1845 + * @mdegC: IN - millidegree Celsius value 1857 1846 * 1858 - * It handles events of temperature crossing alarm thresholds. Since reading 1859 - * of TMPALARM register clears it up, the function doesn't analyze the 1860 - * read value, instead the current temperature value just warningly printed to 1861 - * log. 1862 - * The method is called from PCIe ISR bottom-half routine. 1847 + * Return: 0/0.5 degree fraction of the passed millidegree value 1863 1848 */ 1864 - static void idt_temp_isr(struct idt_ntb_dev *ndev, u32 ntint_sts) 1849 + static inline u8 idt_get_deg_frac(long mdegC) 1865 1850 { 1866 - unsigned char val, frac; 1851 + return (mdegC % 1000) >= 500 ? 5 : 0; 1852 + } 1867 1853 1868 - /* Read the current temperature value */ 1869 - idt_read_temp(ndev, &val, &frac); 1854 + /* 1855 + * idt_get_temp_fmt() - convert millidegree Celsius value to 0:7:1 format 1856 + * @mdegC: IN - millidegree Celsius value 1857 + * 1858 + * Return: 0:7:1 format acceptable by the IDT temperature sensor 1859 + */ 1860 + static inline u8 idt_temp_get_fmt(long mdegC) 1861 + { 1862 + return (idt_get_deg(mdegC) << 1) | (idt_get_deg_frac(mdegC) ? 1 : 0); 1863 + } 1870 1864 1871 - /* Read the temperature alarm to clean the alarm status out */ 1872 - /*(void)idt_sw_read(ndev, IDT_SW_TMPALARM);*/ 1865 + /* 1866 + * idt_get_temp_sval() - convert temp sample to signed millidegree Celsius 1867 + * @data: IN - shifted to LSB 8-bits temperature sample 1868 + * 1869 + * Return: signed millidegree Celsius 1870 + */ 1871 + static inline long idt_get_temp_sval(u32 data) 1872 + { 1873 + return ((s8)data / 2) * 1000 + (data & 0x1 ? 500 : 0); 1874 + } 1873 1875 1874 - /* Clean the corresponding interrupt bit */ 1875 - idt_nt_write(ndev, IDT_NT_NTINTSTS, IDT_NTINTSTS_TMPSENSOR); 1876 + /* 1877 + * idt_get_temp_sval() - convert temp sample to unsigned millidegree Celsius 1878 + * @data: IN - shifted to LSB 8-bits temperature sample 1879 + * 1880 + * Return: unsigned millidegree Celsius 1881 + */ 1882 + static inline long idt_get_temp_uval(u32 data) 1883 + { 1884 + return (data / 2) * 1000 + (data & 0x1 ? 500 : 0); 1885 + } 1876 1886 1877 - dev_dbg(&ndev->ntb.pdev->dev, 1878 - "Temp sensor IRQ detected %#08x", ntint_sts); 1887 + /* 1888 + * idt_read_temp() - read temperature from chip sensor 1889 + * @ntb: NTB device context. 1890 + * @type: IN - type of the temperature value to read 1891 + * @val: OUT - integer value of temperature in millidegree Celsius 1892 + */ 1893 + static void idt_read_temp(struct idt_ntb_dev *ndev, 1894 + const enum idt_temp_val type, long *val) 1895 + { 1896 + u32 data; 1879 1897 1880 - /* Print temperature value to log */ 1881 - dev_warn(&ndev->ntb.pdev->dev, "Temperature %hhu.%hhu", val, frac); 1898 + /* Alter the temperature field in accordance with the passed type */ 1899 + switch (type) { 1900 + case IDT_TEMP_CUR: 1901 + data = GET_FIELD(TMPSTS_TEMP, 1902 + idt_sw_read(ndev, IDT_SW_TMPSTS)); 1903 + break; 1904 + case IDT_TEMP_LOW: 1905 + data = GET_FIELD(TMPSTS_LTEMP, 1906 + idt_sw_read(ndev, IDT_SW_TMPSTS)); 1907 + break; 1908 + case IDT_TEMP_HIGH: 1909 + data = GET_FIELD(TMPSTS_HTEMP, 1910 + idt_sw_read(ndev, IDT_SW_TMPSTS)); 1911 + break; 1912 + case IDT_TEMP_OFFSET: 1913 + /* This is the only field with signed 0:7:1 format */ 1914 + data = GET_FIELD(TMPADJ_OFFSET, 1915 + idt_sw_read(ndev, IDT_SW_TMPADJ)); 1916 + *val = idt_get_temp_sval(data); 1917 + return; 1918 + default: 1919 + data = GET_FIELD(TMPSTS_TEMP, 1920 + idt_sw_read(ndev, IDT_SW_TMPSTS)); 1921 + break; 1922 + } 1923 + 1924 + /* The rest of the fields accept unsigned 0:7:1 format */ 1925 + *val = idt_get_temp_uval(data); 1926 + } 1927 + 1928 + /* 1929 + * idt_write_temp() - write temperature to the chip sensor register 1930 + * @ntb: NTB device context. 1931 + * @type: IN - type of the temperature value to change 1932 + * @val: IN - integer value of temperature in millidegree Celsius 1933 + */ 1934 + static void idt_write_temp(struct idt_ntb_dev *ndev, 1935 + const enum idt_temp_val type, const long val) 1936 + { 1937 + unsigned int reg; 1938 + u32 data; 1939 + u8 fmt; 1940 + 1941 + /* Retrieve the properly formatted temperature value */ 1942 + fmt = idt_temp_get_fmt(val); 1943 + 1944 + mutex_lock(&ndev->hwmon_mtx); 1945 + switch (type) { 1946 + case IDT_TEMP_LOW: 1947 + reg = IDT_SW_TMPALARM; 1948 + data = SET_FIELD(TMPALARM_LTEMP, idt_sw_read(ndev, reg), fmt) & 1949 + ~IDT_TMPALARM_IRQ_MASK; 1950 + break; 1951 + case IDT_TEMP_HIGH: 1952 + reg = IDT_SW_TMPALARM; 1953 + data = SET_FIELD(TMPALARM_HTEMP, idt_sw_read(ndev, reg), fmt) & 1954 + ~IDT_TMPALARM_IRQ_MASK; 1955 + break; 1956 + case IDT_TEMP_OFFSET: 1957 + reg = IDT_SW_TMPADJ; 1958 + data = SET_FIELD(TMPADJ_OFFSET, idt_sw_read(ndev, reg), fmt); 1959 + break; 1960 + default: 1961 + goto inval_spin_unlock; 1962 + } 1963 + 1964 + idt_sw_write(ndev, reg, data); 1965 + 1966 + inval_spin_unlock: 1967 + mutex_unlock(&ndev->hwmon_mtx); 1968 + } 1969 + 1970 + /* 1971 + * idt_sysfs_show_temp() - printout corresponding temperature value 1972 + * @dev: Pointer to the NTB device structure 1973 + * @da: Sensor device attribute structure 1974 + * @buf: Buffer to print temperature out 1975 + * 1976 + * Return: Number of written symbols or negative error 1977 + */ 1978 + static ssize_t idt_sysfs_show_temp(struct device *dev, 1979 + struct device_attribute *da, char *buf) 1980 + { 1981 + struct sensor_device_attribute *attr = to_sensor_dev_attr(da); 1982 + struct idt_ntb_dev *ndev = dev_get_drvdata(dev); 1983 + enum idt_temp_val type = attr->index; 1984 + long mdeg; 1985 + 1986 + idt_read_temp(ndev, type, &mdeg); 1987 + return sprintf(buf, "%ld\n", mdeg); 1988 + } 1989 + 1990 + /* 1991 + * idt_sysfs_set_temp() - set corresponding temperature value 1992 + * @dev: Pointer to the NTB device structure 1993 + * @da: Sensor device attribute structure 1994 + * @buf: Buffer to print temperature out 1995 + * @count: Size of the passed buffer 1996 + * 1997 + * Return: Number of written symbols or negative error 1998 + */ 1999 + static ssize_t idt_sysfs_set_temp(struct device *dev, 2000 + struct device_attribute *da, const char *buf, 2001 + size_t count) 2002 + { 2003 + struct sensor_device_attribute *attr = to_sensor_dev_attr(da); 2004 + struct idt_ntb_dev *ndev = dev_get_drvdata(dev); 2005 + enum idt_temp_val type = attr->index; 2006 + long mdeg; 2007 + int ret; 2008 + 2009 + ret = kstrtol(buf, 10, &mdeg); 2010 + if (ret) 2011 + return ret; 2012 + 2013 + /* Clamp the passed value in accordance with the type */ 2014 + if (type == IDT_TEMP_OFFSET) 2015 + mdeg = clamp_val(mdeg, IDT_TEMP_MIN_OFFSET, 2016 + IDT_TEMP_MAX_OFFSET); 2017 + else 2018 + mdeg = clamp_val(mdeg, IDT_TEMP_MIN_MDEG, IDT_TEMP_MAX_MDEG); 2019 + 2020 + idt_write_temp(ndev, type, mdeg); 2021 + 2022 + return count; 2023 + } 2024 + 2025 + /* 2026 + * idt_sysfs_reset_hist() - reset temperature history 2027 + * @dev: Pointer to the NTB device structure 2028 + * @da: Sensor device attribute structure 2029 + * @buf: Buffer to print temperature out 2030 + * @count: Size of the passed buffer 2031 + * 2032 + * Return: Number of written symbols or negative error 2033 + */ 2034 + static ssize_t idt_sysfs_reset_hist(struct device *dev, 2035 + struct device_attribute *da, 2036 + const char *buf, size_t count) 2037 + { 2038 + struct idt_ntb_dev *ndev = dev_get_drvdata(dev); 2039 + 2040 + /* Just set the maximal value to the lowest temperature field and 2041 + * minimal value to the highest temperature field 2042 + */ 2043 + idt_write_temp(ndev, IDT_TEMP_LOW, IDT_TEMP_MAX_MDEG); 2044 + idt_write_temp(ndev, IDT_TEMP_HIGH, IDT_TEMP_MIN_MDEG); 2045 + 2046 + return count; 2047 + } 2048 + 2049 + /* 2050 + * Hwmon IDT sysfs attributes 2051 + */ 2052 + static SENSOR_DEVICE_ATTR(temp1_input, 0444, idt_sysfs_show_temp, NULL, 2053 + IDT_TEMP_CUR); 2054 + static SENSOR_DEVICE_ATTR(temp1_lowest, 0444, idt_sysfs_show_temp, NULL, 2055 + IDT_TEMP_LOW); 2056 + static SENSOR_DEVICE_ATTR(temp1_highest, 0444, idt_sysfs_show_temp, NULL, 2057 + IDT_TEMP_HIGH); 2058 + static SENSOR_DEVICE_ATTR(temp1_offset, 0644, idt_sysfs_show_temp, 2059 + idt_sysfs_set_temp, IDT_TEMP_OFFSET); 2060 + static DEVICE_ATTR(temp1_reset_history, 0200, NULL, idt_sysfs_reset_hist); 2061 + 2062 + /* 2063 + * Hwmon IDT sysfs attributes group 2064 + */ 2065 + static struct attribute *idt_temp_attrs[] = { 2066 + &sensor_dev_attr_temp1_input.dev_attr.attr, 2067 + &sensor_dev_attr_temp1_lowest.dev_attr.attr, 2068 + &sensor_dev_attr_temp1_highest.dev_attr.attr, 2069 + &sensor_dev_attr_temp1_offset.dev_attr.attr, 2070 + &dev_attr_temp1_reset_history.attr, 2071 + NULL 2072 + }; 2073 + ATTRIBUTE_GROUPS(idt_temp); 2074 + 2075 + /* 2076 + * idt_init_temp() - initialize temperature sensor interface 2077 + * @ndev: IDT NTB hardware driver descriptor 2078 + * 2079 + * Simple sensor initializarion method is responsible for device switching 2080 + * on and resource management based hwmon interface registration. Note, that 2081 + * since the device is shared we won't disable it on remove, but leave it 2082 + * working until the system is powered off. 2083 + */ 2084 + static void idt_init_temp(struct idt_ntb_dev *ndev) 2085 + { 2086 + struct device *hwmon; 2087 + 2088 + /* Enable sensor if it hasn't been already */ 2089 + idt_sw_write(ndev, IDT_SW_TMPCTL, 0x0); 2090 + 2091 + /* Initialize hwmon interface fields */ 2092 + mutex_init(&ndev->hwmon_mtx); 2093 + 2094 + hwmon = devm_hwmon_device_register_with_groups(&ndev->ntb.pdev->dev, 2095 + ndev->swcfg->name, ndev, idt_temp_groups); 2096 + if (IS_ERR(hwmon)) { 2097 + dev_err(&ndev->ntb.pdev->dev, "Couldn't create hwmon device"); 2098 + return; 2099 + } 2100 + 2101 + dev_dbg(&ndev->ntb.pdev->dev, "Temperature HWmon interface registered"); 1882 2102 } 1883 2103 1884 2104 /*============================================================================= ··· 2157 1931 goto err_free_vectors; 2158 1932 } 2159 1933 2160 - /* Unmask Message/Doorbell/SE/Temperature interrupts */ 1934 + /* Unmask Message/Doorbell/SE interrupts */ 2161 1935 ntint_mask = idt_nt_read(ndev, IDT_NT_NTINTMSK) & ~IDT_NTINTMSK_ALL; 2162 1936 idt_nt_write(ndev, IDT_NT_NTINTMSK, ntint_mask); 2163 1937 ··· 2171 1945 2172 1946 return ret; 2173 1947 } 2174 - 2175 1948 2176 1949 /* 2177 1950 * idt_deinit_ist() - deinitialize PCIe interrupt handler ··· 2229 2004 /* Handle switch event interrupts */ 2230 2005 if (ntint_sts & IDT_NTINTSTS_SEVENT) { 2231 2006 idt_se_isr(ndev, ntint_sts); 2232 - handled = true; 2233 - } 2234 - 2235 - /* Handle temperature sensor interrupt */ 2236 - if (ntint_sts & IDT_NTINTSTS_TMPSENSOR) { 2237 - idt_temp_isr(ndev, ntint_sts); 2238 2007 handled = true; 2239 2008 } 2240 2009 ··· 2342 2123 size_t count, loff_t *offp) 2343 2124 { 2344 2125 struct idt_ntb_dev *ndev = filp->private_data; 2345 - unsigned char temp, frac, idx, pidx, cnt; 2126 + unsigned char idx, pidx, cnt; 2127 + unsigned long irqflags, mdeg; 2346 2128 ssize_t ret = 0, off = 0; 2347 - unsigned long irqflags; 2348 2129 enum ntb_speed speed; 2349 2130 enum ntb_width width; 2350 2131 char *strbuf; ··· 2493 2274 off += scnprintf(strbuf + off, size - off, "\n"); 2494 2275 2495 2276 /* Current temperature */ 2496 - idt_read_temp(ndev, &temp, &frac); 2277 + idt_read_temp(ndev, IDT_TEMP_CUR, &mdeg); 2497 2278 off += scnprintf(strbuf + off, size - off, 2498 - "Switch temperature\t\t- %hhu.%hhuC\n", temp, frac); 2279 + "Switch temperature\t\t- %hhd.%hhuC\n", 2280 + idt_get_deg(mdeg), idt_get_deg_frac(mdeg)); 2499 2281 2500 2282 /* Copy the buffer to the User Space */ 2501 2283 ret = simple_read_from_buffer(ubuf, count, offp, strbuf, off); ··· 2610 2390 2611 2391 /* Allocate memory for the IDT PCIe-device descriptor */ 2612 2392 ndev = devm_kzalloc(&pdev->dev, sizeof(*ndev), GFP_KERNEL); 2613 - if (IS_ERR_OR_NULL(ndev)) { 2393 + if (!ndev) { 2614 2394 dev_err(&pdev->dev, "Memory allocation failed for descriptor"); 2615 2395 return ERR_PTR(-ENOMEM); 2616 2396 } ··· 2790 2570 2791 2571 /* Initialize Messaging subsystem */ 2792 2572 idt_init_msg(ndev); 2573 + 2574 + /* Initialize hwmon interface */ 2575 + idt_init_temp(ndev); 2793 2576 2794 2577 /* Initialize IDT interrupts handler */ 2795 2578 ret = idt_init_isr(ndev);

+82 -5

drivers/ntb/hw/idt/ntb_hw_idt.h

··· 4 4 * 5 5 * GPL LICENSE SUMMARY 6 6 * 7 - * Copyright (C) 2016 T-Platforms All Rights Reserved. 7 + * Copyright (C) 2016-2018 T-Platforms JSC All Rights Reserved. 8 8 * 9 9 * This program is free software; you can redistribute it and/or modify it 10 10 * under the terms and conditions of the GNU General Public License, ··· 47 47 #include <linux/pci_ids.h> 48 48 #include <linux/interrupt.h> 49 49 #include <linux/spinlock.h> 50 + #include <linux/mutex.h> 50 51 #include <linux/ntb.h> 51 - 52 52 53 53 /* 54 54 * Macro is used to create the struct pci_device_id that matches ··· 688 688 * @IDT_NTINTMSK_DBELL: Doorbell interrupt mask bit 689 689 * @IDT_NTINTMSK_SEVENT: Switch Event interrupt mask bit 690 690 * @IDT_NTINTMSK_TMPSENSOR: Temperature sensor interrupt mask bit 691 - * @IDT_NTINTMSK_ALL: All the useful interrupts mask 691 + * @IDT_NTINTMSK_ALL: NTB-related interrupts mask 692 692 */ 693 693 #define IDT_NTINTMSK_MSG 0x00000001U 694 694 #define IDT_NTINTMSK_DBELL 0x00000002U 695 695 #define IDT_NTINTMSK_SEVENT 0x00000008U 696 696 #define IDT_NTINTMSK_TMPSENSOR 0x00000080U 697 697 #define IDT_NTINTMSK_ALL \ 698 - (IDT_NTINTMSK_MSG | IDT_NTINTMSK_DBELL | \ 699 - IDT_NTINTMSK_SEVENT | IDT_NTINTMSK_TMPSENSOR) 698 + (IDT_NTINTMSK_MSG | IDT_NTINTMSK_DBELL | IDT_NTINTMSK_SEVENT) 700 699 701 700 /* 702 701 * NTGSIGNAL register fields related constants ··· 885 886 #define IDT_SWPxMSGCTL_PART_FLD 4 886 887 887 888 /* 889 + * TMPCTL register fields related constants 890 + * @IDT_TMPCTL_LTH_MASK: Low temperature threshold field mask 891 + * @IDT_TMPCTL_LTH_FLD: Low temperature threshold field offset 892 + * @IDT_TMPCTL_MTH_MASK: Middle temperature threshold field mask 893 + * @IDT_TMPCTL_MTH_FLD: Middle temperature threshold field offset 894 + * @IDT_TMPCTL_HTH_MASK: High temperature threshold field mask 895 + * @IDT_TMPCTL_HTH_FLD: High temperature threshold field offset 896 + * @IDT_TMPCTL_PDOWN: Temperature sensor power down 897 + */ 898 + #define IDT_TMPCTL_LTH_MASK 0x000000FFU 899 + #define IDT_TMPCTL_LTH_FLD 0 900 + #define IDT_TMPCTL_MTH_MASK 0x0000FF00U 901 + #define IDT_TMPCTL_MTH_FLD 8 902 + #define IDT_TMPCTL_HTH_MASK 0x00FF0000U 903 + #define IDT_TMPCTL_HTH_FLD 16 904 + #define IDT_TMPCTL_PDOWN 0x80000000U 905 + 906 + /* 888 907 * TMPSTS register fields related constants 889 908 * @IDT_TMPSTS_TEMP_MASK: Current temperature field mask 890 909 * @IDT_TMPSTS_TEMP_FLD: Current temperature field offset 910 + * @IDT_TMPSTS_LTEMP_MASK: Lowest temperature field mask 911 + * @IDT_TMPSTS_LTEMP_FLD: Lowest temperature field offset 912 + * @IDT_TMPSTS_HTEMP_MASK: Highest temperature field mask 913 + * @IDT_TMPSTS_HTEMP_FLD: Highest temperature field offset 891 914 */ 892 915 #define IDT_TMPSTS_TEMP_MASK 0x000000FFU 893 916 #define IDT_TMPSTS_TEMP_FLD 0 917 + #define IDT_TMPSTS_LTEMP_MASK 0x0000FF00U 918 + #define IDT_TMPSTS_LTEMP_FLD 8 919 + #define IDT_TMPSTS_HTEMP_MASK 0x00FF0000U 920 + #define IDT_TMPSTS_HTEMP_FLD 16 921 + 922 + /* 923 + * TMPALARM register fields related constants 924 + * @IDT_TMPALARM_LTEMP_MASK: Lowest temperature field mask 925 + * @IDT_TMPALARM_LTEMP_FLD: Lowest temperature field offset 926 + * @IDT_TMPALARM_HTEMP_MASK: Highest temperature field mask 927 + * @IDT_TMPALARM_HTEMP_FLD: Highest temperature field offset 928 + * @IDT_TMPALARM_IRQ_MASK: Alarm IRQ status mask 929 + */ 930 + #define IDT_TMPALARM_LTEMP_MASK 0x0000FF00U 931 + #define IDT_TMPALARM_LTEMP_FLD 8 932 + #define IDT_TMPALARM_HTEMP_MASK 0x00FF0000U 933 + #define IDT_TMPALARM_HTEMP_FLD 16 934 + #define IDT_TMPALARM_IRQ_MASK 0x3F000000U 935 + 936 + /* 937 + * TMPADJ register fields related constants 938 + * @IDT_TMPADJ_OFFSET_MASK: Temperature value offset field mask 939 + * @IDT_TMPADJ_OFFSET_FLD: Temperature value offset field offset 940 + */ 941 + #define IDT_TMPADJ_OFFSET_MASK 0x000000FFU 942 + #define IDT_TMPADJ_OFFSET_FLD 0 894 943 895 944 /* 896 945 * Helper macro to get/set the corresponding field value ··· 996 949 #define IDT_PCIE_REGSIZE 4 997 950 #define IDT_TRANS_ALIGN 4 998 951 #define IDT_DIR_SIZE_ALIGN 1 952 + 953 + /* 954 + * IDT PCIe-switch temperature sensor value limits 955 + * @IDT_TEMP_MIN_MDEG: Minimal integer value of temperature 956 + * @IDT_TEMP_MAX_MDEG: Maximal integer value of temperature 957 + * @IDT_TEMP_MIN_OFFSET:Minimal integer value of temperature offset 958 + * @IDT_TEMP_MAX_OFFSET:Maximal integer value of temperature offset 959 + */ 960 + #define IDT_TEMP_MIN_MDEG 0 961 + #define IDT_TEMP_MAX_MDEG 127500 962 + #define IDT_TEMP_MIN_OFFSET -64000 963 + #define IDT_TEMP_MAX_OFFSET 63500 964 + 965 + /* 966 + * Temperature sensor values enumeration 967 + * @IDT_TEMP_CUR: Current temperature 968 + * @IDT_TEMP_LOW: Lowest historical temperature 969 + * @IDT_TEMP_HIGH: Highest historical temperature 970 + * @IDT_TEMP_OFFSET: Current temperature offset 971 + */ 972 + enum idt_temp_val { 973 + IDT_TEMP_CUR, 974 + IDT_TEMP_LOW, 975 + IDT_TEMP_HIGH, 976 + IDT_TEMP_OFFSET 977 + }; 999 978 1000 979 /* 1001 980 * IDT Memory Windows type. Depending on the device settings, IDT supports ··· 1117 1044 * @msg_mask_lock: Message mask register lock 1118 1045 * @gasa_lock: GASA registers access lock 1119 1046 * 1047 + * @hwmon_mtx: Temperature sensor interface update mutex 1048 + * 1120 1049 * @dbgfs_info: DebugFS info node 1121 1050 */ 1122 1051 struct idt_ntb_dev { ··· 1145 1070 spinlock_t db_mask_lock; 1146 1071 spinlock_t msg_mask_lock; 1147 1072 spinlock_t gasa_lock; 1073 + 1074 + struct mutex hwmon_mtx; 1148 1075 1149 1076 struct dentry *dbgfs_info; 1150 1077 };

+1 -1

drivers/ntb/hw/intel/ntb_hw_gen1.c

··· 265 265 return 0; 266 266 } 267 267 268 - static inline int ndev_vec_mask(struct intel_ntb_dev *ndev, int db_vector) 268 + static inline u64 ndev_vec_mask(struct intel_ntb_dev *ndev, int db_vector) 269 269 { 270 270 u64 shift, mask; 271 271

+65 -23

drivers/ntb/ntb_transport.c

··· 194 194 void __iomem *vbase; 195 195 size_t xlat_size; 196 196 size_t buff_size; 197 + size_t alloc_size; 198 + void *alloc_addr; 197 199 void *virt_addr; 198 200 dma_addr_t dma_addr; 199 201 }; ··· 674 672 return; 675 673 676 674 ntb_mw_clear_trans(nt->ndev, PIDX, num_mw); 677 - dma_free_coherent(&pdev->dev, mw->buff_size, 678 - mw->virt_addr, mw->dma_addr); 675 + dma_free_coherent(&pdev->dev, mw->alloc_size, 676 + mw->alloc_addr, mw->dma_addr); 679 677 mw->xlat_size = 0; 680 678 mw->buff_size = 0; 679 + mw->alloc_size = 0; 680 + mw->alloc_addr = NULL; 681 681 mw->virt_addr = NULL; 682 + } 683 + 684 + static int ntb_alloc_mw_buffer(struct ntb_transport_mw *mw, 685 + struct device *dma_dev, size_t align) 686 + { 687 + dma_addr_t dma_addr; 688 + void *alloc_addr, *virt_addr; 689 + int rc; 690 + 691 + alloc_addr = dma_alloc_coherent(dma_dev, mw->alloc_size, 692 + &dma_addr, GFP_KERNEL); 693 + if (!alloc_addr) { 694 + dev_err(dma_dev, "Unable to alloc MW buff of size %zu\n", 695 + mw->alloc_size); 696 + return -ENOMEM; 697 + } 698 + virt_addr = alloc_addr; 699 + 700 + /* 701 + * we must ensure that the memory address allocated is BAR size 702 + * aligned in order for the XLAT register to take the value. This 703 + * is a requirement of the hardware. It is recommended to setup CMA 704 + * for BAR sizes equal or greater than 4MB. 705 + */ 706 + if (!IS_ALIGNED(dma_addr, align)) { 707 + if (mw->alloc_size > mw->buff_size) { 708 + virt_addr = PTR_ALIGN(alloc_addr, align); 709 + dma_addr = ALIGN(dma_addr, align); 710 + } else { 711 + rc = -ENOMEM; 712 + goto err; 713 + } 714 + } 715 + 716 + mw->alloc_addr = alloc_addr; 717 + mw->virt_addr = virt_addr; 718 + mw->dma_addr = dma_addr; 719 + 720 + return 0; 721 + 722 + err: 723 + dma_free_coherent(dma_dev, mw->alloc_size, alloc_addr, dma_addr); 724 + 725 + return rc; 682 726 } 683 727 684 728 static int ntb_set_mw(struct ntb_transport_ctx *nt, int num_mw, ··· 758 710 /* Alloc memory for receiving data. Must be aligned */ 759 711 mw->xlat_size = xlat_size; 760 712 mw->buff_size = buff_size; 713 + mw->alloc_size = buff_size; 761 714 762 - mw->virt_addr = dma_alloc_coherent(&pdev->dev, buff_size, 763 - &mw->dma_addr, GFP_KERNEL); 764 - if (!mw->virt_addr) { 765 - mw->xlat_size = 0; 766 - mw->buff_size = 0; 767 - dev_err(&pdev->dev, "Unable to alloc MW buff of size %zu\n", 768 - buff_size); 769 - return -ENOMEM; 770 - } 771 - 772 - /* 773 - * we must ensure that the memory address allocated is BAR size 774 - * aligned in order for the XLAT register to take the value. This 775 - * is a requirement of the hardware. It is recommended to setup CMA 776 - * for BAR sizes equal or greater than 4MB. 777 - */ 778 - if (!IS_ALIGNED(mw->dma_addr, xlat_align)) { 779 - dev_err(&pdev->dev, "DMA memory %pad is not aligned\n", 780 - &mw->dma_addr); 781 - ntb_free_mw(nt, num_mw); 782 - return -ENOMEM; 715 + rc = ntb_alloc_mw_buffer(mw, &pdev->dev, xlat_align); 716 + if (rc) { 717 + mw->alloc_size *= 2; 718 + rc = ntb_alloc_mw_buffer(mw, &pdev->dev, xlat_align); 719 + if (rc) { 720 + dev_err(&pdev->dev, 721 + "Unable to alloc aligned MW buff\n"); 722 + mw->xlat_size = 0; 723 + mw->buff_size = 0; 724 + mw->alloc_size = 0; 725 + return rc; 726 + } 783 727 } 784 728 785 729 /* Notify HW the memory location of the receive buffer */ ··· 1318 1278 case DMA_TRANS_READ_FAILED: 1319 1279 case DMA_TRANS_WRITE_FAILED: 1320 1280 entry->errors++; 1281 + /* fall through */ 1321 1282 case DMA_TRANS_ABORTED: 1322 1283 { 1323 1284 struct ntb_transport_qp *qp = entry->qp; ··· 1574 1533 case DMA_TRANS_READ_FAILED: 1575 1534 case DMA_TRANS_WRITE_FAILED: 1576 1535 entry->errors++; 1536 + /* fall through */ 1577 1537 case DMA_TRANS_ABORTED: 1578 1538 { 1579 1539 void __iomem *offset =

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