Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'timers-v5.7' of https://git.linaro.org/people/daniel.lezcano/linux into timers/core
Pull clockevent/clocksource updates from Daniel Lezcano:
- Avoid creating dead devices by flagging the driver with OF_POPULATED
in order to prevent the platform to create another device (Saravana Kannan)
- Remove unused includes from imx family drivers (Anson Huang)
- timer-dm-ti rework to prepare for pwm and suspend support (Lokesh Vutla)
- Fix the rate for the global clock on the pit64b (Claudiu Beznea)
- Fix timer-cs5535 by requesting an irq with non-NULL dev_id (Afzal Mohammed)
- Replace setup_irq() by request_irq() (Afzal Mohammed)
- Add support for the TCU of X1000 (Zhou Yanjie)
- Drop the bogus omap_dm_timer_of_set_source() function (Suman Anna)
- Do not update the counter when updating the period in order to
prevent a disruption when the pwm is used (Lokesh Vutla)
- Improve owl_timer_init() failure messages (Matheus Castello)
- Add driver for the Ingenic JZ47xx OST (Maarten ter Huurne)
- Pass the interrupt and the shutdown callbacks in the init function
for ast2600 support (Joel Stanley)
- Add the ast2600 compatible string for the fttmr010 (Joel Stanley)
+470
-329
+1
Documentation/devicetree/bindings/timer/faraday,fttmr010.txt
+1
Documentation/devicetree/bindings/timer/faraday,fttmr010.txt
+1
Documentation/devicetree/bindings/timer/ingenic,tcu.txt
+1
Documentation/devicetree/bindings/timer/ingenic,tcu.txt
···
10
10
* ingenic,jz4740-tcu
11
11
* ingenic,jz4725b-tcu
12
12
* ingenic,jz4770-tcu
13
+
* ingenic,x1000-tcu
13
14
followed by "simple-mfd".
14
15
- reg: Should be the offset/length value corresponding to the TCU registers
15
16
- clocks: List of phandle & clock specifiers for clocks external to the TCU.
+8
drivers/clocksource/Kconfig
+8
drivers/clocksource/Kconfig
···
697
697
help
698
698
Support for the timer/counter unit of the Ingenic JZ SoCs.
699
699
700
+
config INGENIC_OST
701
+
bool "Clocksource for Ingenic OS Timer"
702
+
depends on MIPS || COMPILE_TEST
703
+
depends on COMMON_CLK
704
+
select MFD_SYSCON
705
+
help
706
+
Support for the Operating System Timer of the Ingenic JZ SoCs.
707
+
700
708
config MICROCHIP_PIT64B
701
709
bool "Microchip PIT64B support"
702
710
depends on OF || COMPILE_TEST
+1
drivers/clocksource/Makefile
+1
drivers/clocksource/Makefile
···
80
80
obj-$(CONFIG_H8300_TMR8) += h8300_timer8.o
81
81
obj-$(CONFIG_H8300_TMR16) += h8300_timer16.o
82
82
obj-$(CONFIG_H8300_TPU) += h8300_tpu.o
83
+
obj-$(CONFIG_INGENIC_OST) += ingenic-ost.o
83
84
obj-$(CONFIG_INGENIC_TIMER) += ingenic-timer.o
84
85
obj-$(CONFIG_CLKSRC_ST_LPC) += clksrc_st_lpc.o
85
86
obj-$(CONFIG_X86_NUMACHIP) += numachip.o
+2
-6
drivers/clocksource/bcm2835_timer.c
+2
-6
drivers/clocksource/bcm2835_timer.c
···
31
31
void __iomem *compare;
32
32
int match_mask;
33
33
struct clock_event_device evt;
34
-
struct irqaction act;
35
34
};
36
35
37
36
static void __iomem *system_clock __read_mostly;
···
112
113
timer->evt.features = CLOCK_EVT_FEAT_ONESHOT;
113
114
timer->evt.set_next_event = bcm2835_time_set_next_event;
114
115
timer->evt.cpumask = cpumask_of(0);
115
-
timer->act.name = node->name;
116
-
timer->act.flags = IRQF_TIMER | IRQF_SHARED;
117
-
timer->act.dev_id = timer;
118
-
timer->act.handler = bcm2835_time_interrupt;
119
116
120
-
ret = setup_irq(irq, &timer->act);
117
+
ret = request_irq(irq, bcm2835_time_interrupt, IRQF_TIMER | IRQF_SHARED,
118
+
node->name, timer);
121
119
if (ret) {
122
120
pr_err("Can't set up timer IRQ\n");
123
121
goto err_timer_free;
+3
-7
drivers/clocksource/bcm_kona_timer.c
+3
-7
drivers/clocksource/bcm_kona_timer.c
···
160
160
return IRQ_HANDLED;
161
161
}
162
162
163
-
static struct irqaction kona_timer_irq = {
164
-
.name = "Kona Timer Tick",
165
-
.flags = IRQF_TIMER,
166
-
.handler = kona_timer_interrupt,
167
-
};
168
-
169
163
static int __init kona_timer_init(struct device_node *node)
170
164
{
171
165
u32 freq;
···
186
192
kona_timer_disable_and_clear(timers.tmr_regs);
187
193
188
194
kona_timer_clockevents_init();
189
-
setup_irq(timers.tmr_irq, &kona_timer_irq);
195
+
if (request_irq(timers.tmr_irq, kona_timer_interrupt, IRQF_TIMER,
196
+
"Kona Timer Tick", NULL))
197
+
pr_err("%s: request_irq() failed\n", "Kona Timer Tick");
190
198
kona_timer_set_next_event((arch_timer_rate / HZ), NULL);
191
199
192
200
return 0;
+3
-8
drivers/clocksource/dw_apb_timer.c
+3
-8
drivers/clocksource/dw_apb_timer.c
···
270
270
dw_ced->ced.rating = rating;
271
271
dw_ced->ced.name = name;
272
272
273
-
dw_ced->irqaction.name = dw_ced->ced.name;
274
-
dw_ced->irqaction.handler = dw_apb_clockevent_irq;
275
-
dw_ced->irqaction.dev_id = &dw_ced->ced;
276
-
dw_ced->irqaction.irq = irq;
277
-
dw_ced->irqaction.flags = IRQF_TIMER | IRQF_IRQPOLL |
278
-
IRQF_NOBALANCING;
279
-
280
273
dw_ced->eoi = apbt_eoi;
281
-
err = setup_irq(irq, &dw_ced->irqaction);
274
+
err = request_irq(irq, dw_apb_clockevent_irq,
275
+
IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING,
276
+
dw_ced->ced.name, &dw_ced->ced);
282
277
if (err) {
283
278
pr_err("failed to request timer irq\n");
284
279
kfree(dw_ced);
+4
-8
drivers/clocksource/exynos_mct.c
+4
-8
drivers/clocksource/exynos_mct.c
···
329
329
return IRQ_HANDLED;
330
330
}
331
331
332
-
static struct irqaction mct_comp_event_irq = {
333
-
.name = "mct_comp_irq",
334
-
.flags = IRQF_TIMER | IRQF_IRQPOLL,
335
-
.handler = exynos4_mct_comp_isr,
336
-
.dev_id = &mct_comp_device,
337
-
};
338
-
339
332
static int exynos4_clockevent_init(void)
340
333
{
341
334
mct_comp_device.cpumask = cpumask_of(0);
342
335
clockevents_config_and_register(&mct_comp_device, clk_rate,
343
336
0xf, 0xffffffff);
344
-
setup_irq(mct_irqs[MCT_G0_IRQ], &mct_comp_event_irq);
337
+
if (request_irq(mct_irqs[MCT_G0_IRQ], exynos4_mct_comp_isr,
338
+
IRQF_TIMER | IRQF_IRQPOLL, "mct_comp_irq",
339
+
&mct_comp_device))
340
+
pr_err("%s: request_irq() failed\n", "mct_comp_irq");
345
341
346
342
return 0;
347
343
}
+189
drivers/clocksource/ingenic-ost.c
+189
drivers/clocksource/ingenic-ost.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* JZ47xx SoCs TCU Operating System Timer driver
4
+
*
5
+
* Copyright (C) 2016 Maarten ter Huurne <maarten@treewalker.org>
6
+
* Copyright (C) 2020 Paul Cercueil <paul@crapouillou.net>
7
+
*/
8
+
9
+
#include <linux/clk.h>
10
+
#include <linux/clocksource.h>
11
+
#include <linux/mfd/ingenic-tcu.h>
12
+
#include <linux/mfd/syscon.h>
13
+
#include <linux/of.h>
14
+
#include <linux/platform_device.h>
15
+
#include <linux/pm.h>
16
+
#include <linux/regmap.h>
17
+
#include <linux/sched_clock.h>
18
+
19
+
#define TCU_OST_TCSR_MASK 0xffc0
20
+
#define TCU_OST_TCSR_CNT_MD BIT(15)
21
+
22
+
#define TCU_OST_CHANNEL 15
23
+
24
+
/*
25
+
* The TCU_REG_OST_CNT{L,R} from <linux/mfd/ingenic-tcu.h> are only for the
26
+
* regmap; these are for use with the __iomem pointer.
27
+
*/
28
+
#define OST_REG_CNTL 0x4
29
+
#define OST_REG_CNTH 0x8
30
+
31
+
struct ingenic_ost_soc_info {
32
+
bool is64bit;
33
+
};
34
+
35
+
struct ingenic_ost {
36
+
void __iomem *regs;
37
+
struct clk *clk;
38
+
39
+
struct clocksource cs;
40
+
};
41
+
42
+
static struct ingenic_ost *ingenic_ost;
43
+
44
+
static u64 notrace ingenic_ost_read_cntl(void)
45
+
{
46
+
/* Read using __iomem pointer instead of regmap to avoid locking */
47
+
return readl(ingenic_ost->regs + OST_REG_CNTL);
48
+
}
49
+
50
+
static u64 notrace ingenic_ost_read_cnth(void)
51
+
{
52
+
/* Read using __iomem pointer instead of regmap to avoid locking */
53
+
return readl(ingenic_ost->regs + OST_REG_CNTH);
54
+
}
55
+
56
+
static u64 notrace ingenic_ost_clocksource_readl(struct clocksource *cs)
57
+
{
58
+
return ingenic_ost_read_cntl();
59
+
}
60
+
61
+
static u64 notrace ingenic_ost_clocksource_readh(struct clocksource *cs)
62
+
{
63
+
return ingenic_ost_read_cnth();
64
+
}
65
+
66
+
static int __init ingenic_ost_probe(struct platform_device *pdev)
67
+
{
68
+
const struct ingenic_ost_soc_info *soc_info;
69
+
struct device *dev = &pdev->dev;
70
+
struct ingenic_ost *ost;
71
+
struct clocksource *cs;
72
+
struct regmap *map;
73
+
unsigned long rate;
74
+
int err;
75
+
76
+
soc_info = device_get_match_data(dev);
77
+
if (!soc_info)
78
+
return -EINVAL;
79
+
80
+
ost = devm_kzalloc(dev, sizeof(*ost), GFP_KERNEL);
81
+
if (!ost)
82
+
return -ENOMEM;
83
+
84
+
ingenic_ost = ost;
85
+
86
+
ost->regs = devm_platform_ioremap_resource(pdev, 0);
87
+
if (IS_ERR(ost->regs))
88
+
return PTR_ERR(ost->regs);
89
+
90
+
map = device_node_to_regmap(dev->parent->of_node);
91
+
if (!map) {
92
+
dev_err(dev, "regmap not found");
93
+
return -EINVAL;
94
+
}
95
+
96
+
ost->clk = devm_clk_get(dev, "ost");
97
+
if (IS_ERR(ost->clk))
98
+
return PTR_ERR(ost->clk);
99
+
100
+
err = clk_prepare_enable(ost->clk);
101
+
if (err)
102
+
return err;
103
+
104
+
/* Clear counter high/low registers */
105
+
if (soc_info->is64bit)
106
+
regmap_write(map, TCU_REG_OST_CNTL, 0);
107
+
regmap_write(map, TCU_REG_OST_CNTH, 0);
108
+
109
+
/* Don't reset counter at compare value. */
110
+
regmap_update_bits(map, TCU_REG_OST_TCSR,
111
+
TCU_OST_TCSR_MASK, TCU_OST_TCSR_CNT_MD);
112
+
113
+
rate = clk_get_rate(ost->clk);
114
+
115
+
/* Enable OST TCU channel */
116
+
regmap_write(map, TCU_REG_TESR, BIT(TCU_OST_CHANNEL));
117
+
118
+
cs = &ost->cs;
119
+
cs->name = "ingenic-ost";
120
+
cs->rating = 320;
121
+
cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
122
+
cs->mask = CLOCKSOURCE_MASK(32);
123
+
124
+
if (soc_info->is64bit)
125
+
cs->read = ingenic_ost_clocksource_readl;
126
+
else
127
+
cs->read = ingenic_ost_clocksource_readh;
128
+
129
+
err = clocksource_register_hz(cs, rate);
130
+
if (err) {
131
+
dev_err(dev, "clocksource registration failed");
132
+
clk_disable_unprepare(ost->clk);
133
+
return err;
134
+
}
135
+
136
+
if (soc_info->is64bit)
137
+
sched_clock_register(ingenic_ost_read_cntl, 32, rate);
138
+
else
139
+
sched_clock_register(ingenic_ost_read_cnth, 32, rate);
140
+
141
+
return 0;
142
+
}
143
+
144
+
static int __maybe_unused ingenic_ost_suspend(struct device *dev)
145
+
{
146
+
struct ingenic_ost *ost = dev_get_drvdata(dev);
147
+
148
+
clk_disable(ost->clk);
149
+
150
+
return 0;
151
+
}
152
+
153
+
static int __maybe_unused ingenic_ost_resume(struct device *dev)
154
+
{
155
+
struct ingenic_ost *ost = dev_get_drvdata(dev);
156
+
157
+
return clk_enable(ost->clk);
158
+
}
159
+
160
+
static const struct dev_pm_ops __maybe_unused ingenic_ost_pm_ops = {
161
+
/* _noirq: We want the OST clock to be gated last / ungated first */
162
+
.suspend_noirq = ingenic_ost_suspend,
163
+
.resume_noirq = ingenic_ost_resume,
164
+
};
165
+
166
+
static const struct ingenic_ost_soc_info jz4725b_ost_soc_info = {
167
+
.is64bit = false,
168
+
};
169
+
170
+
static const struct ingenic_ost_soc_info jz4770_ost_soc_info = {
171
+
.is64bit = true,
172
+
};
173
+
174
+
static const struct of_device_id ingenic_ost_of_match[] = {
175
+
{ .compatible = "ingenic,jz4725b-ost", .data = &jz4725b_ost_soc_info, },
176
+
{ .compatible = "ingenic,jz4770-ost", .data = &jz4770_ost_soc_info, },
177
+
{ }
178
+
};
179
+
180
+
static struct platform_driver ingenic_ost_driver = {
181
+
.driver = {
182
+
.name = "ingenic-ost",
183
+
#ifdef CONFIG_PM_SUSPEND
184
+
.pm = &ingenic_ost_pm_ops,
185
+
#endif
186
+
.of_match_table = ingenic_ost_of_match,
187
+
},
188
+
};
189
+
builtin_platform_driver_probe(ingenic_ost_driver, ingenic_ost_probe);
+2
-1
drivers/clocksource/ingenic-timer.c
+2
-1
drivers/clocksource/ingenic-timer.c
···
230
230
{ .compatible = "ingenic,jz4740-tcu", .data = &jz4740_soc_info, },
231
231
{ .compatible = "ingenic,jz4725b-tcu", .data = &jz4725b_soc_info, },
232
232
{ .compatible = "ingenic,jz4770-tcu", .data = &jz4740_soc_info, },
233
+
{ .compatible = "ingenic,x1000-tcu", .data = &jz4740_soc_info, },
233
234
{ /* sentinel */ }
234
235
};
235
236
···
303
302
TIMER_OF_DECLARE(jz4740_tcu_intc, "ingenic,jz4740-tcu", ingenic_tcu_init);
304
303
TIMER_OF_DECLARE(jz4725b_tcu_intc, "ingenic,jz4725b-tcu", ingenic_tcu_init);
305
304
TIMER_OF_DECLARE(jz4770_tcu_intc, "ingenic,jz4770-tcu", ingenic_tcu_init);
306
-
305
+
TIMER_OF_DECLARE(x1000_tcu_intc, "ingenic,x1000-tcu", ingenic_tcu_init);
307
306
308
307
static int __init ingenic_tcu_probe(struct platform_device *pdev)
309
308
{
+2
-8
drivers/clocksource/mxs_timer.c
+2
-8
drivers/clocksource/mxs_timer.c
···
117
117
return IRQ_HANDLED;
118
118
}
119
119
120
-
static struct irqaction mxs_timer_irq = {
121
-
.name = "MXS Timer Tick",
122
-
.dev_id = &mxs_clockevent_device,
123
-
.flags = IRQF_TIMER | IRQF_IRQPOLL,
124
-
.handler = mxs_timer_interrupt,
125
-
};
126
-
127
120
static void mxs_irq_clear(char *state)
128
121
{
129
122
/* Disable interrupt in timer module */
···
270
277
if (irq <= 0)
271
278
return -EINVAL;
272
279
273
-
return setup_irq(irq, &mxs_timer_irq);
280
+
return request_irq(irq, mxs_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL,
281
+
"MXS Timer Tick", &mxs_clockevent_device);
274
282
}
275
283
TIMER_OF_DECLARE(mxs, "fsl,timrot", mxs_timer_init);
+3
-8
drivers/clocksource/nomadik-mtu.c
+3
-8
drivers/clocksource/nomadik-mtu.c
···
181
181
return IRQ_HANDLED;
182
182
}
183
183
184
-
static struct irqaction nmdk_timer_irq = {
185
-
.name = "Nomadik Timer Tick",
186
-
.flags = IRQF_TIMER,
187
-
.handler = nmdk_timer_interrupt,
188
-
.dev_id = &nmdk_clkevt,
189
-
};
190
-
191
184
static int __init nmdk_timer_init(void __iomem *base, int irq,
192
185
struct clk *pclk, struct clk *clk)
193
186
{
···
225
232
sched_clock_register(nomadik_read_sched_clock, 32, rate);
226
233
227
234
/* Timer 1 is used for events, register irq and clockevents */
228
-
setup_irq(irq, &nmdk_timer_irq);
235
+
if (request_irq(irq, nmdk_timer_interrupt, IRQF_TIMER,
236
+
"Nomadik Timer Tick", &nmdk_clkevt))
237
+
pr_err("%s: request_irq() failed\n", "Nomadik Timer Tick");
229
238
nmdk_clkevt.cpumask = cpumask_of(0);
230
239
nmdk_clkevt.irq = irq;
231
240
clockevents_config_and_register(&nmdk_clkevt, rate, 2, 0xffffffffU);
+4
-8
drivers/clocksource/samsung_pwm_timer.c
+4
-8
drivers/clocksource/samsung_pwm_timer.c
···
256
256
return IRQ_HANDLED;
257
257
}
258
258
259
-
static struct irqaction samsung_clock_event_irq = {
260
-
.name = "samsung_time_irq",
261
-
.flags = IRQF_TIMER | IRQF_IRQPOLL,
262
-
.handler = samsung_clock_event_isr,
263
-
.dev_id = &time_event_device,
264
-
};
265
-
266
259
static void __init samsung_clockevent_init(void)
267
260
{
268
261
unsigned long pclk;
···
275
282
clock_rate, 1, pwm.tcnt_max);
276
283
277
284
irq_number = pwm.irq[pwm.event_id];
278
-
setup_irq(irq_number, &samsung_clock_event_irq);
285
+
if (request_irq(irq_number, samsung_clock_event_isr,
286
+
IRQF_TIMER | IRQF_IRQPOLL, "samsung_time_irq",
287
+
&time_event_device))
288
+
pr_err("%s: request_irq() failed\n", "samsung_time_irq");
279
289
280
290
if (pwm.variant.has_tint_cstat) {
281
291
u32 mask = (1 << pwm.event_id);
+22
-26
drivers/clocksource/timer-atlas7.c
+22
-26
drivers/clocksource/timer-atlas7.c
···
159
159
.resume = sirfsoc_clocksource_resume,
160
160
};
161
161
162
-
static struct irqaction sirfsoc_timer_irq = {
163
-
.name = "sirfsoc_timer0",
164
-
.flags = IRQF_TIMER | IRQF_NOBALANCING,
165
-
.handler = sirfsoc_timer_interrupt,
166
-
};
167
-
168
-
static struct irqaction sirfsoc_timer1_irq = {
169
-
.name = "sirfsoc_timer1",
170
-
.flags = IRQF_TIMER | IRQF_NOBALANCING,
171
-
.handler = sirfsoc_timer_interrupt,
172
-
};
162
+
static unsigned int sirfsoc_timer_irq, sirfsoc_timer1_irq;
173
163
174
164
static int sirfsoc_local_timer_starting_cpu(unsigned int cpu)
175
165
{
176
166
struct clock_event_device *ce = per_cpu_ptr(sirfsoc_clockevent, cpu);
177
-
struct irqaction *action;
167
+
unsigned int irq;
168
+
const char *name;
178
169
179
-
if (cpu == 0)
180
-
action = &sirfsoc_timer_irq;
181
-
else
182
-
action = &sirfsoc_timer1_irq;
170
+
if (cpu == 0) {
171
+
irq = sirfsoc_timer_irq;
172
+
name = "sirfsoc_timer0";
173
+
} else {
174
+
irq = sirfsoc_timer1_irq;
175
+
name = "sirfsoc_timer1";
176
+
}
183
177
184
-
ce->irq = action->irq;
178
+
ce->irq = irq;
185
179
ce->name = "local_timer";
186
180
ce->features = CLOCK_EVT_FEAT_ONESHOT;
187
181
ce->rating = 200;
···
190
196
ce->min_delta_ticks = 2;
191
197
ce->cpumask = cpumask_of(cpu);
192
198
193
-
action->dev_id = ce;
194
-
BUG_ON(setup_irq(ce->irq, action));
195
-
irq_force_affinity(action->irq, cpumask_of(cpu));
199
+
BUG_ON(request_irq(ce->irq, sirfsoc_timer_interrupt,
200
+
IRQF_TIMER | IRQF_NOBALANCING, name, ce));
201
+
irq_force_affinity(ce->irq, cpumask_of(cpu));
196
202
197
203
clockevents_register_device(ce);
198
204
return 0;
···
200
206
201
207
static int sirfsoc_local_timer_dying_cpu(unsigned int cpu)
202
208
{
209
+
struct clock_event_device *ce = per_cpu_ptr(sirfsoc_clockevent, cpu);
210
+
203
211
sirfsoc_timer_count_disable(1);
204
212
205
213
if (cpu == 0)
206
-
remove_irq(sirfsoc_timer_irq.irq, &sirfsoc_timer_irq);
214
+
free_irq(sirfsoc_timer_irq, ce);
207
215
else
208
-
remove_irq(sirfsoc_timer1_irq.irq, &sirfsoc_timer1_irq);
216
+
free_irq(sirfsoc_timer1_irq, ce);
209
217
return 0;
210
218
}
211
219
···
264
268
return -ENXIO;
265
269
}
266
270
267
-
sirfsoc_timer_irq.irq = irq_of_parse_and_map(np, 0);
268
-
if (!sirfsoc_timer_irq.irq) {
271
+
sirfsoc_timer_irq = irq_of_parse_and_map(np, 0);
272
+
if (!sirfsoc_timer_irq) {
269
273
pr_err("No irq passed for timer0 via DT\n");
270
274
return -EINVAL;
271
275
}
272
276
273
-
sirfsoc_timer1_irq.irq = irq_of_parse_and_map(np, 1);
274
-
if (!sirfsoc_timer1_irq.irq) {
277
+
sirfsoc_timer1_irq = irq_of_parse_and_map(np, 1);
278
+
if (!sirfsoc_timer1_irq) {
275
279
pr_err("No irq passed for timer1 via DT\n");
276
280
return -EINVAL;
277
281
}
+2
-7
drivers/clocksource/timer-cs5535.c
+2
-7
drivers/clocksource/timer-cs5535.c
···
131
131
return IRQ_HANDLED;
132
132
}
133
133
134
-
static struct irqaction mfgptirq = {
135
-
.handler = mfgpt_tick,
136
-
.flags = IRQF_NOBALANCING | IRQF_TIMER | IRQF_SHARED,
137
-
.name = DRV_NAME,
138
-
};
139
-
140
134
static int __init cs5535_mfgpt_init(void)
141
135
{
136
+
unsigned long flags = IRQF_NOBALANCING | IRQF_TIMER | IRQF_SHARED;
142
137
struct cs5535_mfgpt_timer *timer;
143
138
int ret;
144
139
uint16_t val;
···
153
158
}
154
159
155
160
/* And register it with the kernel */
156
-
ret = setup_irq(timer_irq, &mfgptirq);
161
+
ret = request_irq(timer_irq, mfgpt_tick, flags, DRV_NAME, timer);
157
162
if (ret) {
158
163
printk(KERN_ERR DRV_NAME ": Unable to set up the interrupt.\n");
159
164
goto err_irq;
+2
-8
drivers/clocksource/timer-efm32.c
+2
-8
drivers/clocksource/timer-efm32.c
···
119
119
},
120
120
};
121
121
122
-
static struct irqaction efm32_clock_event_irq = {
123
-
.name = "efm32 clockevent",
124
-
.flags = IRQF_TIMER,
125
-
.handler = efm32_clock_event_handler,
126
-
.dev_id = &clock_event_ddata,
127
-
};
128
-
129
122
static int __init efm32_clocksource_init(struct device_node *np)
130
123
{
131
124
struct clk *clk;
···
223
230
DIV_ROUND_CLOSEST(rate, 1024),
224
231
0xf, 0xffff);
225
232
226
-
ret = setup_irq(irq, &efm32_clock_event_irq);
233
+
ret = request_irq(irq, efm32_clock_event_handler, IRQF_TIMER,
234
+
"efm32 clockevent", &clock_event_ddata);
227
235
if (ret) {
228
236
pr_err("Failed setup irq\n");
229
237
goto err_setup_irq;
+2
-8
drivers/clocksource/timer-fsl-ftm.c
+2
-8
drivers/clocksource/timer-fsl-ftm.c
···
176
176
.rating = 300,
177
177
};
178
178
179
-
static struct irqaction ftm_timer_irq = {
180
-
.name = "Freescale ftm timer",
181
-
.flags = IRQF_TIMER | IRQF_IRQPOLL,
182
-
.handler = ftm_evt_interrupt,
183
-
.dev_id = &ftm_clockevent,
184
-
};
185
-
186
179
static int __init ftm_clockevent_init(unsigned long freq, int irq)
187
180
{
188
181
int err;
···
185
192
186
193
ftm_reset_counter(priv->clkevt_base);
187
194
188
-
err = setup_irq(irq, &ftm_timer_irq);
195
+
err = request_irq(irq, ftm_evt_interrupt, IRQF_TIMER | IRQF_IRQPOLL,
196
+
"Freescale ftm timer", &ftm_clockevent);
189
197
if (err) {
190
198
pr_err("ftm: setup irq failed: %d\n", err);
191
199
return err;
+53
-15
drivers/clocksource/timer-fttmr010.c
+53
-15
drivers/clocksource/timer-fttmr010.c
···
38
38
#define TIMER_CR (0x30)
39
39
40
40
/*
41
+
* Control register set to clear for ast2600 only.
42
+
*/
43
+
#define AST2600_TIMER_CR_CLR (0x3c)
44
+
45
+
/*
41
46
* Control register (TMC30) bit fields for fttmr010/gemini/moxart timers.
42
47
*/
43
48
#define TIMER_1_CR_ENABLE BIT(0)
···
102
97
bool is_aspeed;
103
98
u32 t1_enable_val;
104
99
struct clock_event_device clkevt;
100
+
int (*timer_shutdown)(struct clock_event_device *evt);
105
101
#ifdef CONFIG_ARM
106
102
struct delay_timer delay_timer;
107
103
#endif
···
146
140
u32 cr;
147
141
148
142
/* Stop */
149
-
cr = readl(fttmr010->base + TIMER_CR);
150
-
cr &= ~fttmr010->t1_enable_val;
151
-
writel(cr, fttmr010->base + TIMER_CR);
143
+
fttmr010->timer_shutdown(evt);
152
144
153
145
if (fttmr010->is_aspeed) {
154
146
/*
···
164
160
cr = readl(fttmr010->base + TIMER_CR);
165
161
cr |= fttmr010->t1_enable_val;
166
162
writel(cr, fttmr010->base + TIMER_CR);
163
+
164
+
return 0;
165
+
}
166
+
167
+
static int ast2600_timer_shutdown(struct clock_event_device *evt)
168
+
{
169
+
struct fttmr010 *fttmr010 = to_fttmr010(evt);
170
+
171
+
/* Stop */
172
+
writel(fttmr010->t1_enable_val, fttmr010->base + AST2600_TIMER_CR_CLR);
167
173
168
174
return 0;
169
175
}
···
197
183
u32 cr;
198
184
199
185
/* Stop */
200
-
cr = readl(fttmr010->base + TIMER_CR);
201
-
cr &= ~fttmr010->t1_enable_val;
202
-
writel(cr, fttmr010->base + TIMER_CR);
186
+
fttmr010->timer_shutdown(evt);
203
187
204
188
/* Setup counter start from 0 or ~0 */
205
189
writel(0, fttmr010->base + TIMER1_COUNT);
···
223
211
u32 cr;
224
212
225
213
/* Stop */
226
-
cr = readl(fttmr010->base + TIMER_CR);
227
-
cr &= ~fttmr010->t1_enable_val;
228
-
writel(cr, fttmr010->base + TIMER_CR);
214
+
fttmr010->timer_shutdown(evt);
229
215
230
216
/* Setup timer to fire at 1/HZ intervals. */
231
217
if (fttmr010->is_aspeed) {
···
259
249
return IRQ_HANDLED;
260
250
}
261
251
262
-
static int __init fttmr010_common_init(struct device_node *np, bool is_aspeed)
252
+
static irqreturn_t ast2600_timer_interrupt(int irq, void *dev_id)
253
+
{
254
+
struct clock_event_device *evt = dev_id;
255
+
struct fttmr010 *fttmr010 = to_fttmr010(evt);
256
+
257
+
writel(0x1, fttmr010->base + TIMER_INTR_STATE);
258
+
259
+
evt->event_handler(evt);
260
+
return IRQ_HANDLED;
261
+
}
262
+
263
+
static int __init fttmr010_common_init(struct device_node *np,
264
+
bool is_aspeed,
265
+
int (*timer_shutdown)(struct clock_event_device *),
266
+
irq_handler_t irq_handler)
263
267
{
264
268
struct fttmr010 *fttmr010;
265
269
int irq;
···
374
350
fttmr010->tick_rate);
375
351
}
376
352
353
+
fttmr010->timer_shutdown = timer_shutdown;
354
+
377
355
/*
378
356
* Setup clockevent timer (interrupt-driven) on timer 1.
379
357
*/
···
383
357
writel(0, fttmr010->base + TIMER1_LOAD);
384
358
writel(0, fttmr010->base + TIMER1_MATCH1);
385
359
writel(0, fttmr010->base + TIMER1_MATCH2);
386
-
ret = request_irq(irq, fttmr010_timer_interrupt, IRQF_TIMER,
360
+
ret = request_irq(irq, irq_handler, IRQF_TIMER,
387
361
"FTTMR010-TIMER1", &fttmr010->clkevt);
388
362
if (ret) {
389
363
pr_err("FTTMR010-TIMER1 no IRQ\n");
···
396
370
fttmr010->clkevt.features = CLOCK_EVT_FEAT_PERIODIC |
397
371
CLOCK_EVT_FEAT_ONESHOT;
398
372
fttmr010->clkevt.set_next_event = fttmr010_timer_set_next_event;
399
-
fttmr010->clkevt.set_state_shutdown = fttmr010_timer_shutdown;
373
+
fttmr010->clkevt.set_state_shutdown = fttmr010->timer_shutdown;
400
374
fttmr010->clkevt.set_state_periodic = fttmr010_timer_set_periodic;
401
375
fttmr010->clkevt.set_state_oneshot = fttmr010_timer_set_oneshot;
402
-
fttmr010->clkevt.tick_resume = fttmr010_timer_shutdown;
376
+
fttmr010->clkevt.tick_resume = fttmr010->timer_shutdown;
403
377
fttmr010->clkevt.cpumask = cpumask_of(0);
404
378
fttmr010->clkevt.irq = irq;
405
379
clockevents_config_and_register(&fttmr010->clkevt,
···
430
404
return ret;
431
405
}
432
406
407
+
static __init int ast2600_timer_init(struct device_node *np)
408
+
{
409
+
return fttmr010_common_init(np, true,
410
+
ast2600_timer_shutdown,
411
+
ast2600_timer_interrupt);
412
+
}
413
+
433
414
static __init int aspeed_timer_init(struct device_node *np)
434
415
{
435
-
return fttmr010_common_init(np, true);
416
+
return fttmr010_common_init(np, true,
417
+
fttmr010_timer_shutdown,
418
+
fttmr010_timer_interrupt);
436
419
}
437
420
438
421
static __init int fttmr010_timer_init(struct device_node *np)
439
422
{
440
-
return fttmr010_common_init(np, false);
423
+
return fttmr010_common_init(np, false,
424
+
fttmr010_timer_shutdown,
425
+
fttmr010_timer_interrupt);
441
426
}
442
427
443
428
TIMER_OF_DECLARE(fttmr010, "faraday,fttmr010", fttmr010_timer_init);
···
456
419
TIMER_OF_DECLARE(moxart, "moxa,moxart-timer", fttmr010_timer_init);
457
420
TIMER_OF_DECLARE(ast2400, "aspeed,ast2400-timer", aspeed_timer_init);
458
421
TIMER_OF_DECLARE(ast2500, "aspeed,ast2500-timer", aspeed_timer_init);
422
+
TIMER_OF_DECLARE(ast2600, "aspeed,ast2600-timer", ast2600_timer_init);
+2
-8
drivers/clocksource/timer-imx-gpt.c
+2
-8
drivers/clocksource/timer-imx-gpt.c
···
67
67
struct clk *clk_ipg;
68
68
const struct imx_gpt_data *gpt;
69
69
struct clock_event_device ced;
70
-
struct irqaction act;
71
70
};
72
71
73
72
struct imx_gpt_data {
···
272
273
static int __init mxc_clockevent_init(struct imx_timer *imxtm)
273
274
{
274
275
struct clock_event_device *ced = &imxtm->ced;
275
-
struct irqaction *act = &imxtm->act;
276
276
277
277
ced->name = "mxc_timer1";
278
278
ced->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_DYNIRQ;
···
285
287
clockevents_config_and_register(ced, clk_get_rate(imxtm->clk_per),
286
288
0xff, 0xfffffffe);
287
289
288
-
act->name = "i.MX Timer Tick";
289
-
act->flags = IRQF_TIMER | IRQF_IRQPOLL;
290
-
act->handler = mxc_timer_interrupt;
291
-
act->dev_id = ced;
292
-
293
-
return setup_irq(imxtm->irq, act);
290
+
return request_irq(imxtm->irq, mxc_timer_interrupt,
291
+
IRQF_TIMER | IRQF_IRQPOLL, "i.MX Timer Tick", ced);
294
292
}
295
293
296
294
static void imx1_gpt_setup_tctl(struct imx_timer *imxtm)
-2
drivers/clocksource/timer-imx-sysctr.c
-2
drivers/clocksource/timer-imx-sysctr.c
-2
drivers/clocksource/timer-imx-tpm.c
-2
drivers/clocksource/timer-imx-tpm.c
+3
-8
drivers/clocksource/timer-integrator-ap.c
+3
-8
drivers/clocksource/timer-integrator-ap.c
···
123
123
.rating = 300,
124
124
};
125
125
126
-
static struct irqaction integrator_timer_irq = {
127
-
.name = "timer",
128
-
.flags = IRQF_TIMER | IRQF_IRQPOLL,
129
-
.handler = integrator_timer_interrupt,
130
-
.dev_id = &integrator_clockevent,
131
-
};
132
-
133
126
static int integrator_clockevent_init(unsigned long inrate,
134
127
void __iomem *base, int irq)
135
128
{
···
142
149
timer_reload = rate / HZ;
143
150
writel(ctrl, clkevt_base + TIMER_CTRL);
144
151
145
-
ret = setup_irq(irq, &integrator_timer_irq);
152
+
ret = request_irq(irq, integrator_timer_interrupt,
153
+
IRQF_TIMER | IRQF_IRQPOLL, "timer",
154
+
&integrator_clockevent);
146
155
if (ret)
147
156
return ret;
148
157
+3
-8
drivers/clocksource/timer-meson6.c
+3
-8
drivers/clocksource/timer-meson6.c
···
150
150
return IRQ_HANDLED;
151
151
}
152
152
153
-
static struct irqaction meson6_timer_irq = {
154
-
.name = "meson6_timer",
155
-
.flags = IRQF_TIMER | IRQF_IRQPOLL,
156
-
.handler = meson6_timer_interrupt,
157
-
.dev_id = &meson6_clockevent,
158
-
};
159
-
160
153
static int __init meson6_timer_init(struct device_node *node)
161
154
{
162
155
u32 val;
···
187
194
/* Stop the timer A */
188
195
meson6_clkevt_time_stop();
189
196
190
-
ret = setup_irq(irq, &meson6_timer_irq);
197
+
ret = request_irq(irq, meson6_timer_interrupt,
198
+
IRQF_TIMER | IRQF_IRQPOLL, "meson6_timer",
199
+
&meson6_clockevent);
191
200
if (ret) {
192
201
pr_warn("failed to setup irq %d\n", irq);
193
202
return ret;
+1
drivers/clocksource/timer-microchip-pit64b.c
+1
drivers/clocksource/timer-microchip-pit64b.c
+2
-7
drivers/clocksource/timer-orion.c
+2
-7
drivers/clocksource/timer-orion.c
···
114
114
return IRQ_HANDLED;
115
115
}
116
116
117
-
static struct irqaction orion_clkevt_irq = {
118
-
.name = "orion_event",
119
-
.flags = IRQF_TIMER,
120
-
.handler = orion_clkevt_irq_handler,
121
-
};
122
-
123
117
static int __init orion_timer_init(struct device_node *np)
124
118
{
125
119
unsigned long rate;
···
166
172
sched_clock_register(orion_read_sched_clock, 32, rate);
167
173
168
174
/* setup timer1 as clockevent timer */
169
-
ret = setup_irq(irq, &orion_clkevt_irq);
175
+
ret = request_irq(irq, orion_clkevt_irq_handler, IRQF_TIMER,
176
+
"orion_event", NULL);
170
177
if (ret) {
171
178
pr_err("%pOFn: unable to setup irq\n", np);
172
179
return ret;
+11
-4
drivers/clocksource/timer-owl.c
+11
-4
drivers/clocksource/timer-owl.c
···
135
135
}
136
136
137
137
clk = of_clk_get(node, 0);
138
-
if (IS_ERR(clk))
139
-
return PTR_ERR(clk);
138
+
if (IS_ERR(clk)) {
139
+
ret = PTR_ERR(clk);
140
+
pr_err("Failed to get clock for clocksource (%d)\n", ret);
141
+
return ret;
142
+
}
140
143
141
144
rate = clk_get_rate(clk);
142
145
···
147
144
owl_timer_set_enabled(owl_clksrc_base, true);
148
145
149
146
sched_clock_register(owl_timer_sched_read, 32, rate);
150
-
clocksource_mmio_init(owl_clksrc_base + OWL_Tx_VAL, node->name,
151
-
rate, 200, 32, clocksource_mmio_readl_up);
147
+
ret = clocksource_mmio_init(owl_clksrc_base + OWL_Tx_VAL, node->name,
148
+
rate, 200, 32, clocksource_mmio_readl_up);
149
+
if (ret) {
150
+
pr_err("Failed to register clocksource (%d)\n", ret);
151
+
return ret;
152
+
}
152
153
153
154
owl_timer_reset(owl_clkevt_base);
154
155
+4
-10
drivers/clocksource/timer-prima2.c
+4
-10
drivers/clocksource/timer-prima2.c
···
165
165
.resume = sirfsoc_clocksource_resume,
166
166
};
167
167
168
-
static struct irqaction sirfsoc_timer_irq = {
169
-
.name = "sirfsoc_timer0",
170
-
.flags = IRQF_TIMER,
171
-
.irq = 0,
172
-
.handler = sirfsoc_timer_interrupt,
173
-
.dev_id = &sirfsoc_clockevent,
174
-
};
175
-
176
168
/* Overwrite weak default sched_clock with more precise one */
177
169
static u64 notrace sirfsoc_read_sched_clock(void)
178
170
{
···
182
190
static int __init sirfsoc_prima2_timer_init(struct device_node *np)
183
191
{
184
192
unsigned long rate;
193
+
unsigned int irq;
185
194
struct clk *clk;
186
195
int ret;
187
196
···
211
218
return -ENXIO;
212
219
}
213
220
214
-
sirfsoc_timer_irq.irq = irq_of_parse_and_map(np, 0);
221
+
irq = irq_of_parse_and_map(np, 0);
215
222
216
223
writel_relaxed(rate / PRIMA2_CLOCK_FREQ / 2 - 1,
217
224
sirfsoc_timer_base + SIRFSOC_TIMER_DIV);
···
227
234
228
235
sched_clock_register(sirfsoc_read_sched_clock, 64, PRIMA2_CLOCK_FREQ);
229
236
230
-
ret = setup_irq(sirfsoc_timer_irq.irq, &sirfsoc_timer_irq);
237
+
ret = request_irq(irq, sirfsoc_timer_interrupt, IRQF_TIMER,
238
+
"sirfsoc_timer0", &sirfsoc_clockevent);
231
239
if (ret) {
232
240
pr_err("Failed to setup irq\n");
233
241
return ret;
+2
drivers/clocksource/timer-probe.c
+2
drivers/clocksource/timer-probe.c
+2
-8
drivers/clocksource/timer-pxa.c
+2
-8
drivers/clocksource/timer-pxa.c
···
143
143
.resume = pxa_timer_resume,
144
144
};
145
145
146
-
static struct irqaction pxa_ost0_irq = {
147
-
.name = "ost0",
148
-
.flags = IRQF_TIMER | IRQF_IRQPOLL,
149
-
.handler = pxa_ost0_interrupt,
150
-
.dev_id = &ckevt_pxa_osmr0,
151
-
};
152
-
153
146
static int __init pxa_timer_common_init(int irq, unsigned long clock_tick_rate)
154
147
{
155
148
int ret;
···
154
161
155
162
ckevt_pxa_osmr0.cpumask = cpumask_of(0);
156
163
157
-
ret = setup_irq(irq, &pxa_ost0_irq);
164
+
ret = request_irq(irq, pxa_ost0_interrupt, IRQF_TIMER | IRQF_IRQPOLL,
165
+
"ost0", &ckevt_pxa_osmr0);
158
166
if (ret) {
159
167
pr_err("Failed to setup irq\n");
160
168
return ret;
+3
-8
drivers/clocksource/timer-sp804.c
+3
-8
drivers/clocksource/timer-sp804.c
···
168
168
.rating = 300,
169
169
};
170
170
171
-
static struct irqaction sp804_timer_irq = {
172
-
.name = "timer",
173
-
.flags = IRQF_TIMER | IRQF_IRQPOLL,
174
-
.handler = sp804_timer_interrupt,
175
-
.dev_id = &sp804_clockevent,
176
-
};
177
-
178
171
int __init __sp804_clockevents_init(void __iomem *base, unsigned int irq, struct clk *clk, const char *name)
179
172
{
180
173
struct clock_event_device *evt = &sp804_clockevent;
···
193
200
194
201
writel(0, base + TIMER_CTRL);
195
202
196
-
setup_irq(irq, &sp804_timer_irq);
203
+
if (request_irq(irq, sp804_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL,
204
+
"timer", &sp804_clockevent))
205
+
pr_err("%s: request_irq() failed\n", "timer");
197
206
clockevents_config_and_register(evt, rate, 0xf, 0xffffffff);
198
207
199
208
return 0;
+110
-107
drivers/clocksource/timer-ti-dm.c
+110
-107
drivers/clocksource/timer-ti-dm.c
···
1
+
// SPDX-License-Identifier: GPL-2.0+
1
2
/*
2
3
* linux/arch/arm/plat-omap/dmtimer.c
3
4
*
···
16
15
*
17
16
* Copyright (C) 2009 Texas Instruments
18
17
* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
19
-
*
20
-
* This program is free software; you can redistribute it and/or modify it
21
-
* under the terms of the GNU General Public License as published by the
22
-
* Free Software Foundation; either version 2 of the License, or (at your
23
-
* option) any later version.
24
-
*
25
-
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
26
-
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
27
-
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
28
-
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
29
-
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
30
-
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31
-
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32
-
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33
-
*
34
-
* You should have received a copy of the GNU General Public License along
35
-
* with this program; if not, write to the Free Software Foundation, Inc.,
36
-
* 675 Mass Ave, Cambridge, MA 02139, USA.
37
18
*/
38
19
39
20
#include <linux/clk.h>
40
21
#include <linux/clk-provider.h>
22
+
#include <linux/cpu_pm.h>
41
23
#include <linux/module.h>
42
24
#include <linux/io.h>
43
25
#include <linux/device.h>
···
93
109
timer->context.tclr);
94
110
}
95
111
112
+
static void omap_timer_save_context(struct omap_dm_timer *timer)
113
+
{
114
+
timer->context.tclr =
115
+
omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
116
+
timer->context.twer =
117
+
omap_dm_timer_read_reg(timer, OMAP_TIMER_WAKEUP_EN_REG);
118
+
timer->context.tldr =
119
+
omap_dm_timer_read_reg(timer, OMAP_TIMER_LOAD_REG);
120
+
timer->context.tmar =
121
+
omap_dm_timer_read_reg(timer, OMAP_TIMER_MATCH_REG);
122
+
timer->context.tier = readl_relaxed(timer->irq_ena);
123
+
timer->context.tsicr =
124
+
omap_dm_timer_read_reg(timer, OMAP_TIMER_IF_CTRL_REG);
125
+
}
126
+
127
+
static int omap_timer_context_notifier(struct notifier_block *nb,
128
+
unsigned long cmd, void *v)
129
+
{
130
+
struct omap_dm_timer *timer;
131
+
132
+
timer = container_of(nb, struct omap_dm_timer, nb);
133
+
134
+
switch (cmd) {
135
+
case CPU_CLUSTER_PM_ENTER:
136
+
if ((timer->capability & OMAP_TIMER_ALWON) ||
137
+
!atomic_read(&timer->enabled))
138
+
break;
139
+
omap_timer_save_context(timer);
140
+
break;
141
+
case CPU_CLUSTER_PM_ENTER_FAILED:
142
+
case CPU_CLUSTER_PM_EXIT:
143
+
if ((timer->capability & OMAP_TIMER_ALWON) ||
144
+
!atomic_read(&timer->enabled))
145
+
break;
146
+
omap_timer_restore_context(timer);
147
+
break;
148
+
}
149
+
150
+
return NOTIFY_OK;
151
+
}
152
+
96
153
static int omap_dm_timer_reset(struct omap_dm_timer *timer)
97
154
{
98
155
u32 l, timeout = 100000;
···
161
136
timer->posted = 0;
162
137
163
138
return 0;
164
-
}
165
-
166
-
static int omap_dm_timer_of_set_source(struct omap_dm_timer *timer)
167
-
{
168
-
int ret;
169
-
struct clk *parent;
170
-
171
-
/*
172
-
* FIXME: OMAP1 devices do not use the clock framework for dmtimers so
173
-
* do not call clk_get() for these devices.
174
-
*/
175
-
if (!timer->fclk)
176
-
return -ENODEV;
177
-
178
-
parent = clk_get(&timer->pdev->dev, NULL);
179
-
if (IS_ERR(parent))
180
-
return -ENODEV;
181
-
182
-
/* Bail out if both clocks point to fck */
183
-
if (clk_is_match(parent, timer->fclk))
184
-
return 0;
185
-
186
-
ret = clk_set_parent(timer->fclk, parent);
187
-
if (ret < 0)
188
-
pr_err("%s: failed to set parent\n", __func__);
189
-
190
-
clk_put(parent);
191
-
192
-
return ret;
193
139
}
194
140
195
141
static int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
···
221
225
222
226
static void omap_dm_timer_enable(struct omap_dm_timer *timer)
223
227
{
224
-
int c;
225
-
226
228
pm_runtime_get_sync(&timer->pdev->dev);
227
-
228
-
if (!(timer->capability & OMAP_TIMER_ALWON)) {
229
-
if (timer->get_context_loss_count) {
230
-
c = timer->get_context_loss_count(&timer->pdev->dev);
231
-
if (c != timer->ctx_loss_count) {
232
-
omap_timer_restore_context(timer);
233
-
timer->ctx_loss_count = c;
234
-
}
235
-
} else {
236
-
omap_timer_restore_context(timer);
237
-
}
238
-
}
239
229
}
240
230
241
231
static void omap_dm_timer_disable(struct omap_dm_timer *timer)
···
258
276
__omap_dm_timer_enable_posted(timer);
259
277
omap_dm_timer_disable(timer);
260
278
261
-
rc = omap_dm_timer_of_set_source(timer);
262
-
if (rc == -ENODEV)
263
-
return omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);
279
+
rc = omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);
264
280
265
281
return rc;
266
282
}
···
488
508
489
509
int omap_dm_timer_trigger(struct omap_dm_timer *timer)
490
510
{
491
-
if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
511
+
if (unlikely(!timer || !atomic_read(&timer->enabled))) {
492
512
pr_err("%s: timer not available or enabled.\n", __func__);
493
513
return -EINVAL;
494
514
}
···
512
532
omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
513
533
}
514
534
515
-
/* Save the context */
516
-
timer->context.tclr = l;
517
535
return 0;
518
536
}
519
537
···
527
549
528
550
__omap_dm_timer_stop(timer, timer->posted, rate);
529
551
530
-
/*
531
-
* Since the register values are computed and written within
532
-
* __omap_dm_timer_stop, we need to use read to retrieve the
533
-
* context.
534
-
*/
535
-
timer->context.tclr =
536
-
omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
537
552
omap_dm_timer_disable(timer);
538
553
return 0;
539
554
}
540
555
541
-
static int omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload,
556
+
static int omap_dm_timer_set_load(struct omap_dm_timer *timer,
542
557
unsigned int load)
543
558
{
544
-
u32 l;
545
-
546
559
if (unlikely(!timer))
547
560
return -EINVAL;
548
561
549
562
omap_dm_timer_enable(timer);
550
-
l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
551
-
if (autoreload)
552
-
l |= OMAP_TIMER_CTRL_AR;
553
-
else
554
-
l &= ~OMAP_TIMER_CTRL_AR;
555
-
omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
556
563
omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
557
564
558
-
omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
559
-
/* Save the context */
560
-
timer->context.tclr = l;
561
-
timer->context.tldr = load;
562
565
omap_dm_timer_disable(timer);
563
566
return 0;
564
567
}
···
561
602
omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match);
562
603
omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
563
604
564
-
/* Save the context */
565
-
timer->context.tclr = l;
566
-
timer->context.tmar = match;
567
605
omap_dm_timer_disable(timer);
568
606
return 0;
569
607
}
570
608
571
609
static int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on,
572
-
int toggle, int trigger)
610
+
int toggle, int trigger, int autoreload)
573
611
{
574
612
u32 l;
575
613
···
576
620
omap_dm_timer_enable(timer);
577
621
l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
578
622
l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM |
579
-
OMAP_TIMER_CTRL_PT | (0x03 << 10));
623
+
OMAP_TIMER_CTRL_PT | (0x03 << 10) | OMAP_TIMER_CTRL_AR);
580
624
if (def_on)
581
625
l |= OMAP_TIMER_CTRL_SCPWM;
582
626
if (toggle)
583
627
l |= OMAP_TIMER_CTRL_PT;
584
628
l |= trigger << 10;
629
+
if (autoreload)
630
+
l |= OMAP_TIMER_CTRL_AR;
585
631
omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
586
632
587
-
/* Save the context */
588
-
timer->context.tclr = l;
589
633
omap_dm_timer_disable(timer);
590
634
return 0;
635
+
}
636
+
637
+
static int omap_dm_timer_get_pwm_status(struct omap_dm_timer *timer)
638
+
{
639
+
u32 l;
640
+
641
+
if (unlikely(!timer))
642
+
return -EINVAL;
643
+
644
+
omap_dm_timer_enable(timer);
645
+
l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
646
+
omap_dm_timer_disable(timer);
647
+
648
+
return l;
591
649
}
592
650
593
651
static int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer,
···
621
651
}
622
652
omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
623
653
624
-
/* Save the context */
625
-
timer->context.tclr = l;
626
654
omap_dm_timer_disable(timer);
627
655
return 0;
628
656
}
···
634
666
omap_dm_timer_enable(timer);
635
667
__omap_dm_timer_int_enable(timer, value);
636
668
637
-
/* Save the context */
638
-
timer->context.tier = value;
639
-
timer->context.twer = value;
640
669
omap_dm_timer_disable(timer);
641
670
return 0;
642
671
}
···
661
696
l = omap_dm_timer_read_reg(timer, OMAP_TIMER_WAKEUP_EN_REG) & ~mask;
662
697
omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, l);
663
698
664
-
/* Save the context */
665
-
timer->context.tier &= ~mask;
666
-
timer->context.twer &= ~mask;
667
699
omap_dm_timer_disable(timer);
668
700
return 0;
669
701
}
···
669
707
{
670
708
unsigned int l;
671
709
672
-
if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
710
+
if (unlikely(!timer || !atomic_read(&timer->enabled))) {
673
711
pr_err("%s: timer not available or enabled.\n", __func__);
674
712
return 0;
675
713
}
···
681
719
682
720
static int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value)
683
721
{
684
-
if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev)))
722
+
if (unlikely(!timer || !atomic_read(&timer->enabled)))
685
723
return -EINVAL;
686
724
687
725
__omap_dm_timer_write_status(timer, value);
···
691
729
692
730
static unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer)
693
731
{
694
-
if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
732
+
if (unlikely(!timer || !atomic_read(&timer->enabled))) {
695
733
pr_err("%s: timer not iavailable or enabled.\n", __func__);
696
734
return 0;
697
735
}
···
701
739
702
740
static int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value)
703
741
{
704
-
if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
742
+
if (unlikely(!timer || !atomic_read(&timer->enabled))) {
705
743
pr_err("%s: timer not available or enabled.\n", __func__);
706
744
return -EINVAL;
707
745
}
···
728
766
}
729
767
return 0;
730
768
}
769
+
770
+
static int __maybe_unused omap_dm_timer_runtime_suspend(struct device *dev)
771
+
{
772
+
struct omap_dm_timer *timer = dev_get_drvdata(dev);
773
+
774
+
atomic_set(&timer->enabled, 0);
775
+
776
+
if (timer->capability & OMAP_TIMER_ALWON || !timer->func_base)
777
+
return 0;
778
+
779
+
omap_timer_save_context(timer);
780
+
781
+
return 0;
782
+
}
783
+
784
+
static int __maybe_unused omap_dm_timer_runtime_resume(struct device *dev)
785
+
{
786
+
struct omap_dm_timer *timer = dev_get_drvdata(dev);
787
+
788
+
if (!(timer->capability & OMAP_TIMER_ALWON) && timer->func_base)
789
+
omap_timer_restore_context(timer);
790
+
791
+
atomic_set(&timer->enabled, 1);
792
+
793
+
return 0;
794
+
}
795
+
796
+
static const struct dev_pm_ops omap_dm_timer_pm_ops = {
797
+
SET_RUNTIME_PM_OPS(omap_dm_timer_runtime_suspend,
798
+
omap_dm_timer_runtime_resume, NULL)
799
+
};
731
800
732
801
static const struct of_device_id omap_timer_match[];
733
802
···
801
808
if (IS_ERR(timer->io_base))
802
809
return PTR_ERR(timer->io_base);
803
810
811
+
platform_set_drvdata(pdev, timer);
812
+
804
813
if (dev->of_node) {
805
814
if (of_find_property(dev->of_node, "ti,timer-alwon", NULL))
806
815
timer->capability |= OMAP_TIMER_ALWON;
···
816
821
timer->id = pdev->id;
817
822
timer->capability = pdata->timer_capability;
818
823
timer->reserved = omap_dm_timer_reserved_systimer(timer->id);
819
-
timer->get_context_loss_count = pdata->get_context_loss_count;
824
+
}
825
+
826
+
if (!(timer->capability & OMAP_TIMER_ALWON)) {
827
+
timer->nb.notifier_call = omap_timer_context_notifier;
828
+
cpu_pm_register_notifier(&timer->nb);
820
829
}
821
830
822
831
if (pdata)
···
874
875
list_for_each_entry(timer, &omap_timer_list, node)
875
876
if (!strcmp(dev_name(&timer->pdev->dev),
876
877
dev_name(&pdev->dev))) {
878
+
if (!(timer->capability & OMAP_TIMER_ALWON))
879
+
cpu_pm_unregister_notifier(&timer->nb);
877
880
list_del(&timer->node);
878
881
ret = 0;
879
882
break;
···
904
903
.set_load = omap_dm_timer_set_load,
905
904
.set_match = omap_dm_timer_set_match,
906
905
.set_pwm = omap_dm_timer_set_pwm,
906
+
.get_pwm_status = omap_dm_timer_get_pwm_status,
907
907
.set_prescaler = omap_dm_timer_set_prescaler,
908
908
.read_counter = omap_dm_timer_read_counter,
909
909
.write_counter = omap_dm_timer_write_counter,
···
955
953
.driver = {
956
954
.name = "omap_timer",
957
955
.of_match_table = of_match_ptr(omap_timer_match),
956
+
.pm = &omap_dm_timer_pm_ops,
958
957
},
959
958
};
960
959
+2
-7
drivers/clocksource/timer-u300.c
+2
-7
drivers/clocksource/timer-u300.c
···
330
330
return IRQ_HANDLED;
331
331
}
332
332
333
-
static struct irqaction u300_timer_irq = {
334
-
.name = "U300 Timer Tick",
335
-
.flags = IRQF_TIMER | IRQF_IRQPOLL,
336
-
.handler = u300_timer_interrupt,
337
-
};
338
-
339
333
/*
340
334
* Override the global weak sched_clock symbol with this
341
335
* local implementation which uses the clocksource to get some
···
414
420
u300_timer_base + U300_TIMER_APP_RGPT1);
415
421
416
422
/* Set up the IRQ handler */
417
-
ret = setup_irq(irq, &u300_timer_irq);
423
+
ret = request_irq(irq, u300_timer_interrupt,
424
+
IRQF_TIMER | IRQF_IRQPOLL, "U300 Timer Tick", NULL);
418
425
if (ret)
419
426
return ret;
420
427
+2
-8
drivers/clocksource/timer-vf-pit.c
+2
-8
drivers/clocksource/timer-vf-pit.c
···
123
123
.rating = 300,
124
124
};
125
125
126
-
static struct irqaction pit_timer_irq = {
127
-
.name = "VF pit timer",
128
-
.flags = IRQF_TIMER | IRQF_IRQPOLL,
129
-
.handler = pit_timer_interrupt,
130
-
.dev_id = &clockevent_pit,
131
-
};
132
-
133
126
static int __init pit_clockevent_init(unsigned long rate, int irq)
134
127
{
135
128
__raw_writel(0, clkevt_base + PITTCTRL);
136
129
__raw_writel(PITTFLG_TIF, clkevt_base + PITTFLG);
137
130
138
-
BUG_ON(setup_irq(irq, &pit_timer_irq));
131
+
BUG_ON(request_irq(irq, pit_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL,
132
+
"VF pit timer", &clockevent_pit);
139
133
140
134
clockevent_pit.cpumask = cpumask_of(0);
141
135
clockevent_pit.irq = irq;
+3
-8
drivers/clocksource/timer-vt8500.c
+3
-8
drivers/clocksource/timer-vt8500.c
···
101
101
return IRQ_HANDLED;
102
102
}
103
103
104
-
static struct irqaction irq = {
105
-
.name = "vt8500_timer",
106
-
.flags = IRQF_TIMER | IRQF_IRQPOLL,
107
-
.handler = vt8500_timer_interrupt,
108
-
.dev_id = &clockevent,
109
-
};
110
-
111
104
static int __init vt8500_timer_init(struct device_node *np)
112
105
{
113
106
int timer_irq, ret;
···
132
139
133
140
clockevent.cpumask = cpumask_of(0);
134
141
135
-
ret = setup_irq(timer_irq, &irq);
142
+
ret = request_irq(timer_irq, vt8500_timer_interrupt,
143
+
IRQF_TIMER | IRQF_IRQPOLL, "vt8500_timer",
144
+
&clockevent);
136
145
if (ret) {
137
146
pr_err("%s: setup_irq failed for %s\n", __func__,
138
147
clockevent.name);
+6
-7
drivers/clocksource/timer-zevio.c
+6
-7
drivers/clocksource/timer-zevio.c
···
53
53
54
54
struct clk *clk;
55
55
struct clock_event_device clkevt;
56
-
struct irqaction clkevt_irq;
57
56
58
57
char clocksource_name[64];
59
58
char clockevent_name[64];
···
171
172
/* Interrupt to occur when timer value matches 0 */
172
173
writel(0, timer->base + IO_MATCH(TIMER_MATCH));
173
174
174
-
timer->clkevt_irq.name = timer->clockevent_name;
175
-
timer->clkevt_irq.handler = zevio_timer_interrupt;
176
-
timer->clkevt_irq.dev_id = timer;
177
-
timer->clkevt_irq.flags = IRQF_TIMER | IRQF_IRQPOLL;
178
-
179
-
setup_irq(irqnr, &timer->clkevt_irq);
175
+
if (request_irq(irqnr, zevio_timer_interrupt,
176
+
IRQF_TIMER | IRQF_IRQPOLL,
177
+
timer->clockevent_name, timer)) {
178
+
pr_err("%s: request_irq() failed\n",
179
+
timer->clockevent_name);
180
+
}
180
181
181
182
clockevents_config_and_register(&timer->clkevt,
182
183
clk_get_rate(timer->clk), 0x0001, 0xffff);
+5
-3
drivers/pwm/pwm-omap-dmtimer.c
+5
-3
drivers/pwm/pwm-omap-dmtimer.c
···
183
183
if (timer_active)
184
184
omap->pdata->stop(omap->dm_timer);
185
185
186
-
omap->pdata->set_load(omap->dm_timer, true, load_value);
186
+
omap->pdata->set_load(omap->dm_timer, load_value);
187
187
omap->pdata->set_match(omap->dm_timer, true, match_value);
188
188
189
189
dev_dbg(chip->dev, "load value: %#08x (%d), match value: %#08x (%d)\n",
···
192
192
omap->pdata->set_pwm(omap->dm_timer,
193
193
pwm_get_polarity(pwm) == PWM_POLARITY_INVERSED,
194
194
true,
195
-
PWM_OMAP_DMTIMER_TRIGGER_OVERFLOW_AND_COMPARE);
195
+
PWM_OMAP_DMTIMER_TRIGGER_OVERFLOW_AND_COMPARE,
196
+
true);
196
197
197
198
/* If config was called while timer was running it must be reenabled. */
198
199
if (timer_active)
···
223
222
omap->pdata->set_pwm(omap->dm_timer,
224
223
polarity == PWM_POLARITY_INVERSED,
225
224
true,
226
-
PWM_OMAP_DMTIMER_TRIGGER_OVERFLOW_AND_COMPARE);
225
+
PWM_OMAP_DMTIMER_TRIGGER_OVERFLOW_AND_COMPARE,
226
+
true);
227
227
mutex_unlock(&omap->mutex);
228
228
229
229
return 0;
+2
-2
include/clocksource/timer-ti-dm.h
+2
-2
include/clocksource/timer-ti-dm.h
···
105
105
void __iomem *pend; /* write pending */
106
106
void __iomem *func_base; /* function register base */
107
107
108
+
atomic_t enabled;
108
109
unsigned long rate;
109
110
unsigned reserved:1;
110
111
unsigned posted:1;
111
112
struct timer_regs context;
112
-
int (*get_context_loss_count)(struct device *);
113
-
int ctx_loss_count;
114
113
int revision;
115
114
u32 capability;
116
115
u32 errata;
117
116
struct platform_device *pdev;
118
117
struct list_head node;
118
+
struct notifier_block nb;
119
119
};
120
120
121
121
int omap_dm_timer_reserve_systimer(int id);
-1
include/linux/dw_apb_timer.h
-1
include/linux/dw_apb_timer.h
+3
-3
include/linux/platform_data/dmtimer-omap.h
+3
-3
include/linux/platform_data/dmtimer-omap.h
···
30
30
int (*stop)(struct omap_dm_timer *timer);
31
31
int (*set_source)(struct omap_dm_timer *timer, int source);
32
32
33
-
int (*set_load)(struct omap_dm_timer *timer, int autoreload,
34
-
unsigned int value);
33
+
int (*set_load)(struct omap_dm_timer *timer, unsigned int value);
35
34
int (*set_match)(struct omap_dm_timer *timer, int enable,
36
35
unsigned int match);
37
36
int (*set_pwm)(struct omap_dm_timer *timer, int def_on,
38
-
int toggle, int trigger);
37
+
int toggle, int trigger, int autoreload);
38
+
int (*get_pwm_status)(struct omap_dm_timer *timer);
39
39
int (*set_prescaler)(struct omap_dm_timer *timer, int prescaler);
40
40
41
41
unsigned int (*read_counter)(struct omap_dm_timer *timer);