tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC fixes from Olof Johansson:
"Another batch of fixes for ARM SoC platforms. Most are smaller fixes.

Two areas that are worth pointing out are:

- OMAP had a handful of changes to voltage specs that caused a bit of
churn, most of volume of change in this branch is due to this.

- There are a couple of _rcuidle fixes from Paul that touch common
code and came in through the OMAP tree since they were the ones who
saw the problems.

The rest is smaller changes across a handful of platforms"

* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (36 commits)
ARM: dts: STi: stih407-family: Disable reserved-memory co-processor nodes
ARM: dts: am437x-sk-evm: Reduce i2c0 bus speed for tps65218
ARM: OMAP2+: timer: add probe for clocksources
ARM: OMAP1: fix ams-delta FIQ handler to work with sparse IRQ
memory: omap-gpmc: Fix omap gpmc EXTRADELAY timing
arm: Use _rcuidle for smp_cross_call() tracepoints
MAINTAINERS: Add myself as reviewer of ARM FSL/NXP
ARM: OMAP: DRA7: powerdomain data: Remove unused pwrsts_mem_ret
ARM: OMAP: DRA7: powerdomain data: Remove unused pwrsts_logic_ret
ARM: OMAP: DRA7: powerdomain data: Set L3init and L4per to ON
ARM: imx6ul: Fix Micrel PHY mask
ARM: OMAP2+: Select OMAP_INTERCONNECT for SOC_AM43XX
ARM: dts: DRA74x: fix DSS PLL2 addresses
ARM: OMAP2: Enable Errata 430973 for OMAP3
ARM: dts: socfpga: Add missing PHY phandle
ARM: dts: exynos: Fix port nodes names for Exynos5420 Peach Pit board
ARM: dts: exynos: Fix port nodes names for Exynos5250 Snow board
ARM: dts: sun6i: yones-toptech-bs1078-v2: Drop constraints on dc1sw regulator
ARM: dts: sun6i: primo81: Drop constraints on dc1sw regulator
ARM: dts: sunxi: Add OLinuXino Lime2 eMMC to the Makefile
...

Linus Torvalds 049a40c0 c141afd1

+252 -136
+1
MAINTAINERS
··· 1159 1159 ARM/FREESCALE IMX / MXC ARM ARCHITECTURE 1160 1160 M: Shawn Guo <shawnguo@kernel.org> 1161 1161 M: Sascha Hauer <kernel@pengutronix.de> 1162 + R: Fabio Estevam <fabio.estevam@nxp.com> 1162 1163 L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) 1163 1164 S: Maintained 1164 1165 T: git git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git
+1
arch/arm/boot/dts/Makefile
··· 741 741 sun7i-a20-olimex-som-evb.dtb \ 742 742 sun7i-a20-olinuxino-lime.dtb \ 743 743 sun7i-a20-olinuxino-lime2.dtb \ 744 + sun7i-a20-olinuxino-lime2-emmc.dtb \ 744 745 sun7i-a20-olinuxino-micro.dtb \ 745 746 sun7i-a20-orangepi.dtb \ 746 747 sun7i-a20-orangepi-mini.dtb \
+1 -1
arch/arm/boot/dts/am437x-sk-evm.dts
··· 418 418 status = "okay"; 419 419 pinctrl-names = "default"; 420 420 pinctrl-0 = <&i2c0_pins>; 421 - clock-frequency = <400000>; 421 + clock-frequency = <100000>; 422 422 423 423 tps@24 { 424 424 compatible = "ti,tps65218";
+17 -15
arch/arm/boot/dts/am57xx-idk-common.dtsi
··· 60 60 61 61 tps659038_pmic { 62 62 compatible = "ti,tps659038-pmic"; 63 + 64 + smps12-in-supply = <&vmain>; 65 + smps3-in-supply = <&vmain>; 66 + smps45-in-supply = <&vmain>; 67 + smps6-in-supply = <&vmain>; 68 + smps7-in-supply = <&vmain>; 69 + smps8-in-supply = <&vmain>; 70 + smps9-in-supply = <&vmain>; 71 + ldo1-in-supply = <&vmain>; 72 + ldo2-in-supply = <&vmain>; 73 + ldo3-in-supply = <&vmain>; 74 + ldo4-in-supply = <&vmain>; 75 + ldo9-in-supply = <&vmain>; 76 + ldoln-in-supply = <&vmain>; 77 + ldousb-in-supply = <&vmain>; 78 + ldortc-in-supply = <&vmain>; 79 + 63 80 regulators { 64 81 smps12_reg: smps12 { 65 82 /* VDD_MPU */ 66 - vin-supply = <&vmain>; 67 83 regulator-name = "smps12"; 68 84 regulator-min-microvolt = <850000>; 69 85 regulator-max-microvolt = <1250000>; ··· 89 73 90 74 smps3_reg: smps3 { 91 75 /* VDD_DDR EMIF1 EMIF2 */ 92 - vin-supply = <&vmain>; 93 76 regulator-name = "smps3"; 94 77 regulator-min-microvolt = <1350000>; 95 78 regulator-max-microvolt = <1350000>; ··· 99 84 smps45_reg: smps45 { 100 85 /* VDD_DSPEVE on AM572 */ 101 86 /* VDD_IVA + VDD_DSP on AM571 */ 102 - vin-supply = <&vmain>; 103 87 regulator-name = "smps45"; 104 88 regulator-min-microvolt = <850000>; 105 89 regulator-max-microvolt = <1250000>; ··· 108 94 109 95 smps6_reg: smps6 { 110 96 /* VDD_GPU */ 111 - vin-supply = <&vmain>; 112 97 regulator-name = "smps6"; 113 98 regulator-min-microvolt = <850000>; 114 99 regulator-max-microvolt = <1250000>; ··· 117 104 118 105 smps7_reg: smps7 { 119 106 /* VDD_CORE */ 120 - vin-supply = <&vmain>; 121 107 regulator-name = "smps7"; 122 108 regulator-min-microvolt = <850000>; 123 109 regulator-max-microvolt = <1150000>; ··· 127 115 smps8_reg: smps8 { 128 116 /* 5728 - VDD_IVAHD */ 129 117 /* 5718 - N.C. test point */ 130 - vin-supply = <&vmain>; 131 118 regulator-name = "smps8"; 132 119 }; 133 120 134 121 smps9_reg: smps9 { 135 122 /* VDD_3_3D */ 136 - vin-supply = <&vmain>; 137 123 regulator-name = "smps9"; 138 124 regulator-min-microvolt = <3300000>; 139 125 regulator-max-microvolt = <3300000>; ··· 142 132 ldo1_reg: ldo1 { 143 133 /* VDDSHV8 - VSDMMC */ 144 134 /* NOTE: on rev 1.3a, data supply */ 145 - vin-supply = <&vmain>; 146 135 regulator-name = "ldo1"; 147 136 regulator-min-microvolt = <1800000>; 148 137 regulator-max-microvolt = <3300000>; ··· 151 142 152 143 ldo2_reg: ldo2 { 153 144 /* VDDSH18V */ 154 - vin-supply = <&vmain>; 155 145 regulator-name = "ldo2"; 156 146 regulator-min-microvolt = <1800000>; 157 147 regulator-max-microvolt = <1800000>; ··· 160 152 161 153 ldo3_reg: ldo3 { 162 154 /* R1.3a 572x V1_8PHY_LDO3: USB, SATA */ 163 - vin-supply = <&vmain>; 164 155 regulator-name = "ldo3"; 165 156 regulator-min-microvolt = <1800000>; 166 157 regulator-max-microvolt = <1800000>; ··· 169 162 170 163 ldo4_reg: ldo4 { 171 164 /* R1.3a 572x V1_8PHY_LDO4: PCIE, HDMI*/ 172 - vin-supply = <&vmain>; 173 165 regulator-name = "ldo4"; 174 166 regulator-min-microvolt = <1800000>; 175 167 regulator-max-microvolt = <1800000>; ··· 180 174 181 175 ldo9_reg: ldo9 { 182 176 /* VDD_RTC */ 183 - vin-supply = <&vmain>; 184 177 regulator-name = "ldo9"; 185 178 regulator-min-microvolt = <840000>; 186 179 regulator-max-microvolt = <1160000>; ··· 189 184 190 185 ldoln_reg: ldoln { 191 186 /* VDDA_1V8_PLL */ 192 - vin-supply = <&vmain>; 193 187 regulator-name = "ldoln"; 194 188 regulator-min-microvolt = <1800000>; 195 189 regulator-max-microvolt = <1800000>; ··· 198 194 199 195 ldousb_reg: ldousb { 200 196 /* VDDA_3V_USB: VDDA_USBHS33 */ 201 - vin-supply = <&vmain>; 202 197 regulator-name = "ldousb"; 203 198 regulator-min-microvolt = <3300000>; 204 199 regulator-max-microvolt = <3300000>; ··· 207 204 208 205 ldortc_reg: ldortc { 209 206 /* VDDA_RTC */ 210 - vin-supply = <&vmain>; 211 207 regulator-name = "ldortc"; 212 208 regulator-min-microvolt = <1800000>; 213 209 regulator-max-microvolt = <1800000>;
+8
arch/arm/boot/dts/dm8148-evm.dts
··· 93 93 }; 94 94 }; 95 95 96 + &mmc1 { 97 + status = "disabled"; 98 + }; 99 + 96 100 &mmc2 { 97 101 pinctrl-names = "default"; 98 102 pinctrl-0 = <&sd1_pins>; 99 103 vmmc-supply = <&vmmcsd_fixed>; 100 104 bus-width = <4>; 101 105 cd-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; 106 + }; 107 + 108 + &mmc3 { 109 + status = "disabled"; 102 110 }; 103 111 104 112 &pincntl {
+9
arch/arm/boot/dts/dm8148-t410.dts
··· 45 45 phy-mode = "rgmii"; 46 46 }; 47 47 48 + &mmc1 { 49 + status = "disabled"; 50 + }; 51 + 52 + &mmc2 { 53 + status = "disabled"; 54 + }; 55 + 48 56 &mmc3 { 49 57 pinctrl-names = "default"; 50 58 pinctrl-0 = <&sd2_pins>; ··· 61 53 dmas = <&edma_xbar 8 0 1 /* use SDTXEVT1 instead of MCASP0TX */ 62 54 &edma_xbar 9 0 2>; /* use SDRXEVT1 instead of MCASP0RX */ 63 55 dma-names = "tx", "rx"; 56 + non-removable; 64 57 }; 65 58 66 59 &pincntl {
+2
arch/arm/boot/dts/dra7.dtsi
··· 1451 1451 ti,hwmods = "gpmc"; 1452 1452 reg = <0x50000000 0x37c>; /* device IO registers */ 1453 1453 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1454 + dmas = <&edma_xbar 4 0>; 1455 + dma-names = "rxtx"; 1454 1456 gpmc,num-cs = <8>; 1455 1457 gpmc,num-waitpins = <2>; 1456 1458 #address-cells = <2>;
+2 -2
arch/arm/boot/dts/dra74x.dtsi
··· 107 107 reg = <0x58000000 0x80>, 108 108 <0x58004054 0x4>, 109 109 <0x58004300 0x20>, 110 - <0x58005054 0x4>, 111 - <0x58005300 0x20>; 110 + <0x58009054 0x4>, 111 + <0x58009300 0x20>; 112 112 reg-names = "dss", "pll1_clkctrl", "pll1", 113 113 "pll2_clkctrl", "pll2"; 114 114
+10 -3
arch/arm/boot/dts/exynos5250-snow-common.dtsi
··· 242 242 hpd-gpios = <&gpx0 7 GPIO_ACTIVE_HIGH>; 243 243 244 244 ports { 245 - port0 { 245 + port { 246 246 dp_out: endpoint { 247 247 remote-endpoint = <&bridge_in>; 248 248 }; ··· 485 485 edid-emulation = <5>; 486 486 487 487 ports { 488 - port0 { 488 + #address-cells = <1>; 489 + #size-cells = <0>; 490 + 491 + port@0 { 492 + reg = <0>; 493 + 489 494 bridge_out: endpoint { 490 495 remote-endpoint = <&panel_in>; 491 496 }; 492 497 }; 493 498 494 - port1 { 499 + port@1 { 500 + reg = <1>; 501 + 495 502 bridge_in: endpoint { 496 503 remote-endpoint = <&dp_out>; 497 504 };
+10 -3
arch/arm/boot/dts/exynos5420-peach-pit.dts
··· 163 163 hpd-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>; 164 164 165 165 ports { 166 - port0 { 166 + port { 167 167 dp_out: endpoint { 168 168 remote-endpoint = <&bridge_in>; 169 169 }; ··· 631 631 use-external-pwm; 632 632 633 633 ports { 634 - port0 { 634 + #address-cells = <1>; 635 + #size-cells = <0>; 636 + 637 + port@0 { 638 + reg = <0>; 639 + 635 640 bridge_out: endpoint { 636 641 remote-endpoint = <&panel_in>; 637 642 }; 638 643 }; 639 644 640 - port1 { 645 + port@1 { 646 + reg = <1>; 647 + 641 648 bridge_in: endpoint { 642 649 remote-endpoint = <&dp_out>; 643 650 };
+1 -1
arch/arm/boot/dts/omap3-evm-37xx.dts
··· 85 85 OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ 86 86 OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ 87 87 OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ 88 - OMAP3_CORE1_IOPAD(0x215e, WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ 88 + OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ 89 89 OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ 90 90 OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ 91 91 >;
+1
arch/arm/boot/dts/omap3-igep.dtsi
··· 188 188 vmmc-supply = <&vmmc1>; 189 189 vmmc_aux-supply = <&vsim>; 190 190 bus-width = <4>; 191 + cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_LOW>; 191 192 }; 192 193 193 194 &mmc3 {
+11
arch/arm/boot/dts/omap3-igep0020-common.dtsi
··· 194 194 OMAP3630_CORE2_IOPAD(0x25f8, PIN_OUTPUT | MUX_MODE4) /* etk_d14.gpio_28 */ 195 195 >; 196 196 }; 197 + 198 + mmc1_wp_pins: pinmux_mmc1_cd_pins { 199 + pinctrl-single,pins = < 200 + OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT | MUX_MODE4) /* etk_d15.gpio_29 */ 201 + >; 202 + }; 197 203 }; 198 204 199 205 &i2c3 { ··· 255 249 data-lines = <24>; 256 250 }; 257 251 }; 252 + }; 253 + 254 + &mmc1 { 255 + pinctrl-0 = <&mmc1_pins &mmc1_wp_pins>; 256 + wp-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; /* gpio_29 */ 258 257 };
+2 -2
arch/arm/boot/dts/omap3-n900.dts
··· 288 288 pinctrl-single,pins = < 289 289 OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLUP | MUX_MODE1) /* ssi1_rdy_tx */ 290 290 OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE1) /* ssi1_flag_tx */ 291 - OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | WAKEUP_EN | MUX_MODE4) /* ssi1_wake_tx (cawake) */ 291 + OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE4) /* ssi1_wake_tx (cawake) */ 292 292 OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE1) /* ssi1_dat_tx */ 293 293 OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT | MUX_MODE1) /* ssi1_dat_rx */ 294 294 OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE1) /* ssi1_flag_rx */ ··· 300 300 modem_pins: pinmux_modem { 301 301 pinctrl-single,pins = < 302 302 OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE4) /* gpio 70 => cmt_apeslpx */ 303 - OMAP3_CORE1_IOPAD(0x20e0, PIN_INPUT | WAKEUP_EN | MUX_MODE4) /* gpio 72 => ape_rst_rq */ 303 + OMAP3_CORE1_IOPAD(0x20e0, PIN_INPUT | MUX_MODE4) /* gpio 72 => ape_rst_rq */ 304 304 OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE4) /* gpio 73 => cmt_rst_rq */ 305 305 OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE4) /* gpio 74 => cmt_en */ 306 306 OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE4) /* gpio 75 => cmt_rst */
+3 -3
arch/arm/boot/dts/omap3-n950-n9.dtsi
··· 97 97 OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE1) /* ssi1_dat_tx */ 98 98 OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE1) /* ssi1_flag_tx */ 99 99 OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLUP | MUX_MODE1) /* ssi1_rdy_tx */ 100 - OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | WAKEUP_EN | MUX_MODE4) /* ssi1_wake_tx (cawake) */ 100 + OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE4) /* ssi1_wake_tx (cawake) */ 101 101 OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT | MUX_MODE1) /* ssi1_dat_rx */ 102 102 OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE1) /* ssi1_flag_rx */ 103 103 OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | MUX_MODE1) /* ssi1_rdy_rx */ ··· 110 110 OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE7) /* ssi1_dat_tx */ 111 111 OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE7) /* ssi1_flag_tx */ 112 112 OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLDOWN | MUX_MODE7) /* ssi1_rdy_tx */ 113 - OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | WAKEUP_EN | MUX_MODE4) /* ssi1_wake_tx (cawake) */ 113 + OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE4) /* ssi1_wake_tx (cawake) */ 114 114 OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT | MUX_MODE7) /* ssi1_dat_rx */ 115 115 OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE7) /* ssi1_flag_rx */ 116 116 OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | MUX_MODE4) /* ssi1_rdy_rx */ ··· 120 120 121 121 modem_pins1: pinmux_modem_core1_pins { 122 122 pinctrl-single,pins = < 123 - OMAP3_CORE1_IOPAD(0x207a, PIN_INPUT | WAKEUP_EN | MUX_MODE4) /* gpio_34 (ape_rst_rq) */ 123 + OMAP3_CORE1_IOPAD(0x207a, PIN_INPUT | MUX_MODE4) /* gpio_34 (ape_rst_rq) */ 124 124 OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE4) /* gpio_88 (cmt_rst_rq) */ 125 125 OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE4) /* gpio_93 (cmt_apeslpx) */ 126 126 >;
+3 -3
arch/arm/boot/dts/omap3-zoom3.dts
··· 98 98 pinctrl-single,pins = < 99 99 OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts */ 100 100 OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */ 101 - OMAP3_CORE1_IOPAD(0x217a, WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ 101 + OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ 102 102 OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ 103 103 >; 104 104 }; ··· 107 107 pinctrl-single,pins = < 108 108 OMAP3_CORE1_IOPAD(0x219a, PIN_INPUT_PULLDOWN | MUX_MODE0) /* uart3_cts_rctx.uart3_cts_rctx */ 109 109 OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_sd.uart3_rts_sd */ 110 - OMAP3_CORE1_IOPAD(0x219e, WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ 110 + OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ 111 111 OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ 112 112 >; 113 113 }; ··· 125 125 pinctrl-single,pins = < 126 126 OMAP3630_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */ 127 127 OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d4.sdmmc3_dat0 */ 128 - OMAP3630_CORE2_IOPAD(0x25e6, WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d5.sdmmc3_dat1 */ 128 + OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d5.sdmmc3_dat1 */ 129 129 OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d6.sdmmc3_dat2 */ 130 130 OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d3.sdmmc3_dat3 */ 131 131 >;
+46 -2
arch/arm/boot/dts/omap5-board-common.dtsi
··· 14 14 display0 = &hdmi0; 15 15 }; 16 16 17 + vmain: fixedregulator-vmain { 18 + compatible = "regulator-fixed"; 19 + regulator-name = "vmain"; 20 + regulator-min-microvolt = <5000000>; 21 + regulator-max-microvolt = <5000000>; 22 + }; 23 + 24 + vsys_cobra: fixedregulator-vsys_cobra { 25 + compatible = "regulator-fixed"; 26 + regulator-name = "vsys_cobra"; 27 + vin-supply = <&vmain>; 28 + regulator-min-microvolt = <5000000>; 29 + regulator-max-microvolt = <5000000>; 30 + }; 31 + 32 + vdds_1v8_main: fixedregulator-vdds_1v8_main { 33 + compatible = "regulator-fixed"; 34 + regulator-name = "vdds_1v8_main"; 35 + vin-supply = <&smps7_reg>; 36 + regulator-min-microvolt = <1800000>; 37 + regulator-max-microvolt = <1800000>; 38 + }; 39 + 17 40 vmmcsd_fixed: fixedregulator-mmcsd { 18 41 compatible = "regulator-fixed"; 19 42 regulator-name = "vmmcsd_fixed"; ··· 332 309 333 310 wlcore_irq_pin: pinmux_wlcore_irq_pin { 334 311 pinctrl-single,pins = < 335 - OMAP5_IOPAD(0x40, WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE6) /* llia_wakereqin.gpio1_wk14 */ 312 + OMAP5_IOPAD(0x40, PIN_INPUT_PULLUP | MUX_MODE6) /* llia_wakereqin.gpio1_wk14 */ 336 313 >; 337 314 }; 338 315 }; ··· 431 408 interrupt-names = "short-irq"; 432 409 433 410 ti,ldo6-vibrator; 411 + 412 + smps123-in-supply = <&vsys_cobra>; 413 + smps45-in-supply = <&vsys_cobra>; 414 + smps6-in-supply = <&vsys_cobra>; 415 + smps7-in-supply = <&vsys_cobra>; 416 + smps8-in-supply = <&vsys_cobra>; 417 + smps9-in-supply = <&vsys_cobra>; 418 + smps10_out2-in-supply = <&vsys_cobra>; 419 + smps10_out1-in-supply = <&vsys_cobra>; 420 + ldo1-in-supply = <&vsys_cobra>; 421 + ldo2-in-supply = <&vsys_cobra>; 422 + ldo3-in-supply = <&vdds_1v8_main>; 423 + ldo4-in-supply = <&vdds_1v8_main>; 424 + ldo5-in-supply = <&vsys_cobra>; 425 + ldo6-in-supply = <&vdds_1v8_main>; 426 + ldo7-in-supply = <&vsys_cobra>; 427 + ldo8-in-supply = <&vsys_cobra>; 428 + ldo9-in-supply = <&vmmcsd_fixed>; 429 + ldoln-in-supply = <&vsys_cobra>; 430 + ldousb-in-supply = <&vsys_cobra>; 434 431 435 432 regulators { 436 433 smps123_reg: smps123 { ··· 643 600 pinctrl-0 = <&twl6040_pins>; 644 601 645 602 interrupts = <GIC_SPI 119 IRQ_TYPE_NONE>; /* IRQ_SYS_2N cascaded to gic */ 646 - ti,audpwron-gpio = <&gpio5 13 GPIO_ACTIVE_HIGH>; /* gpio line 141 */ 603 + 604 + /* audpwron gpio defined in the board specific dts */ 647 605 648 606 vio-supply = <&smps7_reg>; 649 607 v2v1-supply = <&smps9_reg>;
+26
arch/arm/boot/dts/omap5-igep0050.dts
··· 35 35 }; 36 36 }; 37 37 38 + /* LDO4 is VPP1 - ball AD9 */ 39 + &ldo4_reg { 40 + regulator-min-microvolt = <2000000>; 41 + regulator-max-microvolt = <2000000>; 42 + }; 43 + 44 + /* 45 + * LDO7 is used for HDMI: VDDA_DSIPORTA - ball AA33, VDDA_DSIPORTC - ball AE33, 46 + * VDDA_HDMI - ball AN25 47 + */ 48 + &ldo7_reg { 49 + status = "okay"; 50 + regulator-min-microvolt = <1800000>; 51 + regulator-max-microvolt = <1800000>; 52 + }; 53 + 38 54 &omap5_pmx_core { 39 55 i2c4_pins: pinmux_i2c4_pins { 40 56 pinctrl-single,pins = < ··· 68 52 <&gpio7 3 0>; /* 195, SDA */ 69 53 }; 70 54 55 + &twl6040 { 56 + ti,audpwron-gpio = <&gpio5 16 GPIO_ACTIVE_HIGH>; /* gpio line 144 */ 57 + }; 58 + 59 + &twl6040_pins { 60 + pinctrl-single,pins = < 61 + OMAP5_IOPAD(0x1c4, PIN_OUTPUT | MUX_MODE6) /* mcspi1_somi.gpio5_144 */ 62 + OMAP5_IOPAD(0x1ca, PIN_OUTPUT | MUX_MODE6) /* perslimbus2_clock.gpio5_145 */ 63 + >; 64 + };
+10
arch/arm/boot/dts/omap5-uevm.dts
··· 51 51 <&gpio9 1 GPIO_ACTIVE_HIGH>, /* TCA6424A P00, LS OE */ 52 52 <&gpio7 1 GPIO_ACTIVE_HIGH>; /* GPIO 193, HPD */ 53 53 }; 54 + 55 + &twl6040 { 56 + ti,audpwron-gpio = <&gpio5 13 GPIO_ACTIVE_HIGH>; /* gpio line 141 */ 57 + }; 58 + 59 + &twl6040_pins { 60 + pinctrl-single,pins = < 61 + OMAP5_IOPAD(0x1be, PIN_OUTPUT | MUX_MODE6) /* mcspi1_somi.gpio5_141 */ 62 + >; 63 + };
+1
arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
··· 136 136 &gmac1 { 137 137 status = "okay"; 138 138 phy-mode = "rgmii"; 139 + phy-handle = <&phy1>; 139 140 140 141 snps,reset-gpio = <&porta 0 GPIO_ACTIVE_LOW>; 141 142 snps,reset-active-low;
+3
arch/arm/boot/dts/stih407-family.dtsi
··· 24 24 compatible = "shared-dma-pool"; 25 25 reg = <0x40000000 0x01000000>; 26 26 no-map; 27 + status = "disabled"; 27 28 }; 28 29 29 30 gp1_reserved: rproc@41000000 { 30 31 compatible = "shared-dma-pool"; 31 32 reg = <0x41000000 0x01000000>; 32 33 no-map; 34 + status = "disabled"; 33 35 }; 34 36 35 37 audio_reserved: rproc@42000000 { 36 38 compatible = "shared-dma-pool"; 37 39 reg = <0x42000000 0x01000000>; 38 40 no-map; 41 + status = "disabled"; 39 42 }; 40 43 41 44 dmu_reserved: rproc@43000000 {
-2
arch/arm/boot/dts/sun6i-a31s-primo81.dts
··· 176 176 }; 177 177 178 178 &reg_dc1sw { 179 - regulator-min-microvolt = <3000000>; 180 - regulator-max-microvolt = <3000000>; 181 179 regulator-name = "vcc-lcd"; 182 180 }; 183 181
-2
arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts
··· 135 135 136 136 &reg_dc1sw { 137 137 regulator-name = "vcc-lcd-usb2"; 138 - regulator-min-microvolt = <3000000>; 139 - regulator-max-microvolt = <3000000>; 140 138 }; 141 139 142 140 &reg_dc5ldo {
+1
arch/arm/configs/exynos_defconfig
··· 82 82 CONFIG_INPUT_MISC=y 83 83 CONFIG_INPUT_MAX77693_HAPTIC=y 84 84 CONFIG_INPUT_MAX8997_HAPTIC=y 85 + CONFIG_KEYBOARD_SAMSUNG=y 85 86 CONFIG_SERIAL_8250=y 86 87 CONFIG_SERIAL_SAMSUNG=y 87 88 CONFIG_SERIAL_SAMSUNG_CONSOLE=y
+1
arch/arm/configs/multi_v7_defconfig
··· 264 264 CONFIG_KEYBOARD_SPEAR=y 265 265 CONFIG_KEYBOARD_ST_KEYSCAN=y 266 266 CONFIG_KEYBOARD_CROS_EC=m 267 + CONFIG_KEYBOARD_SAMSUNG=m 267 268 CONFIG_MOUSE_PS2_ELANTECH=y 268 269 CONFIG_MOUSE_CYAPA=m 269 270 CONFIG_MOUSE_ELAN_I2C=y
+1 -1
arch/arm/kernel/smp.c
··· 486 486 487 487 static void smp_cross_call(const struct cpumask *target, unsigned int ipinr) 488 488 { 489 - trace_ipi_raise(target, ipi_types[ipinr]); 489 + trace_ipi_raise_rcuidle(target, ipi_types[ipinr]); 490 490 __smp_cross_call(target, ipinr); 491 491 } 492 492
-1
arch/arm/mach-exynos/Kconfig
··· 61 61 select CLKSRC_SAMSUNG_PWM if CPU_EXYNOS4210 62 62 select CPU_EXYNOS4210 63 63 select GIC_NON_BANKED 64 - select KEYBOARD_SAMSUNG if INPUT_KEYBOARD 65 64 select MIGHT_HAVE_CACHE_L2X0 66 65 help 67 66 Samsung EXYNOS4 (Cortex-A9) SoC based systems
+1 -1
arch/arm/mach-imx/mach-imx6ul.c
··· 46 46 static void __init imx6ul_enet_phy_init(void) 47 47 { 48 48 if (IS_BUILTIN(CONFIG_PHYLIB)) 49 - phy_register_fixup_for_uid(PHY_ID_KSZ8081, 0xffffffff, 49 + phy_register_fixup_for_uid(PHY_ID_KSZ8081, MICREL_PHY_ID_MASK, 50 50 ksz8081_phy_fixup); 51 51 } 52 52
+3 -3
arch/arm/mach-omap1/ams-delta-fiq-handler.S
··· 43 43 #define OTHERS_MASK (MODEM_IRQ_MASK | HOOK_SWITCH_MASK) 44 44 45 45 /* IRQ handler register bitmasks */ 46 - #define DEFERRED_FIQ_MASK (0x1 << (INT_DEFERRED_FIQ % IH2_BASE)) 47 - #define GPIO_BANK1_MASK (0x1 << INT_GPIO_BANK1) 46 + #define DEFERRED_FIQ_MASK OMAP_IRQ_BIT(INT_DEFERRED_FIQ) 47 + #define GPIO_BANK1_MASK OMAP_IRQ_BIT(INT_GPIO_BANK1) 48 48 49 49 /* Driver buffer byte offsets */ 50 50 #define BUF_MASK (FIQ_MASK * 4) ··· 110 110 mov r8, #2 @ reset FIQ agreement 111 111 str r8, [r12, #IRQ_CONTROL_REG_OFFSET] 112 112 113 - cmp r10, #INT_GPIO_BANK1 @ is it GPIO bank interrupt? 113 + cmp r10, #(INT_GPIO_BANK1 - NR_IRQS_LEGACY) @ is it GPIO interrupt? 114 114 beq gpio @ yes - process it 115 115 116 116 mov r8, #1
+3 -2
arch/arm/mach-omap1/ams-delta-fiq.c
··· 109 109 * Since no set_type() method is provided by OMAP irq chip, 110 110 * switch to edge triggered interrupt type manually. 111 111 */ 112 - offset = IRQ_ILR0_REG_OFFSET + INT_DEFERRED_FIQ * 0x4; 112 + offset = IRQ_ILR0_REG_OFFSET + 113 + ((INT_DEFERRED_FIQ - NR_IRQS_LEGACY) & 0x1f) * 0x4; 113 114 val = omap_readl(DEFERRED_FIQ_IH_BASE + offset) & ~(1 << 1); 114 115 omap_writel(val, DEFERRED_FIQ_IH_BASE + offset); 115 116 ··· 150 149 /* 151 150 * Redirect GPIO interrupts to FIQ 152 151 */ 153 - offset = IRQ_ILR0_REG_OFFSET + INT_GPIO_BANK1 * 0x4; 152 + offset = IRQ_ILR0_REG_OFFSET + (INT_GPIO_BANK1 - NR_IRQS_LEGACY) * 0x4; 154 153 val = omap_readl(OMAP_IH1_BASE + offset) | 1; 155 154 omap_writel(val, OMAP_IH1_BASE + offset); 156 155 }
+2
arch/arm/mach-omap1/include/mach/ams-delta-fiq.h
··· 14 14 #ifndef __AMS_DELTA_FIQ_H 15 15 #define __AMS_DELTA_FIQ_H 16 16 17 + #include <mach/irqs.h> 18 + 17 19 /* 18 20 * Interrupt number used for passing control from FIQ to IRQ. 19 21 * IRQ12, described as reserved, has been selected.
+12
arch/arm/mach-omap2/Kconfig
··· 17 17 select PM_OPP if PM 18 18 select PM if CPU_IDLE 19 19 select SOC_HAS_OMAP2_SDRC 20 + select ARM_ERRATA_430973 20 21 21 22 config ARCH_OMAP4 22 23 bool "TI OMAP4" ··· 37 36 select PM if CPU_IDLE 38 37 select ARM_ERRATA_754322 39 38 select ARM_ERRATA_775420 39 + select OMAP_INTERCONNECT 40 40 41 41 config SOC_OMAP5 42 42 bool "TI OMAP5" ··· 69 67 select HAVE_ARM_SCU 70 68 select GENERIC_CLOCKEVENTS_BROADCAST 71 69 select HAVE_ARM_TWD 70 + select ARM_ERRATA_754322 71 + select ARM_ERRATA_775420 72 72 73 73 config SOC_DRA7XX 74 74 bool "TI DRA7XX" ··· 243 239 endmenu 244 240 245 241 endif 242 + 243 + config OMAP5_ERRATA_801819 244 + bool "Errata 801819: An eviction from L1 data cache might stall indefinitely" 245 + depends on SOC_OMAP5 || SOC_DRA7XX 246 + help 247 + A livelock can occur in the L2 cache arbitration that might prevent 248 + a snoop from completing. Under certain conditions this can cause the 249 + system to deadlock. 246 250 247 251 endmenu
+1
arch/arm/mach-omap2/omap-secure.h
··· 46 46 47 47 #define OMAP5_DRA7_MON_SET_CNTFRQ_INDEX 0x109 48 48 #define OMAP5_MON_AMBA_IF_INDEX 0x108 49 + #define OMAP5_DRA7_MON_SET_ACR_INDEX 0x107 49 50 50 51 /* Secure PPA(Primary Protected Application) APIs */ 51 52 #define OMAP4_PPA_L2_POR_INDEX 0x23
+43 -5
arch/arm/mach-omap2/omap-smp.c
··· 50 50 return scu_base; 51 51 } 52 52 53 + #ifdef CONFIG_OMAP5_ERRATA_801819 54 + void omap5_erratum_workaround_801819(void) 55 + { 56 + u32 acr, revidr; 57 + u32 acr_mask; 58 + 59 + /* REVIDR[3] indicates erratum fix available on silicon */ 60 + asm volatile ("mrc p15, 0, %0, c0, c0, 6" : "=r" (revidr)); 61 + if (revidr & (0x1 << 3)) 62 + return; 63 + 64 + asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr)); 65 + /* 66 + * BIT(27) - Disables streaming. All write-allocate lines allocate in 67 + * the L1 or L2 cache. 68 + * BIT(25) - Disables streaming. All write-allocate lines allocate in 69 + * the L1 cache. 70 + */ 71 + acr_mask = (0x3 << 25) | (0x3 << 27); 72 + /* do we already have it done.. if yes, skip expensive smc */ 73 + if ((acr & acr_mask) == acr_mask) 74 + return; 75 + 76 + acr |= acr_mask; 77 + omap_smc1(OMAP5_DRA7_MON_SET_ACR_INDEX, acr); 78 + 79 + pr_debug("%s: ARM erratum workaround 801819 applied on CPU%d\n", 80 + __func__, smp_processor_id()); 81 + } 82 + #else 83 + static inline void omap5_erratum_workaround_801819(void) { } 84 + #endif 85 + 53 86 static void omap4_secondary_init(unsigned int cpu) 54 87 { 55 88 /* ··· 97 64 omap_secure_dispatcher(OMAP4_PPA_CPU_ACTRL_SMP_INDEX, 98 65 4, 0, 0, 0, 0, 0); 99 66 100 - /* 101 - * Configure the CNTFRQ register for the secondary cpu's which 102 - * indicates the frequency of the cpu local timers. 103 - */ 104 - if (soc_is_omap54xx() || soc_is_dra7xx()) 67 + if (soc_is_omap54xx() || soc_is_dra7xx()) { 68 + /* 69 + * Configure the CNTFRQ register for the secondary cpu's which 70 + * indicates the frequency of the cpu local timers. 71 + */ 105 72 set_cntfreq(); 73 + /* Configure ACR to disable streaming WA for 801819 */ 74 + omap5_erratum_workaround_801819(); 75 + } 106 76 107 77 /* 108 78 * Synchronise with the boot thread. ··· 254 218 255 219 if (cpu_is_omap446x()) 256 220 startup_addr = omap4460_secondary_startup; 221 + if (soc_is_dra74x() || soc_is_omap54xx()) 222 + omap5_erratum_workaround_801819(); 257 223 258 224 /* 259 225 * Write the address of secondary startup routine into the
+5 -4
arch/arm/mach-omap2/powerdomain.c
··· 186 186 trace_state = (PWRDM_TRACE_STATES_FLAG | 187 187 ((next & OMAP_POWERSTATE_MASK) << 8) | 188 188 ((prev & OMAP_POWERSTATE_MASK) << 0)); 189 - trace_power_domain_target(pwrdm->name, trace_state, 190 - smp_processor_id()); 189 + trace_power_domain_target_rcuidle(pwrdm->name, 190 + trace_state, 191 + smp_processor_id()); 191 192 } 192 193 break; 193 194 default: ··· 524 523 525 524 if (arch_pwrdm && arch_pwrdm->pwrdm_set_next_pwrst) { 526 525 /* Trace the pwrdm desired target state */ 527 - trace_power_domain_target(pwrdm->name, pwrst, 528 - smp_processor_id()); 526 + trace_power_domain_target_rcuidle(pwrdm->name, pwrst, 527 + smp_processor_id()); 529 528 /* Program the pwrdm desired target state */ 530 529 ret = arch_pwrdm->pwrdm_set_next_pwrst(pwrdm, pwrst); 531 530 }
+2 -74
arch/arm/mach-omap2/powerdomains7xx_data.c
··· 36 36 .prcm_offs = DRA7XX_PRM_IVA_INST, 37 37 .prcm_partition = DRA7XX_PRM_PARTITION, 38 38 .pwrsts = PWRSTS_OFF_ON, 39 - .pwrsts_logic_ret = PWRSTS_OFF, 40 39 .banks = 4, 41 - .pwrsts_mem_ret = { 42 - [0] = PWRSTS_OFF_RET, /* hwa_mem */ 43 - [1] = PWRSTS_OFF_RET, /* sl2_mem */ 44 - [2] = PWRSTS_OFF_RET, /* tcm1_mem */ 45 - [3] = PWRSTS_OFF_RET, /* tcm2_mem */ 46 - }, 47 40 .pwrsts_mem_on = { 48 41 [0] = PWRSTS_ON, /* hwa_mem */ 49 42 [1] = PWRSTS_ON, /* sl2_mem */ ··· 69 76 .prcm_offs = DRA7XX_PRM_IPU_INST, 70 77 .prcm_partition = DRA7XX_PRM_PARTITION, 71 78 .pwrsts = PWRSTS_OFF_ON, 72 - .pwrsts_logic_ret = PWRSTS_OFF, 73 79 .banks = 2, 74 - .pwrsts_mem_ret = { 75 - [0] = PWRSTS_OFF_RET, /* aessmem */ 76 - [1] = PWRSTS_OFF_RET, /* periphmem */ 77 - }, 78 80 .pwrsts_mem_on = { 79 81 [0] = PWRSTS_ON, /* aessmem */ 80 82 [1] = PWRSTS_ON, /* periphmem */ ··· 83 95 .prcm_offs = DRA7XX_PRM_DSS_INST, 84 96 .prcm_partition = DRA7XX_PRM_PARTITION, 85 97 .pwrsts = PWRSTS_OFF_ON, 86 - .pwrsts_logic_ret = PWRSTS_OFF, 87 98 .banks = 1, 88 - .pwrsts_mem_ret = { 89 - [0] = PWRSTS_OFF_RET, /* dss_mem */ 90 - }, 91 99 .pwrsts_mem_on = { 92 100 [0] = PWRSTS_ON, /* dss_mem */ 93 101 }, ··· 95 111 .name = "l4per_pwrdm", 96 112 .prcm_offs = DRA7XX_PRM_L4PER_INST, 97 113 .prcm_partition = DRA7XX_PRM_PARTITION, 98 - .pwrsts = PWRSTS_RET_ON, 99 - .pwrsts_logic_ret = PWRSTS_RET, 114 + .pwrsts = PWRSTS_ON, 100 115 .banks = 2, 101 - .pwrsts_mem_ret = { 102 - [0] = PWRSTS_OFF_RET, /* nonretained_bank */ 103 - [1] = PWRSTS_OFF_RET, /* retained_bank */ 104 - }, 105 116 .pwrsts_mem_on = { 106 117 [0] = PWRSTS_ON, /* nonretained_bank */ 107 118 [1] = PWRSTS_ON, /* retained_bank */ ··· 111 132 .prcm_partition = DRA7XX_PRM_PARTITION, 112 133 .pwrsts = PWRSTS_OFF_ON, 113 134 .banks = 1, 114 - .pwrsts_mem_ret = { 115 - [0] = PWRSTS_OFF_RET, /* gpu_mem */ 116 - }, 117 135 .pwrsts_mem_on = { 118 136 [0] = PWRSTS_ON, /* gpu_mem */ 119 137 }, ··· 124 148 .prcm_partition = DRA7XX_PRM_PARTITION, 125 149 .pwrsts = PWRSTS_ON, 126 150 .banks = 1, 127 - .pwrsts_mem_ret = { 128 - }, 129 151 .pwrsts_mem_on = { 130 152 [0] = PWRSTS_ON, /* wkup_bank */ 131 153 }, ··· 135 161 .prcm_offs = DRA7XX_PRM_CORE_INST, 136 162 .prcm_partition = DRA7XX_PRM_PARTITION, 137 163 .pwrsts = PWRSTS_ON, 138 - .pwrsts_logic_ret = PWRSTS_RET, 139 164 .banks = 5, 140 - .pwrsts_mem_ret = { 141 - [0] = PWRSTS_OFF_RET, /* core_nret_bank */ 142 - [1] = PWRSTS_OFF_RET, /* core_ocmram */ 143 - [2] = PWRSTS_OFF_RET, /* core_other_bank */ 144 - [3] = PWRSTS_OFF_RET, /* ipu_l2ram */ 145 - [4] = PWRSTS_OFF_RET, /* ipu_unicache */ 146 - }, 147 165 .pwrsts_mem_on = { 148 166 [0] = PWRSTS_ON, /* core_nret_bank */ 149 167 [1] = PWRSTS_ON, /* core_ocmram */ ··· 192 226 .prcm_offs = DRA7XX_PRM_VPE_INST, 193 227 .prcm_partition = DRA7XX_PRM_PARTITION, 194 228 .pwrsts = PWRSTS_OFF_ON, 195 - .pwrsts_logic_ret = PWRSTS_OFF, 196 229 .banks = 1, 197 - .pwrsts_mem_ret = { 198 - [0] = PWRSTS_OFF_RET, /* vpe_bank */ 199 - }, 200 230 .pwrsts_mem_on = { 201 231 [0] = PWRSTS_ON, /* vpe_bank */ 202 232 }, ··· 222 260 .name = "l3init_pwrdm", 223 261 .prcm_offs = DRA7XX_PRM_L3INIT_INST, 224 262 .prcm_partition = DRA7XX_PRM_PARTITION, 225 - .pwrsts = PWRSTS_RET_ON, 226 - .pwrsts_logic_ret = PWRSTS_RET, 263 + .pwrsts = PWRSTS_ON, 227 264 .banks = 3, 228 - .pwrsts_mem_ret = { 229 - [0] = PWRSTS_OFF_RET, /* gmac_bank */ 230 - [1] = PWRSTS_OFF_RET, /* l3init_bank1 */ 231 - [2] = PWRSTS_OFF_RET, /* l3init_bank2 */ 232 - }, 233 265 .pwrsts_mem_on = { 234 266 [0] = PWRSTS_ON, /* gmac_bank */ 235 267 [1] = PWRSTS_ON, /* l3init_bank1 */ ··· 239 283 .prcm_partition = DRA7XX_PRM_PARTITION, 240 284 .pwrsts = PWRSTS_OFF_ON, 241 285 .banks = 1, 242 - .pwrsts_mem_ret = { 243 - [0] = PWRSTS_OFF_RET, /* eve3_bank */ 244 - }, 245 286 .pwrsts_mem_on = { 246 287 [0] = PWRSTS_ON, /* eve3_bank */ 247 288 }, ··· 252 299 .prcm_partition = DRA7XX_PRM_PARTITION, 253 300 .pwrsts = PWRSTS_OFF_ON, 254 301 .banks = 1, 255 - .pwrsts_mem_ret = { 256 - [0] = PWRSTS_OFF_RET, /* emu_bank */ 257 - }, 258 302 .pwrsts_mem_on = { 259 303 [0] = PWRSTS_ON, /* emu_bank */ 260 304 }, ··· 264 314 .prcm_partition = DRA7XX_PRM_PARTITION, 265 315 .pwrsts = PWRSTS_OFF_ON, 266 316 .banks = 3, 267 - .pwrsts_mem_ret = { 268 - [0] = PWRSTS_OFF_RET, /* dsp2_edma */ 269 - [1] = PWRSTS_OFF_RET, /* dsp2_l1 */ 270 - [2] = PWRSTS_OFF_RET, /* dsp2_l2 */ 271 - }, 272 317 .pwrsts_mem_on = { 273 318 [0] = PWRSTS_ON, /* dsp2_edma */ 274 319 [1] = PWRSTS_ON, /* dsp2_l1 */ ··· 279 334 .prcm_partition = DRA7XX_PRM_PARTITION, 280 335 .pwrsts = PWRSTS_OFF_ON, 281 336 .banks = 3, 282 - .pwrsts_mem_ret = { 283 - [0] = PWRSTS_OFF_RET, /* dsp1_edma */ 284 - [1] = PWRSTS_OFF_RET, /* dsp1_l1 */ 285 - [2] = PWRSTS_OFF_RET, /* dsp1_l2 */ 286 - }, 287 337 .pwrsts_mem_on = { 288 338 [0] = PWRSTS_ON, /* dsp1_edma */ 289 339 [1] = PWRSTS_ON, /* dsp1_l1 */ ··· 294 354 .prcm_partition = DRA7XX_PRM_PARTITION, 295 355 .pwrsts = PWRSTS_OFF_ON, 296 356 .banks = 1, 297 - .pwrsts_mem_ret = { 298 - [0] = PWRSTS_OFF_RET, /* vip_bank */ 299 - }, 300 357 .pwrsts_mem_on = { 301 358 [0] = PWRSTS_ON, /* vip_bank */ 302 359 }, ··· 307 370 .prcm_partition = DRA7XX_PRM_PARTITION, 308 371 .pwrsts = PWRSTS_OFF_ON, 309 372 .banks = 1, 310 - .pwrsts_mem_ret = { 311 - [0] = PWRSTS_OFF_RET, /* eve4_bank */ 312 - }, 313 373 .pwrsts_mem_on = { 314 374 [0] = PWRSTS_ON, /* eve4_bank */ 315 375 }, ··· 320 386 .prcm_partition = DRA7XX_PRM_PARTITION, 321 387 .pwrsts = PWRSTS_OFF_ON, 322 388 .banks = 1, 323 - .pwrsts_mem_ret = { 324 - [0] = PWRSTS_OFF_RET, /* eve2_bank */ 325 - }, 326 389 .pwrsts_mem_on = { 327 390 [0] = PWRSTS_ON, /* eve2_bank */ 328 391 }, ··· 333 402 .prcm_partition = DRA7XX_PRM_PARTITION, 334 403 .pwrsts = PWRSTS_OFF_ON, 335 404 .banks = 1, 336 - .pwrsts_mem_ret = { 337 - [0] = PWRSTS_OFF_RET, /* eve1_bank */ 338 - }, 339 405 .pwrsts_mem_on = { 340 406 [0] = PWRSTS_ON, /* eve1_bank */ 341 407 },
+5 -2
arch/arm/mach-omap2/timer.c
··· 496 496 __omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon", 497 497 2, "timer_sys_ck", NULL, false); 498 498 499 - if (of_have_populated_dt()) 500 - clocksource_probe(); 499 + clocksource_probe(); 501 500 } 502 501 503 502 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM43XX) ··· 504 505 { 505 506 __omap_sync32k_timer_init(12, "secure_32k_fck", "ti,timer-secure", 506 507 2, "timer_sys_ck", NULL, false); 508 + 509 + clocksource_probe(); 507 510 } 508 511 #endif /* CONFIG_ARCH_OMAP3 */ 509 512 ··· 514 513 { 515 514 __omap_sync32k_timer_init(2, "timer_sys_ck", NULL, 516 515 1, "timer_sys_ck", "ti,timer-alwon", true); 516 + 517 + clocksource_probe(); 517 518 } 518 519 #endif 519 520
+1 -1
arch/arm/plat-samsung/devs.c
··· 68 68 #include <linux/platform_data/asoc-s3c.h> 69 69 #include <linux/platform_data/spi-s3c64xx.h> 70 70 71 - static u64 samsung_device_dma_mask = DMA_BIT_MASK(32); 71 + #define samsung_device_dma_mask (*((u64[]) { DMA_BIT_MASK(32) })) 72 72 73 73 /* AC97 */ 74 74 #ifdef CONFIG_CPU_S3C2440
+1 -1
arch/arm64/boot/dts/lg/lg1312.dtsi
··· 125 125 #size-cells = <1>; 126 126 #interrupts-cells = <3>; 127 127 128 - compatible = "arm,amba-bus"; 128 + compatible = "simple-bus"; 129 129 interrupt-parent = <&gic>; 130 130 ranges; 131 131
+1 -1
arch/arm64/boot/dts/rockchip/rk3399.dtsi
··· 163 163 }; 164 164 165 165 amba { 166 - compatible = "arm,amba-bus"; 166 + compatible = "simple-bus"; 167 167 #address-cells = <2>; 168 168 #size-cells = <2>; 169 169 ranges;
+1 -1
drivers/memory/omap-gpmc.c
··· 398 398 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4, 399 399 GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay); 400 400 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4, 401 - GPMC_CONFIG4_OEEXTRADELAY, p->we_extra_delay); 401 + GPMC_CONFIG4_WEEXTRADELAY, p->we_extra_delay); 402 402 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6, 403 403 GPMC_CONFIG6_CYCLE2CYCLESAMECSEN, 404 404 p->cycle2cyclesamecsen);