Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-for-v4.7-rc2' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie:
"A bunch of ARM drivers got into the fixes vibe this time around, so
this contains a bunch of fixes for imx, atmel hlcdc, arm hdlcd (only
so many combos of hlcd), mediatek and omap drm.
Other than that there is one mgag200 fix and a few core drm regression
fixes"
* tag 'drm-fixes-for-v4.7-rc2' of git://people.freedesktop.org/~airlied/linux: (34 commits)
drm/omap: fix unused variable warning.
drm: hdlcd: Add information about the underlying framebuffers in debugfs
drm: hdlcd: Cleanup the atomic plane operations
drm/hdlcd: Fix up crtc_state->event handling
drm: hdlcd: Revamp runtime power management
drm/mediatek: mtk_dsi: Remove spurious drm_connector_unregister
drm/mediatek: mtk_dpi: remove invalid error message
drm: atmel-hlcdc: fix a NULL check
drm: atmel-hlcdc: fix atmel_hlcdc_crtc_reset() implementation
drm/mgag200: Black screen fix for G200e rev 4
drm: Wrap direct calls to driver->gem_free_object from CMA
drm: fix fb refcount issue with atomic modesetting
drm: make drm_atomic_set_mode_prop_for_crtc() more reliable
drm/sti: remove extra mode fixup
drm: add missing drm_mode_set_crtcinfo call
drm/omap: include gpio/consumer.h where needed
drm/omap: include linux/seq_file.h where needed
Revert "drm/omap: no need to select OMAP2_DSS"
drm/omap: Remove regulator API abuse
OMAPDSS: HDMI5: Change DDC timings
...
+225
-226
+1
Documentation/devicetree/bindings/display/imx/ldb.txt
+1
Documentation/devicetree/bindings/display/imx/ldb.txt
···
62
62
display-timings are used instead.
63
63
64
64
Optional properties (required if display-timings are used):
65
+
- ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
65
66
- display-timings : A node that describes the display timings as defined in
66
67
Documentation/devicetree/bindings/display/display-timing.txt.
67
68
- fsl,data-mapping : should be "spwg" or "jeida"
+48
-38
drivers/gpu/drm/arm/hdlcd_crtc.c
+48
-38
drivers/gpu/drm/arm/hdlcd_crtc.c
···
33
33
*
34
34
*/
35
35
36
+
static void hdlcd_crtc_cleanup(struct drm_crtc *crtc)
37
+
{
38
+
struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
39
+
40
+
/* stop the controller on cleanup */
41
+
hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0);
42
+
drm_crtc_cleanup(crtc);
43
+
}
44
+
36
45
static const struct drm_crtc_funcs hdlcd_crtc_funcs = {
37
-
.destroy = drm_crtc_cleanup,
46
+
.destroy = hdlcd_crtc_cleanup,
38
47
.set_config = drm_atomic_helper_set_config,
39
48
.page_flip = drm_atomic_helper_page_flip,
40
49
.reset = drm_atomic_helper_crtc_reset,
···
106
97
struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
107
98
struct drm_display_mode *m = &crtc->state->adjusted_mode;
108
99
struct videomode vm;
109
-
unsigned int polarities, line_length, err;
100
+
unsigned int polarities, err;
110
101
111
102
vm.vfront_porch = m->crtc_vsync_start - m->crtc_vdisplay;
112
103
vm.vback_porch = m->crtc_vtotal - m->crtc_vsync_end;
···
122
113
if (m->flags & DRM_MODE_FLAG_PVSYNC)
123
114
polarities |= HDLCD_POLARITY_VSYNC;
124
115
125
-
line_length = crtc->primary->state->fb->pitches[0];
126
-
127
116
/* Allow max number of outstanding requests and largest burst size */
128
117
hdlcd_write(hdlcd, HDLCD_REG_BUS_OPTIONS,
129
118
HDLCD_BUS_MAX_OUTSTAND | HDLCD_BUS_BURST_16);
130
119
131
-
hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_LENGTH, line_length);
132
-
hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_PITCH, line_length);
133
-
hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_COUNT, m->crtc_vdisplay - 1);
134
120
hdlcd_write(hdlcd, HDLCD_REG_V_DATA, m->crtc_vdisplay - 1);
135
121
hdlcd_write(hdlcd, HDLCD_REG_V_BACK_PORCH, vm.vback_porch - 1);
136
122
hdlcd_write(hdlcd, HDLCD_REG_V_FRONT_PORCH, vm.vfront_porch - 1);
137
123
hdlcd_write(hdlcd, HDLCD_REG_V_SYNC, vm.vsync_len - 1);
124
+
hdlcd_write(hdlcd, HDLCD_REG_H_DATA, m->crtc_hdisplay - 1);
138
125
hdlcd_write(hdlcd, HDLCD_REG_H_BACK_PORCH, vm.hback_porch - 1);
139
126
hdlcd_write(hdlcd, HDLCD_REG_H_FRONT_PORCH, vm.hfront_porch - 1);
140
127
hdlcd_write(hdlcd, HDLCD_REG_H_SYNC, vm.hsync_len - 1);
141
-
hdlcd_write(hdlcd, HDLCD_REG_H_DATA, m->crtc_hdisplay - 1);
142
128
hdlcd_write(hdlcd, HDLCD_REG_POLARITIES, polarities);
143
129
144
130
err = hdlcd_set_pxl_fmt(crtc);
···
148
144
struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
149
145
150
146
clk_prepare_enable(hdlcd->clk);
147
+
hdlcd_crtc_mode_set_nofb(crtc);
151
148
hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 1);
152
-
drm_crtc_vblank_on(crtc);
153
149
}
154
150
155
151
static void hdlcd_crtc_disable(struct drm_crtc *crtc)
156
152
{
157
153
struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
158
154
159
-
if (!crtc->primary->fb)
155
+
if (!crtc->state->active)
160
156
return;
161
157
162
-
clk_disable_unprepare(hdlcd->clk);
163
158
hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0);
164
-
drm_crtc_vblank_off(crtc);
159
+
clk_disable_unprepare(hdlcd->clk);
165
160
}
166
161
167
162
static int hdlcd_crtc_atomic_check(struct drm_crtc *crtc,
···
182
179
static void hdlcd_crtc_atomic_begin(struct drm_crtc *crtc,
183
180
struct drm_crtc_state *state)
184
181
{
185
-
struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
186
-
unsigned long flags;
182
+
struct drm_pending_vblank_event *event = crtc->state->event;
187
183
188
-
if (crtc->state->event) {
189
-
struct drm_pending_vblank_event *event = crtc->state->event;
190
-
184
+
if (event) {
191
185
crtc->state->event = NULL;
192
-
event->pipe = drm_crtc_index(crtc);
193
186
194
-
WARN_ON(drm_crtc_vblank_get(crtc) != 0);
195
-
196
-
spin_lock_irqsave(&crtc->dev->event_lock, flags);
197
-
list_add_tail(&event->base.link, &hdlcd->event_list);
198
-
spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
187
+
spin_lock_irq(&crtc->dev->event_lock);
188
+
if (drm_crtc_vblank_get(crtc) == 0)
189
+
drm_crtc_arm_vblank_event(crtc, event);
190
+
else
191
+
drm_crtc_send_vblank_event(crtc, event);
192
+
spin_unlock_irq(&crtc->dev->event_lock);
199
193
}
200
194
}
201
195
···
225
225
static int hdlcd_plane_atomic_check(struct drm_plane *plane,
226
226
struct drm_plane_state *state)
227
227
{
228
+
u32 src_w, src_h;
229
+
230
+
src_w = state->src_w >> 16;
231
+
src_h = state->src_h >> 16;
232
+
233
+
/* we can't do any scaling of the plane source */
234
+
if ((src_w != state->crtc_w) || (src_h != state->crtc_h))
235
+
return -EINVAL;
236
+
228
237
return 0;
229
238
}
230
239
···
242
233
{
243
234
struct hdlcd_drm_private *hdlcd;
244
235
struct drm_gem_cma_object *gem;
236
+
unsigned int depth, bpp;
237
+
u32 src_w, src_h, dest_w, dest_h;
245
238
dma_addr_t scanout_start;
246
239
247
-
if (!plane->state->crtc || !plane->state->fb)
240
+
if (!plane->state->fb)
248
241
return;
249
242
250
-
hdlcd = crtc_to_hdlcd_priv(plane->state->crtc);
243
+
drm_fb_get_bpp_depth(plane->state->fb->pixel_format, &depth, &bpp);
244
+
src_w = plane->state->src_w >> 16;
245
+
src_h = plane->state->src_h >> 16;
246
+
dest_w = plane->state->crtc_w;
247
+
dest_h = plane->state->crtc_h;
251
248
gem = drm_fb_cma_get_gem_obj(plane->state->fb, 0);
252
-
scanout_start = gem->paddr;
249
+
scanout_start = gem->paddr + plane->state->fb->offsets[0] +
250
+
plane->state->crtc_y * plane->state->fb->pitches[0] +
251
+
plane->state->crtc_x * bpp / 8;
252
+
253
+
hdlcd = plane->dev->dev_private;
254
+
hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_LENGTH, plane->state->fb->pitches[0]);
255
+
hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_PITCH, plane->state->fb->pitches[0]);
256
+
hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_COUNT, dest_h - 1);
253
257
hdlcd_write(hdlcd, HDLCD_REG_FB_BASE, scanout_start);
254
258
}
255
259
256
260
static const struct drm_plane_helper_funcs hdlcd_plane_helper_funcs = {
257
-
.prepare_fb = NULL,
258
-
.cleanup_fb = NULL,
259
261
.atomic_check = hdlcd_plane_atomic_check,
260
262
.atomic_update = hdlcd_plane_atomic_update,
261
263
};
···
312
292
hdlcd->plane = plane;
313
293
314
294
return plane;
315
-
}
316
-
317
-
void hdlcd_crtc_suspend(struct drm_crtc *crtc)
318
-
{
319
-
hdlcd_crtc_disable(crtc);
320
-
}
321
-
322
-
void hdlcd_crtc_resume(struct drm_crtc *crtc)
323
-
{
324
-
hdlcd_crtc_enable(crtc);
325
295
}
326
296
327
297
int hdlcd_setup_crtc(struct drm_device *drm)
+29
-39
drivers/gpu/drm/arm/hdlcd_drv.c
+29
-39
drivers/gpu/drm/arm/hdlcd_drv.c
···
49
49
atomic_set(&hdlcd->dma_end_count, 0);
50
50
#endif
51
51
52
-
INIT_LIST_HEAD(&hdlcd->event_list);
53
-
54
52
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
55
53
hdlcd->mmio = devm_ioremap_resource(drm->dev, res);
56
54
if (IS_ERR(hdlcd->mmio)) {
···
82
84
goto setup_fail;
83
85
}
84
86
85
-
pm_runtime_enable(drm->dev);
86
-
87
-
pm_runtime_get_sync(drm->dev);
88
87
ret = drm_irq_install(drm, platform_get_irq(pdev, 0));
89
-
pm_runtime_put_sync(drm->dev);
90
88
if (ret < 0) {
91
89
DRM_ERROR("failed to install IRQ handler\n");
92
90
goto irq_fail;
···
158
164
atomic_inc(&hdlcd->vsync_count);
159
165
160
166
#endif
161
-
if (irq_status & HDLCD_INTERRUPT_VSYNC) {
162
-
bool events_sent = false;
163
-
unsigned long flags;
164
-
struct drm_pending_vblank_event *e, *t;
165
-
167
+
if (irq_status & HDLCD_INTERRUPT_VSYNC)
166
168
drm_crtc_handle_vblank(&hdlcd->crtc);
167
-
168
-
spin_lock_irqsave(&drm->event_lock, flags);
169
-
list_for_each_entry_safe(e, t, &hdlcd->event_list, base.link) {
170
-
list_del(&e->base.link);
171
-
drm_crtc_send_vblank_event(&hdlcd->crtc, e);
172
-
events_sent = true;
173
-
}
174
-
if (events_sent)
175
-
drm_crtc_vblank_put(&hdlcd->crtc);
176
-
spin_unlock_irqrestore(&drm->event_lock, flags);
177
-
}
178
169
179
170
/* acknowledge interrupt(s) */
180
171
hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, irq_status);
···
254
275
static struct drm_info_list hdlcd_debugfs_list[] = {
255
276
{ "interrupt_count", hdlcd_show_underrun_count, 0 },
256
277
{ "clocks", hdlcd_show_pxlclock, 0 },
278
+
{ "fb", drm_fb_cma_debugfs_show, 0 },
257
279
};
258
280
259
281
static int hdlcd_debugfs_init(struct drm_minor *minor)
···
337
357
return -ENOMEM;
338
358
339
359
drm->dev_private = hdlcd;
360
+
dev_set_drvdata(dev, drm);
361
+
340
362
hdlcd_setup_mode_config(drm);
341
363
ret = hdlcd_load(drm, 0);
342
364
if (ret)
···
348
366
if (ret)
349
367
goto err_unload;
350
368
351
-
dev_set_drvdata(dev, drm);
352
-
353
369
ret = component_bind_all(dev, drm);
354
370
if (ret) {
355
371
DRM_ERROR("Failed to bind all components\n");
356
372
goto err_unregister;
357
373
}
374
+
375
+
ret = pm_runtime_set_active(dev);
376
+
if (ret)
377
+
goto err_pm_active;
378
+
379
+
pm_runtime_enable(dev);
358
380
359
381
ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
360
382
if (ret < 0) {
···
385
399
drm_mode_config_cleanup(drm);
386
400
drm_vblank_cleanup(drm);
387
401
err_vblank:
402
+
pm_runtime_disable(drm->dev);
403
+
err_pm_active:
388
404
component_unbind_all(dev, drm);
389
405
err_unregister:
390
406
drm_dev_unregister(drm);
391
407
err_unload:
392
-
pm_runtime_get_sync(drm->dev);
393
408
drm_irq_uninstall(drm);
394
-
pm_runtime_put_sync(drm->dev);
395
-
pm_runtime_disable(drm->dev);
396
409
of_reserved_mem_device_release(drm->dev);
397
410
err_free:
411
+
dev_set_drvdata(dev, NULL);
398
412
drm_dev_unref(drm);
399
413
400
414
return ret;
···
481
495
static int __maybe_unused hdlcd_pm_suspend(struct device *dev)
482
496
{
483
497
struct drm_device *drm = dev_get_drvdata(dev);
484
-
struct drm_crtc *crtc;
498
+
struct hdlcd_drm_private *hdlcd = drm ? drm->dev_private : NULL;
485
499
486
-
if (pm_runtime_suspended(dev))
500
+
if (!hdlcd)
487
501
return 0;
488
502
489
-
drm_modeset_lock_all(drm);
490
-
list_for_each_entry(crtc, &drm->mode_config.crtc_list, head)
491
-
hdlcd_crtc_suspend(crtc);
492
-
drm_modeset_unlock_all(drm);
503
+
drm_kms_helper_poll_disable(drm);
504
+
505
+
hdlcd->state = drm_atomic_helper_suspend(drm);
506
+
if (IS_ERR(hdlcd->state)) {
507
+
drm_kms_helper_poll_enable(drm);
508
+
return PTR_ERR(hdlcd->state);
509
+
}
510
+
493
511
return 0;
494
512
}
495
513
496
514
static int __maybe_unused hdlcd_pm_resume(struct device *dev)
497
515
{
498
516
struct drm_device *drm = dev_get_drvdata(dev);
499
-
struct drm_crtc *crtc;
517
+
struct hdlcd_drm_private *hdlcd = drm ? drm->dev_private : NULL;
500
518
501
-
if (!pm_runtime_suspended(dev))
519
+
if (!hdlcd)
502
520
return 0;
503
521
504
-
drm_modeset_lock_all(drm);
505
-
list_for_each_entry(crtc, &drm->mode_config.crtc_list, head)
506
-
hdlcd_crtc_resume(crtc);
507
-
drm_modeset_unlock_all(drm);
522
+
drm_atomic_helper_resume(drm, hdlcd->state);
523
+
drm_kms_helper_poll_enable(drm);
524
+
pm_runtime_set_active(dev);
525
+
508
526
return 0;
509
527
}
510
528
+1
-4
drivers/gpu/drm/arm/hdlcd_drv.h
+1
-4
drivers/gpu/drm/arm/hdlcd_drv.h
···
9
9
void __iomem *mmio;
10
10
struct clk *clk;
11
11
struct drm_fbdev_cma *fbdev;
12
-
struct drm_framebuffer *fb;
13
-
struct list_head event_list;
14
12
struct drm_crtc crtc;
15
13
struct drm_plane *plane;
14
+
struct drm_atomic_state *state;
16
15
#ifdef CONFIG_DEBUG_FS
17
16
atomic_t buffer_underrun_count;
18
17
atomic_t bus_error_count;
···
35
36
36
37
int hdlcd_setup_crtc(struct drm_device *dev);
37
38
void hdlcd_set_scanout(struct hdlcd_drm_private *hdlcd);
38
-
void hdlcd_crtc_suspend(struct drm_crtc *crtc);
39
-
void hdlcd_crtc_resume(struct drm_crtc *crtc);
40
39
41
40
#endif /* __HDLCD_DRV_H__ */
+5
-5
drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
+5
-5
drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
···
391
391
{
392
392
struct atmel_hlcdc_crtc_state *state;
393
393
394
-
if (crtc->state && crtc->state->mode_blob)
395
-
drm_property_unreference_blob(crtc->state->mode_blob);
396
-
397
394
if (crtc->state) {
395
+
__drm_atomic_helper_crtc_destroy_state(crtc->state);
398
396
state = drm_crtc_state_to_atmel_hlcdc_crtc_state(crtc->state);
399
397
kfree(state);
398
+
crtc->state = NULL;
400
399
}
401
400
402
401
state = kzalloc(sizeof(*state), GFP_KERNEL);
···
414
415
return NULL;
415
416
416
417
state = kmalloc(sizeof(*state), GFP_KERNEL);
417
-
if (state)
418
-
__drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
418
+
if (!state)
419
+
return NULL;
420
+
__drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
419
421
420
422
cur = drm_crtc_state_to_atmel_hlcdc_crtc_state(crtc->state);
421
423
state->output_mode = cur->output_mode;
+2
-1
drivers/gpu/drm/drm_atomic.c
+2
-1
drivers/gpu/drm/drm_atomic.c
···
351
351
drm_property_unreference_blob(state->mode_blob);
352
352
state->mode_blob = NULL;
353
353
354
+
memset(&state->mode, 0, sizeof(state->mode));
355
+
354
356
if (blob) {
355
357
if (blob->length != sizeof(struct drm_mode_modeinfo) ||
356
358
drm_mode_convert_umode(&state->mode,
···
365
363
DRM_DEBUG_ATOMIC("Set [MODE:%s] for CRTC state %p\n",
366
364
state->mode.name, state);
367
365
} else {
368
-
memset(&state->mode, 0, sizeof(state->mode));
369
366
state->enable = false;
370
367
DRM_DEBUG_ATOMIC("Set [NOMODE] for CRTC state %p\n",
371
368
state);
+2
-3
drivers/gpu/drm/drm_crtc.c
+2
-3
drivers/gpu/drm/drm_crtc.c
···
2821
2821
goto out;
2822
2822
}
2823
2823
2824
-
drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V);
2825
-
2826
2824
/*
2827
2825
* Check whether the primary plane supports the fb pixel format.
2828
2826
* Drivers not implementing the universal planes API use a
···
4839
4841
if (value == 0)
4840
4842
return true;
4841
4843
4842
-
return _object_find(property->dev, value, property->values[0]) != NULL;
4844
+
*ref = _object_find(property->dev, value, property->values[0]);
4845
+
return *ref != NULL;
4843
4846
}
4844
4847
4845
4848
for (i = 0; i < property->num_values; i++)
+1
-1
drivers/gpu/drm/drm_fb_cma_helper.c
+1
-1
drivers/gpu/drm/drm_fb_cma_helper.c
+3
-9
drivers/gpu/drm/drm_gem_cma_helper.c
+3
-9
drivers/gpu/drm/drm_gem_cma_helper.c
···
121
121
return cma_obj;
122
122
123
123
error:
124
-
drm->driver->gem_free_object(&cma_obj->base);
124
+
drm_gem_object_unreference_unlocked(&cma_obj->base);
125
125
return ERR_PTR(ret);
126
126
}
127
127
EXPORT_SYMBOL_GPL(drm_gem_cma_create);
···
162
162
* and handle has the id what user can see.
163
163
*/
164
164
ret = drm_gem_handle_create(file_priv, gem_obj, handle);
165
-
if (ret)
166
-
goto err_handle_create;
167
-
168
165
/* drop reference from allocate - handle holds it now. */
169
166
drm_gem_object_unreference_unlocked(gem_obj);
167
+
if (ret)
168
+
return ERR_PTR(ret);
170
169
171
170
return cma_obj;
172
-
173
-
err_handle_create:
174
-
drm->driver->gem_free_object(gem_obj);
175
-
176
-
return ERR_PTR(ret);
177
171
}
178
172
179
173
/**
+2
drivers/gpu/drm/drm_modes.c
+2
drivers/gpu/drm/drm_modes.c
+8
-5
drivers/gpu/drm/imx/imx-drm-core.c
+8
-5
drivers/gpu/drm/imx/imx-drm-core.c
···
97
97
return NULL;
98
98
}
99
99
100
-
int imx_drm_set_bus_format_pins(struct drm_encoder *encoder, u32 bus_format,
101
-
int hsync_pin, int vsync_pin)
100
+
int imx_drm_set_bus_config(struct drm_encoder *encoder, u32 bus_format,
101
+
int hsync_pin, int vsync_pin, u32 bus_flags)
102
102
{
103
103
struct imx_drm_crtc_helper_funcs *helper;
104
104
struct imx_drm_crtc *imx_crtc;
···
110
110
helper = &imx_crtc->imx_drm_helper_funcs;
111
111
if (helper->set_interface_pix_fmt)
112
112
return helper->set_interface_pix_fmt(encoder->crtc,
113
-
bus_format, hsync_pin, vsync_pin);
113
+
bus_format, hsync_pin, vsync_pin,
114
+
bus_flags);
114
115
return 0;
115
116
}
116
-
EXPORT_SYMBOL_GPL(imx_drm_set_bus_format_pins);
117
+
EXPORT_SYMBOL_GPL(imx_drm_set_bus_config);
117
118
118
119
int imx_drm_set_bus_format(struct drm_encoder *encoder, u32 bus_format)
119
120
{
120
-
return imx_drm_set_bus_format_pins(encoder, bus_format, 2, 3);
121
+
return imx_drm_set_bus_config(encoder, bus_format, 2, 3,
122
+
DRM_BUS_FLAG_DE_HIGH |
123
+
DRM_BUS_FLAG_PIXDATA_NEGEDGE);
121
124
}
122
125
EXPORT_SYMBOL_GPL(imx_drm_set_bus_format);
123
126
+4
-3
drivers/gpu/drm/imx/imx-drm.h
+4
-3
drivers/gpu/drm/imx/imx-drm.h
···
19
19
int (*enable_vblank)(struct drm_crtc *crtc);
20
20
void (*disable_vblank)(struct drm_crtc *crtc);
21
21
int (*set_interface_pix_fmt)(struct drm_crtc *crtc,
22
-
u32 bus_format, int hsync_pin, int vsync_pin);
22
+
u32 bus_format, int hsync_pin, int vsync_pin,
23
+
u32 bus_flags);
23
24
const struct drm_crtc_helper_funcs *crtc_helper_funcs;
24
25
const struct drm_crtc_funcs *crtc_funcs;
25
26
};
···
42
41
43
42
struct drm_gem_cma_object *imx_drm_fb_get_obj(struct drm_framebuffer *fb);
44
43
45
-
int imx_drm_set_bus_format_pins(struct drm_encoder *encoder,
46
-
u32 bus_format, int hsync_pin, int vsync_pin);
44
+
int imx_drm_set_bus_config(struct drm_encoder *encoder, u32 bus_format,
45
+
int hsync_pin, int vsync_pin, u32 bus_flags);
47
46
int imx_drm_set_bus_format(struct drm_encoder *encoder,
48
47
u32 bus_format);
49
48
+52
-24
drivers/gpu/drm/imx/imx-ldb.c
+52
-24
drivers/gpu/drm/imx/imx-ldb.c
···
25
25
#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
26
26
#include <linux/of_device.h>
27
27
#include <linux/of_graph.h>
28
+
#include <video/of_display_timing.h>
28
29
#include <video/of_videomode.h>
29
30
#include <linux/regmap.h>
30
31
#include <linux/videodev2.h>
···
60
59
struct drm_encoder encoder;
61
60
struct drm_panel *panel;
62
61
struct device_node *child;
62
+
struct i2c_adapter *ddc;
63
63
int chno;
64
64
void *edid;
65
65
int edid_len;
···
108
106
if (num_modes > 0)
109
107
return num_modes;
110
108
}
109
+
110
+
if (!imx_ldb_ch->edid && imx_ldb_ch->ddc)
111
+
imx_ldb_ch->edid = drm_get_edid(connector, imx_ldb_ch->ddc);
111
112
112
113
if (imx_ldb_ch->edid) {
113
114
drm_mode_connector_update_edid_property(connector,
···
558
553
559
554
for_each_child_of_node(np, child) {
560
555
struct imx_ldb_channel *channel;
561
-
struct device_node *port;
556
+
struct device_node *ddc_node;
557
+
struct device_node *ep;
562
558
563
559
ret = of_property_read_u32(child, "reg", &i);
564
560
if (ret || i < 0 || i > 1)
···
582
576
* The output port is port@4 with an external 4-port mux or
583
577
* port@2 with the internal 2-port mux.
584
578
*/
585
-
port = of_graph_get_port_by_id(child, imx_ldb->lvds_mux ? 4 : 2);
586
-
if (port) {
587
-
struct device_node *endpoint, *remote;
579
+
ep = of_graph_get_endpoint_by_regs(child,
580
+
imx_ldb->lvds_mux ? 4 : 2,
581
+
-1);
582
+
if (ep) {
583
+
struct device_node *remote;
588
584
589
-
endpoint = of_get_child_by_name(port, "endpoint");
590
-
if (endpoint) {
591
-
remote = of_graph_get_remote_port_parent(endpoint);
592
-
if (remote)
593
-
channel->panel = of_drm_find_panel(remote);
594
-
else
595
-
return -EPROBE_DEFER;
596
-
if (!channel->panel) {
597
-
dev_err(dev, "panel not found: %s\n",
598
-
remote->full_name);
599
-
return -EPROBE_DEFER;
600
-
}
585
+
remote = of_graph_get_remote_port_parent(ep);
586
+
of_node_put(ep);
587
+
if (remote)
588
+
channel->panel = of_drm_find_panel(remote);
589
+
else
590
+
return -EPROBE_DEFER;
591
+
of_node_put(remote);
592
+
if (!channel->panel) {
593
+
dev_err(dev, "panel not found: %s\n",
594
+
remote->full_name);
595
+
return -EPROBE_DEFER;
601
596
}
602
597
}
603
598
604
-
edidp = of_get_property(child, "edid", &channel->edid_len);
605
-
if (edidp) {
606
-
channel->edid = kmemdup(edidp, channel->edid_len,
607
-
GFP_KERNEL);
608
-
} else if (!channel->panel) {
609
-
ret = of_get_drm_display_mode(child, &channel->mode, 0);
610
-
if (!ret)
611
-
channel->mode_valid = 1;
599
+
ddc_node = of_parse_phandle(child, "ddc-i2c-bus", 0);
600
+
if (ddc_node) {
601
+
channel->ddc = of_find_i2c_adapter_by_node(ddc_node);
602
+
of_node_put(ddc_node);
603
+
if (!channel->ddc) {
604
+
dev_warn(dev, "failed to get ddc i2c adapter\n");
605
+
return -EPROBE_DEFER;
606
+
}
607
+
}
608
+
609
+
if (!channel->ddc) {
610
+
/* if no DDC available, fallback to hardcoded EDID */
611
+
dev_dbg(dev, "no ddc available\n");
612
+
613
+
edidp = of_get_property(child, "edid",
614
+
&channel->edid_len);
615
+
if (edidp) {
616
+
channel->edid = kmemdup(edidp,
617
+
channel->edid_len,
618
+
GFP_KERNEL);
619
+
} else if (!channel->panel) {
620
+
/* fallback to display-timings node */
621
+
ret = of_get_drm_display_mode(child,
622
+
&channel->mode,
623
+
OF_USE_NATIVE_MODE);
624
+
if (!ret)
625
+
channel->mode_valid = 1;
626
+
}
612
627
}
613
628
614
629
channel->bus_format = of_get_bus_format(dev, child);
···
674
647
channel->encoder.funcs->destroy(&channel->encoder);
675
648
676
649
kfree(channel->edid);
650
+
i2c_put_adapter(channel->ddc);
677
651
}
678
652
}
679
653
+4
-2
drivers/gpu/drm/imx/imx-tve.c
+4
-2
drivers/gpu/drm/imx/imx-tve.c
···
294
294
295
295
switch (tve->mode) {
296
296
case TVE_MODE_VGA:
297
-
imx_drm_set_bus_format_pins(encoder, MEDIA_BUS_FMT_GBR888_1X24,
298
-
tve->hsync_pin, tve->vsync_pin);
297
+
imx_drm_set_bus_config(encoder, MEDIA_BUS_FMT_GBR888_1X24,
298
+
tve->hsync_pin, tve->vsync_pin,
299
+
DRM_BUS_FLAG_DE_HIGH |
300
+
DRM_BUS_FLAG_PIXDATA_NEGEDGE);
299
301
break;
300
302
case TVE_MODE_TVOUT:
301
303
imx_drm_set_bus_format(encoder, MEDIA_BUS_FMT_YUV8_1X24);
+7
-3
drivers/gpu/drm/imx/ipuv3-crtc.c
+7
-3
drivers/gpu/drm/imx/ipuv3-crtc.c
···
66
66
struct ipu_flip_work *flip_work;
67
67
int irq;
68
68
u32 bus_format;
69
+
u32 bus_flags;
69
70
int di_hsync_pin;
70
71
int di_vsync_pin;
71
72
};
···
272
271
else
273
272
sig_cfg.clkflags = 0;
274
273
275
-
sig_cfg.enable_pol = 1;
276
-
sig_cfg.clk_pol = 0;
274
+
sig_cfg.enable_pol = !(ipu_crtc->bus_flags & DRM_BUS_FLAG_DE_LOW);
275
+
/* Default to driving pixel data on negative clock edges */
276
+
sig_cfg.clk_pol = !!(ipu_crtc->bus_flags &
277
+
DRM_BUS_FLAG_PIXDATA_POSEDGE);
277
278
sig_cfg.bus_format = ipu_crtc->bus_format;
278
279
sig_cfg.v_to_h_sync = 0;
279
280
sig_cfg.hsync_pin = ipu_crtc->di_hsync_pin;
···
399
396
}
400
397
401
398
static int ipu_set_interface_pix_fmt(struct drm_crtc *crtc,
402
-
u32 bus_format, int hsync_pin, int vsync_pin)
399
+
u32 bus_format, int hsync_pin, int vsync_pin, u32 bus_flags)
403
400
{
404
401
struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
405
402
406
403
ipu_crtc->bus_format = bus_format;
404
+
ipu_crtc->bus_flags = bus_flags;
407
405
ipu_crtc->di_hsync_pin = hsync_pin;
408
406
ipu_crtc->di_vsync_pin = vsync_pin;
409
407
+3
-2
drivers/gpu/drm/imx/ipuv3-plane.c
+3
-2
drivers/gpu/drm/imx/ipuv3-plane.c
···
38
38
DRM_FORMAT_RGBX8888,
39
39
DRM_FORMAT_BGRA8888,
40
40
DRM_FORMAT_BGRA8888,
41
+
DRM_FORMAT_UYVY,
42
+
DRM_FORMAT_VYUY,
41
43
DRM_FORMAT_YUYV,
42
44
DRM_FORMAT_YVYU,
43
45
DRM_FORMAT_YUV420,
···
430
428
if (crtc != plane->crtc)
431
429
dev_dbg(plane->dev->dev, "crtc change: %p -> %p\n",
432
430
plane->crtc, crtc);
433
-
plane->crtc = crtc;
434
431
435
432
if (!ipu_plane->enabled)
436
433
ipu_plane_enable(ipu_plane);
···
462
461
kfree(ipu_plane);
463
462
}
464
463
465
-
static struct drm_plane_funcs ipu_plane_funcs = {
464
+
static const struct drm_plane_funcs ipu_plane_funcs = {
466
465
.update_plane = ipu_update_plane,
467
466
.disable_plane = ipu_disable_plane,
468
467
.destroy = ipu_plane_destroy,
+13
-25
drivers/gpu/drm/imx/parallel-display.c
+13
-25
drivers/gpu/drm/imx/parallel-display.c
···
35
35
void *edid;
36
36
int edid_len;
37
37
u32 bus_format;
38
-
int mode_valid;
39
38
struct drm_display_mode mode;
40
39
struct drm_panel *panel;
41
40
};
···
65
66
if (imxpd->edid) {
66
67
drm_mode_connector_update_edid_property(connector, imxpd->edid);
67
68
num_modes = drm_add_edid_modes(connector, imxpd->edid);
68
-
}
69
-
70
-
if (imxpd->mode_valid) {
71
-
struct drm_display_mode *mode = drm_mode_create(connector->dev);
72
-
73
-
if (!mode)
74
-
return -EINVAL;
75
-
drm_mode_copy(mode, &imxpd->mode);
76
-
mode->type |= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
77
-
drm_mode_probed_add(connector, mode);
78
-
num_modes++;
79
69
}
80
70
81
71
if (np) {
···
103
115
static void imx_pd_encoder_prepare(struct drm_encoder *encoder)
104
116
{
105
117
struct imx_parallel_display *imxpd = enc_to_imxpd(encoder);
106
-
107
-
imx_drm_set_bus_format(encoder, imxpd->bus_format);
118
+
imx_drm_set_bus_config(encoder, imxpd->bus_format, 2, 3,
119
+
imxpd->connector.display_info.bus_flags);
108
120
}
109
121
110
122
static void imx_pd_encoder_commit(struct drm_encoder *encoder)
···
191
203
{
192
204
struct drm_device *drm = data;
193
205
struct device_node *np = dev->of_node;
194
-
struct device_node *port;
206
+
struct device_node *ep;
195
207
const u8 *edidp;
196
208
struct imx_parallel_display *imxpd;
197
209
int ret;
···
218
230
}
219
231
220
232
/* port@1 is the output port */
221
-
port = of_graph_get_port_by_id(np, 1);
222
-
if (port) {
223
-
struct device_node *endpoint, *remote;
233
+
ep = of_graph_get_endpoint_by_regs(np, 1, -1);
234
+
if (ep) {
235
+
struct device_node *remote;
224
236
225
-
endpoint = of_get_child_by_name(port, "endpoint");
226
-
if (endpoint) {
227
-
remote = of_graph_get_remote_port_parent(endpoint);
228
-
if (remote)
229
-
imxpd->panel = of_drm_find_panel(remote);
230
-
if (!imxpd->panel)
231
-
return -EPROBE_DEFER;
237
+
remote = of_graph_get_remote_port_parent(ep);
238
+
of_node_put(ep);
239
+
if (remote) {
240
+
imxpd->panel = of_drm_find_panel(remote);
241
+
of_node_put(remote);
232
242
}
243
+
if (!imxpd->panel)
244
+
return -EPROBE_DEFER;
233
245
}
234
246
235
247
imxpd->dev = dev;
-5
drivers/gpu/drm/mediatek/mtk_dpi.c
-5
drivers/gpu/drm/mediatek/mtk_dpi.c
+1
-3
drivers/gpu/drm/mediatek/mtk_dsi.c
+1
-3
drivers/gpu/drm/mediatek/mtk_dsi.c
···
695
695
{
696
696
drm_encoder_cleanup(&dsi->encoder);
697
697
/* Skip connector cleanup if creation was delegated to the bridge */
698
-
if (dsi->conn.dev) {
699
-
drm_connector_unregister(&dsi->conn);
698
+
if (dsi->conn.dev)
700
699
drm_connector_cleanup(&dsi->conn);
701
-
}
702
700
}
703
701
704
702
static void mtk_dsi_ddp_start(struct mtk_ddp_comp *comp)
+9
-1
drivers/gpu/drm/mgag200/mgag200_mode.c
+9
-1
drivers/gpu/drm/mgag200/mgag200_mode.c
···
182
182
}
183
183
}
184
184
185
-
fvv = pllreffreq * testn / testm;
185
+
fvv = pllreffreq * (n + 1) / (m + 1);
186
186
fvv = (fvv - 800000) / 50000;
187
187
188
188
if (fvv > 15)
···
202
202
WREG_DAC(MGA1064_PIX_PLLC_M, m);
203
203
WREG_DAC(MGA1064_PIX_PLLC_N, n);
204
204
WREG_DAC(MGA1064_PIX_PLLC_P, p);
205
+
206
+
if (mdev->unique_rev_id >= 0x04) {
207
+
WREG_DAC(0x1a, 0x09);
208
+
msleep(20);
209
+
WREG_DAC(0x1a, 0x01);
210
+
211
+
}
212
+
205
213
return 0;
206
214
}
207
215
+1
drivers/gpu/drm/omapdrm/Kconfig
+1
drivers/gpu/drm/omapdrm/Kconfig
+1
drivers/gpu/drm/omapdrm/displays/connector-hdmi.c
+1
drivers/gpu/drm/omapdrm/displays/connector-hdmi.c
+1
-1
drivers/gpu/drm/omapdrm/displays/encoder-opa362.c
+1
-1
drivers/gpu/drm/omapdrm/displays/encoder-opa362.c
+1
-1
drivers/gpu/drm/omapdrm/displays/encoder-tfp410.c
+1
-1
drivers/gpu/drm/omapdrm/displays/encoder-tfp410.c
+1
-1
drivers/gpu/drm/omapdrm/displays/panel-dpi.c
+1
-1
drivers/gpu/drm/omapdrm/displays/panel-dpi.c
+1
-1
drivers/gpu/drm/omapdrm/displays/panel-dsi-cm.c
+1
-1
drivers/gpu/drm/omapdrm/displays/panel-dsi-cm.c
+1
drivers/gpu/drm/omapdrm/displays/panel-lgphilips-lb035q02.c
+1
drivers/gpu/drm/omapdrm/displays/panel-lgphilips-lb035q02.c
+1
-1
drivers/gpu/drm/omapdrm/displays/panel-nec-nl8048hl11.c
+1
-1
drivers/gpu/drm/omapdrm/displays/panel-nec-nl8048hl11.c
+1
-1
drivers/gpu/drm/omapdrm/displays/panel-sharp-ls037v7dw01.c
+1
-1
drivers/gpu/drm/omapdrm/displays/panel-sharp-ls037v7dw01.c
+1
-1
drivers/gpu/drm/omapdrm/displays/panel-sony-acx565akm.c
+1
-1
drivers/gpu/drm/omapdrm/displays/panel-sony-acx565akm.c
+1
-1
drivers/gpu/drm/omapdrm/displays/panel-tpo-td043mtea1.c
+1
-1
drivers/gpu/drm/omapdrm/displays/panel-tpo-td043mtea1.c
-9
drivers/gpu/drm/omapdrm/dss/dsi.c
-9
drivers/gpu/drm/omapdrm/dss/dsi.c
···
1180
1180
return PTR_ERR(vdds_dsi);
1181
1181
}
1182
1182
1183
-
if (regulator_can_change_voltage(vdds_dsi)) {
1184
-
r = regulator_set_voltage(vdds_dsi, 1800000, 1800000);
1185
-
if (r) {
1186
-
devm_regulator_put(vdds_dsi);
1187
-
DSSERR("can't set the DSI regulator voltage\n");
1188
-
return r;
1189
-
}
1190
-
}
1191
-
1192
1183
dsi->vdds_dsi_reg = vdds_dsi;
1193
1184
1194
1185
return 0;
+1
drivers/gpu/drm/omapdrm/dss/dss.c
+1
drivers/gpu/drm/omapdrm/dss/dss.c
+1
-10
drivers/gpu/drm/omapdrm/dss/hdmi4.c
+1
-10
drivers/gpu/drm/omapdrm/dss/hdmi4.c
···
33
33
#include <linux/gpio.h>
34
34
#include <linux/regulator/consumer.h>
35
35
#include <linux/component.h>
36
+
#include <linux/of.h>
36
37
#include <video/omapdss.h>
37
38
#include <sound/omap-hdmi-audio.h>
38
39
···
101
100
102
101
static int hdmi_init_regulator(void)
103
102
{
104
-
int r;
105
103
struct regulator *reg;
106
104
107
105
if (hdmi.vdda_reg != NULL)
···
112
112
if (PTR_ERR(reg) != -EPROBE_DEFER)
113
113
DSSERR("can't get VDDA regulator\n");
114
114
return PTR_ERR(reg);
115
-
}
116
-
117
-
if (regulator_can_change_voltage(reg)) {
118
-
r = regulator_set_voltage(reg, 1800000, 1800000);
119
-
if (r) {
120
-
devm_regulator_put(reg);
121
-
DSSWARN("can't set the regulator voltage\n");
122
-
return r;
123
-
}
124
115
}
125
116
126
117
hdmi.vdda_reg = reg;
+1
-1
drivers/gpu/drm/omapdrm/dss/hdmi4_core.c
+1
-1
drivers/gpu/drm/omapdrm/dss/hdmi4_core.c
···
211
211
static void hdmi_core_powerdown_disable(struct hdmi_core_data *core)
212
212
{
213
213
DSSDBG("Enter hdmi_core_powerdown_disable\n");
214
-
REG_FLD_MOD(core->base, HDMI_CORE_SYS_SYS_CTRL1, 0x0, 0, 0);
214
+
REG_FLD_MOD(core->base, HDMI_CORE_SYS_SYS_CTRL1, 0x1, 0, 0);
215
215
}
216
216
217
217
static void hdmi_core_swreset_release(struct hdmi_core_data *core)
+1
-9
drivers/gpu/drm/omapdrm/dss/hdmi5.c
+1
-9
drivers/gpu/drm/omapdrm/dss/hdmi5.c
···
38
38
#include <linux/gpio.h>
39
39
#include <linux/regulator/consumer.h>
40
40
#include <linux/component.h>
41
+
#include <linux/of.h>
41
42
#include <video/omapdss.h>
42
43
#include <sound/omap-hdmi-audio.h>
43
44
···
130
129
if (IS_ERR(reg)) {
131
130
DSSERR("can't get VDDA regulator\n");
132
131
return PTR_ERR(reg);
133
-
}
134
-
135
-
if (regulator_can_change_voltage(reg)) {
136
-
r = regulator_set_voltage(reg, 1800000, 1800000);
137
-
if (r) {
138
-
devm_regulator_put(reg);
139
-
DSSWARN("can't set the regulator voltage\n");
140
-
return r;
141
-
}
142
132
}
143
133
144
134
hdmi.vdda_reg = reg;
+3
-3
drivers/gpu/drm/omapdrm/dss/hdmi5_core.c
+3
-3
drivers/gpu/drm/omapdrm/dss/hdmi5_core.c
···
51
51
{
52
52
void __iomem *base = core->base;
53
53
const unsigned long long iclk = 266000000; /* DSS L3 ICLK */
54
-
const unsigned ss_scl_high = 4000; /* ns */
55
-
const unsigned ss_scl_low = 4700; /* ns */
54
+
const unsigned ss_scl_high = 4600; /* ns */
55
+
const unsigned ss_scl_low = 5400; /* ns */
56
56
const unsigned fs_scl_high = 600; /* ns */
57
57
const unsigned fs_scl_low = 1300; /* ns */
58
58
const unsigned sda_hold = 1000; /* ns */
···
458
458
459
459
c = (ptr[1] >> 6) & 0x3;
460
460
m = (ptr[1] >> 4) & 0x3;
461
-
r = (ptr[1] >> 0) & 0x3;
461
+
r = (ptr[1] >> 0) & 0xf;
462
462
463
463
itc = (ptr[2] >> 7) & 0x1;
464
464
ec = (ptr[2] >> 4) & 0x7;
+1
drivers/gpu/drm/omapdrm/dss/hdmi_phy.c
+1
drivers/gpu/drm/omapdrm/dss/hdmi_phy.c
+1
drivers/gpu/drm/omapdrm/dss/hdmi_pll.c
+1
drivers/gpu/drm/omapdrm/dss/hdmi_pll.c
+1
drivers/gpu/drm/omapdrm/dss/hdmi_wp.c
+1
drivers/gpu/drm/omapdrm/dss/hdmi_wp.c
+2
drivers/gpu/drm/omapdrm/omap_debugfs.c
+2
drivers/gpu/drm/omapdrm/omap_debugfs.c
+1
drivers/gpu/drm/omapdrm/omap_dmm_tiler.c
+1
drivers/gpu/drm/omapdrm/omap_dmm_tiler.c
+2
drivers/gpu/drm/omapdrm/omap_fb.c
+2
drivers/gpu/drm/omapdrm/omap_fb.c
+1
drivers/gpu/drm/omapdrm/omap_gem.c
+1
drivers/gpu/drm/omapdrm/omap_gem.c
-10
drivers/gpu/drm/sti/sti_crtc.c
-10
drivers/gpu/drm/sti/sti_crtc.c
···
51
51
mixer->status = STI_MIXER_DISABLING;
52
52
}
53
53
54
-
static bool sti_crtc_mode_fixup(struct drm_crtc *crtc,
55
-
const struct drm_display_mode *mode,
56
-
struct drm_display_mode *adjusted_mode)
57
-
{
58
-
/* accept the provided drm_display_mode, do not fix it up */
59
-
drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
60
-
return true;
61
-
}
62
-
63
54
static int
64
55
sti_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode)
65
56
{
···
221
230
static const struct drm_crtc_helper_funcs sti_crtc_helper_funcs = {
222
231
.enable = sti_crtc_enable,
223
232
.disable = sti_crtc_disabling,
224
-
.mode_fixup = sti_crtc_mode_fixup,
225
233
.mode_set = drm_helper_crtc_mode_set,
226
234
.mode_set_nofb = sti_crtc_mode_set_nofb,
227
235
.mode_set_base = drm_helper_crtc_mode_set_base,
+3
-3
drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c
+3
-3
drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c
···
51
51
{
52
52
void __iomem *base = core->base;
53
53
const unsigned long long iclk = 266000000; /* DSS L3 ICLK */
54
-
const unsigned ss_scl_high = 4000; /* ns */
55
-
const unsigned ss_scl_low = 4700; /* ns */
54
+
const unsigned ss_scl_high = 4600; /* ns */
55
+
const unsigned ss_scl_low = 5400; /* ns */
56
56
const unsigned fs_scl_high = 600; /* ns */
57
57
const unsigned fs_scl_low = 1300; /* ns */
58
58
const unsigned sda_hold = 1000; /* ns */
···
442
442
443
443
c = (ptr[1] >> 6) & 0x3;
444
444
m = (ptr[1] >> 4) & 0x3;
445
-
r = (ptr[1] >> 0) & 0x3;
445
+
r = (ptr[1] >> 0) & 0xf;
446
446
447
447
itc = (ptr[2] >> 7) & 0x1;
448
448
ec = (ptr[2] >> 4) & 0x7;