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iommu/vt-d: Flush piotlb for SVM and Nested domain

Besides the paging domains that use FS, SVM and Nested domains need to
use piotlb invalidation descriptor as well.

Fixes: b33125296b50 ("iommu/vt-d: Create unique domain ops for each stage")
Cc: stable@vger.kernel.org
Signed-off-by: Yi Liu <yi.l.liu@intel.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
Link: https://lore.kernel.org/r/20251223065824.6164-1-yi.l.liu@intel.com
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>

authored by

Yi Liu and committed by
Joerg Roedel 04b1b069 22d169bd

+8 -1
+8 -1
drivers/iommu/intel/cache.c
··· 363 363 qi_batch_increment_index(iommu, batch); 364 364 } 365 365 366 + static bool intel_domain_use_piotlb(struct dmar_domain *domain) 367 + { 368 + return domain->domain.type == IOMMU_DOMAIN_SVA || 369 + domain->domain.type == IOMMU_DOMAIN_NESTED || 370 + intel_domain_is_fs_paging(domain); 371 + } 372 + 366 373 static void cache_tag_flush_iotlb(struct dmar_domain *domain, struct cache_tag *tag, 367 374 unsigned long addr, unsigned long pages, 368 375 unsigned long mask, int ih) ··· 377 370 struct intel_iommu *iommu = tag->iommu; 378 371 u64 type = DMA_TLB_PSI_FLUSH; 379 372 380 - if (intel_domain_is_fs_paging(domain)) { 373 + if (intel_domain_use_piotlb(domain)) { 381 374 qi_batch_add_piotlb(iommu, tag->domain_id, tag->pasid, addr, 382 375 pages, ih, domain->qi_batch); 383 376 return;