Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch '20240430-a750-raytracing-v3-2-7f57c5ac082d@gmail.com' into drivers-for-6.11
Merge SMEM and SCM patches related to GPU features through a topic
branch to make it possible to share these with the msm-next DRM tree.
+108
-8
+14
drivers/firmware/qcom/qcom_scm.c
+14
drivers/firmware/qcom/qcom_scm.c
···
1393
1393
}
1394
1394
EXPORT_SYMBOL_GPL(qcom_scm_lmh_dcvsh);
1395
1395
1396
+
int qcom_scm_gpu_init_regs(u32 gpu_req)
1397
+
{
1398
+
struct qcom_scm_desc desc = {
1399
+
.svc = QCOM_SCM_SVC_GPU,
1400
+
.cmd = QCOM_SCM_SVC_GPU_INIT_REGS,
1401
+
.arginfo = QCOM_SCM_ARGS(1),
1402
+
.args[0] = gpu_req,
1403
+
.owner = ARM_SMCCC_OWNER_SIP,
1404
+
};
1405
+
1406
+
return qcom_scm_call(__scm->dev, &desc, NULL);
1407
+
}
1408
+
EXPORT_SYMBOL_GPL(qcom_scm_gpu_init_regs);
1409
+
1396
1410
static int qcom_scm_find_dload_address(struct device *dev, u64 *addr)
1397
1411
{
1398
1412
struct device_node *tcsr;
+3
drivers/firmware/qcom/qcom_scm.h
+3
drivers/firmware/qcom/qcom_scm.h
+33
drivers/soc/qcom/smem.c
+33
drivers/soc/qcom/smem.c
···
795
795
}
796
796
EXPORT_SYMBOL_GPL(qcom_smem_get_soc_id);
797
797
798
+
/**
799
+
* qcom_smem_get_feature_code() - return the feature code
800
+
* @code: On success, return the feature code here.
801
+
*
802
+
* Look up the feature code identifier from SMEM and return it.
803
+
*
804
+
* Return: 0 on success, negative errno on failure.
805
+
*/
806
+
int qcom_smem_get_feature_code(u32 *code)
807
+
{
808
+
struct socinfo *info;
809
+
u32 raw_code;
810
+
811
+
info = qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_HW_SW_BUILD_ID, NULL);
812
+
if (IS_ERR(info))
813
+
return PTR_ERR(info);
814
+
815
+
/* This only makes sense for socinfo >= 16 */
816
+
if (__le32_to_cpu(info->fmt) < SOCINFO_VERSION(0, 16))
817
+
return -EOPNOTSUPP;
818
+
819
+
raw_code = __le32_to_cpu(info->feature_code);
820
+
821
+
/* Ensure the value makes sense */
822
+
if (raw_code > SOCINFO_FC_INT_MAX)
823
+
raw_code = SOCINFO_FC_UNKNOWN;
824
+
825
+
*code = raw_code;
826
+
827
+
return 0;
828
+
}
829
+
EXPORT_SYMBOL_GPL(qcom_smem_get_feature_code);
830
+
798
831
static int qcom_smem_get_sbl_version(struct qcom_smem *smem)
799
832
{
800
833
struct smem_header *header;
-8
drivers/soc/qcom/socinfo.c
-8
drivers/soc/qcom/socinfo.c
···
21
21
22
22
#include <dt-bindings/arm/qcom,ids.h>
23
23
24
-
/*
25
-
* SoC version type with major number in the upper 16 bits and minor
26
-
* number in the lower 16 bits.
27
-
*/
28
-
#define SOCINFO_MAJOR(ver) (((ver) >> 16) & 0xffff)
29
-
#define SOCINFO_MINOR(ver) ((ver) & 0xffff)
30
-
#define SOCINFO_VERSION(maj, min) ((((maj) & 0xffff) << 16)|((min) & 0xffff))
31
-
32
24
/* Helper macros to create soc_id table */
33
25
#define qcom_board_id(id) QCOM_ID_ ## id, __stringify(id)
34
26
#define qcom_board_id_named(id, name) QCOM_ID_ ## id, (name)
+23
include/linux/firmware/qcom/qcom_scm.h
+23
include/linux/firmware/qcom/qcom_scm.h
···
115
115
int qcom_scm_lmh_profile_change(u32 profile_id);
116
116
bool qcom_scm_lmh_dcvsh_available(void);
117
117
118
+
/*
119
+
* Request TZ to program set of access controlled registers necessary
120
+
* irrespective of any features
121
+
*/
122
+
#define QCOM_SCM_GPU_ALWAYS_EN_REQ BIT(0)
123
+
/*
124
+
* Request TZ to program BCL id to access controlled register when BCL is
125
+
* enabled
126
+
*/
127
+
#define QCOM_SCM_GPU_BCL_EN_REQ BIT(1)
128
+
/*
129
+
* Request TZ to program set of access controlled register for CLX feature
130
+
* when enabled
131
+
*/
132
+
#define QCOM_SCM_GPU_CLX_EN_REQ BIT(2)
133
+
/*
134
+
* Request TZ to program tsense ids to access controlled registers for reading
135
+
* gpu temperature sensors
136
+
*/
137
+
#define QCOM_SCM_GPU_TSENSE_EN_REQ BIT(3)
138
+
139
+
int qcom_scm_gpu_init_regs(u32 gpu_req);
140
+
118
141
#ifdef CONFIG_QCOM_QSEECOM
119
142
120
143
int qcom_scm_qseecom_app_get_id(const char *app_name, u32 *app_id);
+1
include/linux/soc/qcom/smem.h
+1
include/linux/soc/qcom/smem.h
+34
include/linux/soc/qcom/socinfo.h
+34
include/linux/soc/qcom/socinfo.h
···
3
3
#ifndef __QCOM_SOCINFO_H__
4
4
#define __QCOM_SOCINFO_H__
5
5
6
+
#include <linux/types.h>
7
+
6
8
/*
7
9
* SMEM item id, used to acquire handles to respective
8
10
* SMEM region.
···
13
11
14
12
#define SMEM_SOCINFO_BUILD_ID_LENGTH 32
15
13
#define SMEM_SOCINFO_CHIP_ID_LENGTH 32
14
+
15
+
/*
16
+
* SoC version type with major number in the upper 16 bits and minor
17
+
* number in the lower 16 bits.
18
+
*/
19
+
#define SOCINFO_MAJOR(ver) (((ver) >> 16) & 0xffff)
20
+
#define SOCINFO_MINOR(ver) ((ver) & 0xffff)
21
+
#define SOCINFO_VERSION(maj, min) ((((maj) & 0xffff) << 16)|((min) & 0xffff))
16
22
17
23
/* Socinfo SMEM item structure */
18
24
struct socinfo {
···
83
73
__le32 boot_cluster;
84
74
__le32 boot_core;
85
75
};
76
+
77
+
/* Internal feature codes */
78
+
enum qcom_socinfo_feature_code {
79
+
/* External feature codes */
80
+
SOCINFO_FC_UNKNOWN = 0x0,
81
+
SOCINFO_FC_AA,
82
+
SOCINFO_FC_AB,
83
+
SOCINFO_FC_AC,
84
+
SOCINFO_FC_AD,
85
+
SOCINFO_FC_AE,
86
+
SOCINFO_FC_AF,
87
+
SOCINFO_FC_AG,
88
+
SOCINFO_FC_AH,
89
+
};
90
+
91
+
/* Internal feature codes */
92
+
/* Valid values: 0 <= n <= 0xf */
93
+
#define SOCINFO_FC_Yn(n) (0xf1 + (n))
94
+
#define SOCINFO_FC_INT_MAX SOCINFO_FC_Yn(0xf)
95
+
96
+
/* Product codes */
97
+
#define SOCINFO_PC_UNKNOWN 0
98
+
#define SOCINFO_PCn(n) ((n) + 1)
99
+
#define SOCINFO_PC_RESERVE (BIT(31) - 1)
86
100
87
101
#endif