Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'dmaengine-5.4-rc1' of git://git.infradead.org/users/vkoul/slave-dma
Pull dmaengine updates from Vinod Koul:
- Move Dmaengine DT bindings to YAML and convert Allwinner to schema.
- FSL dma device_synchronize implementation
- DW split acpi and of helpers and updates to driver and support for
Elkhart Lake
- Move filter fn as private for omap-dma and edma drivers and
improvements to these drivers
- Mark expected switch fall-through in couple of drivers
- Renames of shdma and nbpfaxi binding document
- Minor updates to bunch of drivers
* tag 'dmaengine-5.4-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (55 commits)
dmaengine: ti: edma: Use bitmap_set() instead of open coded edma_set_bits()
dmaengine: ti: edma: Only reset region0 access registers
dmaengine: ti: edma: Do not reset reserved paRAM slots
dmaengine: iop-adma.c: fix printk format warning
dmaengine: stm32-dma: Use struct_size() helper
dt-bindings: dmaengine: dma-common: Fix the dma-channel-mask property
dmanegine: ioat/dca: Use struct_size() helper
dmaengine: iop-adma: remove set but not used variable 'slots_per_op'
dmaengine: dmatest: Add support for completion polling
dmaengine: ti: omap-dma: Remove variable override in omap_dma_tx_status()
dmaengine: ti: omap-dma: Remove 'Assignment in if condition'
dmaengine: ti: edma: Remove 'Assignment in if condition'
dmaengine: dw: platform: Split OF helpers to separate module
dmaengine: dw: platform: Split ACPI helpers to separate module
dmaengine: dw: platform: Move handle check to dw_dma_acpi_controller_register()
dmaengine: dw: platform: Switch to acpi_dma_controller_register()
dmaengine: dw: platform: Use devm_platform_ioremap_resource()
dmaengine: dw: platform: Enable iDMA 32-bit on Intel Elkhart Lake
dmaengine: dw: platform: Use struct dw_dma_chip_pdata
dmaengine: dw: Export struct dw_dma_chip_pdata for wider use
...
+1083
-743
+55
Documentation/devicetree/bindings/dma/allwinner,sun4i-a10-dma.yaml
+55
Documentation/devicetree/bindings/dma/allwinner,sun4i-a10-dma.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/dma/allwinner,sun4i-a10-dma.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Allwinner A10 DMA Controller Device Tree Bindings
8
+
9
+
maintainers:
10
+
- Chen-Yu Tsai <wens@csie.org>
11
+
- Maxime Ripard <maxime.ripard@bootlin.com>
12
+
13
+
allOf:
14
+
- $ref: "dma-controller.yaml#"
15
+
16
+
properties:
17
+
"#dma-cells":
18
+
const: 2
19
+
description:
20
+
The first cell is either 0 or 1, the former to use the normal
21
+
DMA, 1 for dedicated DMA. The second cell is the request line
22
+
number.
23
+
24
+
compatible:
25
+
const: allwinner,sun4i-a10-dma
26
+
27
+
reg:
28
+
maxItems: 1
29
+
30
+
interrupts:
31
+
maxItems: 1
32
+
33
+
clocks:
34
+
maxItems: 1
35
+
36
+
required:
37
+
- "#dma-cells"
38
+
- compatible
39
+
- reg
40
+
- interrupts
41
+
- clocks
42
+
43
+
additionalProperties: false
44
+
45
+
examples:
46
+
- |
47
+
dma: dma-controller@1c02000 {
48
+
compatible = "allwinner,sun4i-a10-dma";
49
+
reg = <0x01c02000 0x1000>;
50
+
interrupts = <27>;
51
+
clocks = <&ahb_gates 6>;
52
+
#dma-cells = <2>;
53
+
};
54
+
55
+
...
+88
Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml
+88
Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/dma/allwinner,sun50i-a64-dma.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Allwinner A64 DMA Controller Device Tree Bindings
8
+
9
+
maintainers:
10
+
- Chen-Yu Tsai <wens@csie.org>
11
+
- Maxime Ripard <maxime.ripard@bootlin.com>
12
+
13
+
allOf:
14
+
- $ref: "dma-controller.yaml#"
15
+
16
+
properties:
17
+
"#dma-cells":
18
+
const: 1
19
+
description: The cell is the request line number.
20
+
21
+
compatible:
22
+
enum:
23
+
- allwinner,sun50i-a64-dma
24
+
- allwinner,sun50i-h6-dma
25
+
26
+
reg:
27
+
maxItems: 1
28
+
29
+
interrupts:
30
+
maxItems: 1
31
+
32
+
clocks:
33
+
minItems: 1
34
+
maxItems: 2
35
+
36
+
clock-names:
37
+
items:
38
+
- const: bus
39
+
- const: mbus
40
+
41
+
resets:
42
+
maxItems: 1
43
+
44
+
required:
45
+
- "#dma-cells"
46
+
- compatible
47
+
- reg
48
+
- interrupts
49
+
- clocks
50
+
- resets
51
+
- dma-channels
52
+
53
+
if:
54
+
properties:
55
+
compatible:
56
+
const: allwinner,sun50i-h6-dma
57
+
58
+
then:
59
+
properties:
60
+
clocks:
61
+
maxItems: 2
62
+
63
+
required:
64
+
- clock-names
65
+
66
+
else:
67
+
properties:
68
+
clocks:
69
+
maxItems: 1
70
+
71
+
# FIXME: We should set it, but it would report all the generic
72
+
# properties as additional properties.
73
+
# additionalProperties: false
74
+
75
+
examples:
76
+
- |
77
+
dma: dma-controller@1c02000 {
78
+
compatible = "allwinner,sun50i-a64-dma";
79
+
reg = <0x01c02000 0x1000>;
80
+
interrupts = <0 50 4>;
81
+
clocks = <&ccu 30>;
82
+
dma-channels = <8>;
83
+
dma-requests = <27>;
84
+
resets = <&ccu 7>;
85
+
#dma-cells = <1>;
86
+
};
87
+
88
+
...
+62
Documentation/devicetree/bindings/dma/allwinner,sun6i-a31-dma.yaml
+62
Documentation/devicetree/bindings/dma/allwinner,sun6i-a31-dma.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/dma/allwinner,sun6i-a31-dma.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Allwinner A31 DMA Controller Device Tree Bindings
8
+
9
+
maintainers:
10
+
- Chen-Yu Tsai <wens@csie.org>
11
+
- Maxime Ripard <maxime.ripard@bootlin.com>
12
+
13
+
allOf:
14
+
- $ref: "dma-controller.yaml#"
15
+
16
+
properties:
17
+
"#dma-cells":
18
+
const: 1
19
+
description: The cell is the request line number.
20
+
21
+
compatible:
22
+
oneOf:
23
+
- const: allwinner,sun6i-a31-dma
24
+
- const: allwinner,sun8i-a23-dma
25
+
- const: allwinner,sun8i-a83t-dma
26
+
- const: allwinner,sun8i-h3-dma
27
+
- const: allwinner,sun8i-v3s-dma
28
+
29
+
reg:
30
+
maxItems: 1
31
+
32
+
interrupts:
33
+
maxItems: 1
34
+
35
+
clocks:
36
+
maxItems: 1
37
+
38
+
resets:
39
+
maxItems: 1
40
+
41
+
required:
42
+
- "#dma-cells"
43
+
- compatible
44
+
- reg
45
+
- interrupts
46
+
- clocks
47
+
- resets
48
+
49
+
additionalProperties: false
50
+
51
+
examples:
52
+
- |
53
+
dma: dma-controller@1c02000 {
54
+
compatible = "allwinner,sun6i-a31-dma";
55
+
reg = <0x01c02000 0x1000>;
56
+
interrupts = <0 50 4>;
57
+
clocks = <&ahb1_gates 6>;
58
+
resets = <&ahb1_rst 6>;
59
+
#dma-cells = <1>;
60
+
};
61
+
62
+
...
+45
Documentation/devicetree/bindings/dma/dma-common.yaml
+45
Documentation/devicetree/bindings/dma/dma-common.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/dma/dma-common.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: DMA Engine Generic Binding
8
+
9
+
maintainers:
10
+
- Vinod Koul <vkoul@kernel.org>
11
+
12
+
description:
13
+
Generic binding to provide a way for a driver using DMA Engine to
14
+
retrieve the DMA request or channel information that goes from a
15
+
hardware device to a DMA controller.
16
+
17
+
select: false
18
+
19
+
properties:
20
+
"#dma-cells":
21
+
minimum: 1
22
+
# Should be enough
23
+
maximum: 255
24
+
description:
25
+
Used to provide DMA controller specific information.
26
+
27
+
dma-channel-mask:
28
+
$ref: /schemas/types.yaml#definitions/uint32
29
+
description:
30
+
Bitmask of available DMA channels in ascending order that are
31
+
not reserved by firmware and are available to the
32
+
kernel. i.e. first channel corresponds to LSB.
33
+
34
+
dma-channels:
35
+
$ref: /schemas/types.yaml#definitions/uint32
36
+
description:
37
+
Number of DMA channels supported by the controller.
38
+
39
+
dma-requests:
40
+
$ref: /schemas/types.yaml#definitions/uint32
41
+
description:
42
+
Number of DMA request signals supported by the controller.
43
+
44
+
required:
45
+
- "#dma-cells"
+35
Documentation/devicetree/bindings/dma/dma-controller.yaml
+35
Documentation/devicetree/bindings/dma/dma-controller.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/dma/dma-controller.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: DMA Controller Generic Binding
8
+
9
+
maintainers:
10
+
- Vinod Koul <vkoul@kernel.org>
11
+
12
+
allOf:
13
+
- $ref: "dma-common.yaml#"
14
+
15
+
# Everything else is described in the common file
16
+
properties:
17
+
$nodename:
18
+
pattern: "^dma-controller(@.*)?$"
19
+
20
+
examples:
21
+
- |
22
+
dma: dma-controller@48000000 {
23
+
compatible = "ti,omap-sdma";
24
+
reg = <0x48000000 0x1000>;
25
+
interrupts = <0 12 0x4
26
+
0 13 0x4
27
+
0 14 0x4
28
+
0 15 0x4>;
29
+
#dma-cells = <1>;
30
+
dma-channels = <32>;
31
+
dma-requests = <127>;
32
+
dma-channel-mask = <0xfffe>;
33
+
};
34
+
35
+
...
+50
Documentation/devicetree/bindings/dma/dma-router.yaml
+50
Documentation/devicetree/bindings/dma/dma-router.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/dma/dma-router.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: DMA Router Generic Binding
8
+
9
+
maintainers:
10
+
- Vinod Koul <vkoul@kernel.org>
11
+
12
+
allOf:
13
+
- $ref: "dma-common.yaml#"
14
+
15
+
description:
16
+
DMA routers are transparent IP blocks used to route DMA request
17
+
lines from devices to the DMA controller. Some SoCs (like TI DRA7x)
18
+
have more peripherals integrated with DMA requests than what the DMA
19
+
controller can handle directly.
20
+
21
+
properties:
22
+
$nodename:
23
+
pattern: "^dma-router(@.*)?$"
24
+
25
+
dma-masters:
26
+
$ref: /schemas/types.yaml#definitions/phandle-array
27
+
description:
28
+
Array of phandles to the DMA controllers the router can direct
29
+
the signal to.
30
+
31
+
dma-requests:
32
+
description:
33
+
Number of incoming request lines the router can handle.
34
+
35
+
required:
36
+
- "#dma-cells"
37
+
- dma-masters
38
+
39
+
examples:
40
+
- |
41
+
sdma_xbar: dma-router@4a002b78 {
42
+
compatible = "ti,dra7-dma-crossbar";
43
+
reg = <0x4a002b78 0xfc>;
44
+
#dma-cells = <1>;
45
+
dma-requests = <205>;
46
+
ti,dma-safe-map = <0>;
47
+
dma-masters = <&sdma>;
48
+
};
49
+
50
+
...
+1
-113
Documentation/devicetree/bindings/dma/dma.txt
+1
-113
Documentation/devicetree/bindings/dma/dma.txt
···
1
-
* Generic DMA Controller and DMA request bindings
2
-
3
-
Generic binding to provide a way for a driver using DMA Engine to retrieve the
4
-
DMA request or channel information that goes from a hardware device to a DMA
5
-
controller.
6
-
7
-
8
-
* DMA controller
9
-
10
-
Required property:
11
-
- #dma-cells: Must be at least 1. Used to provide DMA controller
12
-
specific information. See DMA client binding below for
13
-
more details.
14
-
15
-
Optional properties:
16
-
- dma-channels: Number of DMA channels supported by the controller.
17
-
- dma-requests: Number of DMA request signals supported by the
18
-
controller.
19
-
- dma-channel-mask: Bitmask of available DMA channels in ascending order
20
-
that are not reserved by firmware and are available to
21
-
the kernel. i.e. first channel corresponds to LSB.
22
-
23
-
Example:
24
-
25
-
dma: dma@48000000 {
26
-
compatible = "ti,omap-sdma";
27
-
reg = <0x48000000 0x1000>;
28
-
interrupts = <0 12 0x4
29
-
0 13 0x4
30
-
0 14 0x4
31
-
0 15 0x4>;
32
-
#dma-cells = <1>;
33
-
dma-channels = <32>;
34
-
dma-requests = <127>;
35
-
dma-channel-mask = <0xfffe>
36
-
};
37
-
38
-
* DMA router
39
-
40
-
DMA routers are transparent IP blocks used to route DMA request lines from
41
-
devices to the DMA controller. Some SoCs (like TI DRA7x) have more peripherals
42
-
integrated with DMA requests than what the DMA controller can handle directly.
43
-
44
-
Required property:
45
-
- dma-masters: phandle of the DMA controller or list of phandles for
46
-
the DMA controllers the router can direct the signal to.
47
-
- #dma-cells: Must be at least 1. Used to provide DMA router specific
48
-
information. See DMA client binding below for more
49
-
details.
50
-
51
-
Optional properties:
52
-
- dma-requests: Number of incoming request lines the router can handle.
53
-
- In the node pointed by the dma-masters:
54
-
- dma-requests: The router driver might need to look for this in order
55
-
to configure the routing.
56
-
57
-
Example:
58
-
sdma_xbar: dma-router@4a002b78 {
59
-
compatible = "ti,dra7-dma-crossbar";
60
-
reg = <0x4a002b78 0xfc>;
61
-
#dma-cells = <1>;
62
-
dma-requests = <205>;
63
-
ti,dma-safe-map = <0>;
64
-
dma-masters = <&sdma>;
65
-
};
66
-
67
-
* DMA client
68
-
69
-
Client drivers should specify the DMA property using a phandle to the controller
70
-
followed by DMA controller specific data.
71
-
72
-
Required property:
73
-
- dmas: List of one or more DMA specifiers, each consisting of
74
-
- A phandle pointing to DMA controller node
75
-
- A number of integer cells, as determined by the
76
-
#dma-cells property in the node referenced by phandle
77
-
containing DMA controller specific information. This
78
-
typically contains a DMA request line number or a
79
-
channel number, but can contain any data that is
80
-
required for configuring a channel.
81
-
- dma-names: Contains one identifier string for each DMA specifier in
82
-
the dmas property. The specific strings that can be used
83
-
are defined in the binding of the DMA client device.
84
-
Multiple DMA specifiers can be used to represent
85
-
alternatives and in this case the dma-names for those
86
-
DMA specifiers must be identical (see examples).
87
-
88
-
Examples:
89
-
90
-
1. A device with one DMA read channel, one DMA write channel:
91
-
92
-
i2c1: i2c@1 {
93
-
...
94
-
dmas = <&dma 2 /* read channel */
95
-
&dma 3>; /* write channel */
96
-
dma-names = "rx", "tx";
97
-
...
98
-
};
99
-
100
-
2. A single read-write channel with three alternative DMA controllers:
101
-
102
-
dmas = <&dma1 5
103
-
&dma2 7
104
-
&dma3 2>;
105
-
dma-names = "rx-tx", "rx-tx", "rx-tx";
106
-
107
-
3. A device with three channels, one of which has two alternatives:
108
-
109
-
dmas = <&dma1 2 /* read channel */
110
-
&dma1 3 /* write channel */
111
-
&dma2 0 /* error read */
112
-
&dma3 0>; /* alternative error read */
113
-
dma-names = "rx", "tx", "error", "error";
1
+
This file has been moved to dma-controller.yaml.
Documentation/devicetree/bindings/dma/nbpfaxi.txt
Documentation/devicetree/bindings/dma/renesas,nbpfaxi.txt
Documentation/devicetree/bindings/dma/nbpfaxi.txt
Documentation/devicetree/bindings/dma/renesas,nbpfaxi.txt
Documentation/devicetree/bindings/dma/shdma.txt
Documentation/devicetree/bindings/dma/renesas,shdma.txt
Documentation/devicetree/bindings/dma/shdma.txt
Documentation/devicetree/bindings/dma/renesas,shdma.txt
-45
Documentation/devicetree/bindings/dma/sun4i-dma.txt
-45
Documentation/devicetree/bindings/dma/sun4i-dma.txt
···
1
-
Allwinner A10 DMA Controller
2
-
3
-
This driver follows the generic DMA bindings defined in dma.txt.
4
-
5
-
Required properties:
6
-
7
-
- compatible: Must be "allwinner,sun4i-a10-dma"
8
-
- reg: Should contain the registers base address and length
9
-
- interrupts: Should contain a reference to the interrupt used by this device
10
-
- clocks: Should contain a reference to the parent AHB clock
11
-
- #dma-cells : Should be 2, first cell denoting normal or dedicated dma,
12
-
second cell holding the request line number.
13
-
14
-
Example:
15
-
dma: dma-controller@1c02000 {
16
-
compatible = "allwinner,sun4i-a10-dma";
17
-
reg = <0x01c02000 0x1000>;
18
-
interrupts = <27>;
19
-
clocks = <&ahb_gates 6>;
20
-
#dma-cells = <2>;
21
-
};
22
-
23
-
Clients:
24
-
25
-
DMA clients connected to the Allwinner A10 DMA controller must use the
26
-
format described in the dma.txt file, using a three-cell specifier for
27
-
each channel: a phandle plus two integer cells.
28
-
The three cells in order are:
29
-
30
-
1. A phandle pointing to the DMA controller.
31
-
2. Whether it is using normal (0) or dedicated (1) channels
32
-
3. The port ID as specified in the datasheet
33
-
34
-
Example:
35
-
spi2: spi@1c17000 {
36
-
compatible = "allwinner,sun4i-a10-spi";
37
-
reg = <0x01c17000 0x1000>;
38
-
interrupts = <0 12 4>;
39
-
clocks = <&ahb_gates 22>, <&spi2_clk>;
40
-
clock-names = "ahb", "mod";
41
-
dmas = <&dma 1 29>, <&dma 1 28>;
42
-
dma-names = "rx", "tx";
43
-
#address-cells = <1>;
44
-
#size-cells = <0>;
45
-
};
-81
Documentation/devicetree/bindings/dma/sun6i-dma.txt
-81
Documentation/devicetree/bindings/dma/sun6i-dma.txt
···
1
-
Allwinner A31 DMA Controller
2
-
3
-
This driver follows the generic DMA bindings defined in dma.txt.
4
-
5
-
Required properties:
6
-
7
-
- compatible: Must be one of
8
-
"allwinner,sun6i-a31-dma"
9
-
"allwinner,sun8i-a23-dma"
10
-
"allwinner,sun8i-a83t-dma"
11
-
"allwinner,sun8i-h3-dma"
12
-
"allwinner,sun8i-v3s-dma"
13
-
- reg: Should contain the registers base address and length
14
-
- interrupts: Should contain a reference to the interrupt used by this device
15
-
- clocks: Should contain a reference to the parent AHB clock
16
-
- resets: Should contain a reference to the reset controller asserting
17
-
this device in reset
18
-
- #dma-cells : Should be 1, a single cell holding a line request number
19
-
20
-
Example:
21
-
dma: dma-controller@1c02000 {
22
-
compatible = "allwinner,sun6i-a31-dma";
23
-
reg = <0x01c02000 0x1000>;
24
-
interrupts = <0 50 4>;
25
-
clocks = <&ahb1_gates 6>;
26
-
resets = <&ahb1_rst 6>;
27
-
#dma-cells = <1>;
28
-
};
29
-
30
-
------------------------------------------------------------------------------
31
-
For A64 and H6 DMA controller:
32
-
33
-
Required properties:
34
-
- compatible: Must be one of
35
-
"allwinner,sun50i-a64-dma"
36
-
"allwinner,sun50i-h6-dma"
37
-
- dma-channels: Number of DMA channels supported by the controller.
38
-
Refer to Documentation/devicetree/bindings/dma/dma.txt
39
-
- clocks: In addition to parent AHB clock, it should also contain mbus
40
-
clock (H6 only)
41
-
- clock-names: Should contain "bus" and "mbus" (H6 only)
42
-
- all properties above, i.e. reg, interrupts, clocks, resets and #dma-cells
43
-
44
-
Optional properties:
45
-
- dma-requests: Number of DMA request signals supported by the controller.
46
-
Refer to Documentation/devicetree/bindings/dma/dma.txt
47
-
48
-
Example:
49
-
dma: dma-controller@1c02000 {
50
-
compatible = "allwinner,sun50i-a64-dma";
51
-
reg = <0x01c02000 0x1000>;
52
-
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
53
-
clocks = <&ccu CLK_BUS_DMA>;
54
-
dma-channels = <8>;
55
-
dma-requests = <27>;
56
-
resets = <&ccu RST_BUS_DMA>;
57
-
#dma-cells = <1>;
58
-
};
59
-
------------------------------------------------------------------------------
60
-
61
-
Clients:
62
-
63
-
DMA clients connected to the A31 DMA controller must use the format
64
-
described in the dma.txt file, using a two-cell specifier for each
65
-
channel: a phandle plus one integer cells.
66
-
The two cells in order are:
67
-
68
-
1. A phandle pointing to the DMA controller.
69
-
2. The port ID as specified in the datasheet
70
-
71
-
Example:
72
-
spi2: spi@1c6a000 {
73
-
compatible = "allwinner,sun6i-a31-spi";
74
-
reg = <0x01c6a000 0x1000>;
75
-
interrupts = <0 67 4>;
76
-
clocks = <&ahb1_gates 22>, <&spi2_clk>;
77
-
clock-names = "ahb", "mod";
78
-
dmas = <&dma 25>, <&dma 25>;
79
-
dma-names = "rx", "tx";
80
-
resets = <&ahb1_rst 22>;
81
-
};
+1
-1
MAINTAINERS
+1
-1
MAINTAINERS
···
15532
15532
SYNOPSYS DESIGNWARE AXI DMAC DRIVER
15533
15533
M: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
15534
15534
S: Maintained
15535
-
F: drivers/dma/dwi-axi-dmac/
15535
+
F: drivers/dma/dw-axi-dmac/
15536
15536
F: Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt
15537
15537
15538
15538
SYNOPSYS DESIGNWARE DMAC DRIVER
+1
-1
drivers/dma/Kconfig
+1
-1
drivers/dma/Kconfig
+10
-2
drivers/dma/acpi-dma.c
+10
-2
drivers/dma/acpi-dma.c
···
10
10
*/
11
11
12
12
#include <linux/device.h>
13
+
#include <linux/dma-mapping.h>
13
14
#include <linux/err.h>
14
15
#include <linux/module.h>
15
16
#include <linux/kernel.h>
···
83
82
if (si->base_request_line == 0 && si->num_handshake_signals == 0)
84
83
return 0;
85
84
85
+
/* Set up DMA mask based on value from CSRT */
86
+
ret = dma_coerce_mask_and_coherent(&adev->dev,
87
+
DMA_BIT_MASK(si->dma_address_width));
88
+
if (ret)
89
+
return 0;
90
+
86
91
adma->base_request_line = si->base_request_line;
87
92
adma->end_request_line = si->base_request_line +
88
93
si->num_handshake_signals - 1;
···
147
140
* @dev: struct device of DMA controller
148
141
* @acpi_dma_xlate: translation function which converts a dma specifier
149
142
* into a dma_chan structure
150
-
* @data pointer to controller specific data to be used by
143
+
* @data: pointer to controller specific data to be used by
151
144
* translation function
152
145
*
153
146
* Allocated memory should be freed with appropriate acpi_dma_controller_free()
···
231
224
* devm_acpi_dma_controller_register - resource managed acpi_dma_controller_register()
232
225
* @dev: device that is registering this DMA controller
233
226
* @acpi_dma_xlate: translation function
234
-
* @data pointer to controller specific data
227
+
* @data: pointer to controller specific data
235
228
*
236
229
* Managed acpi_dma_controller_register(). DMA controller registered by this
237
230
* function are automatically freed on driver detach. See
···
264
257
265
258
/**
266
259
* devm_acpi_dma_controller_free - resource managed acpi_dma_controller_free()
260
+
* @dev: device that is unregistering as DMA controller
267
261
*
268
262
* Unregister a DMA controller registered with
269
263
* devm_acpi_dma_controller_register(). Normally this function will not need to
+3
-1
drivers/dma/bcm2835-dma.c
+3
-1
drivers/dma/bcm2835-dma.c
···
896
896
pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
897
897
898
898
rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
899
-
if (rc)
899
+
if (rc) {
900
+
dev_err(&pdev->dev, "Unable to set DMA mask\n");
900
901
return rc;
902
+
}
901
903
902
904
od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL);
903
905
if (!od)
+13
-6
drivers/dma/dma-jz4780.c
+13
-6
drivers/dma/dma-jz4780.c
···
92
92
#define JZ_SOC_DATA_PROGRAMMABLE_DMA BIT(1)
93
93
#define JZ_SOC_DATA_PER_CHAN_PM BIT(2)
94
94
#define JZ_SOC_DATA_NO_DCKES_DCKEC BIT(3)
95
+
#define JZ_SOC_DATA_BREAK_LINKS BIT(4)
95
96
96
97
/**
97
98
* struct jz4780_dma_hwdesc - descriptor structure read by the DMA controller.
···
356
355
void *context)
357
356
{
358
357
struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan);
358
+
struct jz4780_dma_dev *jzdma = jz4780_dma_chan_parent(jzchan);
359
359
struct jz4780_dma_desc *desc;
360
360
unsigned int i;
361
361
int err;
···
377
375
378
376
desc->desc[i].dcm |= JZ_DMA_DCM_TIE;
379
377
380
-
if (i != (sg_len - 1)) {
378
+
if (i != (sg_len - 1) &&
379
+
!(jzdma->soc_data->flags & JZ_SOC_DATA_BREAK_LINKS)) {
381
380
/* Automatically proceeed to the next descriptor. */
382
381
desc->desc[i].dcm |= JZ_DMA_DCM_LINK;
383
382
···
667
664
static bool jz4780_dma_chan_irq(struct jz4780_dma_dev *jzdma,
668
665
struct jz4780_dma_chan *jzchan)
669
666
{
667
+
const unsigned int soc_flags = jzdma->soc_data->flags;
668
+
struct jz4780_dma_desc *desc = jzchan->desc;
670
669
uint32_t dcs;
671
670
bool ack = true;
672
671
···
696
691
697
692
jz4780_dma_begin(jzchan);
698
693
} else if (dcs & JZ_DMA_DCS_TT) {
699
-
vchan_cookie_complete(&jzchan->desc->vdesc);
700
-
jzchan->desc = NULL;
694
+
if (!(soc_flags & JZ_SOC_DATA_BREAK_LINKS) ||
695
+
(jzchan->curr_hwdesc + 1 == desc->count)) {
696
+
vchan_cookie_complete(&desc->vdesc);
697
+
jzchan->desc = NULL;
698
+
}
701
699
702
700
jz4780_dma_begin(jzchan);
703
701
} else {
···
886
878
}
887
879
888
880
ret = platform_get_irq(pdev, 0);
889
-
if (ret < 0) {
890
-
dev_err(dev, "failed to get IRQ: %d\n", ret);
881
+
if (ret < 0)
891
882
return ret;
892
-
}
893
883
894
884
jzdma->irq = ret;
895
885
···
998
992
static const struct jz4780_dma_soc_data jz4740_dma_soc_data = {
999
993
.nb_channels = 6,
1000
994
.transfer_ord_max = 5,
995
+
.flags = JZ_SOC_DATA_BREAK_LINKS,
1001
996
};
1002
997
1003
998
static const struct jz4780_dma_soc_data jz4725b_dma_soc_data = {
+28
-7
drivers/dma/dmatest.c
+28
-7
drivers/dma/dmatest.c
···
72
72
module_param(norandom, bool, 0644);
73
73
MODULE_PARM_DESC(norandom, "Disable random offset setup (default: random)");
74
74
75
+
static bool polled;
76
+
module_param(polled, bool, S_IRUGO | S_IWUSR);
77
+
MODULE_PARM_DESC(polled, "Use polling for completion instead of interrupts");
78
+
75
79
static bool verbose;
76
80
module_param(verbose, bool, S_IRUGO | S_IWUSR);
77
81
MODULE_PARM_DESC(verbose, "Enable \"success\" result messages (default: off)");
···
114
110
bool norandom;
115
111
int alignment;
116
112
unsigned int transfer_size;
113
+
bool polled;
117
114
};
118
115
119
116
/**
···
656
651
/*
657
652
* src and dst buffers are freed by ourselves below
658
653
*/
659
-
flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
654
+
if (params->polled)
655
+
flags = DMA_CTRL_ACK;
656
+
else
657
+
flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
660
658
661
659
ktime = ktime_get();
662
660
while (!kthread_should_stop()
···
788
780
}
789
781
790
782
done->done = false;
791
-
tx->callback = dmatest_callback;
792
-
tx->callback_param = done;
783
+
if (!params->polled) {
784
+
tx->callback = dmatest_callback;
785
+
tx->callback_param = done;
786
+
}
793
787
cookie = tx->tx_submit(tx);
794
788
795
789
if (dma_submit_error(cookie)) {
···
800
790
msleep(100);
801
791
goto error_unmap_continue;
802
792
}
803
-
dma_async_issue_pending(chan);
804
793
805
-
wait_event_freezable_timeout(thread->done_wait, done->done,
806
-
msecs_to_jiffies(params->timeout));
794
+
if (params->polled) {
795
+
status = dma_sync_wait(chan, cookie);
796
+
dmaengine_terminate_sync(chan);
797
+
if (status == DMA_COMPLETE)
798
+
done->done = true;
799
+
} else {
800
+
dma_async_issue_pending(chan);
807
801
808
-
status = dma_async_is_tx_complete(chan, cookie, NULL, NULL);
802
+
wait_event_freezable_timeout(thread->done_wait,
803
+
done->done,
804
+
msecs_to_jiffies(params->timeout));
805
+
806
+
status = dma_async_is_tx_complete(chan, cookie, NULL,
807
+
NULL);
808
+
}
809
809
810
810
if (!done->done) {
811
811
result("test timed out", total_tests, src->off, dst->off,
···
1085
1065
params->norandom = norandom;
1086
1066
params->alignment = alignment;
1087
1067
params->transfer_size = transfer_size;
1068
+
params->polled = polled;
1088
1069
1089
1070
request_channels(info, DMA_MEMCPY);
1090
1071
request_channels(info, DMA_MEMSET);
+3
-1
drivers/dma/dw/Makefile
+3
-1
drivers/dma/dw/Makefile
···
3
3
dw_dmac_core-objs := core.o dw.o idma32.o
4
4
5
5
obj-$(CONFIG_DW_DMAC) += dw_dmac.o
6
-
dw_dmac-objs := platform.o
6
+
dw_dmac-y := platform.o
7
+
dw_dmac-$(CONFIG_ACPI) += acpi.o
8
+
dw_dmac-$(CONFIG_OF) += of.o
7
9
8
10
obj-$(CONFIG_DW_DMAC_PCI) += dw_dmac_pci.o
9
11
dw_dmac_pci-objs := pci.o
+53
drivers/dma/dw/acpi.c
+53
drivers/dma/dw/acpi.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
// Copyright (C) 2013,2019 Intel Corporation
3
+
4
+
#include <linux/acpi.h>
5
+
#include <linux/acpi_dma.h>
6
+
7
+
#include "internal.h"
8
+
9
+
static bool dw_dma_acpi_filter(struct dma_chan *chan, void *param)
10
+
{
11
+
struct acpi_dma_spec *dma_spec = param;
12
+
struct dw_dma_slave slave = {
13
+
.dma_dev = dma_spec->dev,
14
+
.src_id = dma_spec->slave_id,
15
+
.dst_id = dma_spec->slave_id,
16
+
.m_master = 0,
17
+
.p_master = 1,
18
+
};
19
+
20
+
return dw_dma_filter(chan, &slave);
21
+
}
22
+
23
+
void dw_dma_acpi_controller_register(struct dw_dma *dw)
24
+
{
25
+
struct device *dev = dw->dma.dev;
26
+
struct acpi_dma_filter_info *info;
27
+
int ret;
28
+
29
+
if (!has_acpi_companion(dev))
30
+
return;
31
+
32
+
info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
33
+
if (!info)
34
+
return;
35
+
36
+
dma_cap_zero(info->dma_cap);
37
+
dma_cap_set(DMA_SLAVE, info->dma_cap);
38
+
info->filter_fn = dw_dma_acpi_filter;
39
+
40
+
ret = acpi_dma_controller_register(dev, acpi_dma_simple_xlate, info);
41
+
if (ret)
42
+
dev_err(dev, "could not register acpi_dma_controller\n");
43
+
}
44
+
45
+
void dw_dma_acpi_controller_free(struct dw_dma *dw)
46
+
{
47
+
struct device *dev = dw->dma.dev;
48
+
49
+
if (!has_acpi_companion(dev))
50
+
return;
51
+
52
+
acpi_dma_controller_free(dev);
53
+
}
+51
drivers/dma/dw/internal.h
+51
drivers/dma/dw/internal.h
···
23
23
24
24
extern bool dw_dma_filter(struct dma_chan *chan, void *param);
25
25
26
+
#ifdef CONFIG_ACPI
27
+
void dw_dma_acpi_controller_register(struct dw_dma *dw);
28
+
void dw_dma_acpi_controller_free(struct dw_dma *dw);
29
+
#else /* !CONFIG_ACPI */
30
+
static inline void dw_dma_acpi_controller_register(struct dw_dma *dw) {}
31
+
static inline void dw_dma_acpi_controller_free(struct dw_dma *dw) {}
32
+
#endif /* !CONFIG_ACPI */
33
+
34
+
struct platform_device;
35
+
36
+
#ifdef CONFIG_OF
37
+
struct dw_dma_platform_data *dw_dma_parse_dt(struct platform_device *pdev);
38
+
void dw_dma_of_controller_register(struct dw_dma *dw);
39
+
void dw_dma_of_controller_free(struct dw_dma *dw);
40
+
#else
41
+
static inline struct dw_dma_platform_data *dw_dma_parse_dt(struct platform_device *pdev)
42
+
{
43
+
return NULL;
44
+
}
45
+
static inline void dw_dma_of_controller_register(struct dw_dma *dw) {}
46
+
static inline void dw_dma_of_controller_free(struct dw_dma *dw) {}
47
+
#endif
48
+
49
+
struct dw_dma_chip_pdata {
50
+
const struct dw_dma_platform_data *pdata;
51
+
int (*probe)(struct dw_dma_chip *chip);
52
+
int (*remove)(struct dw_dma_chip *chip);
53
+
struct dw_dma_chip *chip;
54
+
};
55
+
56
+
static __maybe_unused const struct dw_dma_chip_pdata dw_dma_chip_pdata = {
57
+
.probe = dw_dma_probe,
58
+
.remove = dw_dma_remove,
59
+
};
60
+
61
+
static const struct dw_dma_platform_data idma32_pdata = {
62
+
.nr_channels = 8,
63
+
.chan_allocation_order = CHAN_ALLOCATION_ASCENDING,
64
+
.chan_priority = CHAN_PRIORITY_ASCENDING,
65
+
.block_size = 131071,
66
+
.nr_masters = 1,
67
+
.data_width = {4},
68
+
.multi_block = {1, 1, 1, 1, 1, 1, 1, 1},
69
+
};
70
+
71
+
static __maybe_unused const struct dw_dma_chip_pdata idma32_chip_pdata = {
72
+
.pdata = &idma32_pdata,
73
+
.probe = idma32_dma_probe,
74
+
.remove = idma32_dma_remove,
75
+
};
76
+
26
77
#endif /* _DMA_DW_INTERNAL_H */
+131
drivers/dma/dw/of.c
+131
drivers/dma/dw/of.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Platform driver for the Synopsys DesignWare DMA Controller
4
+
*
5
+
* Copyright (C) 2007-2008 Atmel Corporation
6
+
* Copyright (C) 2010-2011 ST Microelectronics
7
+
* Copyright (C) 2013 Intel Corporation
8
+
*/
9
+
10
+
#include <linux/of.h>
11
+
#include <linux/of_dma.h>
12
+
#include <linux/platform_device.h>
13
+
14
+
#include "internal.h"
15
+
16
+
static struct dma_chan *dw_dma_of_xlate(struct of_phandle_args *dma_spec,
17
+
struct of_dma *ofdma)
18
+
{
19
+
struct dw_dma *dw = ofdma->of_dma_data;
20
+
struct dw_dma_slave slave = {
21
+
.dma_dev = dw->dma.dev,
22
+
};
23
+
dma_cap_mask_t cap;
24
+
25
+
if (dma_spec->args_count != 3)
26
+
return NULL;
27
+
28
+
slave.src_id = dma_spec->args[0];
29
+
slave.dst_id = dma_spec->args[0];
30
+
slave.m_master = dma_spec->args[1];
31
+
slave.p_master = dma_spec->args[2];
32
+
33
+
if (WARN_ON(slave.src_id >= DW_DMA_MAX_NR_REQUESTS ||
34
+
slave.dst_id >= DW_DMA_MAX_NR_REQUESTS ||
35
+
slave.m_master >= dw->pdata->nr_masters ||
36
+
slave.p_master >= dw->pdata->nr_masters))
37
+
return NULL;
38
+
39
+
dma_cap_zero(cap);
40
+
dma_cap_set(DMA_SLAVE, cap);
41
+
42
+
/* TODO: there should be a simpler way to do this */
43
+
return dma_request_channel(cap, dw_dma_filter, &slave);
44
+
}
45
+
46
+
struct dw_dma_platform_data *dw_dma_parse_dt(struct platform_device *pdev)
47
+
{
48
+
struct device_node *np = pdev->dev.of_node;
49
+
struct dw_dma_platform_data *pdata;
50
+
u32 tmp, arr[DW_DMA_MAX_NR_MASTERS], mb[DW_DMA_MAX_NR_CHANNELS];
51
+
u32 nr_masters;
52
+
u32 nr_channels;
53
+
54
+
if (!np) {
55
+
dev_err(&pdev->dev, "Missing DT data\n");
56
+
return NULL;
57
+
}
58
+
59
+
if (of_property_read_u32(np, "dma-masters", &nr_masters))
60
+
return NULL;
61
+
if (nr_masters < 1 || nr_masters > DW_DMA_MAX_NR_MASTERS)
62
+
return NULL;
63
+
64
+
if (of_property_read_u32(np, "dma-channels", &nr_channels))
65
+
return NULL;
66
+
if (nr_channels > DW_DMA_MAX_NR_CHANNELS)
67
+
return NULL;
68
+
69
+
pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
70
+
if (!pdata)
71
+
return NULL;
72
+
73
+
pdata->nr_masters = nr_masters;
74
+
pdata->nr_channels = nr_channels;
75
+
76
+
if (!of_property_read_u32(np, "chan_allocation_order", &tmp))
77
+
pdata->chan_allocation_order = (unsigned char)tmp;
78
+
79
+
if (!of_property_read_u32(np, "chan_priority", &tmp))
80
+
pdata->chan_priority = tmp;
81
+
82
+
if (!of_property_read_u32(np, "block_size", &tmp))
83
+
pdata->block_size = tmp;
84
+
85
+
if (!of_property_read_u32_array(np, "data-width", arr, nr_masters)) {
86
+
for (tmp = 0; tmp < nr_masters; tmp++)
87
+
pdata->data_width[tmp] = arr[tmp];
88
+
} else if (!of_property_read_u32_array(np, "data_width", arr, nr_masters)) {
89
+
for (tmp = 0; tmp < nr_masters; tmp++)
90
+
pdata->data_width[tmp] = BIT(arr[tmp] & 0x07);
91
+
}
92
+
93
+
if (!of_property_read_u32_array(np, "multi-block", mb, nr_channels)) {
94
+
for (tmp = 0; tmp < nr_channels; tmp++)
95
+
pdata->multi_block[tmp] = mb[tmp];
96
+
} else {
97
+
for (tmp = 0; tmp < nr_channels; tmp++)
98
+
pdata->multi_block[tmp] = 1;
99
+
}
100
+
101
+
if (!of_property_read_u32(np, "snps,dma-protection-control", &tmp)) {
102
+
if (tmp > CHAN_PROTCTL_MASK)
103
+
return NULL;
104
+
pdata->protctl = tmp;
105
+
}
106
+
107
+
return pdata;
108
+
}
109
+
110
+
void dw_dma_of_controller_register(struct dw_dma *dw)
111
+
{
112
+
struct device *dev = dw->dma.dev;
113
+
int ret;
114
+
115
+
if (!dev->of_node)
116
+
return;
117
+
118
+
ret = of_dma_controller_register(dev->of_node, dw_dma_of_xlate, dw);
119
+
if (ret)
120
+
dev_err(dev, "could not register of_dma_controller\n");
121
+
}
122
+
123
+
void dw_dma_of_controller_free(struct dw_dma *dw)
124
+
{
125
+
struct device *dev = dw->dma.dev;
126
+
127
+
if (!dev->of_node)
128
+
return;
129
+
130
+
of_dma_controller_free(dev->of_node);
131
+
}
+17
-45
drivers/dma/dw/pci.c
+17
-45
drivers/dma/dw/pci.c
···
12
12
13
13
#include "internal.h"
14
14
15
-
struct dw_dma_pci_data {
16
-
const struct dw_dma_platform_data *pdata;
17
-
int (*probe)(struct dw_dma_chip *chip);
18
-
int (*remove)(struct dw_dma_chip *chip);
19
-
struct dw_dma_chip *chip;
20
-
};
21
-
22
-
static const struct dw_dma_pci_data dw_pci_data = {
23
-
.probe = dw_dma_probe,
24
-
.remove = dw_dma_remove,
25
-
};
26
-
27
-
static const struct dw_dma_platform_data idma32_pdata = {
28
-
.nr_channels = 8,
29
-
.chan_allocation_order = CHAN_ALLOCATION_ASCENDING,
30
-
.chan_priority = CHAN_PRIORITY_ASCENDING,
31
-
.block_size = 131071,
32
-
.nr_masters = 1,
33
-
.data_width = {4},
34
-
.multi_block = {1, 1, 1, 1, 1, 1, 1, 1},
35
-
};
36
-
37
-
static const struct dw_dma_pci_data idma32_pci_data = {
38
-
.pdata = &idma32_pdata,
39
-
.probe = idma32_dma_probe,
40
-
.remove = idma32_dma_remove,
41
-
};
42
-
43
15
static int dw_pci_probe(struct pci_dev *pdev, const struct pci_device_id *pid)
44
16
{
45
-
const struct dw_dma_pci_data *drv_data = (void *)pid->driver_data;
46
-
struct dw_dma_pci_data *data;
17
+
const struct dw_dma_chip_pdata *drv_data = (void *)pid->driver_data;
18
+
struct dw_dma_chip_pdata *data;
47
19
struct dw_dma_chip *chip;
48
20
int ret;
49
21
···
67
95
68
96
static void dw_pci_remove(struct pci_dev *pdev)
69
97
{
70
-
struct dw_dma_pci_data *data = pci_get_drvdata(pdev);
98
+
struct dw_dma_chip_pdata *data = pci_get_drvdata(pdev);
71
99
struct dw_dma_chip *chip = data->chip;
72
100
int ret;
73
101
···
80
108
81
109
static int dw_pci_suspend_late(struct device *dev)
82
110
{
83
-
struct dw_dma_pci_data *data = dev_get_drvdata(dev);
111
+
struct dw_dma_chip_pdata *data = dev_get_drvdata(dev);
84
112
struct dw_dma_chip *chip = data->chip;
85
113
86
114
return do_dw_dma_disable(chip);
···
88
116
89
117
static int dw_pci_resume_early(struct device *dev)
90
118
{
91
-
struct dw_dma_pci_data *data = dev_get_drvdata(dev);
119
+
struct dw_dma_chip_pdata *data = dev_get_drvdata(dev);
92
120
struct dw_dma_chip *chip = data->chip;
93
121
94
122
return do_dw_dma_enable(chip);
···
102
130
103
131
static const struct pci_device_id dw_pci_id_table[] = {
104
132
/* Medfield (GPDMA) */
105
-
{ PCI_VDEVICE(INTEL, 0x0827), (kernel_ulong_t)&dw_pci_data },
133
+
{ PCI_VDEVICE(INTEL, 0x0827), (kernel_ulong_t)&dw_dma_chip_pdata },
106
134
107
135
/* BayTrail */
108
-
{ PCI_VDEVICE(INTEL, 0x0f06), (kernel_ulong_t)&dw_pci_data },
109
-
{ PCI_VDEVICE(INTEL, 0x0f40), (kernel_ulong_t)&dw_pci_data },
136
+
{ PCI_VDEVICE(INTEL, 0x0f06), (kernel_ulong_t)&dw_dma_chip_pdata },
137
+
{ PCI_VDEVICE(INTEL, 0x0f40), (kernel_ulong_t)&dw_dma_chip_pdata },
110
138
111
139
/* Merrifield */
112
-
{ PCI_VDEVICE(INTEL, 0x11a2), (kernel_ulong_t)&idma32_pci_data },
140
+
{ PCI_VDEVICE(INTEL, 0x11a2), (kernel_ulong_t)&idma32_chip_pdata },
113
141
114
142
/* Braswell */
115
-
{ PCI_VDEVICE(INTEL, 0x2286), (kernel_ulong_t)&dw_pci_data },
116
-
{ PCI_VDEVICE(INTEL, 0x22c0), (kernel_ulong_t)&dw_pci_data },
143
+
{ PCI_VDEVICE(INTEL, 0x2286), (kernel_ulong_t)&dw_dma_chip_pdata },
144
+
{ PCI_VDEVICE(INTEL, 0x22c0), (kernel_ulong_t)&dw_dma_chip_pdata },
117
145
118
-
/* Elkhart Lake iDMA 32-bit (OSE DMA) */
119
-
{ PCI_VDEVICE(INTEL, 0x4bb4), (kernel_ulong_t)&idma32_pci_data },
120
-
{ PCI_VDEVICE(INTEL, 0x4bb5), (kernel_ulong_t)&idma32_pci_data },
121
-
{ PCI_VDEVICE(INTEL, 0x4bb6), (kernel_ulong_t)&idma32_pci_data },
146
+
/* Elkhart Lake iDMA 32-bit (PSE DMA) */
147
+
{ PCI_VDEVICE(INTEL, 0x4bb4), (kernel_ulong_t)&idma32_chip_pdata },
148
+
{ PCI_VDEVICE(INTEL, 0x4bb5), (kernel_ulong_t)&idma32_chip_pdata },
149
+
{ PCI_VDEVICE(INTEL, 0x4bb6), (kernel_ulong_t)&idma32_chip_pdata },
122
150
123
151
/* Haswell */
124
-
{ PCI_VDEVICE(INTEL, 0x9c60), (kernel_ulong_t)&dw_pci_data },
152
+
{ PCI_VDEVICE(INTEL, 0x9c60), (kernel_ulong_t)&dw_dma_chip_pdata },
125
153
126
154
/* Broadwell */
127
-
{ PCI_VDEVICE(INTEL, 0x9ce0), (kernel_ulong_t)&dw_pci_data },
155
+
{ PCI_VDEVICE(INTEL, 0x9ce0), (kernel_ulong_t)&dw_dma_chip_pdata },
128
156
129
157
{ }
130
158
};
+48
-173
drivers/dma/dw/platform.c
+48
-173
drivers/dma/dw/platform.c
···
17
17
#include <linux/dmaengine.h>
18
18
#include <linux/dma-mapping.h>
19
19
#include <linux/of.h>
20
-
#include <linux/of_dma.h>
21
20
#include <linux/acpi.h>
22
-
#include <linux/acpi_dma.h>
23
21
24
22
#include "internal.h"
25
23
26
24
#define DRV_NAME "dw_dmac"
27
25
28
-
static struct dma_chan *dw_dma_of_xlate(struct of_phandle_args *dma_spec,
29
-
struct of_dma *ofdma)
30
-
{
31
-
struct dw_dma *dw = ofdma->of_dma_data;
32
-
struct dw_dma_slave slave = {
33
-
.dma_dev = dw->dma.dev,
34
-
};
35
-
dma_cap_mask_t cap;
36
-
37
-
if (dma_spec->args_count != 3)
38
-
return NULL;
39
-
40
-
slave.src_id = dma_spec->args[0];
41
-
slave.dst_id = dma_spec->args[0];
42
-
slave.m_master = dma_spec->args[1];
43
-
slave.p_master = dma_spec->args[2];
44
-
45
-
if (WARN_ON(slave.src_id >= DW_DMA_MAX_NR_REQUESTS ||
46
-
slave.dst_id >= DW_DMA_MAX_NR_REQUESTS ||
47
-
slave.m_master >= dw->pdata->nr_masters ||
48
-
slave.p_master >= dw->pdata->nr_masters))
49
-
return NULL;
50
-
51
-
dma_cap_zero(cap);
52
-
dma_cap_set(DMA_SLAVE, cap);
53
-
54
-
/* TODO: there should be a simpler way to do this */
55
-
return dma_request_channel(cap, dw_dma_filter, &slave);
56
-
}
57
-
58
-
#ifdef CONFIG_ACPI
59
-
static bool dw_dma_acpi_filter(struct dma_chan *chan, void *param)
60
-
{
61
-
struct acpi_dma_spec *dma_spec = param;
62
-
struct dw_dma_slave slave = {
63
-
.dma_dev = dma_spec->dev,
64
-
.src_id = dma_spec->slave_id,
65
-
.dst_id = dma_spec->slave_id,
66
-
.m_master = 0,
67
-
.p_master = 1,
68
-
};
69
-
70
-
return dw_dma_filter(chan, &slave);
71
-
}
72
-
73
-
static void dw_dma_acpi_controller_register(struct dw_dma *dw)
74
-
{
75
-
struct device *dev = dw->dma.dev;
76
-
struct acpi_dma_filter_info *info;
77
-
int ret;
78
-
79
-
info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
80
-
if (!info)
81
-
return;
82
-
83
-
dma_cap_zero(info->dma_cap);
84
-
dma_cap_set(DMA_SLAVE, info->dma_cap);
85
-
info->filter_fn = dw_dma_acpi_filter;
86
-
87
-
ret = devm_acpi_dma_controller_register(dev, acpi_dma_simple_xlate,
88
-
info);
89
-
if (ret)
90
-
dev_err(dev, "could not register acpi_dma_controller\n");
91
-
}
92
-
#else /* !CONFIG_ACPI */
93
-
static inline void dw_dma_acpi_controller_register(struct dw_dma *dw) {}
94
-
#endif /* !CONFIG_ACPI */
95
-
96
-
#ifdef CONFIG_OF
97
-
static struct dw_dma_platform_data *
98
-
dw_dma_parse_dt(struct platform_device *pdev)
99
-
{
100
-
struct device_node *np = pdev->dev.of_node;
101
-
struct dw_dma_platform_data *pdata;
102
-
u32 tmp, arr[DW_DMA_MAX_NR_MASTERS], mb[DW_DMA_MAX_NR_CHANNELS];
103
-
u32 nr_masters;
104
-
u32 nr_channels;
105
-
106
-
if (!np) {
107
-
dev_err(&pdev->dev, "Missing DT data\n");
108
-
return NULL;
109
-
}
110
-
111
-
if (of_property_read_u32(np, "dma-masters", &nr_masters))
112
-
return NULL;
113
-
if (nr_masters < 1 || nr_masters > DW_DMA_MAX_NR_MASTERS)
114
-
return NULL;
115
-
116
-
if (of_property_read_u32(np, "dma-channels", &nr_channels))
117
-
return NULL;
118
-
if (nr_channels > DW_DMA_MAX_NR_CHANNELS)
119
-
return NULL;
120
-
121
-
pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
122
-
if (!pdata)
123
-
return NULL;
124
-
125
-
pdata->nr_masters = nr_masters;
126
-
pdata->nr_channels = nr_channels;
127
-
128
-
if (!of_property_read_u32(np, "chan_allocation_order", &tmp))
129
-
pdata->chan_allocation_order = (unsigned char)tmp;
130
-
131
-
if (!of_property_read_u32(np, "chan_priority", &tmp))
132
-
pdata->chan_priority = tmp;
133
-
134
-
if (!of_property_read_u32(np, "block_size", &tmp))
135
-
pdata->block_size = tmp;
136
-
137
-
if (!of_property_read_u32_array(np, "data-width", arr, nr_masters)) {
138
-
for (tmp = 0; tmp < nr_masters; tmp++)
139
-
pdata->data_width[tmp] = arr[tmp];
140
-
} else if (!of_property_read_u32_array(np, "data_width", arr, nr_masters)) {
141
-
for (tmp = 0; tmp < nr_masters; tmp++)
142
-
pdata->data_width[tmp] = BIT(arr[tmp] & 0x07);
143
-
}
144
-
145
-
if (!of_property_read_u32_array(np, "multi-block", mb, nr_channels)) {
146
-
for (tmp = 0; tmp < nr_channels; tmp++)
147
-
pdata->multi_block[tmp] = mb[tmp];
148
-
} else {
149
-
for (tmp = 0; tmp < nr_channels; tmp++)
150
-
pdata->multi_block[tmp] = 1;
151
-
}
152
-
153
-
if (!of_property_read_u32(np, "snps,dma-protection-control", &tmp)) {
154
-
if (tmp > CHAN_PROTCTL_MASK)
155
-
return NULL;
156
-
pdata->protctl = tmp;
157
-
}
158
-
159
-
return pdata;
160
-
}
161
-
#else
162
-
static inline struct dw_dma_platform_data *
163
-
dw_dma_parse_dt(struct platform_device *pdev)
164
-
{
165
-
return NULL;
166
-
}
167
-
#endif
168
-
169
26
static int dw_probe(struct platform_device *pdev)
170
27
{
28
+
const struct dw_dma_chip_pdata *match;
29
+
struct dw_dma_chip_pdata *data;
171
30
struct dw_dma_chip *chip;
172
31
struct device *dev = &pdev->dev;
173
-
struct resource *mem;
174
-
const struct dw_dma_platform_data *pdata;
175
32
int err;
33
+
34
+
match = device_get_match_data(dev);
35
+
if (!match)
36
+
return -ENODEV;
37
+
38
+
data = devm_kmemdup(&pdev->dev, match, sizeof(*match), GFP_KERNEL);
39
+
if (!data)
40
+
return -ENOMEM;
176
41
177
42
chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
178
43
if (!chip)
···
47
182
if (chip->irq < 0)
48
183
return chip->irq;
49
184
50
-
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
51
-
chip->regs = devm_ioremap_resource(dev, mem);
185
+
chip->regs = devm_platform_ioremap_resource(pdev, 0);
52
186
if (IS_ERR(chip->regs))
53
187
return PTR_ERR(chip->regs);
54
188
···
55
191
if (err)
56
192
return err;
57
193
58
-
pdata = dev_get_platdata(dev);
59
-
if (!pdata)
60
-
pdata = dw_dma_parse_dt(pdev);
194
+
if (!data->pdata)
195
+
data->pdata = dev_get_platdata(dev);
196
+
if (!data->pdata)
197
+
data->pdata = dw_dma_parse_dt(pdev);
61
198
62
199
chip->dev = dev;
63
200
chip->id = pdev->id;
64
-
chip->pdata = pdata;
201
+
chip->pdata = data->pdata;
202
+
203
+
data->chip = chip;
65
204
66
205
chip->clk = devm_clk_get(chip->dev, "hclk");
67
206
if (IS_ERR(chip->clk))
···
75
208
76
209
pm_runtime_enable(&pdev->dev);
77
210
78
-
err = dw_dma_probe(chip);
211
+
err = data->probe(chip);
79
212
if (err)
80
213
goto err_dw_dma_probe;
81
214
82
-
platform_set_drvdata(pdev, chip);
215
+
platform_set_drvdata(pdev, data);
83
216
84
-
if (pdev->dev.of_node) {
85
-
err = of_dma_controller_register(pdev->dev.of_node,
86
-
dw_dma_of_xlate, chip->dw);
87
-
if (err)
88
-
dev_err(&pdev->dev,
89
-
"could not register of_dma_controller\n");
90
-
}
217
+
dw_dma_of_controller_register(chip->dw);
91
218
92
-
if (ACPI_HANDLE(&pdev->dev))
93
-
dw_dma_acpi_controller_register(chip->dw);
219
+
dw_dma_acpi_controller_register(chip->dw);
94
220
95
221
return 0;
96
222
···
95
235
96
236
static int dw_remove(struct platform_device *pdev)
97
237
{
98
-
struct dw_dma_chip *chip = platform_get_drvdata(pdev);
238
+
struct dw_dma_chip_pdata *data = platform_get_drvdata(pdev);
239
+
struct dw_dma_chip *chip = data->chip;
240
+
int ret;
99
241
100
-
if (pdev->dev.of_node)
101
-
of_dma_controller_free(pdev->dev.of_node);
242
+
dw_dma_acpi_controller_free(chip->dw);
102
243
103
-
dw_dma_remove(chip);
244
+
dw_dma_of_controller_free(chip->dw);
245
+
246
+
ret = data->remove(chip);
247
+
if (ret)
248
+
dev_warn(chip->dev, "can't remove device properly: %d\n", ret);
249
+
104
250
pm_runtime_disable(&pdev->dev);
105
251
clk_disable_unprepare(chip->clk);
106
252
···
115
249
116
250
static void dw_shutdown(struct platform_device *pdev)
117
251
{
118
-
struct dw_dma_chip *chip = platform_get_drvdata(pdev);
252
+
struct dw_dma_chip_pdata *data = platform_get_drvdata(pdev);
253
+
struct dw_dma_chip *chip = data->chip;
119
254
120
255
/*
121
256
* We have to call do_dw_dma_disable() to stop any ongoing transfer. On
···
136
269
137
270
#ifdef CONFIG_OF
138
271
static const struct of_device_id dw_dma_of_id_table[] = {
139
-
{ .compatible = "snps,dma-spear1340" },
272
+
{ .compatible = "snps,dma-spear1340", .data = &dw_dma_chip_pdata },
140
273
{}
141
274
};
142
275
MODULE_DEVICE_TABLE(of, dw_dma_of_id_table);
···
144
277
145
278
#ifdef CONFIG_ACPI
146
279
static const struct acpi_device_id dw_dma_acpi_id_table[] = {
147
-
{ "INTL9C60", 0 },
148
-
{ "80862286", 0 },
149
-
{ "808622C0", 0 },
280
+
{ "INTL9C60", (kernel_ulong_t)&dw_dma_chip_pdata },
281
+
{ "80862286", (kernel_ulong_t)&dw_dma_chip_pdata },
282
+
{ "808622C0", (kernel_ulong_t)&dw_dma_chip_pdata },
283
+
284
+
/* Elkhart Lake iDMA 32-bit (PSE DMA) */
285
+
{ "80864BB4", (kernel_ulong_t)&idma32_chip_pdata },
286
+
{ "80864BB5", (kernel_ulong_t)&idma32_chip_pdata },
287
+
{ "80864BB6", (kernel_ulong_t)&idma32_chip_pdata },
288
+
150
289
{ }
151
290
};
152
291
MODULE_DEVICE_TABLE(acpi, dw_dma_acpi_id_table);
···
162
289
163
290
static int dw_suspend_late(struct device *dev)
164
291
{
165
-
struct dw_dma_chip *chip = dev_get_drvdata(dev);
292
+
struct dw_dma_chip_pdata *data = dev_get_drvdata(dev);
293
+
struct dw_dma_chip *chip = data->chip;
166
294
167
295
do_dw_dma_disable(chip);
168
296
clk_disable_unprepare(chip->clk);
···
173
299
174
300
static int dw_resume_early(struct device *dev)
175
301
{
176
-
struct dw_dma_chip *chip = dev_get_drvdata(dev);
302
+
struct dw_dma_chip_pdata *data = dev_get_drvdata(dev);
303
+
struct dw_dma_chip *chip = data->chip;
177
304
int ret;
178
305
179
306
ret = clk_prepare_enable(chip->clk);
+18
-2
drivers/dma/fsl-edma-common.c
+18
-2
drivers/dma/fsl-edma-common.c
···
90
90
iowrite8(val8, addr + off);
91
91
}
92
92
93
+
static void mux_configure32(struct fsl_edma_chan *fsl_chan, void __iomem *addr,
94
+
u32 off, u32 slot, bool enable)
95
+
{
96
+
u32 val;
97
+
98
+
if (enable)
99
+
val = EDMAMUX_CHCFG_ENBL << 24 | slot;
100
+
else
101
+
val = EDMAMUX_CHCFG_DIS;
102
+
103
+
iowrite32(val, addr + off * 4);
104
+
}
105
+
93
106
void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan,
94
-
unsigned int slot, bool enable)
107
+
unsigned int slot, bool enable)
95
108
{
96
109
u32 ch = fsl_chan->vchan.chan.chan_id;
97
110
void __iomem *muxaddr;
···
116
103
muxaddr = fsl_chan->edma->muxbase[ch / chans_per_mux];
117
104
slot = EDMAMUX_CHCFG_SOURCE(slot);
118
105
119
-
mux_configure8(fsl_chan, muxaddr, ch_off, slot, enable);
106
+
if (fsl_chan->edma->drvdata->version == v3)
107
+
mux_configure32(fsl_chan, muxaddr, ch_off, slot, enable);
108
+
else
109
+
mux_configure8(fsl_chan, muxaddr, ch_off, slot, enable);
120
110
}
121
111
EXPORT_SYMBOL_GPL(fsl_edma_chan_mux);
122
112
+4
drivers/dma/fsl-edma-common.h
+4
drivers/dma/fsl-edma-common.h
···
125
125
dma_addr_t dma_dev_addr;
126
126
u32 dma_dev_size;
127
127
enum dma_data_direction dma_dir;
128
+
char chan_name[16];
128
129
};
129
130
130
131
struct fsl_edma_desc {
···
140
139
enum edma_version {
141
140
v1, /* 32ch, Vybrid, mpc57x, etc */
142
141
v2, /* 64ch Coldfire */
142
+
v3, /* 32ch, i.mx7ulp */
143
143
};
144
144
145
145
struct fsl_edma_drvdata {
146
146
enum edma_version version;
147
147
u32 dmamuxs;
148
+
bool has_dmaclk;
148
149
int (*setup_irq)(struct platform_device *pdev,
149
150
struct fsl_edma_engine *fsl_edma);
150
151
};
···
156
153
void __iomem *membase;
157
154
void __iomem *muxbase[DMAMUX_NR];
158
155
struct clk *muxclk[DMAMUX_NR];
156
+
struct clk *dmaclk;
159
157
struct mutex fsl_edma_mutex;
160
158
const struct fsl_edma_drvdata *drvdata;
161
159
u32 n_chans;
+75
-6
drivers/dma/fsl-edma.c
+75
-6
drivers/dma/fsl-edma.c
···
20
20
21
21
#include "fsl-edma-common.h"
22
22
23
+
static void fsl_edma_synchronize(struct dma_chan *chan)
24
+
{
25
+
struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
26
+
27
+
vchan_synchronize(&fsl_chan->vchan);
28
+
}
29
+
23
30
static irqreturn_t fsl_edma_tx_handler(int irq, void *dev_id)
24
31
{
25
32
struct fsl_edma_engine *fsl_edma = dev_id;
···
132
125
int ret;
133
126
134
127
fsl_edma->txirq = platform_get_irq_byname(pdev, "edma-tx");
135
-
if (fsl_edma->txirq < 0) {
136
-
dev_err(&pdev->dev, "Can't get edma-tx irq.\n");
128
+
if (fsl_edma->txirq < 0)
137
129
return fsl_edma->txirq;
138
-
}
139
130
140
131
fsl_edma->errirq = platform_get_irq_byname(pdev, "edma-err");
141
-
if (fsl_edma->errirq < 0) {
142
-
dev_err(&pdev->dev, "Can't get edma-err irq.\n");
132
+
if (fsl_edma->errirq < 0)
143
133
return fsl_edma->errirq;
144
-
}
145
134
146
135
if (fsl_edma->txirq == fsl_edma->errirq) {
147
136
ret = devm_request_irq(&pdev->dev, fsl_edma->txirq,
···
160
157
dev_err(&pdev->dev, "Can't register eDMA err IRQ.\n");
161
158
return ret;
162
159
}
160
+
}
161
+
162
+
return 0;
163
+
}
164
+
165
+
static int
166
+
fsl_edma2_irq_init(struct platform_device *pdev,
167
+
struct fsl_edma_engine *fsl_edma)
168
+
{
169
+
int i, ret, irq;
170
+
int count;
171
+
172
+
count = platform_irq_count(pdev);
173
+
dev_dbg(&pdev->dev, "%s Found %d interrupts\r\n", __func__, count);
174
+
if (count <= 2) {
175
+
dev_err(&pdev->dev, "Interrupts in DTS not correct.\n");
176
+
return -EINVAL;
177
+
}
178
+
/*
179
+
* 16 channel independent interrupts + 1 error interrupt on i.mx7ulp.
180
+
* 2 channel share one interrupt, for example, ch0/ch16, ch1/ch17...
181
+
* For now, just simply request irq without IRQF_SHARED flag, since 16
182
+
* channels are enough on i.mx7ulp whose M4 domain own some peripherals.
183
+
*/
184
+
for (i = 0; i < count; i++) {
185
+
irq = platform_get_irq(pdev, i);
186
+
if (irq < 0)
187
+
return -ENXIO;
188
+
189
+
sprintf(fsl_edma->chans[i].chan_name, "eDMA2-CH%02d", i);
190
+
191
+
/* The last IRQ is for eDMA err */
192
+
if (i == count - 1)
193
+
ret = devm_request_irq(&pdev->dev, irq,
194
+
fsl_edma_err_handler,
195
+
0, "eDMA2-ERR", fsl_edma);
196
+
else
197
+
ret = devm_request_irq(&pdev->dev, irq,
198
+
fsl_edma_tx_handler, 0,
199
+
fsl_edma->chans[i].chan_name,
200
+
fsl_edma);
201
+
if (ret)
202
+
return ret;
163
203
}
164
204
165
205
return 0;
···
233
187
.setup_irq = fsl_edma_irq_init,
234
188
};
235
189
190
+
static struct fsl_edma_drvdata imx7ulp_data = {
191
+
.version = v3,
192
+
.dmamuxs = 1,
193
+
.has_dmaclk = true,
194
+
.setup_irq = fsl_edma2_irq_init,
195
+
};
196
+
236
197
static const struct of_device_id fsl_edma_dt_ids[] = {
237
198
{ .compatible = "fsl,vf610-edma", .data = &vf610_data},
199
+
{ .compatible = "fsl,imx7ulp-edma", .data = &imx7ulp_data},
238
200
{ /* sentinel */ }
239
201
};
240
202
MODULE_DEVICE_TABLE(of, fsl_edma_dt_ids);
···
289
235
290
236
fsl_edma_setup_regs(fsl_edma);
291
237
regs = &fsl_edma->regs;
238
+
239
+
if (drvdata->has_dmaclk) {
240
+
fsl_edma->dmaclk = devm_clk_get(&pdev->dev, "dma");
241
+
if (IS_ERR(fsl_edma->dmaclk)) {
242
+
dev_err(&pdev->dev, "Missing DMA block clock.\n");
243
+
return PTR_ERR(fsl_edma->dmaclk);
244
+
}
245
+
246
+
ret = clk_prepare_enable(fsl_edma->dmaclk);
247
+
if (ret) {
248
+
dev_err(&pdev->dev, "DMA clk block failed.\n");
249
+
return ret;
250
+
}
251
+
}
292
252
293
253
for (i = 0; i < fsl_edma->drvdata->dmamuxs; i++) {
294
254
char clkname[32];
···
370
302
fsl_edma->dma_dev.device_pause = fsl_edma_pause;
371
303
fsl_edma->dma_dev.device_resume = fsl_edma_resume;
372
304
fsl_edma->dma_dev.device_terminate_all = fsl_edma_terminate_all;
305
+
fsl_edma->dma_dev.device_synchronize = fsl_edma_synchronize;
373
306
fsl_edma->dma_dev.device_issue_pending = fsl_edma_issue_pending;
374
307
375
308
fsl_edma->dma_dev.src_addr_widths = FSL_EDMA_BUSWIDTHS;
+2
-7
drivers/dma/fsl-qdma.c
+2
-7
drivers/dma/fsl-qdma.c
···
758
758
759
759
fsl_qdma->error_irq =
760
760
platform_get_irq_byname(pdev, "qdma-error");
761
-
if (fsl_qdma->error_irq < 0) {
762
-
dev_err(&pdev->dev, "Can't get qdma controller irq.\n");
761
+
if (fsl_qdma->error_irq < 0)
763
762
return fsl_qdma->error_irq;
764
-
}
765
763
766
764
ret = devm_request_irq(&pdev->dev, fsl_qdma->error_irq,
767
765
fsl_qdma_error_handler, 0,
···
774
776
fsl_qdma->queue_irq[i] =
775
777
platform_get_irq_byname(pdev, irq_name);
776
778
777
-
if (fsl_qdma->queue_irq[i] < 0) {
778
-
dev_err(&pdev->dev,
779
-
"Can't get qdma queue %d irq.\n", i);
779
+
if (fsl_qdma->queue_irq[i] < 0)
780
780
return fsl_qdma->queue_irq[i];
781
-
}
782
781
783
782
ret = devm_request_irq(&pdev->dev,
784
783
fsl_qdma->queue_irq[i],
+1
drivers/dma/imx-dma.c
+1
drivers/dma/imx-dma.c
···
556
556
* We fall-through here intentionally, since a 2D transfer is
557
557
* similar to MEMCPY just adding the 2D slot configuration.
558
558
*/
559
+
/* Fall through */
559
560
case IMXDMA_DESC_MEMCPY:
560
561
imx_dmav1_writel(imxdma, d->src, DMA_SAR(imxdmac->channel));
561
562
imx_dmav1_writel(imxdma, d->dest, DMA_DAR(imxdmac->channel));
-4
drivers/dma/imx-sdma.c
-4
drivers/dma/imx-sdma.c
···
1886
1886
sdma->context_phys = ccb_phys +
1887
1887
MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1888
1888
1889
-
/* Zero-out the CCB structures array just allocated */
1890
-
memset(sdma->channel_control, 0,
1891
-
MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control));
1892
-
1893
1889
/* disable all channels */
1894
1890
for (i = 0; i < sdma->drvdata->num_events; i++)
1895
1891
writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i));
+1
-2
drivers/dma/ioat/dca.c
+1
-2
drivers/dma/ioat/dca.c
+2
-4
drivers/dma/iop-adma.c
+2
-4
drivers/dma/iop-adma.c
···
116
116
list_for_each_entry_safe(iter, _iter, &iop_chan->chain,
117
117
chain_node) {
118
118
pr_debug("\tcookie: %d slot: %d busy: %d "
119
-
"this_desc: %#x next_desc: %#llx ack: %d\n",
119
+
"this_desc: %pad next_desc: %#llx ack: %d\n",
120
120
iter->async_tx.cookie, iter->idx, busy,
121
-
iter->async_tx.phys, (u64)iop_desc_get_next_desc(iter),
121
+
&iter->async_tx.phys, (u64)iop_desc_get_next_desc(iter),
122
122
async_tx_test_ack(&iter->async_tx));
123
123
prefetch(_iter);
124
124
prefetch(&_iter->async_tx);
···
364
364
struct iop_adma_chan *iop_chan = to_iop_adma_chan(tx->chan);
365
365
struct iop_adma_desc_slot *grp_start, *old_chain_tail;
366
366
int slot_cnt;
367
-
int slots_per_op;
368
367
dma_cookie_t cookie;
369
368
dma_addr_t next_dma;
370
369
371
370
grp_start = sw_desc->group_head;
372
371
slot_cnt = grp_start->slot_cnt;
373
-
slots_per_op = grp_start->slots_per_op;
374
372
375
373
spin_lock_bh(&iop_chan->lock);
376
374
cookie = dma_cookie_assign(tx);
+1
-3
drivers/dma/mediatek/mtk-uart-apdma.c
+1
-3
drivers/dma/mediatek/mtk-uart-apdma.c
+4
-7
drivers/dma/mv_xor_v2.c
+4
-7
drivers/dma/mv_xor_v2.c
···
33
33
#define MV_XOR_V2_DMA_IMSG_CDAT_OFF 0x014
34
34
#define MV_XOR_V2_DMA_IMSG_THRD_OFF 0x018
35
35
#define MV_XOR_V2_DMA_IMSG_THRD_MASK 0x7FFF
36
-
#define MV_XOR_V2_DMA_IMSG_THRD_SHIFT 0x0
37
36
#define MV_XOR_V2_DMA_IMSG_TIMER_EN BIT(18)
38
37
#define MV_XOR_V2_DMA_DESQ_AWATTR_OFF 0x01C
39
38
/* Same flags as MV_XOR_V2_DMA_DESQ_ARATTR_OFF */
···
49
50
#define MV_XOR_V2_DMA_DESQ_ADD_OFF 0x808
50
51
#define MV_XOR_V2_DMA_IMSG_TMOT 0x810
51
52
#define MV_XOR_V2_DMA_IMSG_TIMER_THRD_MASK 0x1FFF
52
-
#define MV_XOR_V2_DMA_IMSG_TIMER_THRD_SHIFT 0
53
53
54
54
/* XOR Global registers */
55
55
#define MV_XOR_V2_GLOB_BW_CTRL 0x4
···
259
261
260
262
/* Configure threshold of number of descriptors, and enable timer */
261
263
reg = readl(xor_dev->dma_base + MV_XOR_V2_DMA_IMSG_THRD_OFF);
262
-
reg &= (~MV_XOR_V2_DMA_IMSG_THRD_MASK << MV_XOR_V2_DMA_IMSG_THRD_SHIFT);
263
-
reg |= (MV_XOR_V2_DONE_IMSG_THRD << MV_XOR_V2_DMA_IMSG_THRD_SHIFT);
264
+
reg &= ~MV_XOR_V2_DMA_IMSG_THRD_MASK;
265
+
reg |= MV_XOR_V2_DONE_IMSG_THRD;
264
266
reg |= MV_XOR_V2_DMA_IMSG_TIMER_EN;
265
267
writel(reg, xor_dev->dma_base + MV_XOR_V2_DMA_IMSG_THRD_OFF);
266
268
267
269
/* Configure Timer Threshold */
268
270
reg = readl(xor_dev->dma_base + MV_XOR_V2_DMA_IMSG_TMOT);
269
-
reg &= (~MV_XOR_V2_DMA_IMSG_TIMER_THRD_MASK <<
270
-
MV_XOR_V2_DMA_IMSG_TIMER_THRD_SHIFT);
271
-
reg |= (MV_XOR_V2_TIMER_THRD << MV_XOR_V2_DMA_IMSG_TIMER_THRD_SHIFT);
271
+
reg &= ~MV_XOR_V2_DMA_IMSG_TIMER_THRD_MASK;
272
+
reg |= MV_XOR_V2_TIMER_THRD;
272
273
writel(reg, xor_dev->dma_base + MV_XOR_V2_DMA_IMSG_TMOT);
273
274
}
274
275
+5
-4
drivers/dma/pl330.c
+5
-4
drivers/dma/pl330.c
···
1922
1922
if (ret) {
1923
1923
dev_err(pl330->ddma.dev, "%s:%d Can't to create channels for DMAC!\n",
1924
1924
__func__, __LINE__);
1925
-
dma_free_coherent(pl330->ddma.dev,
1925
+
dma_free_attrs(pl330->ddma.dev,
1926
1926
chans * pl330->mcbufsz,
1927
-
pl330->mcode_cpu, pl330->mcode_bus);
1927
+
pl330->mcode_cpu, pl330->mcode_bus,
1928
+
DMA_ATTR_PRIVILEGED);
1928
1929
return ret;
1929
1930
}
1930
1931
···
2004
2003
/* Free DMAC resources */
2005
2004
dmac_free_threads(pl330);
2006
2005
2007
-
dma_free_coherent(pl330->ddma.dev,
2006
+
dma_free_attrs(pl330->ddma.dev,
2008
2007
pl330->pcfg.num_chan * pl330->mcbufsz, pl330->mcode_cpu,
2009
-
pl330->mcode_bus);
2008
+
pl330->mcode_bus, DMA_ATTR_PRIVILEGED);
2010
2009
}
2011
2010
2012
2011
/* forward declaration */
-2
drivers/dma/qcom/hidma_ll.c
-2
drivers/dma/qcom/hidma_ll.c
···
749
749
if (!lldev->tre_ring)
750
750
return NULL;
751
751
752
-
memset(lldev->tre_ring, 0, (HIDMA_TRE_SIZE + 1) * nr_tres);
753
752
lldev->tre_ring_size = HIDMA_TRE_SIZE * nr_tres;
754
753
lldev->nr_tres = nr_tres;
755
754
···
768
769
if (!lldev->evre_ring)
769
770
return NULL;
770
771
771
-
memset(lldev->evre_ring, 0, (HIDMA_EVRE_SIZE + 1) * nr_tres);
772
772
lldev->evre_ring_size = HIDMA_EVRE_SIZE * nr_tres;
773
773
774
774
/* the EVRE ring has to be EVRE_SIZE aligned */
+6
-3
drivers/dma/qcom/hidma_mgmt.c
+6
-3
drivers/dma/qcom/hidma_mgmt.c
···
183
183
184
184
irq = platform_get_irq(pdev, 0);
185
185
if (irq < 0) {
186
-
dev_err(&pdev->dev, "irq resources not found\n");
187
186
rc = irq;
188
187
goto out;
189
188
}
···
387
388
ret = PTR_ERR(new_pdev);
388
389
goto out;
389
390
}
390
-
of_node_get(child);
391
391
new_pdev->dev.of_node = child;
392
392
of_dma_configure(&new_pdev->dev, child, true);
393
393
/*
···
394
396
* platforms with or without MSI support.
395
397
*/
396
398
of_msi_configure(&new_pdev->dev, child);
397
-
of_node_put(child);
398
399
}
400
+
401
+
kfree(res);
402
+
403
+
return ret;
404
+
399
405
out:
406
+
of_node_put(child);
400
407
kfree(res);
401
408
402
409
return ret;
+1
-4
drivers/dma/s3c24xx-dma.c
+1
-4
drivers/dma/s3c24xx-dma.c
···
1237
1237
phy->host = s3cdma;
1238
1238
1239
1239
phy->irq = platform_get_irq(pdev, i);
1240
-
if (phy->irq < 0) {
1241
-
dev_err(&pdev->dev, "failed to get irq %d, err %d\n",
1242
-
i, phy->irq);
1240
+
if (phy->irq < 0)
1243
1241
continue;
1244
-
}
1245
1242
1246
1243
ret = devm_request_irq(&pdev->dev, phy->irq, s3c24xx_dma_irq,
1247
1244
0, pdev->name, phy);
+1
-3
drivers/dma/sh/rcar-dmac.c
+1
-3
drivers/dma/sh/rcar-dmac.c
···
1749
1749
/* Request the channel interrupt. */
1750
1750
sprintf(pdev_irqname, "ch%u", index);
1751
1751
rchan->irq = platform_get_irq_byname(pdev, pdev_irqname);
1752
-
if (rchan->irq < 0) {
1753
-
dev_err(dmac->dev, "no IRQ specified for channel %u\n", index);
1752
+
if (rchan->irq < 0)
1754
1753
return -ENODEV;
1755
-
}
1756
1754
1757
1755
irqname = devm_kasprintf(dmac->dev, GFP_KERNEL, "%s:%u",
1758
1756
dev_name(dmac->dev), index);
+1
-3
drivers/dma/sh/usb-dmac.c
+1
-3
drivers/dma/sh/usb-dmac.c
···
717
717
/* Request the channel interrupt. */
718
718
sprintf(pdev_irqname, "ch%u", index);
719
719
uchan->irq = platform_get_irq_byname(pdev, pdev_irqname);
720
-
if (uchan->irq < 0) {
721
-
dev_err(dmac->dev, "no IRQ specified for channel %u\n", index);
720
+
if (uchan->irq < 0)
722
721
return -ENODEV;
723
-
}
724
722
725
723
irqname = devm_kasprintf(dmac->dev, GFP_KERNEL, "%s:%u",
726
724
dev_name(dmac->dev), index);
+1
-3
drivers/dma/st_fdma.c
+1
-3
drivers/dma/st_fdma.c
···
771
771
platform_set_drvdata(pdev, fdev);
772
772
773
773
fdev->irq = platform_get_irq(pdev, 0);
774
-
if (fdev->irq < 0) {
775
-
dev_err(&pdev->dev, "Failed to get irq resource\n");
774
+
if (fdev->irq < 0)
776
775
return -EINVAL;
777
-
}
778
776
779
777
ret = devm_request_irq(&pdev->dev, fdev->irq, st_fdma_irq_handler, 0,
780
778
dev_name(&pdev->dev), fdev);
+4
-14
drivers/dma/stm32-dma.c
+4
-14
drivers/dma/stm32-dma.c
···
243
243
writel_relaxed(val, dmadev->base + reg);
244
244
}
245
245
246
-
static struct stm32_dma_desc *stm32_dma_alloc_desc(u32 num_sgs)
247
-
{
248
-
return kzalloc(sizeof(struct stm32_dma_desc) +
249
-
sizeof(struct stm32_dma_sg_req) * num_sgs, GFP_NOWAIT);
250
-
}
251
-
252
246
static int stm32_dma_get_width(struct stm32_dma_chan *chan,
253
247
enum dma_slave_buswidth width)
254
248
{
···
847
853
return NULL;
848
854
}
849
855
850
-
desc = stm32_dma_alloc_desc(sg_len);
856
+
desc = kzalloc(struct_size(desc, sg_req, sg_len), GFP_NOWAIT);
851
857
if (!desc)
852
858
return NULL;
853
859
···
948
954
949
955
num_periods = buf_len / period_len;
950
956
951
-
desc = stm32_dma_alloc_desc(num_periods);
957
+
desc = kzalloc(struct_size(desc, sg_req, num_periods), GFP_NOWAIT);
952
958
if (!desc)
953
959
return NULL;
954
960
···
983
989
int i;
984
990
985
991
num_sgs = DIV_ROUND_UP(len, STM32_DMA_ALIGNED_MAX_DATA_ITEMS);
986
-
desc = stm32_dma_alloc_desc(num_sgs);
992
+
desc = kzalloc(struct_size(desc, sg_req, num_sgs), GFP_NOWAIT);
987
993
if (!desc)
988
994
return NULL;
989
995
···
1360
1366
for (i = 0; i < STM32_DMA_MAX_CHANNELS; i++) {
1361
1367
chan = &dmadev->chan[i];
1362
1368
ret = platform_get_irq(pdev, i);
1363
-
if (ret < 0) {
1364
-
if (ret != -EPROBE_DEFER)
1365
-
dev_err(&pdev->dev,
1366
-
"No irq resource for chan %d\n", i);
1369
+
if (ret < 0)
1367
1370
goto err_unregister;
1368
-
}
1369
1371
chan->irq = ret;
1370
1372
1371
1373
ret = devm_request_irq(&pdev->dev, chan->irq,
+1
-2
drivers/dma/stm32-dmamux.c
+1
-2
drivers/dma/stm32-dmamux.c
···
185
185
if (!node)
186
186
return -ENODEV;
187
187
188
-
count = device_property_read_u32_array(&pdev->dev, "dma-masters",
189
-
NULL, 0);
188
+
count = device_property_count_u32(&pdev->dev, "dma-masters");
190
189
if (count < 0) {
191
190
dev_err(&pdev->dev, "Can't get DMA master(s) node\n");
192
191
return -ENODEV;
+2
-5
drivers/dma/stm32-mdma.c
+2
-5
drivers/dma/stm32-mdma.c
···
1555
1555
nr_requests);
1556
1556
}
1557
1557
1558
-
count = device_property_read_u32_array(&pdev->dev, "st,ahb-addr-masks",
1559
-
NULL, 0);
1558
+
count = device_property_count_u32(&pdev->dev, "st,ahb-addr-masks");
1560
1559
if (count < 0)
1561
1560
count = 0;
1562
1561
···
1637
1638
}
1638
1639
1639
1640
dmadev->irq = platform_get_irq(pdev, 0);
1640
-
if (dmadev->irq < 0) {
1641
-
dev_err(&pdev->dev, "failed to get IRQ\n");
1641
+
if (dmadev->irq < 0)
1642
1642
return dmadev->irq;
1643
-
}
1644
1643
1645
1644
ret = devm_request_irq(&pdev->dev, dmadev->irq, stm32_mdma_irq_handler,
1646
1645
0, dev_name(&pdev->dev), dmadev);
+1
-3
drivers/dma/sun4i-dma.c
+1
-3
drivers/dma/sun4i-dma.c
···
1132
1132
return PTR_ERR(priv->base);
1133
1133
1134
1134
priv->irq = platform_get_irq(pdev, 0);
1135
-
if (priv->irq < 0) {
1136
-
dev_err(&pdev->dev, "Cannot claim IRQ\n");
1135
+
if (priv->irq < 0)
1137
1136
return priv->irq;
1138
-
}
1139
1137
1140
1138
priv->clk = devm_clk_get(&pdev->dev, NULL);
1141
1139
if (IS_ERR(priv->clk)) {
+1
-3
drivers/dma/sun6i-dma.c
+1
-3
drivers/dma/sun6i-dma.c
···
1251
1251
return PTR_ERR(sdc->base);
1252
1252
1253
1253
sdc->irq = platform_get_irq(pdev, 0);
1254
-
if (sdc->irq < 0) {
1255
-
dev_err(&pdev->dev, "Cannot claim IRQ\n");
1254
+
if (sdc->irq < 0)
1256
1255
return sdc->irq;
1257
-
}
1258
1256
1259
1257
sdc->clk = devm_clk_get(&pdev->dev, NULL);
1260
1258
if (IS_ERR(sdc->clk)) {
+68
-7
drivers/dma/tegra20-apb-dma.c
+68
-7
drivers/dma/tegra20-apb-dma.c
···
152
152
bool last_sg;
153
153
struct list_head node;
154
154
struct tegra_dma_desc *dma_desc;
155
+
unsigned int words_xferred;
155
156
};
156
157
157
158
/*
···
497
496
tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR,
498
497
nsg_req->ch_regs.csr | TEGRA_APBDMA_CSR_ENB);
499
498
nsg_req->configured = true;
499
+
nsg_req->words_xferred = 0;
500
500
501
501
tegra_dma_resume(tdc);
502
502
}
···
513
511
typeof(*sg_req), node);
514
512
tegra_dma_start(tdc, sg_req);
515
513
sg_req->configured = true;
514
+
sg_req->words_xferred = 0;
516
515
tdc->busy = true;
517
516
}
518
517
···
640
637
if (!dma_desc->cb_count)
641
638
list_add_tail(&dma_desc->cb_node, &tdc->cb_desc);
642
639
dma_desc->cb_count++;
640
+
641
+
sgreq->words_xferred = 0;
643
642
644
643
/* If not last req then put at end of pending list */
645
644
if (!list_is_last(&sgreq->node, &tdc->pending_sg_req)) {
···
802
797
return 0;
803
798
}
804
799
800
+
static unsigned int tegra_dma_sg_bytes_xferred(struct tegra_dma_channel *tdc,
801
+
struct tegra_dma_sg_req *sg_req)
802
+
{
803
+
unsigned long status, wcount = 0;
804
+
805
+
if (!list_is_first(&sg_req->node, &tdc->pending_sg_req))
806
+
return 0;
807
+
808
+
if (tdc->tdma->chip_data->support_separate_wcount_reg)
809
+
wcount = tdc_read(tdc, TEGRA_APBDMA_CHAN_WORD_TRANSFER);
810
+
811
+
status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
812
+
813
+
if (!tdc->tdma->chip_data->support_separate_wcount_reg)
814
+
wcount = status;
815
+
816
+
if (status & TEGRA_APBDMA_STATUS_ISE_EOC)
817
+
return sg_req->req_len;
818
+
819
+
wcount = get_current_xferred_count(tdc, sg_req, wcount);
820
+
821
+
if (!wcount) {
822
+
/*
823
+
* If wcount wasn't ever polled for this SG before, then
824
+
* simply assume that transfer hasn't started yet.
825
+
*
826
+
* Otherwise it's the end of the transfer.
827
+
*
828
+
* The alternative would be to poll the status register
829
+
* until EOC bit is set or wcount goes UP. That's so
830
+
* because EOC bit is getting set only after the last
831
+
* burst's completion and counter is less than the actual
832
+
* transfer size by 4 bytes. The counter value wraps around
833
+
* in a cyclic mode before EOC is set(!), so we can't easily
834
+
* distinguish start of transfer from its end.
835
+
*/
836
+
if (sg_req->words_xferred)
837
+
wcount = sg_req->req_len - 4;
838
+
839
+
} else if (wcount < sg_req->words_xferred) {
840
+
/*
841
+
* This case will never happen for a non-cyclic transfer.
842
+
*
843
+
* For a cyclic transfer, although it is possible for the
844
+
* next transfer to have already started (resetting the word
845
+
* count), this case should still not happen because we should
846
+
* have detected that the EOC bit is set and hence the transfer
847
+
* was completed.
848
+
*/
849
+
WARN_ON_ONCE(1);
850
+
851
+
wcount = sg_req->req_len - 4;
852
+
} else {
853
+
sg_req->words_xferred = wcount;
854
+
}
855
+
856
+
return wcount;
857
+
}
858
+
805
859
static enum dma_status tegra_dma_tx_status(struct dma_chan *dc,
806
860
dma_cookie_t cookie, struct dma_tx_state *txstate)
807
861
{
···
870
806
enum dma_status ret;
871
807
unsigned long flags;
872
808
unsigned int residual;
809
+
unsigned int bytes = 0;
873
810
874
811
ret = dma_cookie_status(dc, cookie, txstate);
875
812
if (ret == DMA_COMPLETE)
···
890
825
list_for_each_entry(sg_req, &tdc->pending_sg_req, node) {
891
826
dma_desc = sg_req->dma_desc;
892
827
if (dma_desc->txd.cookie == cookie) {
828
+
bytes = tegra_dma_sg_bytes_xferred(tdc, sg_req);
893
829
ret = dma_desc->dma_status;
894
830
goto found;
895
831
}
···
902
836
found:
903
837
if (dma_desc && txstate) {
904
838
residual = dma_desc->bytes_requested -
905
-
(dma_desc->bytes_transferred %
839
+
((dma_desc->bytes_transferred + bytes) %
906
840
dma_desc->bytes_requested);
907
841
dma_set_residue(txstate, residual);
908
842
}
···
1507
1441
BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
1508
1442
BIT(DMA_SLAVE_BUSWIDTH_8_BYTES);
1509
1443
tdma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
1510
-
/*
1511
-
* XXX The hardware appears to support
1512
-
* DMA_RESIDUE_GRANULARITY_BURST-level reporting, but it's
1513
-
* only used by this driver during tegra_dma_terminate_all()
1514
-
*/
1515
-
tdma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
1444
+
tdma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1516
1445
tdma->dma_dev.device_config = tegra_dma_slave_config;
1517
1446
tdma->dma_dev.device_terminate_all = tegra_dma_terminate_all;
1518
1447
tdma->dma_dev.device_tx_status = tegra_dma_tx_status;
+2
-10
drivers/dma/tegra210-adma.c
+2
-10
drivers/dma/tegra210-adma.c
···
42
42
#define ADMA_CH_CONFIG_MAX_BUFS 8
43
43
44
44
#define ADMA_CH_FIFO_CTRL 0x2c
45
-
#define TEGRA210_ADMA_CH_FIFO_CTRL_OFLWTHRES(val) (((val) & 0xf) << 24)
46
-
#define TEGRA210_ADMA_CH_FIFO_CTRL_STRVTHRES(val) (((val) & 0xf) << 16)
47
45
#define TEGRA210_ADMA_CH_FIFO_CTRL_TXSIZE(val) (((val) & 0xf) << 8)
48
46
#define TEGRA210_ADMA_CH_FIFO_CTRL_RXSIZE(val) ((val) & 0xf)
49
-
#define TEGRA186_ADMA_CH_FIFO_CTRL_OFLWTHRES(val) (((val) & 0x1f) << 24)
50
-
#define TEGRA186_ADMA_CH_FIFO_CTRL_STRVTHRES(val) (((val) & 0x1f) << 16)
51
47
#define TEGRA186_ADMA_CH_FIFO_CTRL_TXSIZE(val) (((val) & 0x1f) << 8)
52
48
#define TEGRA186_ADMA_CH_FIFO_CTRL_RXSIZE(val) ((val) & 0x1f)
53
49
···
60
64
61
65
#define TEGRA_ADMA_BURST_COMPLETE_TIME 20
62
66
63
-
#define TEGRA210_FIFO_CTRL_DEFAULT (TEGRA210_ADMA_CH_FIFO_CTRL_OFLWTHRES(1) | \
64
-
TEGRA210_ADMA_CH_FIFO_CTRL_STRVTHRES(1) | \
65
-
TEGRA210_ADMA_CH_FIFO_CTRL_TXSIZE(3) | \
67
+
#define TEGRA210_FIFO_CTRL_DEFAULT (TEGRA210_ADMA_CH_FIFO_CTRL_TXSIZE(3) | \
66
68
TEGRA210_ADMA_CH_FIFO_CTRL_RXSIZE(3))
67
69
68
-
#define TEGRA186_FIFO_CTRL_DEFAULT (TEGRA186_ADMA_CH_FIFO_CTRL_OFLWTHRES(1) | \
69
-
TEGRA186_ADMA_CH_FIFO_CTRL_STRVTHRES(1) | \
70
-
TEGRA186_ADMA_CH_FIFO_CTRL_TXSIZE(3) | \
70
+
#define TEGRA186_FIFO_CTRL_DEFAULT (TEGRA186_ADMA_CH_FIFO_CTRL_TXSIZE(3) | \
71
71
TEGRA186_ADMA_CH_FIFO_CTRL_RXSIZE(3))
72
72
73
73
#define ADMA_CH_REG_FIELD_VAL(val, mask, shift) (((val) & mask) << shift)
+144
-84
drivers/dma/ti/edma.c
+144
-84
drivers/dma/ti/edma.c
···
15
15
16
16
#include <linux/dmaengine.h>
17
17
#include <linux/dma-mapping.h>
18
-
#include <linux/edma.h>
18
+
#include <linux/bitmap.h>
19
19
#include <linux/err.h>
20
20
#include <linux/init.h>
21
21
#include <linux/interrupt.h>
···
133
133
#define EDMA_CONT_PARAMS_FIXED_EXACT 1002
134
134
#define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003
135
135
136
+
/*
137
+
* 64bit array registers are split into two 32bit registers:
138
+
* reg0: channel/event 0-31
139
+
* reg1: channel/event 32-63
140
+
*
141
+
* bit 5 in the channel number tells the array index (0/1)
142
+
* bit 0-4 (0x1f) is the bit offset within the register
143
+
*/
144
+
#define EDMA_REG_ARRAY_INDEX(channel) ((channel) >> 5)
145
+
#define EDMA_CHANNEL_BIT(channel) (BIT((channel) & 0x1f))
146
+
136
147
/* PaRAM slots are laid out like this */
137
148
struct edmacc_param {
138
149
u32 opt;
···
180
169
struct list_head node;
181
170
enum dma_transfer_direction direction;
182
171
int cyclic;
172
+
bool polled;
183
173
int absync;
184
174
int pset_nr;
185
175
struct edma_chan *echan;
···
424
412
edma_or(ecc, EDMA_PARM + offset + (param_no << 5), or);
425
413
}
426
414
427
-
static inline void edma_set_bits(int offset, int len, unsigned long *p)
428
-
{
429
-
for (; len > 0; len--)
430
-
set_bit(offset + (len - 1), p);
431
-
}
432
-
433
415
static void edma_assign_priority_to_queue(struct edma_cc *ecc, int queue_no,
434
416
int priority)
435
417
{
···
447
441
{
448
442
struct edma_cc *ecc = echan->ecc;
449
443
int channel = EDMA_CHAN_SLOT(echan->ch_num);
444
+
int idx = EDMA_REG_ARRAY_INDEX(channel);
445
+
int ch_bit = EDMA_CHANNEL_BIT(channel);
450
446
451
447
if (enable) {
452
-
edma_shadow0_write_array(ecc, SH_ICR, channel >> 5,
453
-
BIT(channel & 0x1f));
454
-
edma_shadow0_write_array(ecc, SH_IESR, channel >> 5,
455
-
BIT(channel & 0x1f));
448
+
edma_shadow0_write_array(ecc, SH_ICR, idx, ch_bit);
449
+
edma_shadow0_write_array(ecc, SH_IESR, idx, ch_bit);
456
450
} else {
457
-
edma_shadow0_write_array(ecc, SH_IECR, channel >> 5,
458
-
BIT(channel & 0x1f));
451
+
edma_shadow0_write_array(ecc, SH_IECR, idx, ch_bit);
459
452
}
460
453
}
461
454
···
592
587
{
593
588
struct edma_cc *ecc = echan->ecc;
594
589
int channel = EDMA_CHAN_SLOT(echan->ch_num);
595
-
int j = (channel >> 5);
596
-
unsigned int mask = BIT(channel & 0x1f);
590
+
int idx = EDMA_REG_ARRAY_INDEX(channel);
591
+
int ch_bit = EDMA_CHANNEL_BIT(channel);
597
592
598
593
if (!echan->hw_triggered) {
599
594
/* EDMA channels without event association */
600
-
dev_dbg(ecc->dev, "ESR%d %08x\n", j,
601
-
edma_shadow0_read_array(ecc, SH_ESR, j));
602
-
edma_shadow0_write_array(ecc, SH_ESR, j, mask);
595
+
dev_dbg(ecc->dev, "ESR%d %08x\n", idx,
596
+
edma_shadow0_read_array(ecc, SH_ESR, idx));
597
+
edma_shadow0_write_array(ecc, SH_ESR, idx, ch_bit);
603
598
} else {
604
599
/* EDMA channel with event association */
605
-
dev_dbg(ecc->dev, "ER%d %08x\n", j,
606
-
edma_shadow0_read_array(ecc, SH_ER, j));
600
+
dev_dbg(ecc->dev, "ER%d %08x\n", idx,
601
+
edma_shadow0_read_array(ecc, SH_ER, idx));
607
602
/* Clear any pending event or error */
608
-
edma_write_array(ecc, EDMA_ECR, j, mask);
609
-
edma_write_array(ecc, EDMA_EMCR, j, mask);
603
+
edma_write_array(ecc, EDMA_ECR, idx, ch_bit);
604
+
edma_write_array(ecc, EDMA_EMCR, idx, ch_bit);
610
605
/* Clear any SER */
611
-
edma_shadow0_write_array(ecc, SH_SECR, j, mask);
612
-
edma_shadow0_write_array(ecc, SH_EESR, j, mask);
613
-
dev_dbg(ecc->dev, "EER%d %08x\n", j,
614
-
edma_shadow0_read_array(ecc, SH_EER, j));
606
+
edma_shadow0_write_array(ecc, SH_SECR, idx, ch_bit);
607
+
edma_shadow0_write_array(ecc, SH_EESR, idx, ch_bit);
608
+
dev_dbg(ecc->dev, "EER%d %08x\n", idx,
609
+
edma_shadow0_read_array(ecc, SH_EER, idx));
615
610
}
616
611
}
617
612
···
619
614
{
620
615
struct edma_cc *ecc = echan->ecc;
621
616
int channel = EDMA_CHAN_SLOT(echan->ch_num);
622
-
int j = (channel >> 5);
623
-
unsigned int mask = BIT(channel & 0x1f);
617
+
int idx = EDMA_REG_ARRAY_INDEX(channel);
618
+
int ch_bit = EDMA_CHANNEL_BIT(channel);
624
619
625
-
edma_shadow0_write_array(ecc, SH_EECR, j, mask);
626
-
edma_shadow0_write_array(ecc, SH_ECR, j, mask);
627
-
edma_shadow0_write_array(ecc, SH_SECR, j, mask);
628
-
edma_write_array(ecc, EDMA_EMCR, j, mask);
620
+
edma_shadow0_write_array(ecc, SH_EECR, idx, ch_bit);
621
+
edma_shadow0_write_array(ecc, SH_ECR, idx, ch_bit);
622
+
edma_shadow0_write_array(ecc, SH_SECR, idx, ch_bit);
623
+
edma_write_array(ecc, EDMA_EMCR, idx, ch_bit);
629
624
630
625
/* clear possibly pending completion interrupt */
631
-
edma_shadow0_write_array(ecc, SH_ICR, j, mask);
626
+
edma_shadow0_write_array(ecc, SH_ICR, idx, ch_bit);
632
627
633
-
dev_dbg(ecc->dev, "EER%d %08x\n", j,
634
-
edma_shadow0_read_array(ecc, SH_EER, j));
628
+
dev_dbg(ecc->dev, "EER%d %08x\n", idx,
629
+
edma_shadow0_read_array(ecc, SH_EER, idx));
635
630
636
631
/* REVISIT: consider guarding against inappropriate event
637
632
* chaining by overwriting with dummy_paramset.
···
645
640
static void edma_pause(struct edma_chan *echan)
646
641
{
647
642
int channel = EDMA_CHAN_SLOT(echan->ch_num);
648
-
unsigned int mask = BIT(channel & 0x1f);
649
643
650
-
edma_shadow0_write_array(echan->ecc, SH_EECR, channel >> 5, mask);
644
+
edma_shadow0_write_array(echan->ecc, SH_EECR,
645
+
EDMA_REG_ARRAY_INDEX(channel),
646
+
EDMA_CHANNEL_BIT(channel));
651
647
}
652
648
653
649
/* Re-enable EDMA hardware events on the specified channel. */
654
650
static void edma_resume(struct edma_chan *echan)
655
651
{
656
652
int channel = EDMA_CHAN_SLOT(echan->ch_num);
657
-
unsigned int mask = BIT(channel & 0x1f);
658
653
659
-
edma_shadow0_write_array(echan->ecc, SH_EESR, channel >> 5, mask);
654
+
edma_shadow0_write_array(echan->ecc, SH_EESR,
655
+
EDMA_REG_ARRAY_INDEX(channel),
656
+
EDMA_CHANNEL_BIT(channel));
660
657
}
661
658
662
659
static void edma_trigger_channel(struct edma_chan *echan)
663
660
{
664
661
struct edma_cc *ecc = echan->ecc;
665
662
int channel = EDMA_CHAN_SLOT(echan->ch_num);
666
-
unsigned int mask = BIT(channel & 0x1f);
663
+
int idx = EDMA_REG_ARRAY_INDEX(channel);
664
+
int ch_bit = EDMA_CHANNEL_BIT(channel);
667
665
668
-
edma_shadow0_write_array(ecc, SH_ESR, (channel >> 5), mask);
666
+
edma_shadow0_write_array(ecc, SH_ESR, idx, ch_bit);
669
667
670
-
dev_dbg(ecc->dev, "ESR%d %08x\n", (channel >> 5),
671
-
edma_shadow0_read_array(ecc, SH_ESR, (channel >> 5)));
668
+
dev_dbg(ecc->dev, "ESR%d %08x\n", idx,
669
+
edma_shadow0_read_array(ecc, SH_ESR, idx));
672
670
}
673
671
674
672
static void edma_clean_channel(struct edma_chan *echan)
675
673
{
676
674
struct edma_cc *ecc = echan->ecc;
677
675
int channel = EDMA_CHAN_SLOT(echan->ch_num);
678
-
int j = (channel >> 5);
679
-
unsigned int mask = BIT(channel & 0x1f);
676
+
int idx = EDMA_REG_ARRAY_INDEX(channel);
677
+
int ch_bit = EDMA_CHANNEL_BIT(channel);
680
678
681
-
dev_dbg(ecc->dev, "EMR%d %08x\n", j, edma_read_array(ecc, EDMA_EMR, j));
682
-
edma_shadow0_write_array(ecc, SH_ECR, j, mask);
679
+
dev_dbg(ecc->dev, "EMR%d %08x\n", idx,
680
+
edma_read_array(ecc, EDMA_EMR, idx));
681
+
edma_shadow0_write_array(ecc, SH_ECR, idx, ch_bit);
683
682
/* Clear the corresponding EMR bits */
684
-
edma_write_array(ecc, EDMA_EMCR, j, mask);
683
+
edma_write_array(ecc, EDMA_EMCR, idx, ch_bit);
685
684
/* Clear any SER */
686
-
edma_shadow0_write_array(ecc, SH_SECR, j, mask);
685
+
edma_shadow0_write_array(ecc, SH_SECR, idx, ch_bit);
687
686
edma_write(ecc, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0));
688
687
}
689
688
···
717
708
int channel = EDMA_CHAN_SLOT(echan->ch_num);
718
709
719
710
/* ensure access through shadow region 0 */
720
-
edma_or_array2(ecc, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f));
711
+
edma_or_array2(ecc, EDMA_DRAE, 0, EDMA_REG_ARRAY_INDEX(channel),
712
+
EDMA_CHANNEL_BIT(channel));
721
713
722
714
/* ensure no events are pending */
723
715
edma_stop(echan);
···
1021
1011
src_cidx = cidx;
1022
1012
dst_bidx = acnt;
1023
1013
dst_cidx = cidx;
1014
+
epset->addr = src_addr;
1024
1015
} else {
1025
1016
dev_err(dev, "%s: direction not implemented yet\n", __func__);
1026
1017
return -EINVAL;
···
1222
1211
1223
1212
edesc->pset[0].param.opt |= ITCCHEN;
1224
1213
if (nslots == 1) {
1225
-
/* Enable transfer complete interrupt */
1226
-
edesc->pset[0].param.opt |= TCINTEN;
1214
+
/* Enable transfer complete interrupt if requested */
1215
+
if (tx_flags & DMA_PREP_INTERRUPT)
1216
+
edesc->pset[0].param.opt |= TCINTEN;
1227
1217
} else {
1228
1218
/* Enable transfer complete chaining for the first slot */
1229
1219
edesc->pset[0].param.opt |= TCCHEN;
···
1251
1239
}
1252
1240
1253
1241
edesc->pset[1].param.opt |= ITCCHEN;
1254
-
edesc->pset[1].param.opt |= TCINTEN;
1242
+
/* Enable transfer complete interrupt if requested */
1243
+
if (tx_flags & DMA_PREP_INTERRUPT)
1244
+
edesc->pset[1].param.opt |= TCINTEN;
1255
1245
}
1246
+
1247
+
if (!(tx_flags & DMA_PREP_INTERRUPT))
1248
+
edesc->polled = true;
1256
1249
1257
1250
return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
1258
1251
}
···
1738
1721
int loop_count = EDMA_MAX_TR_WAIT_LOOPS;
1739
1722
struct edma_chan *echan = edesc->echan;
1740
1723
struct edma_pset *pset = edesc->pset;
1741
-
dma_addr_t done, pos;
1724
+
dma_addr_t done, pos, pos_old;
1725
+
int channel = EDMA_CHAN_SLOT(echan->ch_num);
1726
+
int idx = EDMA_REG_ARRAY_INDEX(channel);
1727
+
int ch_bit = EDMA_CHANNEL_BIT(channel);
1728
+
int event_reg;
1742
1729
int i;
1743
1730
1744
1731
/*
···
1755
1734
* "pos" may represent a transfer request that is still being
1756
1735
* processed by the EDMACC or EDMATC. We will busy wait until
1757
1736
* any one of the situations occurs:
1758
-
* 1. the DMA hardware is idle
1759
-
* 2. a new transfer request is setup
1737
+
* 1. while and event is pending for the channel
1738
+
* 2. a position updated
1760
1739
* 3. we hit the loop limit
1761
1740
*/
1762
-
while (edma_read(echan->ecc, EDMA_CCSTAT) & EDMA_CCSTAT_ACTV) {
1763
-
/* check if a new transfer request is setup */
1764
-
if (edma_get_position(echan->ecc,
1765
-
echan->slot[0], dst) != pos) {
1741
+
if (is_slave_direction(edesc->direction))
1742
+
event_reg = SH_ER;
1743
+
else
1744
+
event_reg = SH_ESR;
1745
+
1746
+
pos_old = pos;
1747
+
while (edma_shadow0_read_array(echan->ecc, event_reg, idx) & ch_bit) {
1748
+
pos = edma_get_position(echan->ecc, echan->slot[0], dst);
1749
+
if (pos != pos_old)
1766
1750
break;
1767
-
}
1768
1751
1769
1752
if (!--loop_count) {
1770
1753
dev_dbg_ratelimited(echan->vchan.chan.device->dev,
···
1793
1768
return edesc->residue_stat;
1794
1769
}
1795
1770
1771
+
/*
1772
+
* If the position is 0, then EDMA loaded the closing dummy slot, the
1773
+
* transfer is completed
1774
+
*/
1775
+
if (!pos)
1776
+
return 0;
1796
1777
/*
1797
1778
* For SG operation we catch up with the last processed
1798
1779
* status.
···
1827
1796
struct dma_tx_state *txstate)
1828
1797
{
1829
1798
struct edma_chan *echan = to_edma_chan(chan);
1830
-
struct virt_dma_desc *vdesc;
1799
+
struct dma_tx_state txstate_tmp;
1831
1800
enum dma_status ret;
1832
1801
unsigned long flags;
1833
1802
1834
1803
ret = dma_cookie_status(chan, cookie, txstate);
1835
-
if (ret == DMA_COMPLETE || !txstate)
1804
+
1805
+
if (ret == DMA_COMPLETE)
1836
1806
return ret;
1837
1807
1808
+
/* Provide a dummy dma_tx_state for completion checking */
1809
+
if (!txstate)
1810
+
txstate = &txstate_tmp;
1811
+
1838
1812
spin_lock_irqsave(&echan->vchan.lock, flags);
1839
-
if (echan->edesc && echan->edesc->vdesc.tx.cookie == cookie)
1813
+
if (echan->edesc && echan->edesc->vdesc.tx.cookie == cookie) {
1840
1814
txstate->residue = edma_residue(echan->edesc);
1841
-
else if ((vdesc = vchan_find_desc(&echan->vchan, cookie)))
1842
-
txstate->residue = to_edma_desc(&vdesc->tx)->residue;
1815
+
} else {
1816
+
struct virt_dma_desc *vdesc = vchan_find_desc(&echan->vchan,
1817
+
cookie);
1818
+
1819
+
if (vdesc)
1820
+
txstate->residue = to_edma_desc(&vdesc->tx)->residue;
1821
+
else
1822
+
txstate->residue = 0;
1823
+
}
1824
+
1825
+
/*
1826
+
* Mark the cookie completed if the residue is 0 for non cyclic
1827
+
* transfers
1828
+
*/
1829
+
if (ret != DMA_COMPLETE && !txstate->residue &&
1830
+
echan->edesc && echan->edesc->polled &&
1831
+
echan->edesc->vdesc.tx.cookie == cookie) {
1832
+
edma_stop(echan);
1833
+
vchan_cookie_complete(&echan->edesc->vdesc);
1834
+
echan->edesc = NULL;
1835
+
edma_execute(echan);
1836
+
ret = DMA_COMPLETE;
1837
+
}
1838
+
1843
1839
spin_unlock_irqrestore(&echan->vchan.lock, flags);
1844
1840
1845
1841
return ret;
···
2243
2185
}
2244
2186
#endif
2245
2187
2188
+
static bool edma_filter_fn(struct dma_chan *chan, void *param);
2189
+
2246
2190
static int edma_probe(struct platform_device *pdev)
2247
2191
{
2248
2192
struct edma_soc_info *info = pdev->dev.platform_data;
2249
2193
s8 (*queue_priority_mapping)[2];
2250
-
int i, off, ln;
2194
+
int i, off;
2251
2195
const s16 (*rsv_slots)[2];
2252
2196
const s16 (*xbar_chans)[2];
2253
2197
int irq;
···
2333
2273
2334
2274
ecc->default_queue = info->default_queue;
2335
2275
2336
-
for (i = 0; i < ecc->num_slots; i++)
2337
-
edma_write_slot(ecc, i, &dummy_paramset);
2338
-
2339
2276
if (info->rsv) {
2340
2277
/* Set the reserved slots in inuse list */
2341
2278
rsv_slots = info->rsv->rsv_slots;
2342
2279
if (rsv_slots) {
2343
-
for (i = 0; rsv_slots[i][0] != -1; i++) {
2344
-
off = rsv_slots[i][0];
2345
-
ln = rsv_slots[i][1];
2346
-
edma_set_bits(off, ln, ecc->slot_inuse);
2347
-
}
2280
+
for (i = 0; rsv_slots[i][0] != -1; i++)
2281
+
bitmap_set(ecc->slot_inuse, rsv_slots[i][0],
2282
+
rsv_slots[i][1]);
2348
2283
}
2284
+
}
2285
+
2286
+
for (i = 0; i < ecc->num_slots; i++) {
2287
+
/* Reset only unused - not reserved - paRAM slots */
2288
+
if (!test_bit(i, ecc->slot_inuse))
2289
+
edma_write_slot(ecc, i, &dummy_paramset);
2349
2290
}
2350
2291
2351
2292
/* Clear the xbar mapped channels in unused list */
···
2427
2366
edma_assign_priority_to_queue(ecc, queue_priority_mapping[i][0],
2428
2367
queue_priority_mapping[i][1]);
2429
2368
2430
-
for (i = 0; i < ecc->num_region; i++) {
2431
-
edma_write_array2(ecc, EDMA_DRAE, i, 0, 0x0);
2432
-
edma_write_array2(ecc, EDMA_DRAE, i, 1, 0x0);
2433
-
edma_write_array(ecc, EDMA_QRAE, i, 0x0);
2434
-
}
2369
+
edma_write_array2(ecc, EDMA_DRAE, 0, 0, 0x0);
2370
+
edma_write_array2(ecc, EDMA_DRAE, 0, 1, 0x0);
2371
+
edma_write_array(ecc, EDMA_QRAE, 0, 0x0);
2372
+
2435
2373
ecc->info = info;
2436
2374
2437
2375
/* Init the dma device and channels */
···
2542
2482
for (i = 0; i < ecc->num_channels; i++) {
2543
2483
if (echan[i].alloced) {
2544
2484
/* ensure access through shadow region 0 */
2545
-
edma_or_array2(ecc, EDMA_DRAE, 0, i >> 5,
2546
-
BIT(i & 0x1f));
2485
+
edma_or_array2(ecc, EDMA_DRAE, 0,
2486
+
EDMA_REG_ARRAY_INDEX(i),
2487
+
EDMA_CHANNEL_BIT(i));
2547
2488
2548
2489
edma_setup_interrupt(&echan[i], true);
2549
2490
···
2585
2524
},
2586
2525
};
2587
2526
2588
-
bool edma_filter_fn(struct dma_chan *chan, void *param)
2527
+
static bool edma_filter_fn(struct dma_chan *chan, void *param)
2589
2528
{
2590
2529
bool match = false;
2591
2530
···
2600
2539
}
2601
2540
return match;
2602
2541
}
2603
-
EXPORT_SYMBOL(edma_filter_fn);
2604
2542
2605
2543
static int edma_init(void)
2606
2544
{
+39
-23
drivers/dma/ti/omap-dma.c
+39
-23
drivers/dma/ti/omap-dma.c
···
91
91
bool using_ll;
92
92
enum dma_transfer_direction dir;
93
93
dma_addr_t dev_addr;
94
+
bool polled;
94
95
95
96
int32_t fi; /* for OMAP_DMA_SYNC_PACKET / double indexing */
96
97
int16_t ei; /* for double indexing */
···
203
202
[CSDP_DATA_TYPE_32] = 4,
204
203
};
205
204
205
+
static bool omap_dma_filter_fn(struct dma_chan *chan, void *param);
206
206
static struct of_dma_filter_info omap_dma_info = {
207
207
.filter_fn = omap_dma_filter_fn,
208
208
};
···
814
812
dma_cookie_t cookie, struct dma_tx_state *txstate)
815
813
{
816
814
struct omap_chan *c = to_omap_dma_chan(chan);
817
-
struct virt_dma_desc *vd;
818
815
enum dma_status ret;
819
816
unsigned long flags;
817
+
struct omap_desc *d = NULL;
820
818
821
819
ret = dma_cookie_status(chan, cookie, txstate);
822
-
823
-
if (!c->paused && c->running) {
824
-
uint32_t ccr = omap_dma_chan_read(c, CCR);
825
-
/*
826
-
* The channel is no longer active, set the return value
827
-
* accordingly
828
-
*/
829
-
if (!(ccr & CCR_ENABLE))
830
-
ret = DMA_COMPLETE;
831
-
}
832
-
833
-
if (ret == DMA_COMPLETE || !txstate)
820
+
if (ret == DMA_COMPLETE)
834
821
return ret;
835
822
836
823
spin_lock_irqsave(&c->vc.lock, flags);
837
-
vd = vchan_find_desc(&c->vc, cookie);
838
-
if (vd) {
839
-
txstate->residue = omap_dma_desc_size(to_omap_dma_desc(&vd->tx));
840
-
} else if (c->desc && c->desc->vd.tx.cookie == cookie) {
841
-
struct omap_desc *d = c->desc;
824
+
if (c->desc && c->desc->vd.tx.cookie == cookie)
825
+
d = c->desc;
826
+
827
+
if (!txstate)
828
+
goto out;
829
+
830
+
if (d) {
842
831
dma_addr_t pos;
843
832
844
833
if (d->dir == DMA_MEM_TO_DEV)
···
841
848
842
849
txstate->residue = omap_dma_desc_size_pos(d, pos);
843
850
} else {
844
-
txstate->residue = 0;
851
+
struct virt_dma_desc *vd = vchan_find_desc(&c->vc, cookie);
852
+
853
+
if (vd)
854
+
txstate->residue = omap_dma_desc_size(
855
+
to_omap_dma_desc(&vd->tx));
856
+
else
857
+
txstate->residue = 0;
845
858
}
846
-
if (ret == DMA_IN_PROGRESS && c->paused)
859
+
860
+
out:
861
+
if (ret == DMA_IN_PROGRESS && c->paused) {
847
862
ret = DMA_PAUSED;
863
+
} else if (d && d->polled && c->running) {
864
+
uint32_t ccr = omap_dma_chan_read(c, CCR);
865
+
/*
866
+
* The channel is no longer active, set the return value
867
+
* accordingly and mark it as completed
868
+
*/
869
+
if (!(ccr & CCR_ENABLE)) {
870
+
ret = DMA_COMPLETE;
871
+
omap_dma_start_desc(c);
872
+
vchan_cookie_complete(&d->vd);
873
+
}
874
+
}
875
+
848
876
spin_unlock_irqrestore(&c->vc.lock, flags);
849
877
850
878
return ret;
···
1192
1178
d->ccr = c->ccr;
1193
1179
d->ccr |= CCR_DST_AMODE_POSTINC | CCR_SRC_AMODE_POSTINC;
1194
1180
1195
-
d->cicr = CICR_DROP_IE | CICR_FRAME_IE;
1181
+
if (tx_flags & DMA_PREP_INTERRUPT)
1182
+
d->cicr |= CICR_FRAME_IE;
1183
+
else
1184
+
d->polled = true;
1196
1185
1197
1186
d->csdp = data_type;
1198
1187
···
1656
1639
},
1657
1640
};
1658
1641
1659
-
bool omap_dma_filter_fn(struct dma_chan *chan, void *param)
1642
+
static bool omap_dma_filter_fn(struct dma_chan *chan, void *param)
1660
1643
{
1661
1644
if (chan->device->dev->driver == &omap_dma_driver.driver) {
1662
1645
struct omap_dmadev *od = to_omap_dma_dev(chan->device);
···
1670
1653
}
1671
1654
return false;
1672
1655
}
1673
-
EXPORT_SYMBOL_GPL(omap_dma_filter_fn);
1674
1656
1675
1657
static int omap_dma_init(void)
1676
1658
{
+1
-4
drivers/dma/uniphier-mdmac.c
+1
-4
drivers/dma/uniphier-mdmac.c
···
354
354
int irq, ret;
355
355
356
356
irq = platform_get_irq(pdev, chan_id);
357
-
if (irq < 0) {
358
-
dev_err(&pdev->dev, "failed to get IRQ number for ch%d\n",
359
-
chan_id);
357
+
if (irq < 0)
360
358
return irq;
361
-
}
362
359
363
360
irq_name = devm_kasprintf(dev, GFP_KERNEL, "uniphier-mio-dmac-ch%d",
364
361
chan_id);
+2
-6
drivers/dma/xgene-dma.c
+2
-6
drivers/dma/xgene-dma.c
···
1678
1678
1679
1679
/* Get DMA error interrupt */
1680
1680
irq = platform_get_irq(pdev, 0);
1681
-
if (irq <= 0) {
1682
-
dev_err(&pdev->dev, "Failed to get Error IRQ\n");
1681
+
if (irq <= 0)
1683
1682
return -ENXIO;
1684
-
}
1685
1683
1686
1684
pdma->err_irq = irq;
1687
1685
1688
1686
/* Get DMA Rx ring descriptor interrupts for all DMA channels */
1689
1687
for (i = 1; i <= XGENE_DMA_MAX_CHANNEL; i++) {
1690
1688
irq = platform_get_irq(pdev, i);
1691
-
if (irq <= 0) {
1692
-
dev_err(&pdev->dev, "Failed to get Rx IRQ\n");
1689
+
if (irq <= 0)
1693
1690
return -ENXIO;
1694
-
}
1695
1691
1696
1692
pdma->chan[i - 1].rx_irq = irq;
1697
1693
}
-29
include/linux/edma.h
-29
include/linux/edma.h
···
1
-
/*
2
-
* TI EDMA DMA engine driver
3
-
*
4
-
* Copyright 2012 Texas Instruments
5
-
*
6
-
* This program is free software; you can redistribute it and/or
7
-
* modify it under the terms of the GNU General Public License as
8
-
* published by the Free Software Foundation version 2.
9
-
*
10
-
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
11
-
* kind, whether express or implied; without even the implied warranty
12
-
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13
-
* GNU General Public License for more details.
14
-
*/
15
-
#ifndef __LINUX_EDMA_H
16
-
#define __LINUX_EDMA_H
17
-
18
-
struct dma_chan;
19
-
20
-
#if defined(CONFIG_TI_EDMA) || defined(CONFIG_TI_EDMA_MODULE)
21
-
bool edma_filter_fn(struct dma_chan *, void *);
22
-
#else
23
-
static inline bool edma_filter_fn(struct dma_chan *chan, void *param)
24
-
{
25
-
return false;
26
-
}
27
-
#endif
28
-
29
-
#endif
-2
include/linux/omap-dma.h
-2
include/linux/omap-dma.h
-18
include/linux/omap-dmaengine.h
-18
include/linux/omap-dmaengine.h
···
1
-
/* SPDX-License-Identifier: GPL-2.0-only */
2
-
/*
3
-
* OMAP DMA Engine support
4
-
*/
5
-
#ifndef __LINUX_OMAP_DMAENGINE_H
6
-
#define __LINUX_OMAP_DMAENGINE_H
7
-
8
-
struct dma_chan;
9
-
10
-
#if defined(CONFIG_DMA_OMAP) || (defined(CONFIG_DMA_OMAP_MODULE) && defined(MODULE))
11
-
bool omap_dma_filter_fn(struct dma_chan *, void *);
12
-
#else
13
-
static inline bool omap_dma_filter_fn(struct dma_chan *c, void *d)
14
-
{
15
-
return false;
16
-
}
17
-
#endif
18
-
#endif /* __LINUX_OMAP_DMAENGINE_H */