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usb: dwc3: core: Disable USB2 retry for DWC_usb31 1.80a and prior

STAR 9001346572 addresses a USB 2.0 endpoint blocking issue in host mode
for controller versions DWC_usb31 1.70a and 1.80a. This issue affects
devices on both high-speed and full-speed bus instances. When all
endpoint caches are filled and a single active endpoint receives
continuous NAK responses, data transfers to other endpoints may get
blocked.

To resolve this, for controller versions DWC_usb31 1.70a and 1.80a, the
GUCTL3 bit[16] (USB2.0 Internal Retry Disable) is set to 1. This bit
disables the USB2.0 internal retry feature and ensures proper eviction
handling in the host controller endpoind cache. The GUCTL3[16] register
function is available only from DWC_usb31 version 1.70a.

Signed-off-by: Faisal Hassan <quic_faisalh@quicinc.com>
Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
Link: https://lore.kernel.org/r/20241129173422.20063-1-quic_faisalh@quicinc.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

authored by

Faisal Hassan and committed by
Greg Kroah-Hartman 04d5b4c2 a787bfff

+21
+20
drivers/usb/dwc3/core.c
··· 1479 1479 } 1480 1480 } 1481 1481 1482 + /* 1483 + * STAR 9001346572: This issue affects DWC_usb31 versions 1.80a and 1484 + * prior. When an active endpoint not currently cached in the host 1485 + * controller is chosen to be cached to the same index as an endpoint 1486 + * receiving NAKs, the endpoint receiving NAKs enters continuous 1487 + * retry mode. This prevents it from being evicted from the host 1488 + * controller cache, blocking the new endpoint from being cached and 1489 + * serviced. 1490 + * 1491 + * To resolve this, for controller versions 1.70a and 1.80a, set the 1492 + * GUCTL3 bit[16] (USB2.0 Internal Retry Disable) to 1. This bit 1493 + * disables the USB2.0 internal retry feature. The GUCTL3[16] register 1494 + * function is available only from version 1.70a. 1495 + */ 1496 + if (DWC3_VER_IS_WITHIN(DWC31, 170A, 180A)) { 1497 + reg = dwc3_readl(dwc->regs, DWC3_GUCTL3); 1498 + reg |= DWC3_GUCTL3_USB20_RETRY_DISABLE; 1499 + dwc3_writel(dwc->regs, DWC3_GUCTL3, reg); 1500 + } 1501 + 1482 1502 return 0; 1483 1503 1484 1504 err_power_off_phy:
+1
drivers/usb/dwc3/core.h
··· 425 425 426 426 /* Global User Control Register 3 */ 427 427 #define DWC3_GUCTL3_SPLITDISABLE BIT(14) 428 + #define DWC3_GUCTL3_USB20_RETRY_DISABLE BIT(16) 428 429 429 430 /* Device Configuration Register */ 430 431 #define DWC3_DCFG_NUMLANES(n) (((n) & 0x3) << 30) /* DWC_usb32 only */