Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
iio: trigger: stm32-timer-trigger: make use of regmap_clear_bits(), regmap_set_bits()
Instead of using regmap_update_bits() and passing the mask twice, use
regmap_set_bits().
Instead of using regmap_update_bits() and passing val = 0, use
regmap_clear_bits().
Suggested-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com>
Signed-off-by: Trevor Gamblin <tgamblin@baylibre.com>
Acked-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com>
Link: https://patch.msgid.link/20240617-review-v3-41-88d1338c4cca@baylibre.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
authored by
Trevor Gamblin
and committed by
Jonathan Cameron
04eb9499
ac403e8c
+16
-18
+16
-18
drivers/iio/trigger/stm32-timer-trigger.c
+16
-18
drivers/iio/trigger/stm32-timer-trigger.c
···
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regmap_write(priv->regmap, TIM_PSC, prescaler);
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regmap_write(priv->regmap, TIM_ARR, prd - 1);
161
-
regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE);
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+
regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE);
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/* Force master mode to update mode */
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if (stm32_timer_is_trgo2_name(trig->name))
···
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0x2 << TIM_CR2_MMS_SHIFT);
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/* Make sure that registers are updated */
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-
regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
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+
regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG);
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/* Enable controller */
175
-
regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN);
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+
regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
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mutex_unlock(&priv->lock);
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return 0;
···
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mutex_lock(&priv->lock);
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/* Stop timer */
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-
regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0);
193
-
regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
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+
regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE);
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+
regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
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regmap_write(priv->regmap, TIM_PSC, 0);
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regmap_write(priv->regmap, TIM_ARR, 0);
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/* Force disable master mode */
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if (stm32_timer_is_trgo2_name(trig->name))
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-
regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, 0);
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+
regmap_clear_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2);
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else
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-
regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS, 0);
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+
regmap_clear_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS);
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/* Make sure that registers are updated */
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-
regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
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+
regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG);
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if (priv->enabled) {
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priv->enabled = false;
···
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498
priv->enabled = true;
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clk_enable(priv->clk);
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}
501
-
regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN,
502
-
TIM_CR1_CEN);
501
+
regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
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502
} else {
504
-
regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN,
505
-
0);
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+
regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
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if (priv->enabled) {
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priv->enabled = false;
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clk_disable(priv->clk);
···
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555
{
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struct stm32_timer_trigger *priv = iio_priv(indio_dev);
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-
regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, TIM_SMCR_SMS);
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+
regmap_set_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS);
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return 0;
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}
···
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return ret;
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/* TIMx_ARR register shouldn't be buffered (ARPE=0) */
684
-
regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0);
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+
regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE);
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regmap_write(priv->regmap, TIM_ARR, preset);
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return len;
···
755
757
* Master mode selection 2 bits can only be written and read back when
756
758
* timer supports it.
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*/
758
-
regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, TIM_CR2_MMS2);
760
+
regmap_set_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2);
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761
regmap_read(priv->regmap, TIM_CR2, &val);
760
-
regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, 0);
762
+
regmap_clear_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2);
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priv->has_trgo2 = !!val;
762
764
}
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765
···
818
820
/* Check if nobody else use the timer, then disable it */
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regmap_read(priv->regmap, TIM_CCER, &val);
820
822
if (!(val & TIM_CCER_CCXE))
821
-
regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
823
+
regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
822
824
823
825
if (priv->enabled)
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clk_disable(priv->clk);
···
839
841
regmap_read(priv->regmap, TIM_SMCR, &priv->bak.smcr);
840
842
841
843
/* Disable the timer */
842
-
regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
844
+
regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
843
845
clk_disable(priv->clk);
844
846
}
845
847