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clk: qcom: gcc-msm8994: Modernize the driver

Switch to the newer-style parent_data and remove the hardcoded
xo clock.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210923162645.23257-2-konrad.dybcio@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

authored by

Konrad Dybcio and committed by
Stephen Boyd 0519d1d0 85a88d2b

+305 -555
+305 -555
drivers/clk/qcom/gcc-msm8994.c
··· 28 28 P_GPLL4, 29 29 }; 30 30 31 - static const struct parent_map gcc_xo_gpll0_map[] = { 32 - { P_XO, 0 }, 33 - { P_GPLL0, 1 }, 34 - }; 35 - 36 - static const char * const gcc_xo_gpll0[] = { 37 - "xo", 38 - "gpll0", 39 - }; 40 - 41 - static const struct parent_map gcc_xo_gpll0_gpll4_map[] = { 42 - { P_XO, 0 }, 43 - { P_GPLL0, 1 }, 44 - { P_GPLL4, 5 }, 45 - }; 46 - 47 - static const char * const gcc_xo_gpll0_gpll4[] = { 48 - "xo", 49 - "gpll0", 50 - "gpll4", 51 - }; 52 - 53 - static struct clk_fixed_factor xo = { 54 - .mult = 1, 55 - .div = 1, 56 - .hw.init = &(struct clk_init_data) 57 - { 58 - .name = "xo", 59 - .parent_names = (const char *[]) { "xo_board" }, 60 - .num_parents = 1, 61 - .ops = &clk_fixed_factor_ops, 62 - }, 63 - }; 64 - 65 31 static struct clk_alpha_pll gpll0_early = { 66 - .offset = 0x00000, 32 + .offset = 0, 67 33 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 68 34 .clkr = { 69 35 .enable_reg = 0x1480, 70 36 .enable_mask = BIT(0), 71 - .hw.init = &(struct clk_init_data) 72 - { 37 + .hw.init = &(struct clk_init_data){ 73 38 .name = "gpll0_early", 74 - .parent_names = (const char *[]) { "xo" }, 39 + .parent_data = &(const struct clk_parent_data){ 40 + .fw_name = "xo", 41 + }, 75 42 .num_parents = 1, 76 43 .ops = &clk_alpha_pll_ops, 77 44 }, ··· 46 79 }; 47 80 48 81 static struct clk_alpha_pll_postdiv gpll0 = { 49 - .offset = 0x00000, 82 + .offset = 0, 50 83 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 51 - .clkr.hw.init = &(struct clk_init_data) 52 - { 84 + .clkr.hw.init = &(struct clk_init_data){ 53 85 .name = "gpll0", 54 86 .parent_names = (const char *[]) { "gpll0_early" }, 55 87 .num_parents = 1, ··· 62 96 .clkr = { 63 97 .enable_reg = 0x1480, 64 98 .enable_mask = BIT(4), 65 - .hw.init = &(struct clk_init_data) 66 - { 99 + .hw.init = &(struct clk_init_data){ 67 100 .name = "gpll4_early", 68 - .parent_names = (const char *[]) { "xo" }, 101 + .parent_data = &(const struct clk_parent_data){ 102 + .fw_name = "xo", 103 + }, 69 104 .num_parents = 1, 70 105 .ops = &clk_alpha_pll_ops, 71 106 }, ··· 76 109 static struct clk_alpha_pll_postdiv gpll4 = { 77 110 .offset = 0x1dc0, 78 111 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 79 - .clkr.hw.init = &(struct clk_init_data) 80 - { 112 + .clkr.hw.init = &(struct clk_init_data){ 81 113 .name = "gpll4", 82 114 .parent_names = (const char *[]) { "gpll4_early" }, 83 115 .num_parents = 1, 84 116 .ops = &clk_alpha_pll_postdiv_ops, 85 117 }, 118 + }; 119 + 120 + static const struct parent_map gcc_xo_gpll0_map[] = { 121 + { P_XO, 0 }, 122 + { P_GPLL0, 1 }, 123 + }; 124 + 125 + static const struct clk_parent_data gcc_xo_gpll0[] = { 126 + { .fw_name = "xo" }, 127 + { .hw = &gpll0.clkr.hw }, 128 + }; 129 + 130 + static const struct parent_map gcc_xo_gpll0_gpll4_map[] = { 131 + { P_XO, 0 }, 132 + { P_GPLL0, 1 }, 133 + { P_GPLL4, 5 }, 134 + }; 135 + 136 + static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = { 137 + { .fw_name = "xo" }, 138 + { .hw = &gpll0.clkr.hw }, 139 + { .hw = &gpll4.clkr.hw }, 86 140 }; 87 141 88 142 static struct freq_tbl ftbl_ufs_axi_clk_src[] = { ··· 122 134 .hid_width = 5, 123 135 .parent_map = gcc_xo_gpll0_map, 124 136 .freq_tbl = ftbl_ufs_axi_clk_src, 125 - .clkr.hw.init = &(struct clk_init_data) 126 - { 137 + .clkr.hw.init = &(struct clk_init_data){ 127 138 .name = "ufs_axi_clk_src", 128 - .parent_names = gcc_xo_gpll0, 139 + .parent_data = gcc_xo_gpll0, 129 140 .num_parents = 2, 130 141 .ops = &clk_rcg2_ops, 131 142 }, ··· 142 155 .hid_width = 5, 143 156 .parent_map = gcc_xo_gpll0_map, 144 157 .freq_tbl = ftbl_usb30_master_clk_src, 145 - .clkr.hw.init = &(struct clk_init_data) 146 - { 158 + .clkr.hw.init = &(struct clk_init_data){ 147 159 .name = "usb30_master_clk_src", 148 - .parent_names = gcc_xo_gpll0, 160 + .parent_data = gcc_xo_gpll0, 149 161 .num_parents = 2, 150 162 .ops = &clk_rcg2_ops, 151 163 }, ··· 161 175 .hid_width = 5, 162 176 .parent_map = gcc_xo_gpll0_map, 163 177 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 164 - .clkr.hw.init = &(struct clk_init_data) 165 - { 178 + .clkr.hw.init = &(struct clk_init_data){ 166 179 .name = "blsp1_qup1_i2c_apps_clk_src", 167 - .parent_names = gcc_xo_gpll0, 180 + .parent_data = gcc_xo_gpll0, 168 181 .num_parents = 2, 169 182 .ops = &clk_rcg2_ops, 170 183 }, ··· 188 203 .hid_width = 5, 189 204 .parent_map = gcc_xo_gpll0_map, 190 205 .freq_tbl = ftbl_blspqup_spi_apps_clk_src, 191 - .clkr.hw.init = &(struct clk_init_data) 192 - { 206 + .clkr.hw.init = &(struct clk_init_data){ 193 207 .name = "blsp1_qup1_spi_apps_clk_src", 194 - .parent_names = gcc_xo_gpll0, 208 + .parent_data = gcc_xo_gpll0, 195 209 .num_parents = 2, 196 210 .ops = &clk_rcg2_ops, 197 211 }, ··· 201 217 .hid_width = 5, 202 218 .parent_map = gcc_xo_gpll0_map, 203 219 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 204 - .clkr.hw.init = &(struct clk_init_data) 205 - { 220 + .clkr.hw.init = &(struct clk_init_data){ 206 221 .name = "blsp1_qup2_i2c_apps_clk_src", 207 - .parent_names = gcc_xo_gpll0, 222 + .parent_data = gcc_xo_gpll0, 208 223 .num_parents = 2, 209 224 .ops = &clk_rcg2_ops, 210 225 }, ··· 215 232 .hid_width = 5, 216 233 .parent_map = gcc_xo_gpll0_map, 217 234 .freq_tbl = ftbl_blspqup_spi_apps_clk_src, 218 - .clkr.hw.init = &(struct clk_init_data) 219 - { 235 + .clkr.hw.init = &(struct clk_init_data){ 220 236 .name = "blsp1_qup2_spi_apps_clk_src", 221 - .parent_names = gcc_xo_gpll0, 237 + .parent_data = gcc_xo_gpll0, 222 238 .num_parents = 2, 223 239 .ops = &clk_rcg2_ops, 224 240 }, ··· 228 246 .hid_width = 5, 229 247 .parent_map = gcc_xo_gpll0_map, 230 248 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 231 - .clkr.hw.init = &(struct clk_init_data) 232 - { 249 + .clkr.hw.init = &(struct clk_init_data){ 233 250 .name = "blsp1_qup3_i2c_apps_clk_src", 234 - .parent_names = gcc_xo_gpll0, 251 + .parent_data = gcc_xo_gpll0, 235 252 .num_parents = 2, 236 253 .ops = &clk_rcg2_ops, 237 254 }, ··· 242 261 .hid_width = 5, 243 262 .parent_map = gcc_xo_gpll0_map, 244 263 .freq_tbl = ftbl_blspqup_spi_apps_clk_src, 245 - .clkr.hw.init = &(struct clk_init_data) 246 - { 264 + .clkr.hw.init = &(struct clk_init_data){ 247 265 .name = "blsp1_qup3_spi_apps_clk_src", 248 - .parent_names = gcc_xo_gpll0, 266 + .parent_data = gcc_xo_gpll0, 249 267 .num_parents = 2, 250 268 .ops = &clk_rcg2_ops, 251 269 }, ··· 255 275 .hid_width = 5, 256 276 .parent_map = gcc_xo_gpll0_map, 257 277 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 258 - .clkr.hw.init = &(struct clk_init_data) 259 - { 278 + .clkr.hw.init = &(struct clk_init_data){ 260 279 .name = "blsp1_qup4_i2c_apps_clk_src", 261 - .parent_names = gcc_xo_gpll0, 280 + .parent_data = gcc_xo_gpll0, 262 281 .num_parents = 2, 263 282 .ops = &clk_rcg2_ops, 264 283 }, ··· 269 290 .hid_width = 5, 270 291 .parent_map = gcc_xo_gpll0_map, 271 292 .freq_tbl = ftbl_blspqup_spi_apps_clk_src, 272 - .clkr.hw.init = &(struct clk_init_data) 273 - { 293 + .clkr.hw.init = &(struct clk_init_data){ 274 294 .name = "blsp1_qup4_spi_apps_clk_src", 275 - .parent_names = gcc_xo_gpll0, 295 + .parent_data = gcc_xo_gpll0, 276 296 .num_parents = 2, 277 297 .ops = &clk_rcg2_ops, 278 298 }, ··· 282 304 .hid_width = 5, 283 305 .parent_map = gcc_xo_gpll0_map, 284 306 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 285 - .clkr.hw.init = &(struct clk_init_data) 286 - { 307 + .clkr.hw.init = &(struct clk_init_data){ 287 308 .name = "blsp1_qup5_i2c_apps_clk_src", 288 - .parent_names = gcc_xo_gpll0, 309 + .parent_data = gcc_xo_gpll0, 289 310 .num_parents = 2, 290 311 .ops = &clk_rcg2_ops, 291 312 }, ··· 296 319 .hid_width = 5, 297 320 .parent_map = gcc_xo_gpll0_map, 298 321 .freq_tbl = ftbl_blspqup_spi_apps_clk_src, 299 - .clkr.hw.init = &(struct clk_init_data) 300 - { 322 + .clkr.hw.init = &(struct clk_init_data){ 301 323 .name = "blsp1_qup5_spi_apps_clk_src", 302 - .parent_names = gcc_xo_gpll0, 324 + .parent_data = gcc_xo_gpll0, 303 325 .num_parents = 2, 304 326 .ops = &clk_rcg2_ops, 305 327 }, ··· 309 333 .hid_width = 5, 310 334 .parent_map = gcc_xo_gpll0_map, 311 335 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 312 - .clkr.hw.init = &(struct clk_init_data) 313 - { 336 + .clkr.hw.init = &(struct clk_init_data){ 314 337 .name = "blsp1_qup6_i2c_apps_clk_src", 315 - .parent_names = gcc_xo_gpll0, 338 + .parent_data = gcc_xo_gpll0, 316 339 .num_parents = 2, 317 340 .ops = &clk_rcg2_ops, 318 341 }, ··· 323 348 .hid_width = 5, 324 349 .parent_map = gcc_xo_gpll0_map, 325 350 .freq_tbl = ftbl_blspqup_spi_apps_clk_src, 326 - .clkr.hw.init = &(struct clk_init_data) 327 - { 351 + .clkr.hw.init = &(struct clk_init_data){ 328 352 .name = "blsp1_qup6_spi_apps_clk_src", 329 - .parent_names = gcc_xo_gpll0, 353 + .parent_data = gcc_xo_gpll0, 330 354 .num_parents = 2, 331 355 .ops = &clk_rcg2_ops, 332 356 }, ··· 356 382 .hid_width = 5, 357 383 .parent_map = gcc_xo_gpll0_map, 358 384 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 359 - .clkr.hw.init = &(struct clk_init_data) 360 - { 385 + .clkr.hw.init = &(struct clk_init_data){ 361 386 .name = "blsp1_uart1_apps_clk_src", 362 - .parent_names = gcc_xo_gpll0, 387 + .parent_data = gcc_xo_gpll0, 363 388 .num_parents = 2, 364 389 .ops = &clk_rcg2_ops, 365 390 }, ··· 370 397 .hid_width = 5, 371 398 .parent_map = gcc_xo_gpll0_map, 372 399 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 373 - .clkr.hw.init = &(struct clk_init_data) 374 - { 400 + .clkr.hw.init = &(struct clk_init_data){ 375 401 .name = "blsp1_uart2_apps_clk_src", 376 - .parent_names = gcc_xo_gpll0, 402 + .parent_data = gcc_xo_gpll0, 377 403 .num_parents = 2, 378 404 .ops = &clk_rcg2_ops, 379 405 }, ··· 384 412 .hid_width = 5, 385 413 .parent_map = gcc_xo_gpll0_map, 386 414 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 387 - .clkr.hw.init = &(struct clk_init_data) 388 - { 415 + .clkr.hw.init = &(struct clk_init_data){ 389 416 .name = "blsp1_uart3_apps_clk_src", 390 - .parent_names = gcc_xo_gpll0, 417 + .parent_data = gcc_xo_gpll0, 391 418 .num_parents = 2, 392 419 .ops = &clk_rcg2_ops, 393 420 }, ··· 398 427 .hid_width = 5, 399 428 .parent_map = gcc_xo_gpll0_map, 400 429 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 401 - .clkr.hw.init = &(struct clk_init_data) 402 - { 430 + .clkr.hw.init = &(struct clk_init_data){ 403 431 .name = "blsp1_uart4_apps_clk_src", 404 - .parent_names = gcc_xo_gpll0, 432 + .parent_data = gcc_xo_gpll0, 405 433 .num_parents = 2, 406 434 .ops = &clk_rcg2_ops, 407 435 }, ··· 412 442 .hid_width = 5, 413 443 .parent_map = gcc_xo_gpll0_map, 414 444 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 415 - .clkr.hw.init = &(struct clk_init_data) 416 - { 445 + .clkr.hw.init = &(struct clk_init_data){ 417 446 .name = "blsp1_uart5_apps_clk_src", 418 - .parent_names = gcc_xo_gpll0, 447 + .parent_data = gcc_xo_gpll0, 419 448 .num_parents = 2, 420 449 .ops = &clk_rcg2_ops, 421 450 }, ··· 426 457 .hid_width = 5, 427 458 .parent_map = gcc_xo_gpll0_map, 428 459 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 429 - .clkr.hw.init = &(struct clk_init_data) 430 - { 460 + .clkr.hw.init = &(struct clk_init_data){ 431 461 .name = "blsp1_uart6_apps_clk_src", 432 - .parent_names = gcc_xo_gpll0, 462 + .parent_data = gcc_xo_gpll0, 433 463 .num_parents = 2, 434 464 .ops = &clk_rcg2_ops, 435 465 }, ··· 439 471 .hid_width = 5, 440 472 .parent_map = gcc_xo_gpll0_map, 441 473 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 442 - .clkr.hw.init = &(struct clk_init_data) 443 - { 474 + .clkr.hw.init = &(struct clk_init_data){ 444 475 .name = "blsp2_qup1_i2c_apps_clk_src", 445 - .parent_names = gcc_xo_gpll0, 476 + .parent_data = gcc_xo_gpll0, 446 477 .num_parents = 2, 447 478 .ops = &clk_rcg2_ops, 448 479 }, ··· 453 486 .hid_width = 5, 454 487 .parent_map = gcc_xo_gpll0_map, 455 488 .freq_tbl = ftbl_blspqup_spi_apps_clk_src, 456 - .clkr.hw.init = &(struct clk_init_data) 457 - { 489 + .clkr.hw.init = &(struct clk_init_data){ 458 490 .name = "blsp2_qup1_spi_apps_clk_src", 459 - .parent_names = gcc_xo_gpll0, 491 + .parent_data = gcc_xo_gpll0, 460 492 .num_parents = 2, 461 493 .ops = &clk_rcg2_ops, 462 494 }, ··· 466 500 .hid_width = 5, 467 501 .parent_map = gcc_xo_gpll0_map, 468 502 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 469 - .clkr.hw.init = &(struct clk_init_data) 470 - { 503 + .clkr.hw.init = &(struct clk_init_data){ 471 504 .name = "blsp2_qup2_i2c_apps_clk_src", 472 - .parent_names = gcc_xo_gpll0, 505 + .parent_data = gcc_xo_gpll0, 473 506 .num_parents = 2, 474 507 .ops = &clk_rcg2_ops, 475 508 }, ··· 480 515 .hid_width = 5, 481 516 .parent_map = gcc_xo_gpll0_map, 482 517 .freq_tbl = ftbl_blspqup_spi_apps_clk_src, 483 - .clkr.hw.init = &(struct clk_init_data) 484 - { 518 + .clkr.hw.init = &(struct clk_init_data){ 485 519 .name = "blsp2_qup2_spi_apps_clk_src", 486 - .parent_names = gcc_xo_gpll0, 520 + .parent_data = gcc_xo_gpll0, 487 521 .num_parents = 2, 488 522 .ops = &clk_rcg2_ops, 489 523 }, ··· 493 529 .hid_width = 5, 494 530 .parent_map = gcc_xo_gpll0_map, 495 531 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 496 - .clkr.hw.init = &(struct clk_init_data) 497 - { 532 + .clkr.hw.init = &(struct clk_init_data){ 498 533 .name = "blsp2_qup3_i2c_apps_clk_src", 499 - .parent_names = gcc_xo_gpll0, 534 + .parent_data = gcc_xo_gpll0, 500 535 .num_parents = 2, 501 536 .ops = &clk_rcg2_ops, 502 537 }, ··· 507 544 .hid_width = 5, 508 545 .parent_map = gcc_xo_gpll0_map, 509 546 .freq_tbl = ftbl_blspqup_spi_apps_clk_src, 510 - .clkr.hw.init = &(struct clk_init_data) 511 - { 547 + .clkr.hw.init = &(struct clk_init_data){ 512 548 .name = "blsp2_qup3_spi_apps_clk_src", 513 - .parent_names = gcc_xo_gpll0, 549 + .parent_data = gcc_xo_gpll0, 514 550 .num_parents = 2, 515 551 .ops = &clk_rcg2_ops, 516 552 }, ··· 520 558 .hid_width = 5, 521 559 .parent_map = gcc_xo_gpll0_map, 522 560 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 523 - .clkr.hw.init = &(struct clk_init_data) 524 - { 561 + .clkr.hw.init = &(struct clk_init_data){ 525 562 .name = "blsp2_qup4_i2c_apps_clk_src", 526 - .parent_names = gcc_xo_gpll0, 563 + .parent_data = gcc_xo_gpll0, 527 564 .num_parents = 2, 528 565 .ops = &clk_rcg2_ops, 529 566 }, ··· 534 573 .hid_width = 5, 535 574 .parent_map = gcc_xo_gpll0_map, 536 575 .freq_tbl = ftbl_blspqup_spi_apps_clk_src, 537 - .clkr.hw.init = &(struct clk_init_data) 538 - { 576 + .clkr.hw.init = &(struct clk_init_data){ 539 577 .name = "blsp2_qup4_spi_apps_clk_src", 540 - .parent_names = gcc_xo_gpll0, 578 + .parent_data = gcc_xo_gpll0, 541 579 .num_parents = 2, 542 580 .ops = &clk_rcg2_ops, 543 581 }, ··· 547 587 .hid_width = 5, 548 588 .parent_map = gcc_xo_gpll0_map, 549 589 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 550 - .clkr.hw.init = &(struct clk_init_data) 551 - { 590 + .clkr.hw.init = &(struct clk_init_data){ 552 591 .name = "blsp2_qup5_i2c_apps_clk_src", 553 - .parent_names = gcc_xo_gpll0, 592 + .parent_data = gcc_xo_gpll0, 554 593 .num_parents = 2, 555 594 .ops = &clk_rcg2_ops, 556 595 }, ··· 561 602 .hid_width = 5, 562 603 .parent_map = gcc_xo_gpll0_map, 563 604 .freq_tbl = ftbl_blspqup_spi_apps_clk_src, 564 - .clkr.hw.init = &(struct clk_init_data) 565 - { 605 + .clkr.hw.init = &(struct clk_init_data){ 566 606 .name = "blsp2_qup5_spi_apps_clk_src", 567 - .parent_names = gcc_xo_gpll0, 607 + .parent_data = gcc_xo_gpll0, 568 608 .num_parents = 2, 569 609 .ops = &clk_rcg2_ops, 570 610 }, ··· 574 616 .hid_width = 5, 575 617 .parent_map = gcc_xo_gpll0_map, 576 618 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 577 - .clkr.hw.init = &(struct clk_init_data) 578 - { 619 + .clkr.hw.init = &(struct clk_init_data){ 579 620 .name = "blsp2_qup6_i2c_apps_clk_src", 580 - .parent_names = gcc_xo_gpll0, 621 + .parent_data = gcc_xo_gpll0, 581 622 .num_parents = 2, 582 623 .ops = &clk_rcg2_ops, 583 624 }, ··· 588 631 .hid_width = 5, 589 632 .parent_map = gcc_xo_gpll0_map, 590 633 .freq_tbl = ftbl_blspqup_spi_apps_clk_src, 591 - .clkr.hw.init = &(struct clk_init_data) 592 - { 634 + .clkr.hw.init = &(struct clk_init_data){ 593 635 .name = "blsp2_qup6_spi_apps_clk_src", 594 - .parent_names = gcc_xo_gpll0, 636 + .parent_data = gcc_xo_gpll0, 595 637 .num_parents = 2, 596 638 .ops = &clk_rcg2_ops, 597 639 }, ··· 602 646 .hid_width = 5, 603 647 .parent_map = gcc_xo_gpll0_map, 604 648 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 605 - .clkr.hw.init = &(struct clk_init_data) 606 - { 649 + .clkr.hw.init = &(struct clk_init_data){ 607 650 .name = "blsp2_uart1_apps_clk_src", 608 - .parent_names = gcc_xo_gpll0, 651 + .parent_data = gcc_xo_gpll0, 609 652 .num_parents = 2, 610 653 .ops = &clk_rcg2_ops, 611 654 }, ··· 616 661 .hid_width = 5, 617 662 .parent_map = gcc_xo_gpll0_map, 618 663 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 619 - .clkr.hw.init = &(struct clk_init_data) 620 - { 664 + .clkr.hw.init = &(struct clk_init_data){ 621 665 .name = "blsp2_uart2_apps_clk_src", 622 - .parent_names = gcc_xo_gpll0, 666 + .parent_data = gcc_xo_gpll0, 623 667 .num_parents = 2, 624 668 .ops = &clk_rcg2_ops, 625 669 }, ··· 630 676 .hid_width = 5, 631 677 .parent_map = gcc_xo_gpll0_map, 632 678 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 633 - .clkr.hw.init = &(struct clk_init_data) 634 - { 679 + .clkr.hw.init = &(struct clk_init_data){ 635 680 .name = "blsp2_uart3_apps_clk_src", 636 - .parent_names = gcc_xo_gpll0, 681 + .parent_data = gcc_xo_gpll0, 637 682 .num_parents = 2, 638 683 .ops = &clk_rcg2_ops, 639 684 }, ··· 644 691 .hid_width = 5, 645 692 .parent_map = gcc_xo_gpll0_map, 646 693 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 647 - .clkr.hw.init = &(struct clk_init_data) 648 - { 694 + .clkr.hw.init = &(struct clk_init_data){ 649 695 .name = "blsp2_uart4_apps_clk_src", 650 - .parent_names = gcc_xo_gpll0, 696 + .parent_data = gcc_xo_gpll0, 651 697 .num_parents = 2, 652 698 .ops = &clk_rcg2_ops, 653 699 }, ··· 658 706 .hid_width = 5, 659 707 .parent_map = gcc_xo_gpll0_map, 660 708 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 661 - .clkr.hw.init = &(struct clk_init_data) 662 - { 709 + .clkr.hw.init = &(struct clk_init_data){ 663 710 .name = "blsp2_uart5_apps_clk_src", 664 - .parent_names = gcc_xo_gpll0, 711 + .parent_data = gcc_xo_gpll0, 665 712 .num_parents = 2, 666 713 .ops = &clk_rcg2_ops, 667 714 }, ··· 672 721 .hid_width = 5, 673 722 .parent_map = gcc_xo_gpll0_map, 674 723 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 675 - .clkr.hw.init = &(struct clk_init_data) 676 - { 724 + .clkr.hw.init = &(struct clk_init_data){ 677 725 .name = "blsp2_uart6_apps_clk_src", 678 - .parent_names = gcc_xo_gpll0, 726 + .parent_data = gcc_xo_gpll0, 679 727 .num_parents = 2, 680 728 .ops = &clk_rcg2_ops, 681 729 }, ··· 693 743 .hid_width = 5, 694 744 .parent_map = gcc_xo_gpll0_map, 695 745 .freq_tbl = ftbl_gp1_clk_src, 696 - .clkr.hw.init = &(struct clk_init_data) 697 - { 746 + .clkr.hw.init = &(struct clk_init_data){ 698 747 .name = "gp1_clk_src", 699 - .parent_names = gcc_xo_gpll0, 748 + .parent_data = gcc_xo_gpll0, 700 749 .num_parents = 2, 701 750 .ops = &clk_rcg2_ops, 702 751 }, ··· 714 765 .hid_width = 5, 715 766 .parent_map = gcc_xo_gpll0_map, 716 767 .freq_tbl = ftbl_gp2_clk_src, 717 - .clkr.hw.init = &(struct clk_init_data) 718 - { 768 + .clkr.hw.init = &(struct clk_init_data){ 719 769 .name = "gp2_clk_src", 720 - .parent_names = gcc_xo_gpll0, 770 + .parent_data = gcc_xo_gpll0, 721 771 .num_parents = 2, 722 772 .ops = &clk_rcg2_ops, 723 773 }, ··· 735 787 .hid_width = 5, 736 788 .parent_map = gcc_xo_gpll0_map, 737 789 .freq_tbl = ftbl_gp3_clk_src, 738 - .clkr.hw.init = &(struct clk_init_data) 739 - { 790 + .clkr.hw.init = &(struct clk_init_data){ 740 791 .name = "gp3_clk_src", 741 - .parent_names = gcc_xo_gpll0, 792 + .parent_data = gcc_xo_gpll0, 742 793 .num_parents = 2, 743 794 .ops = &clk_rcg2_ops, 744 795 }, ··· 753 806 .mnd_width = 8, 754 807 .hid_width = 5, 755 808 .freq_tbl = ftbl_pcie_0_aux_clk_src, 756 - .clkr.hw.init = &(struct clk_init_data) 757 - { 809 + .clkr.hw.init = &(struct clk_init_data){ 758 810 .name = "pcie_0_aux_clk_src", 759 - .parent_names = (const char *[]) { "xo" }, 811 + .parent_data = &(const struct clk_parent_data){ 812 + .fw_name = "xo", 813 + }, 760 814 .num_parents = 1, 761 815 .ops = &clk_rcg2_ops, 762 816 }, ··· 772 824 .cmd_rcgr = 0x1adc, 773 825 .hid_width = 5, 774 826 .freq_tbl = ftbl_pcie_pipe_clk_src, 775 - .clkr.hw.init = &(struct clk_init_data) 776 - { 827 + .clkr.hw.init = &(struct clk_init_data){ 777 828 .name = "pcie_0_pipe_clk_src", 778 - .parent_names = (const char *[]) { "xo" }, 829 + .parent_data = &(const struct clk_parent_data){ 830 + .fw_name = "xo", 831 + }, 779 832 .num_parents = 1, 780 833 .ops = &clk_rcg2_ops, 781 834 }, ··· 792 843 .mnd_width = 8, 793 844 .hid_width = 5, 794 845 .freq_tbl = ftbl_pcie_1_aux_clk_src, 795 - .clkr.hw.init = &(struct clk_init_data) 796 - { 846 + .clkr.hw.init = &(struct clk_init_data){ 797 847 .name = "pcie_1_aux_clk_src", 798 - .parent_names = (const char *[]) { "xo" }, 848 + .parent_data = &(const struct clk_parent_data){ 849 + .fw_name = "xo", 850 + }, 799 851 .num_parents = 1, 800 852 .ops = &clk_rcg2_ops, 801 853 }, ··· 806 856 .cmd_rcgr = 0x1b5c, 807 857 .hid_width = 5, 808 858 .freq_tbl = ftbl_pcie_pipe_clk_src, 809 - .clkr.hw.init = &(struct clk_init_data) 810 - { 859 + .clkr.hw.init = &(struct clk_init_data){ 811 860 .name = "pcie_1_pipe_clk_src", 812 - .parent_names = (const char *[]) { "xo" }, 861 + .parent_data = &(const struct clk_parent_data){ 862 + .fw_name = "xo", 863 + }, 813 864 .num_parents = 1, 814 865 .ops = &clk_rcg2_ops, 815 866 }, ··· 826 875 .hid_width = 5, 827 876 .parent_map = gcc_xo_gpll0_map, 828 877 .freq_tbl = ftbl_pdm2_clk_src, 829 - .clkr.hw.init = &(struct clk_init_data) 830 - { 878 + .clkr.hw.init = &(struct clk_init_data){ 831 879 .name = "pdm2_clk_src", 832 - .parent_names = gcc_xo_gpll0, 880 + .parent_data = gcc_xo_gpll0, 833 881 .num_parents = 2, 834 882 .ops = &clk_rcg2_ops, 835 883 }, ··· 852 902 .hid_width = 5, 853 903 .parent_map = gcc_xo_gpll0_gpll4_map, 854 904 .freq_tbl = ftbl_sdcc1_apps_clk_src, 855 - .clkr.hw.init = &(struct clk_init_data) 856 - { 905 + .clkr.hw.init = &(struct clk_init_data){ 857 906 .name = "sdcc1_apps_clk_src", 858 - .parent_names = gcc_xo_gpll0_gpll4, 907 + .parent_data = gcc_xo_gpll0_gpll4, 859 908 .num_parents = 3, 860 909 .ops = &clk_rcg2_floor_ops, 861 910 }, ··· 877 928 .hid_width = 5, 878 929 .parent_map = gcc_xo_gpll0_map, 879 930 .freq_tbl = ftbl_sdcc2_4_apps_clk_src, 880 - .clkr.hw.init = &(struct clk_init_data) 881 - { 931 + .clkr.hw.init = &(struct clk_init_data){ 882 932 .name = "sdcc2_apps_clk_src", 883 - .parent_names = gcc_xo_gpll0, 933 + .parent_data = gcc_xo_gpll0, 884 934 .num_parents = 2, 885 935 .ops = &clk_rcg2_floor_ops, 886 936 }, ··· 891 943 .hid_width = 5, 892 944 .parent_map = gcc_xo_gpll0_map, 893 945 .freq_tbl = ftbl_sdcc2_4_apps_clk_src, 894 - .clkr.hw.init = &(struct clk_init_data) 895 - { 946 + .clkr.hw.init = &(struct clk_init_data){ 896 947 .name = "sdcc3_apps_clk_src", 897 - .parent_names = gcc_xo_gpll0, 948 + .parent_data = gcc_xo_gpll0, 898 949 .num_parents = 2, 899 950 .ops = &clk_rcg2_floor_ops, 900 951 }, ··· 905 958 .hid_width = 5, 906 959 .parent_map = gcc_xo_gpll0_map, 907 960 .freq_tbl = ftbl_sdcc2_4_apps_clk_src, 908 - .clkr.hw.init = &(struct clk_init_data) 909 - { 961 + .clkr.hw.init = &(struct clk_init_data){ 910 962 .name = "sdcc4_apps_clk_src", 911 - .parent_names = gcc_xo_gpll0, 963 + .parent_data = gcc_xo_gpll0, 912 964 .num_parents = 2, 913 965 .ops = &clk_rcg2_floor_ops, 914 966 }, ··· 923 977 .mnd_width = 8, 924 978 .hid_width = 5, 925 979 .freq_tbl = ftbl_tsif_ref_clk_src, 926 - .clkr.hw.init = &(struct clk_init_data) 927 - { 980 + .clkr.hw.init = &(struct clk_init_data){ 928 981 .name = "tsif_ref_clk_src", 929 - .parent_names = (const char *[]) { "xo" }, 982 + .parent_data = &(const struct clk_parent_data){ 983 + .fw_name = "xo", 984 + }, 930 985 .num_parents = 1, 931 986 .ops = &clk_rcg2_ops, 932 987 }, ··· 944 997 .hid_width = 5, 945 998 .parent_map = gcc_xo_gpll0_map, 946 999 .freq_tbl = ftbl_usb30_mock_utmi_clk_src, 947 - .clkr.hw.init = &(struct clk_init_data) 948 - { 1000 + .clkr.hw.init = &(struct clk_init_data){ 949 1001 .name = "usb30_mock_utmi_clk_src", 950 - .parent_names = gcc_xo_gpll0, 1002 + .parent_data = gcc_xo_gpll0, 951 1003 .num_parents = 2, 952 1004 .ops = &clk_rcg2_ops, 953 1005 }, ··· 961 1015 .cmd_rcgr = 0x1414, 962 1016 .hid_width = 5, 963 1017 .freq_tbl = ftbl_usb3_phy_aux_clk_src, 964 - .clkr.hw.init = &(struct clk_init_data) 965 - { 1018 + .clkr.hw.init = &(struct clk_init_data){ 966 1019 .name = "usb3_phy_aux_clk_src", 967 - .parent_names = (const char *[]) { "xo" }, 1020 + .parent_data = &(const struct clk_parent_data){ 1021 + .fw_name = "xo", 1022 + }, 968 1023 .num_parents = 1, 969 1024 .ops = &clk_rcg2_ops, 970 1025 }, ··· 981 1034 .hid_width = 5, 982 1035 .parent_map = gcc_xo_gpll0_map, 983 1036 .freq_tbl = ftbl_usb_hs_system_clk_src, 984 - .clkr.hw.init = &(struct clk_init_data) 985 - { 1037 + .clkr.hw.init = &(struct clk_init_data){ 986 1038 .name = "usb_hs_system_clk_src", 987 - .parent_names = gcc_xo_gpll0, 1039 + .parent_data = gcc_xo_gpll0, 988 1040 .num_parents = 2, 989 1041 .ops = &clk_rcg2_ops, 990 1042 }, ··· 995 1049 .clkr = { 996 1050 .enable_reg = 0x1484, 997 1051 .enable_mask = BIT(17), 998 - .hw.init = &(struct clk_init_data) 999 - { 1052 + .hw.init = &(struct clk_init_data){ 1000 1053 .name = "gcc_blsp1_ahb_clk", 1001 1054 .ops = &clk_branch2_ops, 1002 1055 }, ··· 1007 1062 .clkr = { 1008 1063 .enable_reg = 0x0648, 1009 1064 .enable_mask = BIT(0), 1010 - .hw.init = &(struct clk_init_data) 1011 - { 1065 + .hw.init = &(struct clk_init_data){ 1012 1066 .name = "gcc_blsp1_qup1_i2c_apps_clk", 1013 - .parent_names = (const char *[]) { 1014 - "blsp1_qup1_i2c_apps_clk_src", 1015 - }, 1067 + .parent_hws = (const struct clk_hw *[]){ &blsp1_qup1_i2c_apps_clk_src.clkr.hw }, 1016 1068 .num_parents = 1, 1017 1069 .flags = CLK_SET_RATE_PARENT, 1018 1070 .ops = &clk_branch2_ops, ··· 1022 1080 .clkr = { 1023 1081 .enable_reg = 0x0644, 1024 1082 .enable_mask = BIT(0), 1025 - .hw.init = &(struct clk_init_data) 1026 - { 1083 + .hw.init = &(struct clk_init_data){ 1027 1084 .name = "gcc_blsp1_qup1_spi_apps_clk", 1028 - .parent_names = (const char *[]) { 1029 - "blsp1_qup1_spi_apps_clk_src", 1030 - }, 1085 + .parent_hws = (const struct clk_hw *[]){ &blsp1_qup1_spi_apps_clk_src.clkr.hw }, 1031 1086 .num_parents = 1, 1032 1087 .flags = CLK_SET_RATE_PARENT, 1033 1088 .ops = &clk_branch2_ops, ··· 1037 1098 .clkr = { 1038 1099 .enable_reg = 0x06c8, 1039 1100 .enable_mask = BIT(0), 1040 - .hw.init = &(struct clk_init_data) 1041 - { 1101 + .hw.init = &(struct clk_init_data){ 1042 1102 .name = "gcc_blsp1_qup2_i2c_apps_clk", 1043 - .parent_names = (const char *[]) { 1044 - "blsp1_qup2_i2c_apps_clk_src", 1045 - }, 1103 + .parent_hws = (const struct clk_hw *[]){ &blsp1_qup2_i2c_apps_clk_src.clkr.hw }, 1046 1104 .num_parents = 1, 1047 1105 .flags = CLK_SET_RATE_PARENT, 1048 1106 .ops = &clk_branch2_ops, ··· 1052 1116 .clkr = { 1053 1117 .enable_reg = 0x06c4, 1054 1118 .enable_mask = BIT(0), 1055 - .hw.init = &(struct clk_init_data) 1056 - { 1119 + .hw.init = &(struct clk_init_data){ 1057 1120 .name = "gcc_blsp1_qup2_spi_apps_clk", 1058 - .parent_names = (const char *[]) { 1059 - "blsp1_qup2_spi_apps_clk_src", 1060 - }, 1121 + .parent_hws = (const struct clk_hw *[]){ &blsp1_qup2_spi_apps_clk_src.clkr.hw }, 1061 1122 .num_parents = 1, 1062 1123 .flags = CLK_SET_RATE_PARENT, 1063 1124 .ops = &clk_branch2_ops, ··· 1067 1134 .clkr = { 1068 1135 .enable_reg = 0x0748, 1069 1136 .enable_mask = BIT(0), 1070 - .hw.init = &(struct clk_init_data) 1071 - { 1137 + .hw.init = &(struct clk_init_data){ 1072 1138 .name = "gcc_blsp1_qup3_i2c_apps_clk", 1073 - .parent_names = (const char *[]) { 1074 - "blsp1_qup3_i2c_apps_clk_src", 1075 - }, 1139 + .parent_hws = (const struct clk_hw *[]){ &blsp1_qup3_i2c_apps_clk_src.clkr.hw }, 1076 1140 .num_parents = 1, 1077 1141 .flags = CLK_SET_RATE_PARENT, 1078 1142 .ops = &clk_branch2_ops, ··· 1082 1152 .clkr = { 1083 1153 .enable_reg = 0x0744, 1084 1154 .enable_mask = BIT(0), 1085 - .hw.init = &(struct clk_init_data) 1086 - { 1155 + .hw.init = &(struct clk_init_data){ 1087 1156 .name = "gcc_blsp1_qup3_spi_apps_clk", 1088 - .parent_names = (const char *[]) { 1089 - "blsp1_qup3_spi_apps_clk_src", 1090 - }, 1157 + .parent_hws = (const struct clk_hw *[]){ &blsp1_qup3_spi_apps_clk_src.clkr.hw }, 1091 1158 .num_parents = 1, 1092 1159 .flags = CLK_SET_RATE_PARENT, 1093 1160 .ops = &clk_branch2_ops, ··· 1097 1170 .clkr = { 1098 1171 .enable_reg = 0x07c8, 1099 1172 .enable_mask = BIT(0), 1100 - .hw.init = &(struct clk_init_data) 1101 - { 1173 + .hw.init = &(struct clk_init_data){ 1102 1174 .name = "gcc_blsp1_qup4_i2c_apps_clk", 1103 - .parent_names = (const char *[]) { 1104 - "blsp1_qup4_i2c_apps_clk_src", 1105 - }, 1175 + .parent_hws = (const struct clk_hw *[]){ &blsp1_qup4_i2c_apps_clk_src.clkr.hw }, 1106 1176 .num_parents = 1, 1107 1177 .flags = CLK_SET_RATE_PARENT, 1108 1178 .ops = &clk_branch2_ops, ··· 1112 1188 .clkr = { 1113 1189 .enable_reg = 0x07c4, 1114 1190 .enable_mask = BIT(0), 1115 - .hw.init = &(struct clk_init_data) 1116 - { 1191 + .hw.init = &(struct clk_init_data){ 1117 1192 .name = "gcc_blsp1_qup4_spi_apps_clk", 1118 - .parent_names = (const char *[]) { 1119 - "blsp1_qup4_spi_apps_clk_src", 1120 - }, 1193 + .parent_hws = (const struct clk_hw *[]){ &blsp1_qup4_spi_apps_clk_src.clkr.hw }, 1121 1194 .num_parents = 1, 1122 1195 .flags = CLK_SET_RATE_PARENT, 1123 1196 .ops = &clk_branch2_ops, ··· 1127 1206 .clkr = { 1128 1207 .enable_reg = 0x0848, 1129 1208 .enable_mask = BIT(0), 1130 - .hw.init = &(struct clk_init_data) 1131 - { 1209 + .hw.init = &(struct clk_init_data){ 1132 1210 .name = "gcc_blsp1_qup5_i2c_apps_clk", 1133 - .parent_names = (const char *[]) { 1134 - "blsp1_qup5_i2c_apps_clk_src", 1135 - }, 1211 + .parent_hws = (const struct clk_hw *[]){ &blsp1_qup5_i2c_apps_clk_src.clkr.hw }, 1136 1212 .num_parents = 1, 1137 1213 .flags = CLK_SET_RATE_PARENT, 1138 1214 .ops = &clk_branch2_ops, ··· 1142 1224 .clkr = { 1143 1225 .enable_reg = 0x0844, 1144 1226 .enable_mask = BIT(0), 1145 - .hw.init = &(struct clk_init_data) 1146 - { 1227 + .hw.init = &(struct clk_init_data){ 1147 1228 .name = "gcc_blsp1_qup5_spi_apps_clk", 1148 - .parent_names = (const char *[]) { 1149 - "blsp1_qup5_spi_apps_clk_src", 1150 - }, 1229 + .parent_hws = (const struct clk_hw *[]){ &blsp1_qup5_spi_apps_clk_src.clkr.hw }, 1151 1230 .num_parents = 1, 1152 1231 .flags = CLK_SET_RATE_PARENT, 1153 1232 .ops = &clk_branch2_ops, ··· 1157 1242 .clkr = { 1158 1243 .enable_reg = 0x08c8, 1159 1244 .enable_mask = BIT(0), 1160 - .hw.init = &(struct clk_init_data) 1161 - { 1245 + .hw.init = &(struct clk_init_data){ 1162 1246 .name = "gcc_blsp1_qup6_i2c_apps_clk", 1163 - .parent_names = (const char *[]) { 1164 - "blsp1_qup6_i2c_apps_clk_src", 1165 - }, 1247 + .parent_hws = (const struct clk_hw *[]){ &blsp1_qup6_i2c_apps_clk_src.clkr.hw }, 1166 1248 .num_parents = 1, 1167 1249 .flags = CLK_SET_RATE_PARENT, 1168 1250 .ops = &clk_branch2_ops, ··· 1172 1260 .clkr = { 1173 1261 .enable_reg = 0x08c4, 1174 1262 .enable_mask = BIT(0), 1175 - .hw.init = &(struct clk_init_data) 1176 - { 1263 + .hw.init = &(struct clk_init_data){ 1177 1264 .name = "gcc_blsp1_qup6_spi_apps_clk", 1178 - .parent_names = (const char *[]) { 1179 - "blsp1_qup6_spi_apps_clk_src", 1180 - }, 1265 + .parent_hws = (const struct clk_hw *[]){ &blsp1_qup6_spi_apps_clk_src.clkr.hw }, 1181 1266 .num_parents = 1, 1182 1267 .flags = CLK_SET_RATE_PARENT, 1183 1268 .ops = &clk_branch2_ops, ··· 1187 1278 .clkr = { 1188 1279 .enable_reg = 0x0684, 1189 1280 .enable_mask = BIT(0), 1190 - .hw.init = &(struct clk_init_data) 1191 - { 1281 + .hw.init = &(struct clk_init_data){ 1192 1282 .name = "gcc_blsp1_uart1_apps_clk", 1193 - .parent_names = (const char *[]) { 1194 - "blsp1_uart1_apps_clk_src", 1195 - }, 1283 + .parent_hws = (const struct clk_hw *[]){ &blsp1_uart1_apps_clk_src.clkr.hw }, 1196 1284 .num_parents = 1, 1197 1285 .flags = CLK_SET_RATE_PARENT, 1198 1286 .ops = &clk_branch2_ops, ··· 1202 1296 .clkr = { 1203 1297 .enable_reg = 0x0704, 1204 1298 .enable_mask = BIT(0), 1205 - .hw.init = &(struct clk_init_data) 1206 - { 1299 + .hw.init = &(struct clk_init_data){ 1207 1300 .name = "gcc_blsp1_uart2_apps_clk", 1208 - .parent_names = (const char *[]) { 1209 - "blsp1_uart2_apps_clk_src", 1210 - }, 1301 + .parent_hws = (const struct clk_hw *[]){ &blsp1_uart2_apps_clk_src.clkr.hw }, 1211 1302 .num_parents = 1, 1212 1303 .flags = CLK_SET_RATE_PARENT, 1213 1304 .ops = &clk_branch2_ops, ··· 1217 1314 .clkr = { 1218 1315 .enable_reg = 0x0784, 1219 1316 .enable_mask = BIT(0), 1220 - .hw.init = &(struct clk_init_data) 1221 - { 1317 + .hw.init = &(struct clk_init_data){ 1222 1318 .name = "gcc_blsp1_uart3_apps_clk", 1223 - .parent_names = (const char *[]) { 1224 - "blsp1_uart3_apps_clk_src", 1225 - }, 1319 + .parent_hws = (const struct clk_hw *[]){ &blsp1_uart3_apps_clk_src.clkr.hw }, 1226 1320 .num_parents = 1, 1227 1321 .flags = CLK_SET_RATE_PARENT, 1228 1322 .ops = &clk_branch2_ops, ··· 1232 1332 .clkr = { 1233 1333 .enable_reg = 0x0804, 1234 1334 .enable_mask = BIT(0), 1235 - .hw.init = &(struct clk_init_data) 1236 - { 1335 + .hw.init = &(struct clk_init_data){ 1237 1336 .name = "gcc_blsp1_uart4_apps_clk", 1238 - .parent_names = (const char *[]) { 1239 - "blsp1_uart4_apps_clk_src", 1240 - }, 1337 + .parent_hws = (const struct clk_hw *[]){ &blsp1_uart4_apps_clk_src.clkr.hw }, 1241 1338 .num_parents = 1, 1242 1339 .flags = CLK_SET_RATE_PARENT, 1243 1340 .ops = &clk_branch2_ops, ··· 1247 1350 .clkr = { 1248 1351 .enable_reg = 0x0884, 1249 1352 .enable_mask = BIT(0), 1250 - .hw.init = &(struct clk_init_data) 1251 - { 1353 + .hw.init = &(struct clk_init_data){ 1252 1354 .name = "gcc_blsp1_uart5_apps_clk", 1253 - .parent_names = (const char *[]) { 1254 - "blsp1_uart5_apps_clk_src", 1255 - }, 1355 + .parent_hws = (const struct clk_hw *[]){ &blsp1_uart5_apps_clk_src.clkr.hw }, 1256 1356 .num_parents = 1, 1257 1357 .flags = CLK_SET_RATE_PARENT, 1258 1358 .ops = &clk_branch2_ops, ··· 1262 1368 .clkr = { 1263 1369 .enable_reg = 0x0904, 1264 1370 .enable_mask = BIT(0), 1265 - .hw.init = &(struct clk_init_data) 1266 - { 1371 + .hw.init = &(struct clk_init_data){ 1267 1372 .name = "gcc_blsp1_uart6_apps_clk", 1268 - .parent_names = (const char *[]) { 1269 - "blsp1_uart6_apps_clk_src", 1270 - }, 1373 + .parent_hws = (const struct clk_hw *[]){ &blsp1_uart6_apps_clk_src.clkr.hw }, 1271 1374 .num_parents = 1, 1272 1375 .flags = CLK_SET_RATE_PARENT, 1273 1376 .ops = &clk_branch2_ops, ··· 1278 1387 .clkr = { 1279 1388 .enable_reg = 0x1484, 1280 1389 .enable_mask = BIT(15), 1281 - .hw.init = &(struct clk_init_data) 1282 - { 1390 + .hw.init = &(struct clk_init_data){ 1283 1391 .name = "gcc_blsp2_ahb_clk", 1284 1392 .ops = &clk_branch2_ops, 1285 1393 }, ··· 1290 1400 .clkr = { 1291 1401 .enable_reg = 0x0988, 1292 1402 .enable_mask = BIT(0), 1293 - .hw.init = &(struct clk_init_data) 1294 - { 1403 + .hw.init = &(struct clk_init_data){ 1295 1404 .name = "gcc_blsp2_qup1_i2c_apps_clk", 1296 - .parent_names = (const char *[]) { 1297 - "blsp2_qup1_i2c_apps_clk_src", 1298 - }, 1405 + .parent_hws = (const struct clk_hw *[]){ &blsp2_qup1_i2c_apps_clk_src.clkr.hw }, 1299 1406 .num_parents = 1, 1300 1407 .flags = CLK_SET_RATE_PARENT, 1301 1408 .ops = &clk_branch2_ops, ··· 1305 1418 .clkr = { 1306 1419 .enable_reg = 0x0984, 1307 1420 .enable_mask = BIT(0), 1308 - .hw.init = &(struct clk_init_data) 1309 - { 1421 + .hw.init = &(struct clk_init_data){ 1310 1422 .name = "gcc_blsp2_qup1_spi_apps_clk", 1311 - .parent_names = (const char *[]) { 1312 - "blsp2_qup1_spi_apps_clk_src", 1313 - }, 1423 + .parent_hws = (const struct clk_hw *[]){ &blsp2_qup1_spi_apps_clk_src.clkr.hw }, 1314 1424 .num_parents = 1, 1315 1425 .flags = CLK_SET_RATE_PARENT, 1316 1426 .ops = &clk_branch2_ops, ··· 1320 1436 .clkr = { 1321 1437 .enable_reg = 0x0a08, 1322 1438 .enable_mask = BIT(0), 1323 - .hw.init = &(struct clk_init_data) 1324 - { 1439 + .hw.init = &(struct clk_init_data){ 1325 1440 .name = "gcc_blsp2_qup2_i2c_apps_clk", 1326 - .parent_names = (const char *[]) { 1327 - "blsp2_qup2_i2c_apps_clk_src", 1328 - }, 1441 + .parent_hws = (const struct clk_hw *[]){ &blsp2_qup2_i2c_apps_clk_src.clkr.hw }, 1329 1442 .num_parents = 1, 1330 1443 .flags = CLK_SET_RATE_PARENT, 1331 1444 .ops = &clk_branch2_ops, ··· 1335 1454 .clkr = { 1336 1455 .enable_reg = 0x0a04, 1337 1456 .enable_mask = BIT(0), 1338 - .hw.init = &(struct clk_init_data) 1339 - { 1457 + .hw.init = &(struct clk_init_data){ 1340 1458 .name = "gcc_blsp2_qup2_spi_apps_clk", 1341 - .parent_names = (const char *[]) { 1342 - "blsp2_qup2_spi_apps_clk_src", 1343 - }, 1459 + .parent_hws = (const struct clk_hw *[]){ &blsp2_qup2_spi_apps_clk_src.clkr.hw }, 1344 1460 .num_parents = 1, 1345 1461 .flags = CLK_SET_RATE_PARENT, 1346 1462 .ops = &clk_branch2_ops, ··· 1350 1472 .clkr = { 1351 1473 .enable_reg = 0x0a88, 1352 1474 .enable_mask = BIT(0), 1353 - .hw.init = &(struct clk_init_data) 1354 - { 1475 + .hw.init = &(struct clk_init_data){ 1355 1476 .name = "gcc_blsp2_qup3_i2c_apps_clk", 1356 - .parent_names = (const char *[]) { 1357 - "blsp2_qup3_i2c_apps_clk_src", 1358 - }, 1477 + .parent_hws = (const struct clk_hw *[]){ &blsp2_qup3_i2c_apps_clk_src.clkr.hw }, 1359 1478 .num_parents = 1, 1360 1479 .flags = CLK_SET_RATE_PARENT, 1361 1480 .ops = &clk_branch2_ops, ··· 1365 1490 .clkr = { 1366 1491 .enable_reg = 0x0a84, 1367 1492 .enable_mask = BIT(0), 1368 - .hw.init = &(struct clk_init_data) 1369 - { 1493 + .hw.init = &(struct clk_init_data){ 1370 1494 .name = "gcc_blsp2_qup3_spi_apps_clk", 1371 - .parent_names = (const char *[]) { 1372 - "blsp2_qup3_spi_apps_clk_src", 1373 - }, 1495 + .parent_hws = (const struct clk_hw *[]){ &blsp2_qup3_spi_apps_clk_src.clkr.hw }, 1374 1496 .num_parents = 1, 1375 1497 .flags = CLK_SET_RATE_PARENT, 1376 1498 .ops = &clk_branch2_ops, ··· 1380 1508 .clkr = { 1381 1509 .enable_reg = 0x0b08, 1382 1510 .enable_mask = BIT(0), 1383 - .hw.init = &(struct clk_init_data) 1384 - { 1511 + .hw.init = &(struct clk_init_data){ 1385 1512 .name = "gcc_blsp2_qup4_i2c_apps_clk", 1386 - .parent_names = (const char *[]) { 1387 - "blsp2_qup4_i2c_apps_clk_src", 1388 - }, 1513 + .parent_hws = (const struct clk_hw *[]){ &blsp2_qup4_i2c_apps_clk_src.clkr.hw }, 1389 1514 .num_parents = 1, 1390 1515 .flags = CLK_SET_RATE_PARENT, 1391 1516 .ops = &clk_branch2_ops, ··· 1395 1526 .clkr = { 1396 1527 .enable_reg = 0x0b04, 1397 1528 .enable_mask = BIT(0), 1398 - .hw.init = &(struct clk_init_data) 1399 - { 1529 + .hw.init = &(struct clk_init_data){ 1400 1530 .name = "gcc_blsp2_qup4_spi_apps_clk", 1401 - .parent_names = (const char *[]) { 1402 - "blsp2_qup4_spi_apps_clk_src", 1403 - }, 1531 + .parent_hws = (const struct clk_hw *[]){ &blsp2_qup4_spi_apps_clk_src.clkr.hw }, 1404 1532 .num_parents = 1, 1405 1533 .flags = CLK_SET_RATE_PARENT, 1406 1534 .ops = &clk_branch2_ops, ··· 1410 1544 .clkr = { 1411 1545 .enable_reg = 0x0b88, 1412 1546 .enable_mask = BIT(0), 1413 - .hw.init = &(struct clk_init_data) 1414 - { 1547 + .hw.init = &(struct clk_init_data){ 1415 1548 .name = "gcc_blsp2_qup5_i2c_apps_clk", 1416 - .parent_names = (const char *[]) { 1417 - "blsp2_qup5_i2c_apps_clk_src", 1418 - }, 1549 + .parent_hws = (const struct clk_hw *[]){ &blsp2_qup5_i2c_apps_clk_src.clkr.hw }, 1419 1550 .num_parents = 1, 1420 1551 .flags = CLK_SET_RATE_PARENT, 1421 1552 .ops = &clk_branch2_ops, ··· 1425 1562 .clkr = { 1426 1563 .enable_reg = 0x0b84, 1427 1564 .enable_mask = BIT(0), 1428 - .hw.init = &(struct clk_init_data) 1429 - { 1565 + .hw.init = &(struct clk_init_data){ 1430 1566 .name = "gcc_blsp2_qup5_spi_apps_clk", 1431 - .parent_names = (const char *[]) { 1432 - "blsp2_qup5_spi_apps_clk_src", 1433 - }, 1567 + .parent_hws = (const struct clk_hw *[]){ &blsp2_qup5_spi_apps_clk_src.clkr.hw }, 1434 1568 .num_parents = 1, 1435 1569 .flags = CLK_SET_RATE_PARENT, 1436 1570 .ops = &clk_branch2_ops, ··· 1440 1580 .clkr = { 1441 1581 .enable_reg = 0x0c08, 1442 1582 .enable_mask = BIT(0), 1443 - .hw.init = &(struct clk_init_data) 1444 - { 1583 + .hw.init = &(struct clk_init_data){ 1445 1584 .name = "gcc_blsp2_qup6_i2c_apps_clk", 1446 - .parent_names = (const char *[]) { 1447 - "blsp2_qup6_i2c_apps_clk_src", 1448 - }, 1585 + .parent_hws = (const struct clk_hw *[]){ &blsp2_qup6_i2c_apps_clk_src.clkr.hw }, 1449 1586 .num_parents = 1, 1450 1587 .flags = CLK_SET_RATE_PARENT, 1451 1588 .ops = &clk_branch2_ops, ··· 1455 1598 .clkr = { 1456 1599 .enable_reg = 0x0c04, 1457 1600 .enable_mask = BIT(0), 1458 - .hw.init = &(struct clk_init_data) 1459 - { 1601 + .hw.init = &(struct clk_init_data){ 1460 1602 .name = "gcc_blsp2_qup6_spi_apps_clk", 1461 - .parent_names = (const char *[]) { 1462 - "blsp2_qup6_spi_apps_clk_src", 1463 - }, 1603 + .parent_hws = (const struct clk_hw *[]){ &blsp2_qup6_spi_apps_clk_src.clkr.hw }, 1464 1604 .num_parents = 1, 1465 1605 .flags = CLK_SET_RATE_PARENT, 1466 1606 .ops = &clk_branch2_ops, ··· 1470 1616 .clkr = { 1471 1617 .enable_reg = 0x09c4, 1472 1618 .enable_mask = BIT(0), 1473 - .hw.init = &(struct clk_init_data) 1474 - { 1619 + .hw.init = &(struct clk_init_data){ 1475 1620 .name = "gcc_blsp2_uart1_apps_clk", 1476 - .parent_names = (const char *[]) { 1477 - "blsp2_uart1_apps_clk_src", 1478 - }, 1621 + .parent_hws = (const struct clk_hw *[]){ &blsp2_uart1_apps_clk_src.clkr.hw }, 1479 1622 .num_parents = 1, 1480 1623 .flags = CLK_SET_RATE_PARENT, 1481 1624 .ops = &clk_branch2_ops, ··· 1485 1634 .clkr = { 1486 1635 .enable_reg = 0x0a44, 1487 1636 .enable_mask = BIT(0), 1488 - .hw.init = &(struct clk_init_data) 1489 - { 1637 + .hw.init = &(struct clk_init_data){ 1490 1638 .name = "gcc_blsp2_uart2_apps_clk", 1491 - .parent_names = (const char *[]) { 1492 - "blsp2_uart2_apps_clk_src", 1493 - }, 1639 + .parent_hws = (const struct clk_hw *[]){ &blsp2_uart2_apps_clk_src.clkr.hw }, 1494 1640 .num_parents = 1, 1495 1641 .flags = CLK_SET_RATE_PARENT, 1496 1642 .ops = &clk_branch2_ops, ··· 1500 1652 .clkr = { 1501 1653 .enable_reg = 0x0ac4, 1502 1654 .enable_mask = BIT(0), 1503 - .hw.init = &(struct clk_init_data) 1504 - { 1655 + .hw.init = &(struct clk_init_data){ 1505 1656 .name = "gcc_blsp2_uart3_apps_clk", 1506 - .parent_names = (const char *[]) { 1507 - "blsp2_uart3_apps_clk_src", 1508 - }, 1657 + .parent_hws = (const struct clk_hw *[]){ &blsp2_uart3_apps_clk_src.clkr.hw }, 1509 1658 .num_parents = 1, 1510 1659 .flags = CLK_SET_RATE_PARENT, 1511 1660 .ops = &clk_branch2_ops, ··· 1515 1670 .clkr = { 1516 1671 .enable_reg = 0x0b44, 1517 1672 .enable_mask = BIT(0), 1518 - .hw.init = &(struct clk_init_data) 1519 - { 1673 + .hw.init = &(struct clk_init_data){ 1520 1674 .name = "gcc_blsp2_uart4_apps_clk", 1521 - .parent_names = (const char *[]) { 1522 - "blsp2_uart4_apps_clk_src", 1523 - }, 1675 + .parent_hws = (const struct clk_hw *[]){ &blsp2_uart4_apps_clk_src.clkr.hw }, 1524 1676 .num_parents = 1, 1525 1677 .flags = CLK_SET_RATE_PARENT, 1526 1678 .ops = &clk_branch2_ops, ··· 1530 1688 .clkr = { 1531 1689 .enable_reg = 0x0bc4, 1532 1690 .enable_mask = BIT(0), 1533 - .hw.init = &(struct clk_init_data) 1534 - { 1691 + .hw.init = &(struct clk_init_data){ 1535 1692 .name = "gcc_blsp2_uart5_apps_clk", 1536 - .parent_names = (const char *[]) { 1537 - "blsp2_uart5_apps_clk_src", 1538 - }, 1693 + .parent_hws = (const struct clk_hw *[]){ &blsp2_uart5_apps_clk_src.clkr.hw }, 1539 1694 .num_parents = 1, 1540 1695 .flags = CLK_SET_RATE_PARENT, 1541 1696 .ops = &clk_branch2_ops, ··· 1545 1706 .clkr = { 1546 1707 .enable_reg = 0x0c44, 1547 1708 .enable_mask = BIT(0), 1548 - .hw.init = &(struct clk_init_data) 1549 - { 1709 + .hw.init = &(struct clk_init_data){ 1550 1710 .name = "gcc_blsp2_uart6_apps_clk", 1551 - .parent_names = (const char *[]) { 1552 - "blsp2_uart6_apps_clk_src", 1553 - }, 1711 + .parent_hws = (const struct clk_hw *[]){ &blsp2_uart6_apps_clk_src.clkr.hw }, 1554 1712 .num_parents = 1, 1555 1713 .flags = CLK_SET_RATE_PARENT, 1556 1714 .ops = &clk_branch2_ops, ··· 1560 1724 .clkr = { 1561 1725 .enable_reg = 0x1900, 1562 1726 .enable_mask = BIT(0), 1563 - .hw.init = &(struct clk_init_data) 1564 - { 1727 + .hw.init = &(struct clk_init_data){ 1565 1728 .name = "gcc_gp1_clk", 1566 - .parent_names = (const char *[]) { 1567 - "gp1_clk_src", 1568 - }, 1729 + .parent_hws = (const struct clk_hw *[]){ &gp1_clk_src.clkr.hw }, 1569 1730 .num_parents = 1, 1570 1731 .flags = CLK_SET_RATE_PARENT, 1571 1732 .ops = &clk_branch2_ops, ··· 1575 1742 .clkr = { 1576 1743 .enable_reg = 0x1940, 1577 1744 .enable_mask = BIT(0), 1578 - .hw.init = &(struct clk_init_data) 1579 - { 1745 + .hw.init = &(struct clk_init_data){ 1580 1746 .name = "gcc_gp2_clk", 1581 - .parent_names = (const char *[]) { 1582 - "gp2_clk_src", 1583 - }, 1747 + .parent_hws = (const struct clk_hw *[]){ &gp2_clk_src.clkr.hw }, 1584 1748 .num_parents = 1, 1585 1749 .flags = CLK_SET_RATE_PARENT, 1586 1750 .ops = &clk_branch2_ops, ··· 1590 1760 .clkr = { 1591 1761 .enable_reg = 0x1980, 1592 1762 .enable_mask = BIT(0), 1593 - .hw.init = &(struct clk_init_data) 1594 - { 1763 + .hw.init = &(struct clk_init_data){ 1595 1764 .name = "gcc_gp3_clk", 1596 - .parent_names = (const char *[]) { 1597 - "gp3_clk_src", 1598 - }, 1765 + .parent_hws = (const struct clk_hw *[]){ &gp3_clk_src.clkr.hw }, 1599 1766 .num_parents = 1, 1600 1767 .flags = CLK_SET_RATE_PARENT, 1601 1768 .ops = &clk_branch2_ops, ··· 1605 1778 .clkr = { 1606 1779 .enable_reg = 0x0280, 1607 1780 .enable_mask = BIT(0), 1608 - .hw.init = &(struct clk_init_data) 1609 - { 1781 + .hw.init = &(struct clk_init_data){ 1610 1782 .name = "gcc_lpass_q6_axi_clk", 1611 1783 .ops = &clk_branch2_ops, 1612 1784 }, ··· 1617 1791 .clkr = { 1618 1792 .enable_reg = 0x0284, 1619 1793 .enable_mask = BIT(0), 1620 - .hw.init = &(struct clk_init_data) 1621 - { 1794 + .hw.init = &(struct clk_init_data){ 1622 1795 .name = "gcc_mss_q6_bimc_axi_clk", 1623 1796 .ops = &clk_branch2_ops, 1624 1797 }, ··· 1629 1804 .clkr = { 1630 1805 .enable_reg = 0x1ad4, 1631 1806 .enable_mask = BIT(0), 1632 - .hw.init = &(struct clk_init_data) 1633 - { 1807 + .hw.init = &(struct clk_init_data){ 1634 1808 .name = "gcc_pcie_0_aux_clk", 1635 - .parent_names = (const char *[]) { 1636 - "pcie_0_aux_clk_src", 1637 - }, 1809 + .parent_hws = (const struct clk_hw *[]){ &pcie_0_aux_clk_src.clkr.hw }, 1638 1810 .num_parents = 1, 1639 1811 .flags = CLK_SET_RATE_PARENT, 1640 1812 .ops = &clk_branch2_ops, ··· 1644 1822 .clkr = { 1645 1823 .enable_reg = 0x1ad0, 1646 1824 .enable_mask = BIT(0), 1647 - .hw.init = &(struct clk_init_data) 1648 - { 1825 + .hw.init = &(struct clk_init_data){ 1649 1826 .name = "gcc_pcie_0_cfg_ahb_clk", 1650 1827 .ops = &clk_branch2_ops, 1651 1828 }, ··· 1656 1835 .clkr = { 1657 1836 .enable_reg = 0x1acc, 1658 1837 .enable_mask = BIT(0), 1659 - .hw.init = &(struct clk_init_data) 1660 - { 1838 + .hw.init = &(struct clk_init_data){ 1661 1839 .name = "gcc_pcie_0_mstr_axi_clk", 1662 1840 .ops = &clk_branch2_ops, 1663 1841 }, ··· 1669 1849 .clkr = { 1670 1850 .enable_reg = 0x1ad8, 1671 1851 .enable_mask = BIT(0), 1672 - .hw.init = &(struct clk_init_data) 1673 - { 1852 + .hw.init = &(struct clk_init_data){ 1674 1853 .name = "gcc_pcie_0_pipe_clk", 1675 - .parent_names = (const char *[]) { 1676 - "pcie_0_pipe_clk_src", 1677 - }, 1854 + .parent_hws = (const struct clk_hw *[]){ &pcie_0_pipe_clk_src.clkr.hw }, 1678 1855 .num_parents = 1, 1679 1856 .flags = CLK_SET_RATE_PARENT, 1680 1857 .ops = &clk_branch2_ops, ··· 1685 1868 .clkr = { 1686 1869 .enable_reg = 0x1ac8, 1687 1870 .enable_mask = BIT(0), 1688 - .hw.init = &(struct clk_init_data) 1689 - { 1871 + .hw.init = &(struct clk_init_data){ 1690 1872 .name = "gcc_pcie_0_slv_axi_clk", 1691 1873 .ops = &clk_branch2_ops, 1692 1874 }, ··· 1697 1881 .clkr = { 1698 1882 .enable_reg = 0x1b54, 1699 1883 .enable_mask = BIT(0), 1700 - .hw.init = &(struct clk_init_data) 1701 - { 1884 + .hw.init = &(struct clk_init_data){ 1702 1885 .name = "gcc_pcie_1_aux_clk", 1703 - .parent_names = (const char *[]) { 1704 - "pcie_1_aux_clk_src", 1705 - }, 1886 + .parent_hws = (const struct clk_hw *[]){ &pcie_1_aux_clk_src.clkr.hw }, 1706 1887 .num_parents = 1, 1707 1888 .flags = CLK_SET_RATE_PARENT, 1708 1889 .ops = &clk_branch2_ops, ··· 1712 1899 .clkr = { 1713 1900 .enable_reg = 0x1b54, 1714 1901 .enable_mask = BIT(0), 1715 - .hw.init = &(struct clk_init_data) 1716 - { 1902 + .hw.init = &(struct clk_init_data){ 1717 1903 .name = "gcc_pcie_1_cfg_ahb_clk", 1718 1904 .ops = &clk_branch2_ops, 1719 1905 }, ··· 1724 1912 .clkr = { 1725 1913 .enable_reg = 0x1b50, 1726 1914 .enable_mask = BIT(0), 1727 - .hw.init = &(struct clk_init_data) 1728 - { 1915 + .hw.init = &(struct clk_init_data){ 1729 1916 .name = "gcc_pcie_1_mstr_axi_clk", 1730 1917 .ops = &clk_branch2_ops, 1731 1918 }, ··· 1737 1926 .clkr = { 1738 1927 .enable_reg = 0x1b58, 1739 1928 .enable_mask = BIT(0), 1740 - .hw.init = &(struct clk_init_data) 1741 - { 1929 + .hw.init = &(struct clk_init_data){ 1742 1930 .name = "gcc_pcie_1_pipe_clk", 1743 - .parent_names = (const char *[]) { 1744 - "pcie_1_pipe_clk_src", 1745 - }, 1931 + .parent_hws = (const struct clk_hw *[]){ &pcie_1_pipe_clk_src.clkr.hw }, 1746 1932 .num_parents = 1, 1747 1933 .flags = CLK_SET_RATE_PARENT, 1748 1934 .ops = &clk_branch2_ops, ··· 1752 1944 .clkr = { 1753 1945 .enable_reg = 0x1b48, 1754 1946 .enable_mask = BIT(0), 1755 - .hw.init = &(struct clk_init_data) 1756 - { 1947 + .hw.init = &(struct clk_init_data){ 1757 1948 .name = "gcc_pcie_1_slv_axi_clk", 1758 1949 .ops = &clk_branch2_ops, 1759 1950 }, ··· 1764 1957 .clkr = { 1765 1958 .enable_reg = 0x0ccc, 1766 1959 .enable_mask = BIT(0), 1767 - .hw.init = &(struct clk_init_data) 1768 - { 1960 + .hw.init = &(struct clk_init_data){ 1769 1961 .name = "gcc_pdm2_clk", 1770 - .parent_names = (const char *[]) { 1771 - "pdm2_clk_src", 1772 - }, 1962 + .parent_hws = (const struct clk_hw *[]){ &pdm2_clk_src.clkr.hw }, 1773 1963 .num_parents = 1, 1774 1964 .flags = CLK_SET_RATE_PARENT, 1775 1965 .ops = &clk_branch2_ops, ··· 1779 1975 .clkr = { 1780 1976 .enable_reg = 0x0cc4, 1781 1977 .enable_mask = BIT(0), 1782 - .hw.init = &(struct clk_init_data) 1783 - { 1978 + .hw.init = &(struct clk_init_data){ 1784 1979 .name = "gcc_pdm_ahb_clk", 1785 1980 .ops = &clk_branch2_ops, 1786 1981 }, ··· 1791 1988 .clkr = { 1792 1989 .enable_reg = 0x04c4, 1793 1990 .enable_mask = BIT(0), 1794 - .hw.init = &(struct clk_init_data) 1795 - { 1991 + .hw.init = &(struct clk_init_data){ 1796 1992 .name = "gcc_sdcc1_apps_clk", 1797 - .parent_names = (const char *[]) { 1798 - "sdcc1_apps_clk_src", 1799 - }, 1993 + .parent_hws = (const struct clk_hw *[]){ &sdcc1_apps_clk_src.clkr.hw }, 1800 1994 .num_parents = 1, 1801 1995 .flags = CLK_SET_RATE_PARENT, 1802 1996 .ops = &clk_branch2_ops, ··· 1806 2006 .clkr = { 1807 2007 .enable_reg = 0x04c8, 1808 2008 .enable_mask = BIT(0), 1809 - .hw.init = &(struct clk_init_data) 1810 - { 2009 + .hw.init = &(struct clk_init_data){ 1811 2010 .name = "gcc_sdcc1_ahb_clk", 1812 2011 .parent_names = (const char *[]){ 1813 2012 "periph_noc_clk_src", ··· 1822 2023 .clkr = { 1823 2024 .enable_reg = 0x0508, 1824 2025 .enable_mask = BIT(0), 1825 - .hw.init = &(struct clk_init_data) 1826 - { 2026 + .hw.init = &(struct clk_init_data){ 1827 2027 .name = "gcc_sdcc2_ahb_clk", 1828 2028 .parent_names = (const char *[]){ 1829 2029 "periph_noc_clk_src", ··· 1838 2040 .clkr = { 1839 2041 .enable_reg = 0x0504, 1840 2042 .enable_mask = BIT(0), 1841 - .hw.init = &(struct clk_init_data) 1842 - { 2043 + .hw.init = &(struct clk_init_data){ 1843 2044 .name = "gcc_sdcc2_apps_clk", 1844 - .parent_names = (const char *[]) { 1845 - "sdcc2_apps_clk_src", 1846 - }, 2045 + .parent_hws = (const struct clk_hw *[]){ &sdcc2_apps_clk_src.clkr.hw }, 1847 2046 .num_parents = 1, 1848 2047 .flags = CLK_SET_RATE_PARENT, 1849 2048 .ops = &clk_branch2_ops, ··· 1853 2058 .clkr = { 1854 2059 .enable_reg = 0x0548, 1855 2060 .enable_mask = BIT(0), 1856 - .hw.init = &(struct clk_init_data) 1857 - { 2061 + .hw.init = &(struct clk_init_data){ 1858 2062 .name = "gcc_sdcc3_ahb_clk", 1859 2063 .parent_names = (const char *[]){ 1860 2064 "periph_noc_clk_src", ··· 1869 2075 .clkr = { 1870 2076 .enable_reg = 0x0544, 1871 2077 .enable_mask = BIT(0), 1872 - .hw.init = &(struct clk_init_data) 1873 - { 2078 + .hw.init = &(struct clk_init_data){ 1874 2079 .name = "gcc_sdcc3_apps_clk", 1875 - .parent_names = (const char *[]) { 1876 - "sdcc3_apps_clk_src", 1877 - }, 2080 + .parent_hws = (const struct clk_hw *[]){ &sdcc3_apps_clk_src.clkr.hw }, 1878 2081 .num_parents = 1, 1879 2082 .flags = CLK_SET_RATE_PARENT, 1880 2083 .ops = &clk_branch2_ops, ··· 1884 2093 .clkr = { 1885 2094 .enable_reg = 0x0588, 1886 2095 .enable_mask = BIT(0), 1887 - .hw.init = &(struct clk_init_data) 1888 - { 2096 + .hw.init = &(struct clk_init_data){ 1889 2097 .name = "gcc_sdcc4_ahb_clk", 1890 2098 .parent_names = (const char *[]){ 1891 2099 "periph_noc_clk_src", ··· 1900 2110 .clkr = { 1901 2111 .enable_reg = 0x0584, 1902 2112 .enable_mask = BIT(0), 1903 - .hw.init = &(struct clk_init_data) 1904 - { 2113 + .hw.init = &(struct clk_init_data){ 1905 2114 .name = "gcc_sdcc4_apps_clk", 1906 - .parent_names = (const char *[]) { 1907 - "sdcc4_apps_clk_src", 1908 - }, 2115 + .parent_hws = (const struct clk_hw *[]){ &sdcc4_apps_clk_src.clkr.hw }, 1909 2116 .num_parents = 1, 1910 2117 .flags = CLK_SET_RATE_PARENT, 1911 2118 .ops = &clk_branch2_ops, ··· 1915 2128 .clkr = { 1916 2129 .enable_reg = 0x1d7c, 1917 2130 .enable_mask = BIT(0), 1918 - .hw.init = &(struct clk_init_data) 1919 - { 2131 + .hw.init = &(struct clk_init_data){ 1920 2132 .name = "gcc_sys_noc_ufs_axi_clk", 1921 - .parent_names = (const char *[]) { 1922 - "ufs_axi_clk_src", 1923 - }, 2133 + .parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw }, 1924 2134 .num_parents = 1, 1925 2135 .flags = CLK_SET_RATE_PARENT, 1926 2136 .ops = &clk_branch2_ops, ··· 1930 2146 .clkr = { 1931 2147 .enable_reg = 0x03fc, 1932 2148 .enable_mask = BIT(0), 1933 - .hw.init = &(struct clk_init_data) 1934 - { 2149 + .hw.init = &(struct clk_init_data){ 1935 2150 .name = "gcc_sys_noc_usb3_axi_clk", 1936 - .parent_names = (const char *[]) { 1937 - "usb30_master_clk_src", 1938 - }, 2151 + .parent_hws = (const struct clk_hw *[]){ &usb30_master_clk_src.clkr.hw }, 1939 2152 .num_parents = 1, 1940 2153 .flags = CLK_SET_RATE_PARENT, 1941 2154 .ops = &clk_branch2_ops, ··· 1945 2164 .clkr = { 1946 2165 .enable_reg = 0x0d84, 1947 2166 .enable_mask = BIT(0), 1948 - .hw.init = &(struct clk_init_data) 1949 - { 2167 + .hw.init = &(struct clk_init_data){ 1950 2168 .name = "gcc_tsif_ahb_clk", 1951 2169 .ops = &clk_branch2_ops, 1952 2170 }, ··· 1957 2177 .clkr = { 1958 2178 .enable_reg = 0x0d88, 1959 2179 .enable_mask = BIT(0), 1960 - .hw.init = &(struct clk_init_data) 1961 - { 2180 + .hw.init = &(struct clk_init_data){ 1962 2181 .name = "gcc_tsif_ref_clk", 1963 - .parent_names = (const char *[]) { 1964 - "tsif_ref_clk_src", 1965 - }, 2182 + .parent_hws = (const struct clk_hw *[]){ &tsif_ref_clk_src.clkr.hw }, 1966 2183 .num_parents = 1, 1967 2184 .flags = CLK_SET_RATE_PARENT, 1968 2185 .ops = &clk_branch2_ops, ··· 1972 2195 .clkr = { 1973 2196 .enable_reg = 0x1d4c, 1974 2197 .enable_mask = BIT(0), 1975 - .hw.init = &(struct clk_init_data) 1976 - { 2198 + .hw.init = &(struct clk_init_data){ 1977 2199 .name = "gcc_ufs_ahb_clk", 1978 2200 .ops = &clk_branch2_ops, 1979 2201 }, ··· 1984 2208 .clkr = { 1985 2209 .enable_reg = 0x1d48, 1986 2210 .enable_mask = BIT(0), 1987 - .hw.init = &(struct clk_init_data) 1988 - { 2211 + .hw.init = &(struct clk_init_data){ 1989 2212 .name = "gcc_ufs_axi_clk", 1990 - .parent_names = (const char *[]) { 1991 - "ufs_axi_clk_src", 1992 - }, 2213 + .parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw }, 1993 2214 .num_parents = 1, 1994 2215 .flags = CLK_SET_RATE_PARENT, 1995 2216 .ops = &clk_branch2_ops, ··· 1999 2226 .clkr = { 2000 2227 .enable_reg = 0x1d54, 2001 2228 .enable_mask = BIT(0), 2002 - .hw.init = &(struct clk_init_data) 2003 - { 2229 + .hw.init = &(struct clk_init_data){ 2004 2230 .name = "gcc_ufs_rx_cfg_clk", 2005 - .parent_names = (const char *[]) { 2006 - "ufs_axi_clk_src", 2007 - }, 2231 + .parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw }, 2008 2232 .num_parents = 1, 2009 2233 .flags = CLK_SET_RATE_PARENT, 2010 2234 .ops = &clk_branch2_ops, ··· 2015 2245 .clkr = { 2016 2246 .enable_reg = 0x1d60, 2017 2247 .enable_mask = BIT(0), 2018 - .hw.init = &(struct clk_init_data) 2019 - { 2248 + .hw.init = &(struct clk_init_data){ 2020 2249 .name = "gcc_ufs_rx_symbol_0_clk", 2021 2250 .ops = &clk_branch2_ops, 2022 2251 }, ··· 2028 2259 .clkr = { 2029 2260 .enable_reg = 0x1d64, 2030 2261 .enable_mask = BIT(0), 2031 - .hw.init = &(struct clk_init_data) 2032 - { 2262 + .hw.init = &(struct clk_init_data){ 2033 2263 .name = "gcc_ufs_rx_symbol_1_clk", 2034 2264 .ops = &clk_branch2_ops, 2035 2265 }, ··· 2040 2272 .clkr = { 2041 2273 .enable_reg = 0x1d50, 2042 2274 .enable_mask = BIT(0), 2043 - .hw.init = &(struct clk_init_data) 2044 - { 2275 + .hw.init = &(struct clk_init_data){ 2045 2276 .name = "gcc_ufs_tx_cfg_clk", 2046 - .parent_names = (const char *[]) { 2047 - "ufs_axi_clk_src", 2048 - }, 2277 + .parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw }, 2049 2278 .num_parents = 1, 2050 2279 .flags = CLK_SET_RATE_PARENT, 2051 2280 .ops = &clk_branch2_ops, ··· 2056 2291 .clkr = { 2057 2292 .enable_reg = 0x1d58, 2058 2293 .enable_mask = BIT(0), 2059 - .hw.init = &(struct clk_init_data) 2060 - { 2294 + .hw.init = &(struct clk_init_data){ 2061 2295 .name = "gcc_ufs_tx_symbol_0_clk", 2062 2296 .ops = &clk_branch2_ops, 2063 2297 }, ··· 2069 2305 .clkr = { 2070 2306 .enable_reg = 0x1d5c, 2071 2307 .enable_mask = BIT(0), 2072 - .hw.init = &(struct clk_init_data) 2073 - { 2308 + .hw.init = &(struct clk_init_data){ 2074 2309 .name = "gcc_ufs_tx_symbol_1_clk", 2075 2310 .ops = &clk_branch2_ops, 2076 2311 }, ··· 2081 2318 .clkr = { 2082 2319 .enable_reg = 0x04ac, 2083 2320 .enable_mask = BIT(0), 2084 - .hw.init = &(struct clk_init_data) 2085 - { 2321 + .hw.init = &(struct clk_init_data){ 2086 2322 .name = "gcc_usb2_hs_phy_sleep_clk", 2323 + .parent_data = &(const struct clk_parent_data){ 2324 + .fw_name = "sleep", 2325 + .name = "sleep" 2326 + }, 2327 + .num_parents = 1, 2087 2328 .ops = &clk_branch2_ops, 2088 2329 }, 2089 2330 }, ··· 2098 2331 .clkr = { 2099 2332 .enable_reg = 0x03c8, 2100 2333 .enable_mask = BIT(0), 2101 - .hw.init = &(struct clk_init_data) 2102 - { 2334 + .hw.init = &(struct clk_init_data){ 2103 2335 .name = "gcc_usb30_master_clk", 2104 - .parent_names = (const char *[]) { 2105 - "usb30_master_clk_src", 2106 - }, 2336 + .parent_hws = (const struct clk_hw *[]){ &usb30_master_clk_src.clkr.hw }, 2107 2337 .num_parents = 1, 2108 2338 .flags = CLK_SET_RATE_PARENT, 2109 2339 .ops = &clk_branch2_ops, ··· 2113 2349 .clkr = { 2114 2350 .enable_reg = 0x03d0, 2115 2351 .enable_mask = BIT(0), 2116 - .hw.init = &(struct clk_init_data) 2117 - { 2352 + .hw.init = &(struct clk_init_data){ 2118 2353 .name = "gcc_usb30_mock_utmi_clk", 2119 - .parent_names = (const char *[]) { 2120 - "usb30_mock_utmi_clk_src", 2121 - }, 2354 + .parent_hws = (const struct clk_hw *[]){ &usb30_mock_utmi_clk_src.clkr.hw }, 2122 2355 .num_parents = 1, 2123 2356 .flags = CLK_SET_RATE_PARENT, 2124 2357 .ops = &clk_branch2_ops, ··· 2128 2367 .clkr = { 2129 2368 .enable_reg = 0x03cc, 2130 2369 .enable_mask = BIT(0), 2131 - .hw.init = &(struct clk_init_data) 2132 - { 2370 + .hw.init = &(struct clk_init_data){ 2133 2371 .name = "gcc_usb30_sleep_clk", 2372 + .parent_data = &(const struct clk_parent_data){ 2373 + .fw_name = "sleep", 2374 + .name = "sleep" 2375 + }, 2376 + .num_parents = 1, 2134 2377 .ops = &clk_branch2_ops, 2135 2378 }, 2136 2379 }, ··· 2145 2380 .clkr = { 2146 2381 .enable_reg = 0x1408, 2147 2382 .enable_mask = BIT(0), 2148 - .hw.init = &(struct clk_init_data) 2149 - { 2383 + .hw.init = &(struct clk_init_data){ 2150 2384 .name = "gcc_usb3_phy_aux_clk", 2151 - .parent_names = (const char *[]) { 2152 - "usb3_phy_aux_clk_src", 2153 - }, 2385 + .parent_hws = (const struct clk_hw *[]){ &usb3_phy_aux_clk_src.clkr.hw }, 2154 2386 .num_parents = 1, 2155 2387 .flags = CLK_SET_RATE_PARENT, 2156 2388 .ops = &clk_branch2_ops, ··· 2160 2398 .clkr = { 2161 2399 .enable_reg = 0x0488, 2162 2400 .enable_mask = BIT(0), 2163 - .hw.init = &(struct clk_init_data) 2164 - { 2401 + .hw.init = &(struct clk_init_data){ 2165 2402 .name = "gcc_usb_hs_ahb_clk", 2166 2403 .ops = &clk_branch2_ops, 2167 2404 }, ··· 2172 2411 .clkr = { 2173 2412 .enable_reg = 0x0484, 2174 2413 .enable_mask = BIT(0), 2175 - .hw.init = &(struct clk_init_data) 2176 - { 2414 + .hw.init = &(struct clk_init_data){ 2177 2415 .name = "gcc_usb_hs_system_clk", 2178 - .parent_names = (const char *[]) { 2179 - "usb_hs_system_clk_src", 2180 - }, 2416 + .parent_hws = (const struct clk_hw *[]){ &usb_hs_system_clk_src.clkr.hw }, 2181 2417 .num_parents = 1, 2182 2418 .flags = CLK_SET_RATE_PARENT, 2183 2419 .ops = &clk_branch2_ops, ··· 2187 2429 .clkr = { 2188 2430 .enable_reg = 0x1a84, 2189 2431 .enable_mask = BIT(0), 2190 - .hw.init = &(struct clk_init_data) 2191 - { 2432 + .hw.init = &(struct clk_init_data){ 2192 2433 .name = "gcc_usb_phy_cfg_ahb2phy_clk", 2193 2434 .ops = &clk_branch2_ops, 2194 2435 }, ··· 2420 2663 2421 2664 static int gcc_msm8994_probe(struct platform_device *pdev) 2422 2665 { 2423 - struct device *dev = &pdev->dev; 2424 - struct clk *clk; 2425 - 2426 - clk = devm_clk_register(dev, &xo.hw); 2427 - if (IS_ERR(clk)) 2428 - return PTR_ERR(clk); 2429 - 2430 2666 return qcom_cc_probe(pdev, &gcc_msm8994_desc); 2431 2667 } 2432 2668