drm/amd/display: Refactor DPG test pattern logic for ODM cases

+8

drivers/gpu/drm/amd/display/dc/core/dc.c

··· 3169 3169 BREAK_TO_DEBUGGER(); 3170 3170 goto fail; 3171 3171 } 3172 + 3173 + for (i = 0; i < context->stream_count; i++) { 3174 + struct pipe_ctx *otg_master = resource_get_otg_master_for_stream(&context->res_ctx, 3175 + context->streams[i]); 3176 + 3177 + if (otg_master->stream->test_pattern.type != DP_TEST_PATTERN_VIDEO_MODE) 3178 + resource_build_test_pattern_params(&context->res_ctx, otg_master); 3179 + } 3172 3180 } 3173 3181 3174 3182 *new_context = context;

+104

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

··· 1367 1367 return false; 1368 1368 } 1369 1369 1370 + static enum controller_dp_test_pattern convert_dp_to_controller_test_pattern( 1371 + enum dp_test_pattern test_pattern) 1372 + { 1373 + enum controller_dp_test_pattern controller_test_pattern; 1374 + 1375 + switch (test_pattern) { 1376 + case DP_TEST_PATTERN_COLOR_SQUARES: 1377 + controller_test_pattern = 1378 + CONTROLLER_DP_TEST_PATTERN_COLORSQUARES; 1379 + break; 1380 + case DP_TEST_PATTERN_COLOR_SQUARES_CEA: 1381 + controller_test_pattern = 1382 + CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA; 1383 + break; 1384 + case DP_TEST_PATTERN_VERTICAL_BARS: 1385 + controller_test_pattern = 1386 + CONTROLLER_DP_TEST_PATTERN_VERTICALBARS; 1387 + break; 1388 + case DP_TEST_PATTERN_HORIZONTAL_BARS: 1389 + controller_test_pattern = 1390 + CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS; 1391 + break; 1392 + case DP_TEST_PATTERN_COLOR_RAMP: 1393 + controller_test_pattern = 1394 + CONTROLLER_DP_TEST_PATTERN_COLORRAMP; 1395 + break; 1396 + default: 1397 + controller_test_pattern = 1398 + CONTROLLER_DP_TEST_PATTERN_VIDEOMODE; 1399 + break; 1400 + } 1401 + 1402 + return controller_test_pattern; 1403 + } 1404 + 1405 + static enum controller_dp_color_space convert_dp_to_controller_color_space( 1406 + enum dp_test_pattern_color_space color_space) 1407 + { 1408 + enum controller_dp_color_space controller_color_space; 1409 + 1410 + switch (color_space) { 1411 + case DP_TEST_PATTERN_COLOR_SPACE_RGB: 1412 + controller_color_space = CONTROLLER_DP_COLOR_SPACE_RGB; 1413 + break; 1414 + case DP_TEST_PATTERN_COLOR_SPACE_YCBCR601: 1415 + controller_color_space = CONTROLLER_DP_COLOR_SPACE_YCBCR601; 1416 + break; 1417 + case DP_TEST_PATTERN_COLOR_SPACE_YCBCR709: 1418 + controller_color_space = CONTROLLER_DP_COLOR_SPACE_YCBCR709; 1419 + break; 1420 + case DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED: 1421 + default: 1422 + controller_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED; 1423 + break; 1424 + } 1425 + 1426 + return controller_color_space; 1427 + } 1428 + 1429 + void resource_build_test_pattern_params(struct resource_context *res_ctx, 1430 + struct pipe_ctx *otg_master) 1431 + { 1432 + int odm_slice_width, last_odm_slice_width, offset = 0; 1433 + struct pipe_ctx *opp_heads[MAX_PIPES]; 1434 + struct test_pattern_params *params; 1435 + int odm_cnt = 1; 1436 + enum controller_dp_test_pattern controller_test_pattern; 1437 + enum controller_dp_color_space controller_color_space; 1438 + enum dc_color_depth color_depth = otg_master->stream->timing.display_color_depth; 1439 + int h_active = otg_master->stream->timing.h_addressable + 1440 + otg_master->stream->timing.h_border_left + 1441 + otg_master->stream->timing.h_border_right; 1442 + int v_active = otg_master->stream->timing.v_addressable + 1443 + otg_master->stream->timing.v_border_bottom + 1444 + otg_master->stream->timing.v_border_top; 1445 + int i; 1446 + 1447 + controller_test_pattern = convert_dp_to_controller_test_pattern( 1448 + otg_master->stream->test_pattern.type); 1449 + controller_color_space = convert_dp_to_controller_color_space( 1450 + otg_master->stream->test_pattern.color_space); 1451 + 1452 + odm_cnt = resource_get_opp_heads_for_otg_master(otg_master, res_ctx, opp_heads); 1453 + 1454 + odm_slice_width = h_active / odm_cnt; 1455 + last_odm_slice_width = h_active - odm_slice_width * (odm_cnt - 1); 1456 + 1457 + for (i = 0; i < odm_cnt; i++) { 1458 + params = &opp_heads[i]->stream_res.test_pattern_params; 1459 + params->test_pattern = controller_test_pattern; 1460 + params->color_space = controller_color_space; 1461 + params->color_depth = color_depth; 1462 + params->height = v_active; 1463 + params->offset = offset; 1464 + 1465 + if (i < odm_cnt - 1) 1466 + params->width = odm_slice_width; 1467 + else 1468 + params->width = last_odm_slice_width; 1469 + 1470 + offset += odm_slice_width; 1471 + } 1472 + } 1473 + 1370 1474 bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) 1371 1475 { 1372 1476 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;

+22

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

··· 1538 1538 1539 1539 if (old_pipe->unbounded_req != new_pipe->unbounded_req) 1540 1540 new_pipe->update_flags.bits.unbounded_req = 1; 1541 + 1542 + if (memcmp(&old_pipe->stream_res.test_pattern_params, 1543 + &new_pipe->stream_res.test_pattern_params, sizeof(struct test_pattern_params))) { 1544 + new_pipe->update_flags.bits.test_pattern_changed = 1; 1545 + } 1541 1546 } 1542 1547 1543 1548 static void dcn20_update_dchubp_dpp( ··· 1850 1845 pipe_ctx->stream_res.abm->funcs->set_abm_level(pipe_ctx->stream_res.abm, 1851 1846 pipe_ctx->stream->abm_level); 1852 1847 } 1848 + } 1849 + 1850 + if (pipe_ctx->update_flags.bits.test_pattern_changed) { 1851 + struct output_pixel_processor *odm_opp = pipe_ctx->stream_res.opp; 1852 + struct bit_depth_reduction_params params; 1853 + 1854 + memset(&params, 0, sizeof(params)); 1855 + odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, &params); 1856 + dc->hwss.set_disp_pattern_generator(dc, 1857 + pipe_ctx, 1858 + pipe_ctx->stream_res.test_pattern_params.test_pattern, 1859 + pipe_ctx->stream_res.test_pattern_params.color_space, 1860 + pipe_ctx->stream_res.test_pattern_params.color_depth, 1861 + NULL, 1862 + pipe_ctx->stream_res.test_pattern_params.width, 1863 + pipe_ctx->stream_res.test_pattern_params.height, 1864 + pipe_ctx->stream_res.test_pattern_params.offset); 1853 1865 } 1854 1866 } 1855 1867

+13

drivers/gpu/drm/amd/display/dc/inc/core_types.h

··· 308 308 309 309 }; 310 310 311 + /* Parameters needed to call set_disp_pattern_generator */ 312 + struct test_pattern_params { 313 + enum controller_dp_test_pattern test_pattern; 314 + enum controller_dp_color_space color_space; 315 + enum dc_color_depth color_depth; 316 + int width; 317 + int height; 318 + int offset; 319 + }; 320 + 311 321 struct stream_resource { 312 322 struct output_pixel_processor *opp; 313 323 struct display_stream_compressor *dsc; ··· 334 324 * otherwise it's using group number 'gsl_group-1' 335 325 */ 336 326 uint8_t gsl_group; 327 + 328 + struct test_pattern_params test_pattern_params; 337 329 }; 338 330 339 331 struct plane_resource { ··· 379 367 uint32_t plane_changed : 1; 380 368 uint32_t det_size : 1; 381 369 uint32_t unbounded_req : 1; 370 + uint32_t test_pattern_changed : 1; 382 371 } bits; 383 372 uint32_t raw; 384 373 };

+4

drivers/gpu/drm/amd/display/dc/inc/resource.h

··· 103 103 struct dc_state *context, 104 104 struct dc_stream_state *stream); 105 105 106 + void resource_build_test_pattern_params( 107 + struct resource_context *res_ctx, 108 + struct pipe_ctx *pipe_ctx); 109 + 106 110 bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx); 107 111 108 112 enum dc_status resource_build_scaling_params_for_context(

+24 -93

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

··· 429 429 struct bit_depth_reduction_params params; 430 430 struct output_pixel_processor *opp = pipe_ctx->stream_res.opp; 431 431 struct pipe_ctx *odm_pipe; 432 - int odm_cnt = 1; 433 - int h_active = pipe_ctx->stream->timing.h_addressable + 434 - pipe_ctx->stream->timing.h_border_left + 435 - pipe_ctx->stream->timing.h_border_right; 436 - int v_active = pipe_ctx->stream->timing.v_addressable + 437 - pipe_ctx->stream->timing.v_border_bottom + 438 - pipe_ctx->stream->timing.v_border_top; 439 - int odm_slice_width, last_odm_slice_width, offset = 0; 432 + struct test_pattern_params *tp_params; 440 433 441 434 memset(&params, 0, sizeof(params)); 442 435 443 - for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 444 - odm_cnt++; 445 - 446 - odm_slice_width = h_active / odm_cnt; 447 - last_odm_slice_width = h_active - odm_slice_width * (odm_cnt - 1); 448 - 449 - switch (test_pattern) { 450 - case DP_TEST_PATTERN_COLOR_SQUARES: 451 - controller_test_pattern = 452 - CONTROLLER_DP_TEST_PATTERN_COLORSQUARES; 453 - break; 454 - case DP_TEST_PATTERN_COLOR_SQUARES_CEA: 455 - controller_test_pattern = 456 - CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA; 457 - break; 458 - case DP_TEST_PATTERN_VERTICAL_BARS: 459 - controller_test_pattern = 460 - CONTROLLER_DP_TEST_PATTERN_VERTICALBARS; 461 - break; 462 - case DP_TEST_PATTERN_HORIZONTAL_BARS: 463 - controller_test_pattern = 464 - CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS; 465 - break; 466 - case DP_TEST_PATTERN_COLOR_RAMP: 467 - controller_test_pattern = 468 - CONTROLLER_DP_TEST_PATTERN_COLORRAMP; 469 - break; 470 - default: 471 - controller_test_pattern = 472 - CONTROLLER_DP_TEST_PATTERN_VIDEOMODE; 473 - break; 474 - } 436 + resource_build_test_pattern_params(&link->dc->current_state->res_ctx, 437 + pipe_ctx); 438 + controller_test_pattern = pipe_ctx->stream_res.test_pattern_params.test_pattern; 475 439 476 440 switch (test_pattern) { 477 441 case DP_TEST_PATTERN_COLOR_SQUARES: ··· 454 490 enum controller_dp_color_space controller_color_space; 455 491 struct output_pixel_processor *odm_opp; 456 492 457 - switch (test_pattern_color_space) { 458 - case DP_TEST_PATTERN_COLOR_SPACE_RGB: 459 - controller_color_space = CONTROLLER_DP_COLOR_SPACE_RGB; 460 - break; 461 - case DP_TEST_PATTERN_COLOR_SPACE_YCBCR601: 462 - controller_color_space = CONTROLLER_DP_COLOR_SPACE_YCBCR601; 463 - break; 464 - case DP_TEST_PATTERN_COLOR_SPACE_YCBCR709: 465 - controller_color_space = CONTROLLER_DP_COLOR_SPACE_YCBCR709; 466 - break; 467 - case DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED: 468 - default: 469 - controller_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED; 470 - DC_LOG_ERROR("%s: Color space must be defined for test pattern", __func__); 493 + controller_color_space = pipe_ctx->stream_res.test_pattern_params.color_space; 494 + 495 + if (controller_color_space == CONTROLLER_DP_COLOR_SPACE_UDEFINED) { 496 + DC_LOG_WARNING("%s: Color space must be defined for test pattern", __func__); 471 497 ASSERT(0); 472 - break; 473 498 } 474 499 475 500 odm_pipe = pipe_ctx; 476 - while (odm_pipe->next_odm_pipe) { 501 + while (odm_pipe) { 502 + tp_params = &odm_pipe->stream_res.test_pattern_params; 477 503 odm_opp = odm_pipe->stream_res.opp; 478 504 odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, &params); 479 505 link->dc->hwss.set_disp_pattern_generator(link->dc, 480 506 odm_pipe, 481 - controller_test_pattern, 482 - controller_color_space, 483 - color_depth, 507 + tp_params->test_pattern, 508 + tp_params->color_space, 509 + tp_params->color_depth, 484 510 NULL, 485 - odm_slice_width, 486 - v_active, 487 - offset); 488 - offset += odm_slice_width; 511 + tp_params->width, 512 + tp_params->height, 513 + tp_params->offset); 489 514 odm_pipe = odm_pipe->next_odm_pipe; 490 515 } 491 - odm_opp = odm_pipe->stream_res.opp; 492 - odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, &params); 493 - link->dc->hwss.set_disp_pattern_generator(link->dc, 494 - odm_pipe, 495 - controller_test_pattern, 496 - controller_color_space, 497 - color_depth, 498 - NULL, 499 - last_odm_slice_width, 500 - v_active, 501 - offset); 502 516 } 503 517 } 504 518 break; ··· 494 552 struct output_pixel_processor *odm_opp; 495 553 496 554 odm_pipe = pipe_ctx; 497 - while (odm_pipe->next_odm_pipe) { 555 + while (odm_pipe) { 556 + tp_params = &odm_pipe->stream_res.test_pattern_params; 498 557 odm_opp = odm_pipe->stream_res.opp; 499 558 odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, &params); 500 559 link->dc->hwss.set_disp_pattern_generator(link->dc, 501 560 odm_pipe, 502 - CONTROLLER_DP_TEST_PATTERN_VIDEOMODE, 503 - CONTROLLER_DP_COLOR_SPACE_UDEFINED, 504 - color_depth, 561 + tp_params->test_pattern, 562 + tp_params->color_space, 563 + tp_params->color_depth, 505 564 NULL, 506 - odm_slice_width, 507 - v_active, 508 - offset); 509 - offset += odm_slice_width; 565 + tp_params->width, 566 + tp_params->height, 567 + tp_params->offset); 510 568 odm_pipe = odm_pipe->next_odm_pipe; 511 569 } 512 - odm_opp = odm_pipe->stream_res.opp; 513 - odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, &params); 514 - link->dc->hwss.set_disp_pattern_generator(link->dc, 515 - odm_pipe, 516 - CONTROLLER_DP_TEST_PATTERN_VIDEOMODE, 517 - CONTROLLER_DP_COLOR_SPACE_UDEFINED, 518 - color_depth, 519 - NULL, 520 - last_odm_slice_width, 521 - v_active, 522 - offset); 523 570 } 524 571 } 525 572 break;

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