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phy: lynx-28g: configure more equalization params for 1GbE and 10GbE

While adding support for 25GbE, it was noticed that the RCCR0 and TTLCR0
registers have different values for this protocol than the 10GbE and
1GbE modes.

Expand the lynx_28g_proto_conf[] array with the expected values for the
currently supported protocols. These were dumped from a live system, and
are the out-of-reset values. It will ensure that the lane is configured
with these values when transitioning from 25GbE back into one of these
modes.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Link: https://patch.msgid.link/20251125114847.804961-14-vladimir.oltean@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Ioana Ciornei and committed by
Vinod Koul 055d08be 55ce1d64

+37
+37
drivers/phy/freescale/phy-fsl-lynx-28g.c
··· 166 166 #define LNaRECR4_EQ_BIN_DATA GENMASK(8, 0) /* bit 9 is reserved */ 167 167 #define LNaRECR4_EQ_BIN_DATA_SGN BIT(8) 168 168 169 + #define LNaRCCR0(lane) (0x800 + (lane) * 0x100 + 0x68) 170 + #define LNaRCCR0_CAL_EN BIT(31) 171 + #define LNaRCCR0_MEAS_EN BIT(30) 172 + #define LNaRCCR0_CAL_BIN_SEL BIT(28) 173 + #define LNaRCCR0_CAL_DC3_DIS BIT(27) 174 + #define LNaRCCR0_CAL_DC2_DIS BIT(26) 175 + #define LNaRCCR0_CAL_DC1_DIS BIT(25) 176 + #define LNaRCCR0_CAL_DC0_DIS BIT(24) 177 + #define LNaRCCR0_CAL_AC3_OV_EN BIT(15) 178 + #define LNaRCCR0_CAL_AC3_OV GENMASK(11, 8) 179 + #define LNaRCCR0_CAL_AC2_OV_EN BIT(7) 180 + 169 181 #define LNaRSCCR0(lane) (0x800 + (lane) * 0x100 + 0x74) 170 182 #define LNaRSCCR0_SMP_OFF_EN BIT(31) 171 183 #define LNaRSCCR0_SMP_OFF_OV_EN BIT(30) ··· 191 179 #define LNaRSCCR0_SMP_AUTOZ_D1F GENMASK(9, 8) 192 180 #define LNaRSCCR0_SMP_AUTOZ_EG1R GENMASK(5, 4) 193 181 #define LNaRSCCR0_SMP_AUTOZ_EG1F GENMASK(1, 0) 182 + 183 + #define LNaTTLCR0(lane) (0x800 + (lane) * 0x100 + 0x80) 184 + #define LNaTTLCR0_TTL_FLT_SEL GENMASK(29, 24) 185 + #define LNaTTLCR0_TTL_SLO_PM_BYP BIT(22) 186 + #define LNaTTLCR0_STALL_DET_DIS BIT(21) 187 + #define LNaTTLCR0_INACT_MON_DIS BIT(20) 188 + #define LNaTTLCR0_CDR_OV GENMASK(18, 16) 189 + #define LNaTTLCR0_DATA_IN_SSC BIT(15) 190 + #define LNaTTLCR0_CDR_MIN_SMP_ON GENMASK(1, 0) 194 191 195 192 #define LNaTCSR0(lane) (0x800 + (lane) * 0x100 + 0xa0) 196 193 #define LNaTCSR0_SD_STAT_OBS_EN BIT(31) ··· 307 286 /* LNaRSCCR0 */ 308 287 int smp_autoz_d1r; 309 288 int smp_autoz_eg1r; 289 + /* LNaRCCR0 */ 290 + int rccr0; 291 + /* LNaTTLCR0 */ 292 + int ttlcr0; 310 293 }; 311 294 312 295 static const struct lynx_28g_proto_conf lynx_28g_proto_conf[LANE_MODE_MAX] = { ··· 341 316 .spare_in = 0, 342 317 .smp_autoz_d1r = 0, 343 318 .smp_autoz_eg1r = 0, 319 + .rccr0 = LNaRCCR0_CAL_EN, 320 + .ttlcr0 = LNaTTLCR0_TTL_SLO_PM_BYP | 321 + LNaTTLCR0_DATA_IN_SSC, 344 322 }, 345 323 [LANE_MODE_USXGMII] = { 346 324 .proto_sel = LNaGCR0_PROTO_SEL_XFI, ··· 372 344 .spare_in = 0, 373 345 .smp_autoz_d1r = 2, 374 346 .smp_autoz_eg1r = 0, 347 + .rccr0 = LNaRCCR0_CAL_EN, 348 + .ttlcr0 = LNaTTLCR0_TTL_SLO_PM_BYP | 349 + LNaTTLCR0_DATA_IN_SSC, 375 350 }, 376 351 [LANE_MODE_10GBASER] = { 377 352 .proto_sel = LNaGCR0_PROTO_SEL_XFI, ··· 403 372 .spare_in = 0, 404 373 .smp_autoz_d1r = 2, 405 374 .smp_autoz_eg1r = 0, 375 + .rccr0 = LNaRCCR0_CAL_EN, 376 + .ttlcr0 = LNaTTLCR0_TTL_SLO_PM_BYP | 377 + LNaTTLCR0_DATA_IN_SSC, 406 378 }, 407 379 }; 408 380 ··· 863 829 FIELD_PREP(LNaRSCCR0_SMP_AUTOZ_EG1R, conf->smp_autoz_eg1r), 864 830 LNaRSCCR0_SMP_AUTOZ_D1R | 865 831 LNaRSCCR0_SMP_AUTOZ_EG1R); 832 + 833 + lynx_28g_lane_write(lane, LNaRCCR0, conf->rccr0); 834 + lynx_28g_lane_write(lane, LNaTTLCR0, conf->ttlcr0); 866 835 } 867 836 868 837 static int lynx_28g_lane_disable_pcvt(struct lynx_28g_lane *lane,