Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'i2c/for-current' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux
Pull i2c fixes from Wolfram Sang:
"Some driver bugfixes for the I2C subsystem"
* 'i2c/for-current' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux:
i2c: ismt: initialize DMA buffer
i2c: designware: 10-bit addressing mode enabling if I2C_DYNAMIC_TAR_UPDATE is set
i2c: mv64xxx: Do not use writel_relaxed()
i2c: mv64xxx: Fix some build warnings
i2c: s3c2410: fix clk_disable/clk_unprepare WARNings
+32
-15
+20
-6
drivers/i2c/busses/i2c-designware-core.c
+20
-6
drivers/i2c/busses/i2c-designware-core.c
···
98
98
99
99
#define DW_IC_ERR_TX_ABRT 0x1
100
100
101
+
#define DW_IC_TAR_10BITADDR_MASTER BIT(12)
102
+
101
103
/*
102
104
* status codes
103
105
*/
···
390
388
static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
391
389
{
392
390
struct i2c_msg *msgs = dev->msgs;
393
-
u32 ic_con;
391
+
u32 ic_con, ic_tar = 0;
394
392
395
393
/* Disable the adapter */
396
394
__i2c_dw_enable(dev, false);
397
395
398
-
/* set the slave (target) address */
399
-
dw_writel(dev, msgs[dev->msg_write_idx].addr, DW_IC_TAR);
400
-
401
396
/* if the slave address is ten bit address, enable 10BITADDR */
402
397
ic_con = dw_readl(dev, DW_IC_CON);
403
-
if (msgs[dev->msg_write_idx].flags & I2C_M_TEN)
398
+
if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) {
404
399
ic_con |= DW_IC_CON_10BITADDR_MASTER;
405
-
else
400
+
/*
401
+
* If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing
402
+
* mode has to be enabled via bit 12 of IC_TAR register.
403
+
* We set it always as I2C_DYNAMIC_TAR_UPDATE can't be
404
+
* detected from registers.
405
+
*/
406
+
ic_tar = DW_IC_TAR_10BITADDR_MASTER;
407
+
} else {
406
408
ic_con &= ~DW_IC_CON_10BITADDR_MASTER;
409
+
}
410
+
407
411
dw_writel(dev, ic_con, DW_IC_CON);
412
+
413
+
/*
414
+
* Set the slave (target) address and enable 10-bit addressing mode
415
+
* if applicable.
416
+
*/
417
+
dw_writel(dev, msgs[dev->msg_write_idx].addr | ic_tar, DW_IC_TAR);
408
418
409
419
/* Enable the adapter */
410
420
__i2c_dw_enable(dev, true);
+3
drivers/i2c/busses/i2c-ismt.c
+3
drivers/i2c/busses/i2c-ismt.c
···
393
393
394
394
desc = &priv->hw[priv->head];
395
395
396
+
/* Initialize the DMA buffer */
397
+
memset(priv->dma_buffer, 0, sizeof(priv->dma_buffer));
398
+
396
399
/* Initialize the descriptor */
397
400
memset(desc, 0, sizeof(struct ismt_desc));
398
401
desc->tgtaddr_rw = ISMT_DESC_ADDR_RW(addr, read_write);
+9
-7
drivers/i2c/busses/i2c-mv64xxx.c
+9
-7
drivers/i2c/busses/i2c-mv64xxx.c
···
234
234
ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_WR |
235
235
(msg->len - 1) << MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT;
236
236
237
-
writel_relaxed(data_reg_lo,
237
+
writel(data_reg_lo,
238
238
drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_LO);
239
-
writel_relaxed(data_reg_hi,
239
+
writel(data_reg_hi,
240
240
drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_HI);
241
241
242
242
} else {
···
697
697
MODULE_DEVICE_TABLE(of, mv64xxx_i2c_of_match_table);
698
698
699
699
#ifdef CONFIG_OF
700
+
#ifdef CONFIG_HAVE_CLK
700
701
static int
701
702
mv64xxx_calc_freq(const int tclk, const int n, const int m)
702
703
{
···
727
726
return false;
728
727
return true;
729
728
}
729
+
#endif /* CONFIG_HAVE_CLK */
730
730
731
731
static int
732
732
mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data,
733
733
struct device *dev)
734
734
{
735
-
const struct of_device_id *device;
736
-
struct device_node *np = dev->of_node;
737
-
u32 bus_freq, tclk;
738
-
int rc = 0;
739
-
740
735
/* CLK is mandatory when using DT to describe the i2c bus. We
741
736
* need to know tclk in order to calculate bus clock
742
737
* factors.
···
741
744
/* Have OF but no CLK */
742
745
return -ENODEV;
743
746
#else
747
+
const struct of_device_id *device;
748
+
struct device_node *np = dev->of_node;
749
+
u32 bus_freq, tclk;
750
+
int rc = 0;
751
+
744
752
if (IS_ERR(drv_data->clk)) {
745
753
rc = -ENODEV;
746
754
goto out;