tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'drm-fixes-2020-12-11' of git://anongit.freedesktop.org/drm/drm

Pull drm fixes from Dave Airlie:
"Last week of fixes, just amdgpu and i915 collections. We had a i915
regression reported by HJ Lu reported this morning, and this contains
a fix for that he has tested.

There are a fair few other fixes, but they are spread across the two
drivers, and all fairly self contained.

amdgpu:
- Fan fix for CI asics
- Fix a warning in possible_crtcs
- Build fix for when debugfs is disabled
- Display overflow fix
- Display watermark fixes for Renoir
- SDMA 5.2 fix
- Stolen vga memory regression fix
- Power profile fixes
- Fix a regression from removal of GEM and PRIME callbacks

amdkfd:
- Fix a memory leak in dmabuf import

i915:
- rc7 regression fix for modesetting
- vdsc/dp slice fixes
- gen9 mocs entries fix
- preemption timeout fix
- unsigned compare against 0 fix
- selftest fix
- submission error propogatig fix
- request flow suspend fix"

* tag 'drm-fixes-2020-12-11' of git://anongit.freedesktop.org/drm/drm:
drm/i915/display: Go softly softly on initial modeset failure
drm/amd/pm: typo fix (CUSTOM -> COMPUTE)
drm/amdgpu: Initialise drm_gem_object_funcs for imported BOs
drm/amdgpu: fix size calculation with stolen vga memory
drm/amd/pm: update smu10.h WORKLOAD_PPLIB setting for raven
drm/amdkfd: Fix leak in dmabuf import
drm/amdgpu: fix sdma instance fw version and feature version init
drm/amd/display: Add wm table for Renoir
drm/amd/display: Prevent bandwidth overflow
drm/amdgpu: fix debugfs creation/removal, again
drm/amdgpu/disply: set num_crtc earlier
drm/amdgpu/powerplay: parse fan table for CI asics
drm/i915/gt: Declare gen9 has 64 mocs entries!
drm/i915/display/dp: Compute the correct slice count for VDSC on DP
drm/i915: fix size_t greater or equal to zero comparison
drm/i915/gt: Cancel the preemption timeout on responding to it
drm/i915/gt: Ignore repeated attempts to suspend request flow across reset
drm/i915/gem: Propagate error from cancelled submit due to context closure
drm/i915/gem: Check the correct variable in selftest

Linus Torvalds 059fe829 33dc9614

+269 -74
+6 -2
drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
··· 459 459 struct amdgpu_device *adev = drm_to_adev(dev); 460 460 struct amdgpu_bo *bo; 461 461 struct amdgpu_bo_param bp; 462 + struct drm_gem_object *gobj; 462 463 int ret; 463 464 464 465 memset(&bp, 0, sizeof(bp)); ··· 470 469 bp.type = ttm_bo_type_sg; 471 470 bp.resv = resv; 472 471 dma_resv_lock(resv, NULL); 473 - ret = amdgpu_bo_create(adev, &bp, &bo); 472 + ret = amdgpu_gem_object_create(adev, dma_buf->size, PAGE_SIZE, 473 + AMDGPU_GEM_DOMAIN_CPU, 474 + 0, ttm_bo_type_sg, resv, &gobj); 474 475 if (ret) 475 476 goto error; 476 477 478 + bo = gem_to_amdgpu_bo(gobj); 477 479 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT; 478 480 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT; 479 481 if (dma_buf->ops != &amdgpu_dmabuf_ops) 480 482 bo->prime_shared_count = 1; 481 483 482 484 dma_resv_unlock(resv); 483 - return &bo->tbo.base; 485 + return gobj; 484 486 485 487 error: 486 488 dma_resv_unlock(resv);
+23 -18
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
··· 66 66 bp.type = type; 67 67 bp.resv = resv; 68 68 bp.preferred_domain = initial_domain; 69 - retry: 70 69 bp.flags = flags; 71 70 bp.domain = initial_domain; 72 71 r = amdgpu_bo_create(adev, &bp, &bo); 73 - if (r) { 74 - if (r != -ERESTARTSYS) { 75 - if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) { 76 - flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 77 - goto retry; 78 - } 79 - 80 - if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) { 81 - initial_domain |= AMDGPU_GEM_DOMAIN_GTT; 82 - goto retry; 83 - } 84 - DRM_DEBUG("Failed to allocate GEM object (%ld, %d, %u, %d)\n", 85 - size, initial_domain, alignment, r); 86 - } 72 + if (r) 87 73 return r; 88 - } 74 + 89 75 *obj = &bo->tbo.base; 90 76 91 77 return 0; ··· 211 225 uint64_t size = args->in.bo_size; 212 226 struct dma_resv *resv = NULL; 213 227 struct drm_gem_object *gobj; 214 - uint32_t handle; 228 + uint32_t handle, initial_domain; 215 229 int r; 216 230 217 231 /* reject invalid gem flags */ ··· 255 269 resv = vm->root.base.bo->tbo.base.resv; 256 270 } 257 271 272 + retry: 273 + initial_domain = (u32)(0xffffffff & args->in.domains); 258 274 r = amdgpu_gem_object_create(adev, size, args->in.alignment, 259 - (u32)(0xffffffff & args->in.domains), 275 + initial_domain, 260 276 flags, ttm_bo_type_device, resv, &gobj); 277 + if (r) { 278 + if (r != -ERESTARTSYS) { 279 + if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) { 280 + flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 281 + goto retry; 282 + } 283 + 284 + if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) { 285 + initial_domain |= AMDGPU_GEM_DOMAIN_GTT; 286 + goto retry; 287 + } 288 + DRM_DEBUG("Failed to allocate GEM object (%llu, %d, %llu, %d)\n", 289 + size, initial_domain, args->in.alignment, r); 290 + } 291 + return r; 292 + } 293 + 261 294 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { 262 295 if (!r) { 263 296 struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
+3
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
··· 499 499 else 500 500 size = amdgpu_gmc_get_vbios_fb_size(adev); 501 501 502 + if (adev->mman.keep_stolen_vga_memory) 503 + size = max(size, (unsigned)AMDGPU_VBIOS_VGA_ALLOCATION); 504 + 502 505 /* set to 0 if the pre-OS buffer uses up most of vram */ 503 506 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024)) 504 507 size = 0;
+5 -8
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
··· 1172 1172 con->dir, &con->disable_ras_err_cnt_harvest); 1173 1173 } 1174 1174 1175 - void amdgpu_ras_debugfs_create(struct amdgpu_device *adev, 1175 + static void amdgpu_ras_debugfs_create(struct amdgpu_device *adev, 1176 1176 struct ras_fs_if *head) 1177 1177 { 1178 1178 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); ··· 1194 1194 1195 1195 void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev) 1196 1196 { 1197 - #if defined(CONFIG_DEBUG_FS) 1198 1197 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 1199 1198 struct ras_manager *obj; 1200 1199 struct ras_fs_if fs_info; ··· 1202 1203 * it won't be called in resume path, no need to check 1203 1204 * suspend and gpu reset status 1204 1205 */ 1205 - if (!con) 1206 + if (!IS_ENABLED(CONFIG_DEBUG_FS) || !con) 1206 1207 return; 1207 1208 1208 1209 amdgpu_ras_debugfs_create_ctrl_node(adev); ··· 1216 1217 amdgpu_ras_debugfs_create(adev, &fs_info); 1217 1218 } 1218 1219 } 1219 - #endif 1220 1220 } 1221 1221 1222 - void amdgpu_ras_debugfs_remove(struct amdgpu_device *adev, 1222 + static void amdgpu_ras_debugfs_remove(struct amdgpu_device *adev, 1223 1223 struct ras_common_if *head) 1224 1224 { 1225 1225 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); ··· 1232 1234 1233 1235 static void amdgpu_ras_debugfs_remove_all(struct amdgpu_device *adev) 1234 1236 { 1235 - #if defined(CONFIG_DEBUG_FS) 1236 1237 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 1237 1238 struct ras_manager *obj, *tmp; 1238 1239 ··· 1240 1243 } 1241 1244 1242 1245 con->dir = NULL; 1243 - #endif 1244 1246 } 1245 1247 /* debugfs end */ 1246 1248 ··· 1287 1291 1288 1292 static int amdgpu_ras_fs_fini(struct amdgpu_device *adev) 1289 1293 { 1290 - amdgpu_ras_debugfs_remove_all(adev); 1294 + if (IS_ENABLED(CONFIG_DEBUG_FS)) 1295 + amdgpu_ras_debugfs_remove_all(adev); 1291 1296 amdgpu_ras_sysfs_remove_all(adev); 1292 1297 return 0; 1293 1298 }
-6
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
··· 607 607 int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev, 608 608 struct ras_common_if *head); 609 609 610 - void amdgpu_ras_debugfs_create(struct amdgpu_device *adev, 611 - struct ras_fs_if *head); 612 - 613 610 void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev); 614 - 615 - void amdgpu_ras_debugfs_remove(struct amdgpu_device *adev, 616 - struct ras_common_if *head); 617 611 618 612 int amdgpu_ras_error_query(struct amdgpu_device *adev, 619 613 struct ras_query_if *info);
+1 -1
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
··· 186 186 if (err) 187 187 goto out; 188 188 189 - err = sdma_v5_2_init_inst_ctx(&adev->sdma.instance[0]); 189 + err = sdma_v5_2_init_inst_ctx(&adev->sdma.instance[i]); 190 190 if (err) 191 191 goto out; 192 192 }
+2
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
··· 1736 1736 } 1737 1737 1738 1738 mutex_unlock(&p->mutex); 1739 + dma_buf_put(dmabuf); 1739 1740 1740 1741 args->handle = MAKE_HANDLE(args->gpu_id, idr_handle); 1741 1742 ··· 1746 1745 amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->kgd, (struct kgd_mem *)mem, NULL); 1747 1746 err_unlock: 1748 1747 mutex_unlock(&p->mutex); 1748 + dma_buf_put(dmabuf); 1749 1749 return r; 1750 1750 } 1751 1751
+4 -5
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
··· 1058 1058 goto error; 1059 1059 } 1060 1060 1061 - /* Update the actual used number of crtc */ 1062 - adev->mode_info.num_crtc = adev->dm.display_indexes_num; 1063 - 1064 1061 /* create fake encoders for MST */ 1065 1062 dm_dp_create_fake_mst_encoders(adev); 1066 1063 ··· 3248 3251 enum dc_connection_type new_connection_type = dc_connection_none; 3249 3252 const struct dc_plane_cap *plane; 3250 3253 3254 + dm->display_indexes_num = dm->dc->caps.max_streams; 3255 + /* Update the actual used number of crtc */ 3256 + adev->mode_info.num_crtc = adev->dm.display_indexes_num; 3257 + 3251 3258 link_cnt = dm->dc->caps.max_links; 3252 3259 if (amdgpu_dm_mode_config_init(dm->adev)) { 3253 3260 DRM_ERROR("DM: Failed to initialize mode config\n"); ··· 3312 3311 DRM_ERROR("KMS: Failed to initialize crtc\n"); 3313 3312 goto fail; 3314 3313 } 3315 - 3316 - dm->display_indexes_num = dm->dc->caps.max_streams; 3317 3314 3318 3315 /* loops over all connectors on the board */ 3319 3316 for (i = 0; i < link_cnt; i++) {
+89 -4
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
··· 579 579 580 580 }; 581 581 582 - static struct wm_table ddr4_wm_table = { 582 + static struct wm_table ddr4_wm_table_gs = { 583 583 .entries = { 584 584 { 585 585 .wm_inst = WM_A, ··· 616 616 } 617 617 }; 618 618 619 - static struct wm_table lpddr4_wm_table = { 619 + static struct wm_table lpddr4_wm_table_gs = { 620 620 .entries = { 621 621 { 622 622 .wm_inst = WM_A, ··· 661 661 .pstate_latency_us = 11.65333, 662 662 .sr_exit_time_us = 8.32, 663 663 .sr_enter_plus_exit_time_us = 9.38, 664 + .valid = true, 665 + }, 666 + { 667 + .wm_inst = WM_B, 668 + .wm_type = WM_TYPE_PSTATE_CHG, 669 + .pstate_latency_us = 11.65333, 670 + .sr_exit_time_us = 9.82, 671 + .sr_enter_plus_exit_time_us = 11.196, 672 + .valid = true, 673 + }, 674 + { 675 + .wm_inst = WM_C, 676 + .wm_type = WM_TYPE_PSTATE_CHG, 677 + .pstate_latency_us = 11.65333, 678 + .sr_exit_time_us = 9.89, 679 + .sr_enter_plus_exit_time_us = 11.24, 680 + .valid = true, 681 + }, 682 + { 683 + .wm_inst = WM_D, 684 + .wm_type = WM_TYPE_PSTATE_CHG, 685 + .pstate_latency_us = 11.65333, 686 + .sr_exit_time_us = 9.748, 687 + .sr_enter_plus_exit_time_us = 11.102, 688 + .valid = true, 689 + }, 690 + } 691 + }; 692 + 693 + static struct wm_table ddr4_wm_table_rn = { 694 + .entries = { 695 + { 696 + .wm_inst = WM_A, 697 + .wm_type = WM_TYPE_PSTATE_CHG, 698 + .pstate_latency_us = 11.72, 699 + .sr_exit_time_us = 9.09, 700 + .sr_enter_plus_exit_time_us = 10.14, 701 + .valid = true, 702 + }, 703 + { 704 + .wm_inst = WM_B, 705 + .wm_type = WM_TYPE_PSTATE_CHG, 706 + .pstate_latency_us = 11.72, 707 + .sr_exit_time_us = 10.12, 708 + .sr_enter_plus_exit_time_us = 11.48, 709 + .valid = true, 710 + }, 711 + { 712 + .wm_inst = WM_C, 713 + .wm_type = WM_TYPE_PSTATE_CHG, 714 + .pstate_latency_us = 11.72, 715 + .sr_exit_time_us = 10.12, 716 + .sr_enter_plus_exit_time_us = 11.48, 717 + .valid = true, 718 + }, 719 + { 720 + .wm_inst = WM_D, 721 + .wm_type = WM_TYPE_PSTATE_CHG, 722 + .pstate_latency_us = 11.72, 723 + .sr_exit_time_us = 10.12, 724 + .sr_enter_plus_exit_time_us = 11.48, 725 + .valid = true, 726 + }, 727 + } 728 + }; 729 + 730 + static struct wm_table lpddr4_wm_table_rn = { 731 + .entries = { 732 + { 733 + .wm_inst = WM_A, 734 + .wm_type = WM_TYPE_PSTATE_CHG, 735 + .pstate_latency_us = 11.65333, 736 + .sr_exit_time_us = 7.32, 737 + .sr_enter_plus_exit_time_us = 8.38, 664 738 .valid = true, 665 739 }, 666 740 { ··· 845 771 struct dc_debug_options *debug = &ctx->dc->debug; 846 772 struct dpm_clocks clock_table = { 0 }; 847 773 enum pp_smu_status status = 0; 774 + int is_green_sardine = 0; 775 + 776 + #if defined(CONFIG_DRM_AMD_DC_DCN) 777 + is_green_sardine = ASICREV_IS_GREEN_SARDINE(ctx->asic_id.hw_internal_rev); 778 + #endif 848 779 849 780 clk_mgr->base.ctx = ctx; 850 781 clk_mgr->base.funcs = &dcn21_funcs; ··· 890 811 if (clk_mgr->periodic_retraining_disabled) { 891 812 rn_bw_params.wm_table = lpddr4_wm_table_with_disabled_ppt; 892 813 } else { 893 - rn_bw_params.wm_table = lpddr4_wm_table; 814 + if (is_green_sardine) 815 + rn_bw_params.wm_table = lpddr4_wm_table_gs; 816 + else 817 + rn_bw_params.wm_table = lpddr4_wm_table_rn; 894 818 } 895 819 } else { 896 - rn_bw_params.wm_table = ddr4_wm_table; 820 + if (is_green_sardine) 821 + rn_bw_params.wm_table = ddr4_wm_table_gs; 822 + else 823 + rn_bw_params.wm_table = ddr4_wm_table_rn; 897 824 } 898 825 /* Saved clocks configured at boot for debug purposes */ 899 826 rn_dump_clk_registers(&clk_mgr->base.boot_snapshot, &clk_mgr->base, &log_info);
+5 -2
drivers/gpu/drm/amd/display/dc/core/dc_link.c
··· 3394 3394 { 3395 3395 uint32_t bits_per_channel = 0; 3396 3396 uint32_t kbps; 3397 + struct fixed31_32 link_bw_kbps; 3397 3398 3398 3399 if (timing->flags.DSC) { 3399 - kbps = (timing->pix_clk_100hz * timing->dsc_cfg.bits_per_pixel); 3400 - kbps = kbps / 160 + ((kbps % 160) ? 1 : 0); 3400 + link_bw_kbps = dc_fixpt_from_int(timing->pix_clk_100hz); 3401 + link_bw_kbps = dc_fixpt_div_int(link_bw_kbps, 160); 3402 + link_bw_kbps = dc_fixpt_mul_int(link_bw_kbps, timing->dsc_cfg.bits_per_pixel); 3403 + kbps = dc_fixpt_ceil(link_bw_kbps); 3401 3404 return kbps; 3402 3405 } 3403 3406
+6 -8
drivers/gpu/drm/amd/pm/inc/smu10.h
··· 136 136 #define FEATURE_CORE_CSTATES_MASK (1 << FEATURE_CORE_CSTATES_BIT) 137 137 138 138 /* Workload bits */ 139 - #define WORKLOAD_DEFAULT_BIT 0 140 - #define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 1 141 - #define WORKLOAD_PPLIB_POWER_SAVING_BIT 2 142 - #define WORKLOAD_PPLIB_VIDEO_BIT 3 143 - #define WORKLOAD_PPLIB_VR_BIT 4 144 - #define WORKLOAD_PPLIB_COMPUTE_BIT 5 145 - #define WORKLOAD_PPLIB_CUSTOM_BIT 6 146 - #define WORKLOAD_PPLIB_COUNT 7 139 + #define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 0 140 + #define WORKLOAD_PPLIB_VIDEO_BIT 2 141 + #define WORKLOAD_PPLIB_VR_BIT 3 142 + #define WORKLOAD_PPLIB_COMPUTE_BIT 4 143 + #define WORKLOAD_PPLIB_CUSTOM_BIT 5 144 + #define WORKLOAD_PPLIB_COUNT 6 147 145 148 146 typedef struct { 149 147 /* MP1_EXT_SCRATCH0 */
+102 -1
drivers/gpu/drm/amd/pm/powerplay/hwmgr/processpptables.c
··· 24 24 #include <linux/types.h> 25 25 #include <linux/kernel.h> 26 26 #include <linux/slab.h> 27 + #include <linux/pci.h> 28 + 27 29 #include <drm/amdgpu_drm.h> 28 30 #include "processpptables.h" 29 31 #include <atom-types.h> ··· 986 984 struct pp_hwmgr *hwmgr, 987 985 const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table) 988 986 { 987 + struct amdgpu_device *adev = hwmgr->adev; 988 + 989 989 hwmgr->thermal_controller.ucType = 990 990 powerplay_table->sThermalController.ucType; 991 991 hwmgr->thermal_controller.ucI2cLine = ··· 1012 1008 ATOM_PP_THERMALCONTROLLER_NONE != hwmgr->thermal_controller.ucType, 1013 1009 PHM_PlatformCaps_ThermalController); 1014 1010 1015 - hwmgr->thermal_controller.use_hw_fan_control = 1; 1011 + if (powerplay_table->usTableSize >= sizeof(ATOM_PPLIB_POWERPLAYTABLE3)) { 1012 + const ATOM_PPLIB_POWERPLAYTABLE3 *powerplay_table3 = 1013 + (const ATOM_PPLIB_POWERPLAYTABLE3 *)powerplay_table; 1014 + 1015 + if (0 == le16_to_cpu(powerplay_table3->usFanTableOffset)) { 1016 + hwmgr->thermal_controller.use_hw_fan_control = 1; 1017 + return 0; 1018 + } else { 1019 + const ATOM_PPLIB_FANTABLE *fan_table = 1020 + (const ATOM_PPLIB_FANTABLE *)(((unsigned long)powerplay_table) + 1021 + le16_to_cpu(powerplay_table3->usFanTableOffset)); 1022 + 1023 + if (1 <= fan_table->ucFanTableFormat) { 1024 + hwmgr->thermal_controller.advanceFanControlParameters.ucTHyst = 1025 + fan_table->ucTHyst; 1026 + hwmgr->thermal_controller.advanceFanControlParameters.usTMin = 1027 + le16_to_cpu(fan_table->usTMin); 1028 + hwmgr->thermal_controller.advanceFanControlParameters.usTMed = 1029 + le16_to_cpu(fan_table->usTMed); 1030 + hwmgr->thermal_controller.advanceFanControlParameters.usTHigh = 1031 + le16_to_cpu(fan_table->usTHigh); 1032 + hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin = 1033 + le16_to_cpu(fan_table->usPWMMin); 1034 + hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed = 1035 + le16_to_cpu(fan_table->usPWMMed); 1036 + hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh = 1037 + le16_to_cpu(fan_table->usPWMHigh); 1038 + hwmgr->thermal_controller.advanceFanControlParameters.usTMax = 10900; 1039 + hwmgr->thermal_controller.advanceFanControlParameters.ulCycleDelay = 100000; 1040 + 1041 + phm_cap_set(hwmgr->platform_descriptor.platformCaps, 1042 + PHM_PlatformCaps_MicrocodeFanControl); 1043 + } 1044 + 1045 + if (2 <= fan_table->ucFanTableFormat) { 1046 + const ATOM_PPLIB_FANTABLE2 *fan_table2 = 1047 + (const ATOM_PPLIB_FANTABLE2 *)(((unsigned long)powerplay_table) + 1048 + le16_to_cpu(powerplay_table3->usFanTableOffset)); 1049 + hwmgr->thermal_controller.advanceFanControlParameters.usTMax = 1050 + le16_to_cpu(fan_table2->usTMax); 1051 + } 1052 + 1053 + if (3 <= fan_table->ucFanTableFormat) { 1054 + const ATOM_PPLIB_FANTABLE3 *fan_table3 = 1055 + (const ATOM_PPLIB_FANTABLE3 *) (((unsigned long)powerplay_table) + 1056 + le16_to_cpu(powerplay_table3->usFanTableOffset)); 1057 + 1058 + hwmgr->thermal_controller.advanceFanControlParameters.ucFanControlMode = 1059 + fan_table3->ucFanControlMode; 1060 + 1061 + if ((3 == fan_table->ucFanTableFormat) && 1062 + (0x67B1 == adev->pdev->device)) 1063 + hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM = 1064 + 47; 1065 + else 1066 + hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM = 1067 + le16_to_cpu(fan_table3->usFanPWMMax); 1068 + 1069 + hwmgr->thermal_controller.advanceFanControlParameters.usDefaultFanOutputSensitivity = 1070 + 4836; 1071 + hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity = 1072 + le16_to_cpu(fan_table3->usFanOutputSensitivity); 1073 + } 1074 + 1075 + if (6 <= fan_table->ucFanTableFormat) { 1076 + const ATOM_PPLIB_FANTABLE4 *fan_table4 = 1077 + (const ATOM_PPLIB_FANTABLE4 *)(((unsigned long)powerplay_table) + 1078 + le16_to_cpu(powerplay_table3->usFanTableOffset)); 1079 + 1080 + phm_cap_set(hwmgr->platform_descriptor.platformCaps, 1081 + PHM_PlatformCaps_FanSpeedInTableIsRPM); 1082 + 1083 + hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM = 1084 + le16_to_cpu(fan_table4->usFanRPMMax); 1085 + } 1086 + 1087 + if (7 <= fan_table->ucFanTableFormat) { 1088 + const ATOM_PPLIB_FANTABLE5 *fan_table5 = 1089 + (const ATOM_PPLIB_FANTABLE5 *)(((unsigned long)powerplay_table) + 1090 + le16_to_cpu(powerplay_table3->usFanTableOffset)); 1091 + 1092 + if (0x67A2 == adev->pdev->device || 1093 + 0x67A9 == adev->pdev->device || 1094 + 0x67B9 == adev->pdev->device) { 1095 + phm_cap_set(hwmgr->platform_descriptor.platformCaps, 1096 + PHM_PlatformCaps_GeminiRegulatorFanControlSupport); 1097 + hwmgr->thermal_controller.advanceFanControlParameters.usFanCurrentLow = 1098 + le16_to_cpu(fan_table5->usFanCurrentLow); 1099 + hwmgr->thermal_controller.advanceFanControlParameters.usFanCurrentHigh = 1100 + le16_to_cpu(fan_table5->usFanCurrentHigh); 1101 + hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMLow = 1102 + le16_to_cpu(fan_table5->usFanRPMLow); 1103 + hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMHigh = 1104 + le16_to_cpu(fan_table5->usFanRPMHigh); 1105 + } 1106 + } 1107 + } 1108 + } 1016 1109 1017 1110 return 0; 1018 1111 }
+3 -6
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
··· 1297 1297 int pplib_workload = 0; 1298 1298 1299 1299 switch (power_profile) { 1300 - case PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT: 1301 - pplib_workload = WORKLOAD_DEFAULT_BIT; 1302 - break; 1303 1300 case PP_SMC_POWER_PROFILE_FULLSCREEN3D: 1304 1301 pplib_workload = WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT; 1305 - break; 1306 - case PP_SMC_POWER_PROFILE_POWERSAVING: 1307 - pplib_workload = WORKLOAD_PPLIB_POWER_SAVING_BIT; 1308 1302 break; 1309 1303 case PP_SMC_POWER_PROFILE_VIDEO: 1310 1304 pplib_workload = WORKLOAD_PPLIB_VIDEO_BIT; ··· 1308 1314 break; 1309 1315 case PP_SMC_POWER_PROFILE_COMPUTE: 1310 1316 pplib_workload = WORKLOAD_PPLIB_COMPUTE_BIT; 1317 + break; 1318 + case PP_SMC_POWER_PROFILE_CUSTOM: 1319 + pplib_workload = WORKLOAD_PPLIB_CUSTOM_BIT; 1311 1320 break; 1312 1321 } 1313 1322
+1 -1
drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
··· 217 217 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT), 218 218 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT), 219 219 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT), 220 - WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_CUSTOM_BIT), 220 + WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT), 221 221 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), 222 222 }; 223 223
+1 -1
drivers/gpu/drm/i915/display/intel_display.c
··· 18040 18040 */ 18041 18041 ret = intel_initial_commit(&i915->drm); 18042 18042 if (ret) 18043 - return ret; 18043 + drm_dbg_kms(&i915->drm, "Initial modeset failed, %d\n", ret); 18044 18044 18045 18045 intel_overlay_setup(i915); 18046 18046
+1 -1
drivers/gpu/drm/i915/display/intel_dp.c
··· 573 573 return 0; 574 574 } 575 575 /* Also take into account max slice width */ 576 - min_slice_count = min_t(u8, min_slice_count, 576 + min_slice_count = max_t(u8, min_slice_count, 577 577 DIV_ROUND_UP(mode_hdisplay, 578 578 max_slice_width)); 579 579
+5 -2
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
··· 3097 3097 break; 3098 3098 } 3099 3099 3100 - static void eb_request_add(struct i915_execbuffer *eb) 3100 + static int eb_request_add(struct i915_execbuffer *eb, int err) 3101 3101 { 3102 3102 struct i915_request *rq = eb->request; 3103 3103 struct intel_timeline * const tl = i915_request_timeline(rq); ··· 3118 3118 /* Serialise with context_close via the add_to_timeline */ 3119 3119 i915_request_set_error_once(rq, -ENOENT); 3120 3120 __i915_request_skip(rq); 3121 + err = -ENOENT; /* override any transient errors */ 3121 3122 } 3122 3123 3123 3124 __i915_request_queue(rq, &attr); ··· 3128 3127 retire_requests(tl, prev); 3129 3128 3130 3129 mutex_unlock(&tl->mutex); 3130 + 3131 + return err; 3131 3132 } 3132 3133 3133 3134 static const i915_user_extension_fn execbuf_extensions[] = { ··· 3335 3332 err = eb_submit(&eb, batch); 3336 3333 err_request: 3337 3334 i915_request_get(eb.request); 3338 - eb_request_add(&eb); 3335 + err = eb_request_add(&eb, err); 3339 3336 3340 3337 if (eb.fences) 3341 3338 signal_fence_array(&eb);
+6 -1
drivers/gpu/drm/i915/gt/intel_lrc.c
··· 2788 2788 static bool execlists_hold(struct intel_engine_cs *engine, 2789 2789 struct i915_request *rq) 2790 2790 { 2791 + if (i915_request_on_hold(rq)) 2792 + return false; 2793 + 2791 2794 spin_lock_irq(&engine->active.lock); 2792 2795 2793 2796 if (i915_request_completed(rq)) { /* too late! */ ··· 3172 3169 spin_unlock_irqrestore(&engine->active.lock, flags); 3173 3170 3174 3171 /* Recheck after serialising with direct-submission */ 3175 - if (unlikely(timeout && preempt_timeout(engine))) 3172 + if (unlikely(timeout && preempt_timeout(engine))) { 3173 + cancel_timer(&engine->execlists.preempt); 3176 3174 execlists_reset(engine, "preemption time out"); 3175 + } 3177 3176 } 3178 3177 } 3179 3178
+3 -4
drivers/gpu/drm/i915/gt/intel_mocs.c
··· 59 59 #define _L3_CACHEABILITY(value) ((value) << 4) 60 60 61 61 /* Helper defines */ 62 - #define GEN9_NUM_MOCS_ENTRIES 62 /* 62 out of 64 - 63 & 64 are reserved. */ 63 - #define GEN11_NUM_MOCS_ENTRIES 64 /* 63-64 are reserved, but configured. */ 62 + #define GEN9_NUM_MOCS_ENTRIES 64 /* 63-64 are reserved, but configured. */ 64 63 65 64 /* (e)LLC caching options */ 66 65 /* ··· 327 328 if (INTEL_GEN(i915) >= 12) { 328 329 table->size = ARRAY_SIZE(tgl_mocs_table); 329 330 table->table = tgl_mocs_table; 330 - table->n_entries = GEN11_NUM_MOCS_ENTRIES; 331 + table->n_entries = GEN9_NUM_MOCS_ENTRIES; 331 332 } else if (IS_GEN(i915, 11)) { 332 333 table->size = ARRAY_SIZE(icl_mocs_table); 333 334 table->table = icl_mocs_table; 334 - table->n_entries = GEN11_NUM_MOCS_ENTRIES; 335 + table->n_entries = GEN9_NUM_MOCS_ENTRIES; 335 336 } else if (IS_GEN9_BC(i915) || IS_CANNONLAKE(i915)) { 336 337 table->size = ARRAY_SIZE(skl_mocs_table); 337 338 table->n_entries = GEN9_NUM_MOCS_ENTRIES;
+1 -1
drivers/gpu/drm/i915/gt/shmem_utils.c
··· 73 73 mapping_set_unevictable(file->f_mapping); 74 74 return vaddr; 75 75 err_page: 76 - while (--i >= 0) 76 + while (i--) 77 77 put_page(pages[i]); 78 78 kvfree(pages); 79 79 return NULL;
+2 -2
drivers/gpu/drm/i915/selftests/i915_gem.c
··· 211 211 return PTR_ERR(obj); 212 212 213 213 obj2 = i915_gem_object_create_internal(i915, PAGE_SIZE); 214 - if (IS_ERR(obj)) { 215 - err = PTR_ERR(obj); 214 + if (IS_ERR(obj2)) { 215 + err = PTR_ERR(obj2); 216 216 goto put1; 217 217 } 218 218