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clk: microchip: mpfs: make the rtc's ahb clock critical

The onboard RTC's AHB bus clock must be kept running as the RTC will
stop & lose track of time if the AHB interface clock is disabled.

Fixes: 635e5e73370e ("clk: microchip: Add driver for Microchip PolarFire SoC")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220909123123.2699583-3-conor.dooley@microchip.com

authored by

Conor Dooley and committed by
Claudiu Beznea 05d27090 5da39ac5

+3 -1
+3 -1
drivers/clk/microchip/clk-mpfs.c
··· 375 375 * trap handler 376 376 * - CLK_MMUART0: reserved by the hss 377 377 * - CLK_DDRC: provides clock to the ddr subsystem 378 + * - CLK_RTC: the onboard RTC's AHB bus clock must be kept running as the rtc will stop 379 + * if the AHB interface clock is disabled 378 380 * - CLK_FICx: these provide the processor side clocks to the "FIC" (Fabric InterConnect) 379 381 * clock domain crossers which provide the interface to the FPGA fabric. Disabling them 380 382 * causes the FPGA fabric to go into reset. ··· 401 399 CLK_PERIPH(CLK_CAN0, "clk_periph_can0", PARENT_CLK(AHB), 14, 0), 402 400 CLK_PERIPH(CLK_CAN1, "clk_periph_can1", PARENT_CLK(AHB), 15, 0), 403 401 CLK_PERIPH(CLK_USB, "clk_periph_usb", PARENT_CLK(AHB), 16, 0), 404 - CLK_PERIPH(CLK_RTC, "clk_periph_rtc", PARENT_CLK(AHB), 18, 0), 402 + CLK_PERIPH(CLK_RTC, "clk_periph_rtc", PARENT_CLK(AHB), 18, CLK_IS_CRITICAL), 405 403 CLK_PERIPH(CLK_QSPI, "clk_periph_qspi", PARENT_CLK(AHB), 19, 0), 406 404 CLK_PERIPH(CLK_GPIO0, "clk_periph_gpio0", PARENT_CLK(AHB), 20, 0), 407 405 CLK_PERIPH(CLK_GPIO1, "clk_periph_gpio1", PARENT_CLK(AHB), 21, 0),