Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'net-dsa-move-ks8995-phy-driver-to-dsa'
Linus Walleij says:
====================
net: dsa: Move ks8995 "phy" driver to DSA
After we concluded that the KS8995 is a DSA switch, see
commit a0f29a07b654a50ebc9b070ef6dcb3219c4de867
it is time to move the driver to it's right place under
DSA.
Developing full support for the custom tagging, but we
can make sure the driver does the job it did as a "phy",
act as a switch with individually represented ports.
This patch series achieves that first step so the
current device tree bindings produces working set-ups
and paves the way for custom tagging.
====================
Link: https://patch.msgid.link/20250813-ks8995-to-dsa-v1-0-75c359ede3a5@linaro.org
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+411
-56
+8
drivers/net/dsa/Kconfig
+8
drivers/net/dsa/Kconfig
···
99
99
This driver supports the A5PSW switch, which is embedded in Renesas
100
100
RZ/N1 SoC.
101
101
102
+
config NET_DSA_KS8995
103
+
tristate "Micrel KS8995 family 5-ports 10/100 Ethernet switches"
104
+
depends on SPI
105
+
select NET_DSA_TAG_NONE
106
+
help
107
+
This driver supports the Micrel KS8995 family of 10/100 Mbit ethernet
108
+
switches, managed over SPI.
109
+
102
110
config NET_DSA_SMSC_LAN9303
103
111
tristate
104
112
select NET_DSA_TAG_LAN9303
+1
drivers/net/dsa/Makefile
+1
drivers/net/dsa/Makefile
-4
drivers/net/phy/Kconfig
-4
drivers/net/phy/Kconfig
-1
drivers/net/phy/Makefile
-1
drivers/net/phy/Makefile
···
72
72
obj-$(CONFIG_MAXLINEAR_86110_PHY) += mxl-86110.o
73
73
obj-y += mediatek/
74
74
obj-$(CONFIG_MESON_GXL_PHY) += meson-gxl.o
75
-
obj-$(CONFIG_MICREL_KS8995MA) += spi_ks8995.o
76
75
obj-$(CONFIG_MICREL_PHY) += micrel.o
77
76
obj-$(CONFIG_MICROCHIP_PHY) += microchip.o
78
77
obj-$(CONFIG_MICROCHIP_PHY_RDS_PTP) += microchip_rds_ptp.o
+402
-51
drivers/net/phy/spi_ks8995.c
drivers/net/dsa/ks8995.c
+402
-51
drivers/net/phy/spi_ks8995.c
drivers/net/dsa/ks8995.c
···
3
3
* SPI driver for Micrel/Kendin KS8995M and KSZ8864RMN ethernet switches
4
4
*
5
5
* Copyright (C) 2008 Gabor Juhos <juhosg at openwrt.org>
6
+
* Copyright (C) 2025 Linus Walleij <linus.walleij@linaro.org>
6
7
*
7
8
* This file was based on: drivers/spi/at25.c
8
9
* Copyright (C) 2006 David Brownell
···
11
10
12
11
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
13
12
13
+
#include <linux/bits.h>
14
+
#include <linux/if_bridge.h>
15
+
#include <linux/if_vlan.h>
14
16
#include <linux/types.h>
15
17
#include <linux/kernel.h>
16
18
#include <linux/module.h>
···
21
17
#include <linux/device.h>
22
18
#include <linux/gpio/consumer.h>
23
19
#include <linux/of.h>
24
-
25
20
#include <linux/spi/spi.h>
21
+
#include <net/dsa.h>
26
22
27
23
#define DRV_VERSION "0.1.1"
28
24
#define DRV_DESC "Micrel KS8995 Ethernet switch SPI driver"
···
33
29
#define KS8995_REG_ID1 0x01 /* Chip ID1 */
34
30
35
31
#define KS8995_REG_GC0 0x02 /* Global Control 0 */
32
+
33
+
#define KS8995_GC0_P5_PHY BIT(3) /* Port 5 PHY enabled */
34
+
36
35
#define KS8995_REG_GC1 0x03 /* Global Control 1 */
37
36
#define KS8995_REG_GC2 0x04 /* Global Control 2 */
37
+
38
+
#define KS8995_GC2_HUGE BIT(2) /* Huge packet support */
39
+
#define KS8995_GC2_LEGAL BIT(1) /* Legal size override */
40
+
38
41
#define KS8995_REG_GC3 0x05 /* Global Control 3 */
39
42
#define KS8995_REG_GC4 0x06 /* Global Control 4 */
43
+
44
+
#define KS8995_GC4_10BT BIT(4) /* Force switch to 10Mbit */
45
+
#define KS8995_GC4_MII_FLOW BIT(5) /* MII full-duplex flow control enable */
46
+
#define KS8995_GC4_MII_HD BIT(6) /* MII half-duplex mode enable */
47
+
40
48
#define KS8995_REG_GC5 0x07 /* Global Control 5 */
41
49
#define KS8995_REG_GC6 0x08 /* Global Control 6 */
42
50
#define KS8995_REG_GC7 0x09 /* Global Control 7 */
43
51
#define KS8995_REG_GC8 0x0a /* Global Control 8 */
44
52
#define KS8995_REG_GC9 0x0b /* Global Control 9 */
45
53
46
-
#define KS8995_REG_PC(p, r) ((0x10 * p) + r) /* Port Control */
47
-
#define KS8995_REG_PS(p, r) ((0x10 * p) + r + 0xe) /* Port Status */
54
+
#define KS8995_GC9_SPECIAL BIT(0) /* Special tagging mode (DSA) */
55
+
56
+
/* In DSA the ports 1-4 are numbered 0-3 and the CPU port is port 4 */
57
+
#define KS8995_REG_PC(p, r) (0x10 + (0x10 * (p)) + (r)) /* Port Control */
58
+
#define KS8995_REG_PS(p, r) (0x1e + (0x10 * (p)) + (r)) /* Port Status */
59
+
60
+
#define KS8995_REG_PC0 0x00 /* Port Control 0 */
61
+
#define KS8995_REG_PC1 0x01 /* Port Control 1 */
62
+
#define KS8995_REG_PC2 0x02 /* Port Control 2 */
63
+
#define KS8995_REG_PC3 0x03 /* Port Control 3 */
64
+
#define KS8995_REG_PC4 0x04 /* Port Control 4 */
65
+
#define KS8995_REG_PC5 0x05 /* Port Control 5 */
66
+
#define KS8995_REG_PC6 0x06 /* Port Control 6 */
67
+
#define KS8995_REG_PC7 0x07 /* Port Control 7 */
68
+
#define KS8995_REG_PC8 0x08 /* Port Control 8 */
69
+
#define KS8995_REG_PC9 0x09 /* Port Control 9 */
70
+
#define KS8995_REG_PC10 0x0a /* Port Control 10 */
71
+
#define KS8995_REG_PC11 0x0b /* Port Control 11 */
72
+
#define KS8995_REG_PC12 0x0c /* Port Control 12 */
73
+
#define KS8995_REG_PC13 0x0d /* Port Control 13 */
74
+
75
+
#define KS8995_PC0_TAG_INS BIT(2) /* Enable tag insertion on port */
76
+
#define KS8995_PC0_TAG_REM BIT(1) /* Enable tag removal on port */
77
+
#define KS8995_PC0_PRIO_EN BIT(0) /* Enable priority handling */
78
+
79
+
#define KS8995_PC2_TXEN BIT(2) /* Enable TX on port */
80
+
#define KS8995_PC2_RXEN BIT(1) /* Enable RX on port */
81
+
#define KS8995_PC2_LEARN_DIS BIT(0) /* Disable learning on port */
82
+
83
+
#define KS8995_PC13_TXDIS BIT(6) /* Disable transmitter */
84
+
#define KS8995_PC13_PWDN BIT(3) /* Power down */
48
85
49
86
#define KS8995_REG_TPC0 0x60 /* TOS Priority Control 0 */
50
87
#define KS8995_REG_TPC1 0x61 /* TOS Priority Control 1 */
···
136
91
#define KS8995_CMD_WRITE 0x02U
137
92
#define KS8995_CMD_READ 0x03U
138
93
94
+
#define KS8995_CPU_PORT 4
95
+
#define KS8995_NUM_PORTS 5 /* 5 ports including the CPU port */
139
96
#define KS8995_RESET_DELAY 10 /* usec */
140
97
141
98
enum ks8995_chip_variant {
···
185
138
186
139
struct ks8995_switch {
187
140
struct spi_device *spi;
141
+
struct device *dev;
142
+
struct dsa_switch *ds;
188
143
struct mutex lock;
189
144
struct gpio_desc *reset_gpio;
190
145
struct bin_attribute regs_attr;
191
146
const struct ks8995_chip_params *chip;
192
147
int revision_id;
148
+
unsigned int max_mtu[KS8995_NUM_PORTS];
193
149
};
194
150
195
151
static const struct spi_device_id ks8995_id[] = {
···
338
288
return ks8995_start(ks);
339
289
}
340
290
341
-
static ssize_t ks8995_registers_read(struct file *filp, struct kobject *kobj,
342
-
const struct bin_attribute *bin_attr, char *buf, loff_t off, size_t count)
343
-
{
344
-
struct device *dev;
345
-
struct ks8995_switch *ks8995;
346
-
347
-
dev = kobj_to_dev(kobj);
348
-
ks8995 = dev_get_drvdata(dev);
349
-
350
-
return ks8995_read(ks8995, buf, off, count);
351
-
}
352
-
353
-
static ssize_t ks8995_registers_write(struct file *filp, struct kobject *kobj,
354
-
const struct bin_attribute *bin_attr, char *buf, loff_t off, size_t count)
355
-
{
356
-
struct device *dev;
357
-
struct ks8995_switch *ks8995;
358
-
359
-
dev = kobj_to_dev(kobj);
360
-
ks8995 = dev_get_drvdata(dev);
361
-
362
-
return ks8995_write(ks8995, buf, off, count);
363
-
}
364
-
365
291
/* ks8995_get_revision - get chip revision
366
292
* @ks: pointer to switch instance
367
293
*
···
421
395
return err;
422
396
}
423
397
424
-
static const struct bin_attribute ks8995_registers_attr = {
425
-
.attr = {
426
-
.name = "registers",
427
-
.mode = 0600,
428
-
},
429
-
.size = KS8995_REGS_SIZE,
430
-
.read = ks8995_registers_read,
431
-
.write = ks8995_registers_write,
398
+
static int ks8995_check_config(struct ks8995_switch *ks)
399
+
{
400
+
int ret;
401
+
u8 val;
402
+
403
+
ret = ks8995_read_reg(ks, KS8995_REG_GC0, &val);
404
+
if (ret) {
405
+
dev_err(ks->dev, "failed to read KS8995_REG_GC0\n");
406
+
return ret;
407
+
}
408
+
409
+
dev_dbg(ks->dev, "port 5 PHY %senabled\n",
410
+
(val & KS8995_GC0_P5_PHY) ? "" : "not ");
411
+
412
+
val |= KS8995_GC0_P5_PHY;
413
+
ret = ks8995_write_reg(ks, KS8995_REG_GC0, val);
414
+
if (ret)
415
+
dev_err(ks->dev, "failed to set KS8995_REG_GC0\n");
416
+
417
+
dev_dbg(ks->dev, "set KS8995_REG_GC0 to 0x%02x\n", val);
418
+
419
+
return 0;
420
+
}
421
+
422
+
static void
423
+
ks8995_mac_config(struct phylink_config *config, unsigned int mode,
424
+
const struct phylink_link_state *state)
425
+
{
426
+
}
427
+
428
+
static void
429
+
ks8995_mac_link_up(struct phylink_config *config, struct phy_device *phydev,
430
+
unsigned int mode, phy_interface_t interface,
431
+
int speed, int duplex, bool tx_pause, bool rx_pause)
432
+
{
433
+
struct dsa_port *dp = dsa_phylink_to_port(config);
434
+
struct ks8995_switch *ks = dp->ds->priv;
435
+
int port = dp->index;
436
+
int ret;
437
+
u8 val;
438
+
439
+
/* Allow forcing the mode on the fixed CPU port, no autonegotiation.
440
+
* We assume autonegotiation works on the PHY-facing ports.
441
+
*/
442
+
if (port != KS8995_CPU_PORT)
443
+
return;
444
+
445
+
dev_dbg(ks->dev, "MAC link up on CPU port (%d)\n", port);
446
+
447
+
ret = ks8995_read_reg(ks, KS8995_REG_GC4, &val);
448
+
if (ret) {
449
+
dev_err(ks->dev, "failed to read KS8995_REG_GC4\n");
450
+
return;
451
+
}
452
+
453
+
/* Conjure port config */
454
+
switch (speed) {
455
+
case SPEED_10:
456
+
dev_dbg(ks->dev, "set switch MII to 100Mbit mode\n");
457
+
val |= KS8995_GC4_10BT;
458
+
break;
459
+
case SPEED_100:
460
+
default:
461
+
dev_dbg(ks->dev, "set switch MII to 100Mbit mode\n");
462
+
val &= ~KS8995_GC4_10BT;
463
+
break;
464
+
}
465
+
466
+
if (duplex == DUPLEX_HALF) {
467
+
dev_dbg(ks->dev, "set switch MII to half duplex\n");
468
+
val |= KS8995_GC4_MII_HD;
469
+
} else {
470
+
dev_dbg(ks->dev, "set switch MII to full duplex\n");
471
+
val &= ~KS8995_GC4_MII_HD;
472
+
}
473
+
474
+
dev_dbg(ks->dev, "set KS8995_REG_GC4 to %02x\n", val);
475
+
476
+
/* Enable the CPU port */
477
+
ret = ks8995_write_reg(ks, KS8995_REG_GC4, val);
478
+
if (ret)
479
+
dev_err(ks->dev, "failed to set KS8995_REG_GC4\n");
480
+
}
481
+
482
+
static void
483
+
ks8995_mac_link_down(struct phylink_config *config, unsigned int mode,
484
+
phy_interface_t interface)
485
+
{
486
+
struct dsa_port *dp = dsa_phylink_to_port(config);
487
+
struct ks8995_switch *ks = dp->ds->priv;
488
+
int port = dp->index;
489
+
490
+
if (port != KS8995_CPU_PORT)
491
+
return;
492
+
493
+
dev_dbg(ks->dev, "MAC link down on CPU port (%d)\n", port);
494
+
495
+
/* Disable the CPU port */
496
+
}
497
+
498
+
static const struct phylink_mac_ops ks8995_phylink_mac_ops = {
499
+
.mac_config = ks8995_mac_config,
500
+
.mac_link_up = ks8995_mac_link_up,
501
+
.mac_link_down = ks8995_mac_link_down,
502
+
};
503
+
504
+
static enum
505
+
dsa_tag_protocol ks8995_get_tag_protocol(struct dsa_switch *ds,
506
+
int port,
507
+
enum dsa_tag_protocol mp)
508
+
{
509
+
/* This switch actually uses the 6 byte KS8995 protocol */
510
+
return DSA_TAG_PROTO_NONE;
511
+
}
512
+
513
+
static int ks8995_setup(struct dsa_switch *ds)
514
+
{
515
+
return 0;
516
+
}
517
+
518
+
static int ks8995_port_enable(struct dsa_switch *ds, int port,
519
+
struct phy_device *phy)
520
+
{
521
+
struct ks8995_switch *ks = ds->priv;
522
+
523
+
dev_dbg(ks->dev, "enable port %d\n", port);
524
+
525
+
return 0;
526
+
}
527
+
528
+
static void ks8995_port_disable(struct dsa_switch *ds, int port)
529
+
{
530
+
struct ks8995_switch *ks = ds->priv;
531
+
532
+
dev_dbg(ks->dev, "disable port %d\n", port);
533
+
}
534
+
535
+
static int ks8995_port_pre_bridge_flags(struct dsa_switch *ds, int port,
536
+
struct switchdev_brport_flags flags,
537
+
struct netlink_ext_ack *extack)
538
+
{
539
+
/* We support enabling/disabling learning */
540
+
if (flags.mask & ~(BR_LEARNING))
541
+
return -EINVAL;
542
+
543
+
return 0;
544
+
}
545
+
546
+
static int ks8995_port_bridge_flags(struct dsa_switch *ds, int port,
547
+
struct switchdev_brport_flags flags,
548
+
struct netlink_ext_ack *extack)
549
+
{
550
+
struct ks8995_switch *ks = ds->priv;
551
+
int ret;
552
+
u8 val;
553
+
554
+
if (flags.mask & BR_LEARNING) {
555
+
ret = ks8995_read_reg(ks, KS8995_REG_PC(port, KS8995_REG_PC2), &val);
556
+
if (ret) {
557
+
dev_err(ks->dev, "failed to read KS8995_REG_PC2 on port %d\n", port);
558
+
return ret;
559
+
}
560
+
561
+
if (flags.val & BR_LEARNING)
562
+
val &= ~KS8995_PC2_LEARN_DIS;
563
+
else
564
+
val |= KS8995_PC2_LEARN_DIS;
565
+
566
+
ret = ks8995_write_reg(ks, KS8995_REG_PC(port, KS8995_REG_PC2), val);
567
+
if (ret) {
568
+
dev_err(ks->dev, "failed to write KS8995_REG_PC2 on port %d\n", port);
569
+
return ret;
570
+
}
571
+
}
572
+
573
+
return 0;
574
+
}
575
+
576
+
static void ks8995_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
577
+
{
578
+
struct ks8995_switch *ks = ds->priv;
579
+
int ret;
580
+
u8 val;
581
+
582
+
ret = ks8995_read_reg(ks, KS8995_REG_PC(port, KS8995_REG_PC2), &val);
583
+
if (ret) {
584
+
dev_err(ks->dev, "failed to read KS8995_REG_PC2 on port %d\n", port);
585
+
return;
586
+
}
587
+
588
+
/* Set the bits for the different STP states in accordance with
589
+
* the datasheet, pages 36-37 "Spanning tree support".
590
+
*/
591
+
switch (state) {
592
+
case BR_STATE_DISABLED:
593
+
case BR_STATE_BLOCKING:
594
+
case BR_STATE_LISTENING:
595
+
val &= ~KS8995_PC2_TXEN;
596
+
val &= ~KS8995_PC2_RXEN;
597
+
val |= KS8995_PC2_LEARN_DIS;
598
+
break;
599
+
case BR_STATE_LEARNING:
600
+
val &= ~KS8995_PC2_TXEN;
601
+
val &= ~KS8995_PC2_RXEN;
602
+
val &= ~KS8995_PC2_LEARN_DIS;
603
+
break;
604
+
case BR_STATE_FORWARDING:
605
+
val |= KS8995_PC2_TXEN;
606
+
val |= KS8995_PC2_RXEN;
607
+
val &= ~KS8995_PC2_LEARN_DIS;
608
+
break;
609
+
default:
610
+
dev_err(ks->dev, "unknown bridge state requested\n");
611
+
return;
612
+
}
613
+
614
+
ret = ks8995_write_reg(ks, KS8995_REG_PC(port, KS8995_REG_PC2), val);
615
+
if (ret) {
616
+
dev_err(ks->dev, "failed to write KS8995_REG_PC2 on port %d\n", port);
617
+
return;
618
+
}
619
+
620
+
dev_dbg(ks->dev, "set KS8995_REG_PC2 for port %d to %02x\n", port, val);
621
+
}
622
+
623
+
static void ks8995_phylink_get_caps(struct dsa_switch *dsa, int port,
624
+
struct phylink_config *config)
625
+
{
626
+
unsigned long *interfaces = config->supported_interfaces;
627
+
628
+
if (port == KS8995_CPU_PORT)
629
+
__set_bit(PHY_INTERFACE_MODE_MII, interfaces);
630
+
631
+
if (port <= 3) {
632
+
/* Internal PHYs */
633
+
__set_bit(PHY_INTERFACE_MODE_INTERNAL, interfaces);
634
+
/* phylib default */
635
+
__set_bit(PHY_INTERFACE_MODE_MII, interfaces);
636
+
}
637
+
638
+
config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100;
639
+
}
640
+
641
+
/* Huge packet support up to 1916 byte packages "inclusive"
642
+
* which means that tags are included. If the bit is not set
643
+
* it is 1536 bytes "inclusive". We present the length without
644
+
* tags or ethernet headers. The setting affects all ports.
645
+
*/
646
+
static int ks8995_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
647
+
{
648
+
struct ks8995_switch *ks = ds->priv;
649
+
unsigned int max_mtu;
650
+
int ret;
651
+
u8 val;
652
+
int i;
653
+
654
+
ks->max_mtu[port] = new_mtu;
655
+
656
+
/* Roof out the MTU for the entire switch to the greatest
657
+
* common denominator: the biggest set for any one port will
658
+
* be the biggest MTU for the switch.
659
+
*/
660
+
max_mtu = ETH_DATA_LEN;
661
+
for (i = 0; i < KS8995_NUM_PORTS; i++) {
662
+
if (ks->max_mtu[i] > max_mtu)
663
+
max_mtu = ks->max_mtu[i];
664
+
}
665
+
666
+
/* Translate to layer 2 size.
667
+
* Add ethernet and (possible) VLAN headers, and checksum to the size.
668
+
* For ETH_DATA_LEN (1500 bytes) this will add up to 1522 bytes.
669
+
*/
670
+
max_mtu += VLAN_ETH_HLEN;
671
+
max_mtu += ETH_FCS_LEN;
672
+
673
+
ret = ks8995_read_reg(ks, KS8995_REG_GC2, &val);
674
+
if (ret) {
675
+
dev_err(ks->dev, "failed to read KS8995_REG_GC2\n");
676
+
return ret;
677
+
}
678
+
679
+
if (max_mtu <= 1522) {
680
+
val &= ~KS8995_GC2_HUGE;
681
+
val &= ~KS8995_GC2_LEGAL;
682
+
} else if (max_mtu > 1522 && max_mtu <= 1536) {
683
+
/* This accepts packets up to 1536 bytes */
684
+
val &= ~KS8995_GC2_HUGE;
685
+
val |= KS8995_GC2_LEGAL;
686
+
} else {
687
+
/* This accepts packets up to 1916 bytes */
688
+
val |= KS8995_GC2_HUGE;
689
+
val |= KS8995_GC2_LEGAL;
690
+
}
691
+
692
+
dev_dbg(ks->dev, "new max MTU %d bytes (inclusive)\n", max_mtu);
693
+
694
+
ret = ks8995_write_reg(ks, KS8995_REG_GC2, val);
695
+
if (ret)
696
+
dev_err(ks->dev, "failed to set KS8995_REG_GC2\n");
697
+
698
+
return ret;
699
+
}
700
+
701
+
static int ks8995_get_max_mtu(struct dsa_switch *ds, int port)
702
+
{
703
+
return 1916 - ETH_HLEN - ETH_FCS_LEN;
704
+
}
705
+
706
+
static const struct dsa_switch_ops ks8995_ds_ops = {
707
+
.get_tag_protocol = ks8995_get_tag_protocol,
708
+
.setup = ks8995_setup,
709
+
.port_pre_bridge_flags = ks8995_port_pre_bridge_flags,
710
+
.port_bridge_flags = ks8995_port_bridge_flags,
711
+
.port_enable = ks8995_port_enable,
712
+
.port_disable = ks8995_port_disable,
713
+
.port_stp_state_set = ks8995_port_stp_state_set,
714
+
.port_change_mtu = ks8995_change_mtu,
715
+
.port_max_mtu = ks8995_get_max_mtu,
716
+
.phylink_get_caps = ks8995_phylink_get_caps,
432
717
};
433
718
434
719
/* ------------------------------------------------------------------------ */
···
760
423
761
424
mutex_init(&ks->lock);
762
425
ks->spi = spi;
426
+
ks->dev = &spi->dev;
763
427
ks->chip = &ks8995_chip[variant];
764
428
765
429
ks->reset_gpio = devm_gpiod_get_optional(&spi->dev, "reset",
···
776
438
if (err)
777
439
return err;
778
440
779
-
/* de-assert switch reset */
780
-
/* FIXME: this likely requires a delay */
781
-
gpiod_set_value_cansleep(ks->reset_gpio, 0);
441
+
if (ks->reset_gpio) {
442
+
/*
443
+
* If a reset line was obtained, wait for 100us after
444
+
* de-asserting RESET before accessing any registers, see
445
+
* the KS8995MA datasheet, page 44.
446
+
*/
447
+
gpiod_set_value_cansleep(ks->reset_gpio, 0);
448
+
udelay(100);
449
+
}
782
450
783
451
spi_set_drvdata(spi, ks);
784
452
···
800
456
if (err)
801
457
return err;
802
458
803
-
memcpy(&ks->regs_attr, &ks8995_registers_attr, sizeof(ks->regs_attr));
804
-
ks->regs_attr.size = ks->chip->regs_size;
805
-
806
459
err = ks8995_reset(ks);
807
460
if (err)
808
461
return err;
809
462
810
-
sysfs_attr_init(&ks->regs_attr.attr);
811
-
err = sysfs_create_bin_file(&spi->dev.kobj, &ks->regs_attr);
812
-
if (err) {
813
-
dev_err(&spi->dev, "unable to create sysfs file, err=%d\n",
814
-
err);
815
-
return err;
816
-
}
817
-
818
463
dev_info(&spi->dev, "%s device found, Chip ID:%x, Revision:%x\n",
819
464
ks->chip->name, ks->chip->chip_id, ks->revision_id);
465
+
466
+
err = ks8995_check_config(ks);
467
+
if (err)
468
+
return err;
469
+
470
+
ks->ds = devm_kzalloc(&spi->dev, sizeof(*ks->ds), GFP_KERNEL);
471
+
if (!ks->ds)
472
+
return -ENOMEM;
473
+
474
+
ks->ds->dev = &spi->dev;
475
+
ks->ds->num_ports = KS8995_NUM_PORTS;
476
+
ks->ds->ops = &ks8995_ds_ops;
477
+
ks->ds->phylink_mac_ops = &ks8995_phylink_mac_ops;
478
+
ks->ds->priv = ks;
479
+
480
+
err = dsa_register_switch(ks->ds);
481
+
if (err)
482
+
return dev_err_probe(&spi->dev, err,
483
+
"unable to register DSA switch\n");
820
484
821
485
return 0;
822
486
}
···
833
481
{
834
482
struct ks8995_switch *ks = spi_get_drvdata(spi);
835
483
836
-
sysfs_remove_bin_file(&spi->dev.kobj, &ks->regs_attr);
837
-
484
+
dsa_unregister_switch(ks->ds);
838
485
/* assert reset */
839
486
gpiod_set_value_cansleep(ks->reset_gpio, 1);
840
487
}