Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
pwm: Add support for RZ/G2L GPT
RZ/G2L General PWM Timer (GPT) composed of 8 channels with 32-bit timer
(GPT32E). It supports the following functions
* 32 bits x 8 channels
* Up-counting or down-counting (saw waves) or up/down-counting
(triangle waves) for each counter.
* Clock sources independently selectable for each channel
* Two I/O pins per channel
* Two output compare/input capture registers per channel
* For the two output compare/input capture registers of each channel,
four registers are provided as buffer registers and are capable of
operating as comparison registers when buffering is not in use.
* In output compare operation, buffer switching can be at crests or
troughs, enabling the generation of laterally asymmetric PWM waveforms.
* Registers for setting up frame cycles in each channel (with capability
for generating interrupts at overflow or underflow)
* Generation of dead times in PWM operation
* Synchronous starting, stopping and clearing counters for arbitrary
channels
* Starting, stopping, clearing and up/down counters in response to input
level comparison
* Starting, clearing, stopping and up/down counters in response to a
maximum of four external triggers
* Output pin disable function by dead time error and detected
short-circuits between output pins
* A/D converter start triggers can be generated (GPT32E0 to GPT32E3)
* Enables the noise filter for input capture and external trigger
operation
Add basic pwm support for RZ/G2L GPT driver by creating separate
logical channels for each IOs.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20250226144531.176819-4-biju.das.jz@bp.renesas.com
Signed-off-by: Uwe Kleine-König <ukleinek@kernel.org>
authored by
Biju Das
and committed by
Uwe Kleine-König
061f087f
9549d226
+455
+11
drivers/pwm/Kconfig
+11
drivers/pwm/Kconfig
···
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Generic PWM framework driver for the PWM controller found on
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Rockchip SoCs.
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config PWM_RZG2L_GPT
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tristate "Renesas RZ/G2L General PWM Timer support"
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depends on ARCH_RZG2L || COMPILE_TEST
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depends on HAS_IOMEM
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help
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This driver exposes the General PWM Timer controller found in Renesas
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RZ/G2L like chips through the PWM API.
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To compile this driver as a module, choose M here: the module
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will be called pwm-rzg2l-gpt.
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config PWM_RZ_MTU3
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tristate "Renesas RZ/G2L MTU3a PWM Timer support"
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depends on RZ_MTU3
+1
drivers/pwm/Makefile
+1
drivers/pwm/Makefile
···
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obj-$(CONFIG_PWM_RCAR) += pwm-rcar.o
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obj-$(CONFIG_PWM_RENESAS_TPU) += pwm-renesas-tpu.o
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obj-$(CONFIG_PWM_ROCKCHIP) += pwm-rockchip.o
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obj-$(CONFIG_PWM_RZG2L_GPT) += pwm-rzg2l-gpt.o
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obj-$(CONFIG_PWM_RZ_MTU3) += pwm-rz-mtu3.o
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obj-$(CONFIG_PWM_SAMSUNG) += pwm-samsung.o
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obj-$(CONFIG_PWM_SIFIVE) += pwm-sifive.o
+443
drivers/pwm/pwm-rzg2l-gpt.c
+443
drivers/pwm/pwm-rzg2l-gpt.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
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/*
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* Renesas RZ/G2L General PWM Timer (GPT) driver
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*
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* Copyright (C) 2025 Renesas Electronics Corporation
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*
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* Hardware manual for this IP can be found here
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* https://www.renesas.com/eu/en/document/mah/rzg2l-group-rzg2lc-group-users-manual-hardware-0?language=en
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*
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* Limitations:
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* - Counter must be stopped before modifying Mode and Prescaler.
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* - When PWM is disabled, the output is driven to inactive.
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* - While the hardware supports both polarities, the driver (for now)
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* only handles normal polarity.
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* - General PWM Timer (GPT) has 8 HW channels for PWM operations and
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* each HW channel have 2 IOs.
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* - Each IO is modelled as an independent PWM channel.
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* - When both channels are used, disabling the channel on one stops the
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* other.
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* - When both channels are used, the period of both IOs in the HW channel
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* must be same (for now).
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/limits.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pwm.h>
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#include <linux/reset.h>
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#include <linux/time.h>
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#include <linux/units.h>
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#define RZG2L_GET_CH(hwpwm) ((hwpwm) / 2)
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#define RZG2L_GET_CH_OFFS(ch) (0x100 * (ch))
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+
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#define RZG2L_GTCR(ch) (0x2c + RZG2L_GET_CH_OFFS(ch))
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#define RZG2L_GTUDDTYC(ch) (0x30 + RZG2L_GET_CH_OFFS(ch))
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#define RZG2L_GTIOR(ch) (0x34 + RZG2L_GET_CH_OFFS(ch))
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#define RZG2L_GTBER(ch) (0x40 + RZG2L_GET_CH_OFFS(ch))
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#define RZG2L_GTCNT(ch) (0x48 + RZG2L_GET_CH_OFFS(ch))
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#define RZG2L_GTCCR(ch, sub_ch) (0x4c + RZG2L_GET_CH_OFFS(ch) + 4 * (sub_ch))
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#define RZG2L_GTPR(ch) (0x64 + RZG2L_GET_CH_OFFS(ch))
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+
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#define RZG2L_GTCR_CST BIT(0)
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#define RZG2L_GTCR_MD GENMASK(18, 16)
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#define RZG2L_GTCR_TPCS GENMASK(26, 24)
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+
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#define RZG2L_GTCR_MD_SAW_WAVE_PWM_MODE FIELD_PREP(RZG2L_GTCR_MD, 0)
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+
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#define RZG2L_GTUDDTYC_UP BIT(0)
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#define RZG2L_GTUDDTYC_UDF BIT(1)
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#define RZG2L_GTUDDTYC_UP_COUNTING (RZG2L_GTUDDTYC_UP | RZG2L_GTUDDTYC_UDF)
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+
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#define RZG2L_GTIOR_GTIOA GENMASK(4, 0)
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#define RZG2L_GTIOR_GTIOB GENMASK(20, 16)
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#define RZG2L_GTIOR_GTIOx(sub_ch) ((sub_ch) ? RZG2L_GTIOR_GTIOB : RZG2L_GTIOR_GTIOA)
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#define RZG2L_GTIOR_OAE BIT(8)
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#define RZG2L_GTIOR_OBE BIT(24)
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#define RZG2L_GTIOR_OxE(sub_ch) ((sub_ch) ? RZG2L_GTIOR_OBE : RZG2L_GTIOR_OAE)
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#define RZG2L_INIT_OUT_HI_OUT_HI_END_TOGGLE 0x1b
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#define RZG2L_GTIOR_GTIOA_OUT_HI_END_TOGGLE_CMP_MATCH \
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(RZG2L_INIT_OUT_HI_OUT_HI_END_TOGGLE | RZG2L_GTIOR_OAE)
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#define RZG2L_GTIOR_GTIOB_OUT_HI_END_TOGGLE_CMP_MATCH \
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(FIELD_PREP(RZG2L_GTIOR_GTIOB, RZG2L_INIT_OUT_HI_OUT_HI_END_TOGGLE) | RZG2L_GTIOR_OBE)
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#define RZG2L_GTIOR_GTIOx_OUT_HI_END_TOGGLE_CMP_MATCH(sub_ch) \
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((sub_ch) ? RZG2L_GTIOR_GTIOB_OUT_HI_END_TOGGLE_CMP_MATCH : \
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RZG2L_GTIOR_GTIOA_OUT_HI_END_TOGGLE_CMP_MATCH)
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#define RZG2L_MAX_HW_CHANNELS 8
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#define RZG2L_CHANNELS_PER_IO 2
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#define RZG2L_MAX_PWM_CHANNELS (RZG2L_MAX_HW_CHANNELS * RZG2L_CHANNELS_PER_IO)
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#define RZG2L_MAX_SCALE_FACTOR 1024
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#define RZG2L_MAX_TICKS ((u64)U32_MAX * RZG2L_MAX_SCALE_FACTOR)
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struct rzg2l_gpt_chip {
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void __iomem *mmio;
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struct mutex lock; /* lock to protect shared channel resources */
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unsigned long rate_khz;
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u32 period_ticks[RZG2L_MAX_HW_CHANNELS];
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u32 channel_request_count[RZG2L_MAX_HW_CHANNELS];
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u32 channel_enable_count[RZG2L_MAX_HW_CHANNELS];
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};
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static inline struct rzg2l_gpt_chip *to_rzg2l_gpt_chip(struct pwm_chip *chip)
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{
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return pwmchip_get_drvdata(chip);
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}
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static inline unsigned int rzg2l_gpt_subchannel(unsigned int hwpwm)
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{
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return hwpwm & 0x1;
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}
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static void rzg2l_gpt_write(struct rzg2l_gpt_chip *rzg2l_gpt, u32 reg, u32 data)
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{
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writel(data, rzg2l_gpt->mmio + reg);
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}
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static u32 rzg2l_gpt_read(struct rzg2l_gpt_chip *rzg2l_gpt, u32 reg)
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{
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return readl(rzg2l_gpt->mmio + reg);
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}
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static void rzg2l_gpt_modify(struct rzg2l_gpt_chip *rzg2l_gpt, u32 reg, u32 clr,
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u32 set)
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{
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rzg2l_gpt_write(rzg2l_gpt, reg,
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(rzg2l_gpt_read(rzg2l_gpt, reg) & ~clr) | set);
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}
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static u8 rzg2l_gpt_calculate_prescale(struct rzg2l_gpt_chip *rzg2l_gpt,
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u64 period_ticks)
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{
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u32 prescaled_period_ticks;
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u8 prescale;
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prescaled_period_ticks = period_ticks >> 32;
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if (prescaled_period_ticks >= 256)
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prescale = 5;
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else
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prescale = (fls(prescaled_period_ticks) + 1) / 2;
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return prescale;
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}
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static int rzg2l_gpt_request(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct rzg2l_gpt_chip *rzg2l_gpt = to_rzg2l_gpt_chip(chip);
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u32 ch = RZG2L_GET_CH(pwm->hwpwm);
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guard(mutex)(&rzg2l_gpt->lock);
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rzg2l_gpt->channel_request_count[ch]++;
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return 0;
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}
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static void rzg2l_gpt_free(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct rzg2l_gpt_chip *rzg2l_gpt = to_rzg2l_gpt_chip(chip);
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u32 ch = RZG2L_GET_CH(pwm->hwpwm);
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guard(mutex)(&rzg2l_gpt->lock);
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rzg2l_gpt->channel_request_count[ch]--;
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}
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static bool rzg2l_gpt_is_ch_enabled(struct rzg2l_gpt_chip *rzg2l_gpt, u8 hwpwm)
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{
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u8 ch = RZG2L_GET_CH(hwpwm);
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u32 val;
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val = rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTCR(ch));
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if (!(val & RZG2L_GTCR_CST))
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return false;
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val = rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTIOR(ch));
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return val & RZG2L_GTIOR_OxE(rzg2l_gpt_subchannel(hwpwm));
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}
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/* Caller holds the lock while calling rzg2l_gpt_enable() */
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static void rzg2l_gpt_enable(struct rzg2l_gpt_chip *rzg2l_gpt,
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struct pwm_device *pwm)
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{
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u8 sub_ch = rzg2l_gpt_subchannel(pwm->hwpwm);
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u32 val = RZG2L_GTIOR_GTIOx(sub_ch) | RZG2L_GTIOR_OxE(sub_ch);
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u8 ch = RZG2L_GET_CH(pwm->hwpwm);
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/* Enable pin output */
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rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTIOR(ch), val,
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RZG2L_GTIOR_GTIOx_OUT_HI_END_TOGGLE_CMP_MATCH(sub_ch));
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if (!rzg2l_gpt->channel_enable_count[ch])
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rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTCR(ch), 0, RZG2L_GTCR_CST);
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rzg2l_gpt->channel_enable_count[ch]++;
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}
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/* Caller holds the lock while calling rzg2l_gpt_disable() */
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static void rzg2l_gpt_disable(struct rzg2l_gpt_chip *rzg2l_gpt,
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struct pwm_device *pwm)
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{
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u8 sub_ch = rzg2l_gpt_subchannel(pwm->hwpwm);
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u8 ch = RZG2L_GET_CH(pwm->hwpwm);
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/* Stop count, Output low on GTIOCx pin when counting stops */
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rzg2l_gpt->channel_enable_count[ch]--;
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if (!rzg2l_gpt->channel_enable_count[ch])
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rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTCR(ch), RZG2L_GTCR_CST, 0);
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/* Disable pin output */
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rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTIOR(ch), RZG2L_GTIOR_OxE(sub_ch), 0);
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}
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static u64 rzg2l_gpt_calculate_period_or_duty(struct rzg2l_gpt_chip *rzg2l_gpt,
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u32 val, u8 prescale)
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{
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u64 tmp;
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/*
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* The calculation doesn't overflow an u64 because prescale ≤ 5 and so
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* tmp = val << (2 * prescale) * USEC_PER_SEC
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* < 2^32 * 2^10 * 10^6
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* < 2^32 * 2^10 * 2^20
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* = 2^62
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*/
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tmp = (u64)val << (2 * prescale);
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tmp *= USEC_PER_SEC;
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return DIV64_U64_ROUND_UP(tmp, rzg2l_gpt->rate_khz);
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}
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static int rzg2l_gpt_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
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struct pwm_state *state)
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{
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struct rzg2l_gpt_chip *rzg2l_gpt = to_rzg2l_gpt_chip(chip);
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state->enabled = rzg2l_gpt_is_ch_enabled(rzg2l_gpt, pwm->hwpwm);
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if (state->enabled) {
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u32 sub_ch = rzg2l_gpt_subchannel(pwm->hwpwm);
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u32 ch = RZG2L_GET_CH(pwm->hwpwm);
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u8 prescale;
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u32 val;
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val = rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTCR(ch));
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prescale = FIELD_GET(RZG2L_GTCR_TPCS, val);
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val = rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTPR(ch));
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state->period = rzg2l_gpt_calculate_period_or_duty(rzg2l_gpt, val, prescale);
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+
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val = rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTCCR(ch, sub_ch));
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state->duty_cycle = rzg2l_gpt_calculate_period_or_duty(rzg2l_gpt, val, prescale);
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if (state->duty_cycle > state->period)
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state->duty_cycle = state->period;
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}
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state->polarity = PWM_POLARITY_NORMAL;
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return 0;
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}
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+
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static u32 rzg2l_gpt_calculate_pv_or_dc(u64 period_or_duty_cycle, u8 prescale)
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{
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return min_t(u64, DIV_ROUND_DOWN_ULL(period_or_duty_cycle, 1 << (2 * prescale)),
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U32_MAX);
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}
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+
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/* Caller holds the lock while calling rzg2l_gpt_config() */
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static int rzg2l_gpt_config(struct pwm_chip *chip, struct pwm_device *pwm,
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const struct pwm_state *state)
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{
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struct rzg2l_gpt_chip *rzg2l_gpt = to_rzg2l_gpt_chip(chip);
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u8 sub_ch = rzg2l_gpt_subchannel(pwm->hwpwm);
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u8 ch = RZG2L_GET_CH(pwm->hwpwm);
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u64 period_ticks, duty_ticks;
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unsigned long pv, dc;
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u8 prescale;
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+
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/* Limit period/duty cycle to max value supported by the HW */
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period_ticks = mul_u64_u64_div_u64(state->period, rzg2l_gpt->rate_khz, USEC_PER_SEC);
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if (period_ticks > RZG2L_MAX_TICKS)
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period_ticks = RZG2L_MAX_TICKS;
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/*
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* GPT counter is shared by the two IOs of a single channel, so
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* prescale and period can NOT be modified when there are multiple IOs
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* in use with different settings.
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*/
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if (rzg2l_gpt->channel_request_count[ch] > 1 && period_ticks != rzg2l_gpt->period_ticks[ch])
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return -EBUSY;
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+
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prescale = rzg2l_gpt_calculate_prescale(rzg2l_gpt, period_ticks);
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pv = rzg2l_gpt_calculate_pv_or_dc(period_ticks, prescale);
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+
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duty_ticks = mul_u64_u64_div_u64(state->duty_cycle, rzg2l_gpt->rate_khz, USEC_PER_SEC);
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if (duty_ticks > RZG2L_MAX_TICKS)
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duty_ticks = RZG2L_MAX_TICKS;
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dc = rzg2l_gpt_calculate_pv_or_dc(duty_ticks, prescale);
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+
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/*
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* GPT counter is shared by multiple channels, we cache the period ticks
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* from the first enabled channel and use the same value for both
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* channels.
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*/
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rzg2l_gpt->period_ticks[ch] = period_ticks;
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+
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/*
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* Counter must be stopped before modifying mode, prescaler, timer
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* counter and buffer enable registers. These registers are shared
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* between both channels. So allow updating these registers only for the
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* first enabled channel.
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*/
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if (rzg2l_gpt->channel_enable_count[ch] <= 1) {
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rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTCR(ch), RZG2L_GTCR_CST, 0);
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+
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/* GPT set operating mode (saw-wave up-counting) */
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rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTCR(ch), RZG2L_GTCR_MD,
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RZG2L_GTCR_MD_SAW_WAVE_PWM_MODE);
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+
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/* Set count direction */
305
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rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTUDDTYC(ch), RZG2L_GTUDDTYC_UP_COUNTING);
306
+
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/* Select count clock */
308
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rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTCR(ch), RZG2L_GTCR_TPCS,
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FIELD_PREP(RZG2L_GTCR_TPCS, prescale));
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+
311
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/* Set period */
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rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTPR(ch), pv);
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+
}
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+
315
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/* Set duty cycle */
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rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTCCR(ch, sub_ch), dc);
317
+
318
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if (rzg2l_gpt->channel_enable_count[ch] <= 1) {
319
+
/* Set initial value for counter */
320
+
rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTCNT(ch), 0);
321
+
322
+
/* Set no buffer operation */
323
+
rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTBER(ch), 0);
324
+
325
+
/* Restart the counter after updating the registers */
326
+
rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTCR(ch),
327
+
RZG2L_GTCR_CST, RZG2L_GTCR_CST);
328
+
}
329
+
330
+
return 0;
331
+
}
332
+
333
+
static int rzg2l_gpt_apply(struct pwm_chip *chip, struct pwm_device *pwm,
334
+
const struct pwm_state *state)
335
+
{
336
+
struct rzg2l_gpt_chip *rzg2l_gpt = to_rzg2l_gpt_chip(chip);
337
+
bool enabled = pwm->state.enabled;
338
+
int ret;
339
+
340
+
if (state->polarity != PWM_POLARITY_NORMAL)
341
+
return -EINVAL;
342
+
343
+
guard(mutex)(&rzg2l_gpt->lock);
344
+
if (!state->enabled) {
345
+
if (enabled)
346
+
rzg2l_gpt_disable(rzg2l_gpt, pwm);
347
+
348
+
return 0;
349
+
}
350
+
351
+
ret = rzg2l_gpt_config(chip, pwm, state);
352
+
if (!ret && !enabled)
353
+
rzg2l_gpt_enable(rzg2l_gpt, pwm);
354
+
355
+
return ret;
356
+
}
357
+
358
+
static const struct pwm_ops rzg2l_gpt_ops = {
359
+
.request = rzg2l_gpt_request,
360
+
.free = rzg2l_gpt_free,
361
+
.get_state = rzg2l_gpt_get_state,
362
+
.apply = rzg2l_gpt_apply,
363
+
};
364
+
365
+
static int rzg2l_gpt_probe(struct platform_device *pdev)
366
+
{
367
+
struct rzg2l_gpt_chip *rzg2l_gpt;
368
+
struct device *dev = &pdev->dev;
369
+
struct reset_control *rstc;
370
+
struct pwm_chip *chip;
371
+
unsigned long rate;
372
+
struct clk *clk;
373
+
int ret;
374
+
375
+
chip = devm_pwmchip_alloc(dev, RZG2L_MAX_PWM_CHANNELS, sizeof(*rzg2l_gpt));
376
+
if (IS_ERR(chip))
377
+
return PTR_ERR(chip);
378
+
rzg2l_gpt = to_rzg2l_gpt_chip(chip);
379
+
380
+
rzg2l_gpt->mmio = devm_platform_ioremap_resource(pdev, 0);
381
+
if (IS_ERR(rzg2l_gpt->mmio))
382
+
return PTR_ERR(rzg2l_gpt->mmio);
383
+
384
+
rstc = devm_reset_control_get_exclusive_deasserted(dev, NULL);
385
+
if (IS_ERR(rstc))
386
+
return dev_err_probe(dev, PTR_ERR(rstc), "Cannot deassert reset control\n");
387
+
388
+
clk = devm_clk_get_enabled(dev, NULL);
389
+
if (IS_ERR(clk))
390
+
return dev_err_probe(dev, PTR_ERR(clk), "Cannot get clock\n");
391
+
392
+
ret = devm_clk_rate_exclusive_get(dev, clk);
393
+
if (ret)
394
+
return ret;
395
+
396
+
rate = clk_get_rate(clk);
397
+
if (!rate)
398
+
return dev_err_probe(dev, -EINVAL, "The gpt clk rate is 0");
399
+
400
+
/*
401
+
* Refuse clk rates > 1 GHz to prevent overflow later for computing
402
+
* period and duty cycle.
403
+
*/
404
+
if (rate > NSEC_PER_SEC)
405
+
return dev_err_probe(dev, -EINVAL, "The gpt clk rate is > 1GHz");
406
+
407
+
/*
408
+
* Rate is in MHz and is always integer for peripheral clk
409
+
* 2^32 * 2^10 (prescalar) * 10^6 (rate_khz) < 2^64
410
+
* So make sure rate is multiple of 1000.
411
+
*/
412
+
rzg2l_gpt->rate_khz = rate / KILO;
413
+
if (rzg2l_gpt->rate_khz * KILO != rate)
414
+
return dev_err_probe(dev, -EINVAL, "Rate is not multiple of 1000");
415
+
416
+
mutex_init(&rzg2l_gpt->lock);
417
+
418
+
chip->ops = &rzg2l_gpt_ops;
419
+
ret = devm_pwmchip_add(dev, chip);
420
+
if (ret)
421
+
return dev_err_probe(dev, ret, "Failed to add PWM chip\n");
422
+
423
+
return 0;
424
+
}
425
+
426
+
static const struct of_device_id rzg2l_gpt_of_table[] = {
427
+
{ .compatible = "renesas,rzg2l-gpt", },
428
+
{ /* Sentinel */ }
429
+
};
430
+
MODULE_DEVICE_TABLE(of, rzg2l_gpt_of_table);
431
+
432
+
static struct platform_driver rzg2l_gpt_driver = {
433
+
.driver = {
434
+
.name = "pwm-rzg2l-gpt",
435
+
.of_match_table = rzg2l_gpt_of_table,
436
+
},
437
+
.probe = rzg2l_gpt_probe,
438
+
};
439
+
module_platform_driver(rzg2l_gpt_driver);
440
+
441
+
MODULE_AUTHOR("Biju Das <biju.das.jz@bp.renesas.com>");
442
+
MODULE_DESCRIPTION("Renesas RZ/G2L General PWM Timer (GPT) Driver");
443
+
MODULE_LICENSE("GPL");