tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

drm/i915: Extract display registers from i915_reg.h to display

There are certain register definitions which are defined in i915_reg.h
which are exclusively needed by display. Move the same to display
headers to remove i915_reg.h includes from display. This is a step
towards making display independent of i915.

intel_clock_gating.c can include display header directly, since its
usage is planned to be re-factored and will be moved within display.

v3: Updated subject and commit message (Jani)

v2: Drop common header in include and use display_regs.h (Jani)

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Link: https://patch.msgid.link/20260205094341.1882816-2-uma.shankar@intel.com

Uma Shankar 0635d554 c0a27a0c

+11 -12
+10
drivers/gpu/drm/i915/display/intel_display_regs.h
··· 2021 2021 #define TRANS_BPC_6 REG_FIELD_PREP(TRANS_BPC_MASK, 2) 2022 2022 #define TRANS_BPC_12 REG_FIELD_PREP(TRANS_BPC_MASK, 3) 2023 2023 2024 + #define _TRANSA_CHICKEN2 0xf0064 2025 + #define _TRANSB_CHICKEN2 0xf1064 2026 + #define TRANS_CHICKEN2(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2) 2027 + #define TRANS_CHICKEN2_TIMING_OVERRIDE REG_BIT(31) 2028 + #define TRANS_CHICKEN2_FDI_POLARITY_REVERSED REG_BIT(29) 2029 + #define TRANS_CHICKEN2_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) 2030 + #define TRANS_CHICKEN2_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANS_CHICKEN2_FRAME_START_DELAY_MASK, (x)) /* 0-3 */ 2031 + #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER REG_BIT(26) 2032 + #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH REG_BIT(25) 2033 + 2024 2034 #define PCH_DP_B _MMIO(0xe4100) 2025 2035 #define PCH_DP_C _MMIO(0xe4200) 2026 2036 #define PCH_DP_D _MMIO(0xe4300)
-1
drivers/gpu/drm/i915/display/intel_pch_display.c
··· 6 6 #include <drm/drm_print.h> 7 7 8 8 #include "g4x_dp.h" 9 - #include "i915_reg.h" 10 9 #include "intel_crt.h" 11 10 #include "intel_crt_regs.h" 12 11 #include "intel_de.h"
-10
drivers/gpu/drm/i915/i915_reg.h
··· 1023 1023 #define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE REG_BIT(10) 1024 1024 #define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE REG_BIT(4) 1025 1025 1026 - #define _TRANSA_CHICKEN2 0xf0064 1027 - #define _TRANSB_CHICKEN2 0xf1064 1028 - #define TRANS_CHICKEN2(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2) 1029 - #define TRANS_CHICKEN2_TIMING_OVERRIDE REG_BIT(31) 1030 - #define TRANS_CHICKEN2_FDI_POLARITY_REVERSED REG_BIT(29) 1031 - #define TRANS_CHICKEN2_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) 1032 - #define TRANS_CHICKEN2_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANS_CHICKEN2_FRAME_START_DELAY_MASK, (x)) /* 0-3 */ 1033 - #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER REG_BIT(26) 1034 - #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH REG_BIT(25) 1035 - 1036 1026 #define SOUTH_CHICKEN1 _MMIO(0xc2000) 1037 1027 #define FDIA_PHASE_SYNC_SHIFT_OVR 19 1038 1028 #define FDIA_PHASE_SYNC_SHIFT_EN 18
+1 -1
drivers/gpu/drm/i915/intel_clock_gating.c
··· 30 30 #include "display/i9xx_plane_regs.h" 31 31 #include "display/intel_display.h" 32 32 #include "display/intel_display_core.h" 33 - 33 + #include "display/intel_display_regs.h" 34 34 #include "gt/intel_engine_regs.h" 35 35 #include "gt/intel_gt.h" 36 36 #include "gt/intel_gt_mcr.h"