Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk fixes from Stephen Boyd:
"A set of clk driver fixes that resolve issues for various SoCs.
Most of these are incorrect clk data, like bad parent descriptions.
When the clk tree is improperly described things don't work, like USB
and UFS controllers, because clk frequencies are wonky. Here are the
extra details:
- Fix the parent of UFS reference clks on Qualcomm SC8280XP so that
UFS works properly
- Fix the clk ID for USB on AT91 RM9200 so the USB driver continues
to probe
- Stop using of_device_get_match_data() on the wrong device for a
Samsung Exynos driver so it gets the proper clk data
- Fix ExynosAutov9 binding
- Fix the parent of the div4 clk on Exynos7885
- Stop calling runtime PM APIs from the Qualcomm GDSC driver directly
as it leads to a lockdep splat and is just plain wrong because it
violates runtime PM semantics by calling runtime PM APIs when the
device has been runtime PM disabled"
* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
clk: qcom: gcc-sc8280xp: add cxo as parent for three ufs ref clks
ARM: at91: rm9200: fix usb device clock id
clk: samsung: Revert "clk: samsung: exynos-clkout: Use of_device_get_match_data()"
dt-bindings: clock: exynosautov9: fix reference to CMU_FSYS1
clk: qcom: gdsc: Remove direct runtime PM calls
clk: samsung: exynos7885: Correct "div4" clock parents
+21
-64
+1
-1
Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml
+1
-1
Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml
+1
-1
arch/arm/boot/dts/at91rm9200.dtsi
+1
-1
arch/arm/boot/dts/at91rm9200.dtsi
···
666
666
compatible = "atmel,at91rm9200-udc";
667
667
reg = <0xfffb0000 0x4000>;
668
668
interrupts = <11 IRQ_TYPE_LEVEL_HIGH 2>;
669
-
clocks = <&pmc PMC_TYPE_PERIPHERAL 11>, <&pmc PMC_TYPE_SYSTEM 2>;
669
+
clocks = <&pmc PMC_TYPE_PERIPHERAL 11>, <&pmc PMC_TYPE_SYSTEM 1>;
670
670
clock-names = "pclk", "hclk";
671
671
status = "disabled";
672
672
};
+1
-1
drivers/clk/at91/at91rm9200.c
+1
-1
drivers/clk/at91/at91rm9200.c
···
40
40
};
41
41
42
42
static const struct sck at91rm9200_systemck[] = {
43
-
{ .n = "udpck", .p = "usbck", .id = 2 },
43
+
{ .n = "udpck", .p = "usbck", .id = 1 },
44
44
{ .n = "uhpck", .p = "usbck", .id = 4 },
45
45
{ .n = "pck0", .p = "prog0", .id = 8 },
46
46
{ .n = "pck1", .p = "prog1", .id = 9 },
+6
drivers/clk/qcom/gcc-sc8280xp.c
+6
drivers/clk/qcom/gcc-sc8280xp.c
···
5364
5364
.enable_mask = BIT(0),
5365
5365
.hw.init = &(const struct clk_init_data) {
5366
5366
.name = "gcc_ufs_1_card_clkref_clk",
5367
+
.parent_data = &gcc_parent_data_tcxo,
5368
+
.num_parents = 1,
5367
5369
.ops = &clk_branch2_ops,
5368
5370
},
5369
5371
},
···
5434
5432
.enable_mask = BIT(0),
5435
5433
.hw.init = &(const struct clk_init_data) {
5436
5434
.name = "gcc_ufs_card_clkref_clk",
5435
+
.parent_data = &gcc_parent_data_tcxo,
5436
+
.num_parents = 1,
5437
5437
.ops = &clk_branch2_ops,
5438
5438
},
5439
5439
},
···
5852
5848
.enable_mask = BIT(0),
5853
5849
.hw.init = &(const struct clk_init_data) {
5854
5850
.name = "gcc_ufs_ref_clkref_clk",
5851
+
.parent_data = &gcc_parent_data_tcxo,
5852
+
.num_parents = 1,
5855
5853
.ops = &clk_branch2_ops,
5856
5854
},
5857
5855
},
+6
-55
drivers/clk/qcom/gdsc.c
+6
-55
drivers/clk/qcom/gdsc.c
···
11
11
#include <linux/kernel.h>
12
12
#include <linux/ktime.h>
13
13
#include <linux/pm_domain.h>
14
-
#include <linux/pm_runtime.h>
15
14
#include <linux/regmap.h>
16
15
#include <linux/regulator/consumer.h>
17
16
#include <linux/reset-controller.h>
···
54
55
GDSC_OFF,
55
56
GDSC_ON
56
57
};
57
-
58
-
static int gdsc_pm_runtime_get(struct gdsc *sc)
59
-
{
60
-
if (!sc->dev)
61
-
return 0;
62
-
63
-
return pm_runtime_resume_and_get(sc->dev);
64
-
}
65
-
66
-
static int gdsc_pm_runtime_put(struct gdsc *sc)
67
-
{
68
-
if (!sc->dev)
69
-
return 0;
70
-
71
-
return pm_runtime_put_sync(sc->dev);
72
-
}
73
58
74
59
/* Returns 1 if GDSC status is status, 0 if not, and < 0 on error */
75
60
static int gdsc_check_status(struct gdsc *sc, enum gdsc_status status)
···
254
271
regmap_update_bits(sc->regmap, sc->gdscr, mask, mask);
255
272
}
256
273
257
-
static int _gdsc_enable(struct gdsc *sc)
274
+
static int gdsc_enable(struct generic_pm_domain *domain)
258
275
{
276
+
struct gdsc *sc = domain_to_gdsc(domain);
259
277
int ret;
260
278
261
279
if (sc->pwrsts == PWRSTS_ON)
···
312
328
return 0;
313
329
}
314
330
315
-
static int gdsc_enable(struct generic_pm_domain *domain)
331
+
static int gdsc_disable(struct generic_pm_domain *domain)
316
332
{
317
333
struct gdsc *sc = domain_to_gdsc(domain);
318
-
int ret;
319
-
320
-
ret = gdsc_pm_runtime_get(sc);
321
-
if (ret)
322
-
return ret;
323
-
324
-
return _gdsc_enable(sc);
325
-
}
326
-
327
-
static int _gdsc_disable(struct gdsc *sc)
328
-
{
329
334
int ret;
330
335
331
336
if (sc->pwrsts == PWRSTS_ON)
···
359
386
gdsc_assert_clamp_io(sc);
360
387
361
388
return 0;
362
-
}
363
-
364
-
static int gdsc_disable(struct generic_pm_domain *domain)
365
-
{
366
-
struct gdsc *sc = domain_to_gdsc(domain);
367
-
int ret;
368
-
369
-
ret = _gdsc_disable(sc);
370
-
371
-
gdsc_pm_runtime_put(sc);
372
-
373
-
return ret;
374
389
}
375
390
376
391
static int gdsc_init(struct gdsc *sc)
···
408
447
return ret;
409
448
}
410
449
411
-
/* ...and the power-domain */
412
-
ret = gdsc_pm_runtime_get(sc);
413
-
if (ret)
414
-
goto err_disable_supply;
415
-
416
450
/*
417
451
* Votable GDSCs can be ON due to Vote from other masters.
418
452
* If a Votable GDSC is ON, make sure we have a Vote.
···
415
459
if (sc->flags & VOTABLE) {
416
460
ret = gdsc_update_collapse_bit(sc, false);
417
461
if (ret)
418
-
goto err_put_rpm;
462
+
goto err_disable_supply;
419
463
}
420
464
421
465
/* Turn on HW trigger mode if supported */
422
466
if (sc->flags & HW_CTRL) {
423
467
ret = gdsc_hwctrl(sc, true);
424
468
if (ret < 0)
425
-
goto err_put_rpm;
469
+
goto err_disable_supply;
426
470
}
427
471
428
472
/*
···
452
496
453
497
ret = pm_genpd_init(&sc->pd, NULL, !on);
454
498
if (ret)
455
-
goto err_put_rpm;
499
+
goto err_disable_supply;
456
500
457
501
return 0;
458
502
459
-
err_put_rpm:
460
-
if (on)
461
-
gdsc_pm_runtime_put(sc);
462
503
err_disable_supply:
463
504
if (on && sc->rsupply)
464
505
regulator_disable(sc->rsupply);
···
494
541
for (i = 0; i < num; i++) {
495
542
if (!scs[i])
496
543
continue;
497
-
if (pm_runtime_enabled(dev))
498
-
scs[i]->dev = dev;
499
544
scs[i]->regmap = regmap;
500
545
scs[i]->rcdev = rcdev;
501
546
ret = gdsc_init(scs[i]);
-2
drivers/clk/qcom/gdsc.h
-2
drivers/clk/qcom/gdsc.h
···
30
30
* @resets: ids of resets associated with this gdsc
31
31
* @reset_count: number of @resets
32
32
* @rcdev: reset controller
33
-
* @dev: the device holding the GDSC, used for pm_runtime calls
34
33
*/
35
34
struct gdsc {
36
35
struct generic_pm_domain pd;
···
73
74
74
75
const char *supply;
75
76
struct regulator *rsupply;
76
-
struct device *dev;
77
77
};
78
78
79
79
struct gdsc_desc {
+4
-2
drivers/clk/samsung/clk-exynos-clkout.c
+4
-2
drivers/clk/samsung/clk-exynos-clkout.c
···
81
81
static int exynos_clkout_match_parent_dev(struct device *dev, u32 *mux_mask)
82
82
{
83
83
const struct exynos_clkout_variant *variant;
84
+
const struct of_device_id *match;
84
85
85
86
if (!dev->parent) {
86
87
dev_err(dev, "not instantiated from MFD\n");
87
88
return -EINVAL;
88
89
}
89
90
90
-
variant = of_device_get_match_data(dev->parent);
91
-
if (!variant) {
91
+
match = of_match_device(exynos_clkout_ids, dev->parent);
92
+
if (!match) {
92
93
dev_err(dev, "cannot match parent device\n");
93
94
return -EINVAL;
94
95
}
96
+
variant = match->data;
95
97
96
98
*mux_mask = variant->mux_mask;
97
99
+2
-2
drivers/clk/samsung/clk-exynos7885.c
+2
-2
drivers/clk/samsung/clk-exynos7885.c
···
231
231
CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
232
232
DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3", "fout_shared0_pll",
233
233
CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
234
-
DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "fout_shared0_pll",
234
+
DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "dout_shared0_div2",
235
235
CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1),
236
236
DIV(CLK_DOUT_SHARED0_DIV5, "dout_shared0_div5", "fout_shared0_pll",
237
237
CLK_CON_DIV_PLL_SHARED0_DIV5, 0, 3),
···
239
239
CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
240
240
DIV(CLK_DOUT_SHARED1_DIV3, "dout_shared1_div3", "fout_shared1_pll",
241
241
CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
242
-
DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "fout_shared1_pll",
242
+
DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "dout_shared1_div2",
243
243
CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
244
244
245
245
/* CORE */