dt-bindings: clock: qcom: Add Nord Global Clock Controller

+58

Documentation/devicetree/bindings/clock/qcom,nord-gcc.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/clock/qcom,nord-gcc.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Qualcomm Global Clock & Reset Controller on Nord SoC 8 + 9 + maintainers: 10 + - Taniya Das <taniya.das@oss.qualcomm.com> 11 + 12 + description: | 13 + Qualcomm global clock control module provides the clocks, resets and power 14 + domains on Nord SoC. 15 + 16 + See also: include/dt-bindings/clock/qcom,nord-gcc.h 17 + 18 + properties: 19 + compatible: 20 + const: qcom,nord-gcc 21 + 22 + clocks: 23 + items: 24 + - description: Board XO source 25 + - description: Sleep clock source 26 + - description: PCIE A Pipe clock source 27 + - description: PCIE B Pipe clock source 28 + - description: PCIE C Pipe clock source 29 + - description: PCIE D Pipe clock source 30 + 31 + required: 32 + - compatible 33 + - clocks 34 + - '#power-domain-cells' 35 + 36 + allOf: 37 + - $ref: qcom,gcc.yaml# 38 + 39 + unevaluatedProperties: false 40 + 41 + examples: 42 + - | 43 + #include <dt-bindings/clock/qcom,rpmh.h> 44 + clock-controller@100000 { 45 + compatible = "qcom,nord-gcc"; 46 + reg = <0x00100000 0x1f4200>; 47 + clocks = <&rpmhcc RPMH_CXO_CLK>, 48 + <&sleep_clk>, 49 + <&pcie_a_pipe_clk>, 50 + <&pcie_b_pipe_clk>, 51 + <&pcie_c_pipe_clk>, 52 + <&pcie_d_pipe_clk>; 53 + #clock-cells = <1>; 54 + #reset-cells = <1>; 55 + #power-domain-cells = <1>; 56 + }; 57 + 58 + ...

+60

Documentation/devicetree/bindings/clock/qcom,nord-negcc.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/clock/qcom,nord-negcc.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Qualcomm Global North East Clock & Reset Controller on Nord SoC 8 + 9 + maintainers: 10 + - Taniya Das <taniya.das@oss.qualcomm.com> 11 + 12 + description: | 13 + Qualcomm global clock control (NE) module provides the clocks, resets 14 + and power domains on Nord SoC. 15 + 16 + See also: include/dt-bindings/clock/qcom,nord-negcc.h 17 + 18 + properties: 19 + compatible: 20 + const: qcom,nord-negcc 21 + 22 + clocks: 23 + items: 24 + - description: Board XO source 25 + - description: Sleep clock source 26 + - description: UFS Phy Rx symbol 0 clock source 27 + - description: UFS Phy Rx symbol 1 clock source 28 + - description: UFS Phy Tx symbol 0 clock source 29 + - description: USB3 Phy sec wrapper pipe clock source 30 + - description: USB3 Phy wrapper pipe clock source 31 + 32 + required: 33 + - compatible 34 + - clocks 35 + - '#power-domain-cells' 36 + 37 + allOf: 38 + - $ref: qcom,gcc.yaml# 39 + 40 + unevaluatedProperties: false 41 + 42 + examples: 43 + - | 44 + #include <dt-bindings/clock/qcom,rpmh.h> 45 + clock-controller@8900000 { 46 + compatible = "qcom,nord-negcc"; 47 + reg = <0x08900000 0xf4200>; 48 + clocks = <&rpmhcc RPMH_CXO_CLK>, 49 + <&sleep_clk>, 50 + <&ufs_phy_rx_symbol_0_clk>, 51 + <&ufs_phy_rx_symbol_1_clk>, 52 + <&ufs_phy_tx_symbol_0_clk>, 53 + <&usb3_phy_sec_pipe_clk>, 54 + <&usb3_phy_pipe_clk>; 55 + #clock-cells = <1>; 56 + #reset-cells = <1>; 57 + #power-domain-cells = <1>; 58 + }; 59 + 60 + ...

+55

Documentation/devicetree/bindings/clock/qcom,nord-nwgcc.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/clock/qcom,nord-nwgcc.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Qualcomm Global North West and South East Clock & Reset Controller 8 + on Nord SoC 9 + 10 + maintainers: 11 + - Taniya Das <taniya.das@oss.qualcomm.com> 12 + 13 + description: | 14 + Qualcomm global clock control (NW, SE) module provides the clocks, resets 15 + and power domains on Nord SoC. 16 + 17 + See also: 18 + include/dt-bindings/clock/qcom,nord-nwgcc.h 19 + include/dt-bindings/clock/qcom,nord-segcc.h 20 + 21 + properties: 22 + compatible: 23 + enum: 24 + - qcom,nord-nwgcc 25 + - qcom,nord-segcc 26 + 27 + clocks: 28 + items: 29 + - description: Board XO source 30 + - description: Sleep clock source 31 + 32 + required: 33 + - compatible 34 + - clocks 35 + - '#power-domain-cells' 36 + 37 + allOf: 38 + - $ref: qcom,gcc.yaml# 39 + 40 + unevaluatedProperties: false 41 + 42 + examples: 43 + - | 44 + #include <dt-bindings/clock/qcom,rpmh.h> 45 + clock-controller@8b00000 { 46 + compatible = "qcom,nord-nwgcc"; 47 + reg = <0x08b00000 0xf4200>; 48 + clocks = <&rpmhcc RPMH_CXO_CLK>, 49 + <&sleep_clk>; 50 + #clock-cells = <1>; 51 + #reset-cells = <1>; 52 + #power-domain-cells = <1>; 53 + }; 54 + 55 + ...

+147

include/dt-bindings/clock/qcom,nord-gcc.h

··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 + /* 3 + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 + */ 5 + 6 + #ifndef _DT_BINDINGS_CLK_QCOM_GCC_NORD_H 7 + #define _DT_BINDINGS_CLK_QCOM_GCC_NORD_H 8 + 9 + /* GCC clocks */ 10 + #define GCC_BOOT_ROM_AHB_CLK 0 11 + #define GCC_GP1_CLK 1 12 + #define GCC_GP1_CLK_SRC 2 13 + #define GCC_GP2_CLK 3 14 + #define GCC_GP2_CLK_SRC 4 15 + #define GCC_GPLL0 5 16 + #define GCC_GPLL0_OUT_EVEN 6 17 + #define GCC_MMU_0_TCU_VOTE_CLK 7 18 + #define GCC_PCIE_A_AUX_CLK 8 19 + #define GCC_PCIE_A_AUX_CLK_SRC 9 20 + #define GCC_PCIE_A_CFG_AHB_CLK 10 21 + #define GCC_PCIE_A_DTI_QTC_CLK 11 22 + #define GCC_PCIE_A_MSTR_AXI_CLK 12 23 + #define GCC_PCIE_A_PHY_AUX_CLK 13 24 + #define GCC_PCIE_A_PHY_AUX_CLK_SRC 14 25 + #define GCC_PCIE_A_PHY_RCHNG_CLK 15 26 + #define GCC_PCIE_A_PHY_RCHNG_CLK_SRC 16 27 + #define GCC_PCIE_A_PIPE_CLK 17 28 + #define GCC_PCIE_A_PIPE_CLK_SRC 18 29 + #define GCC_PCIE_A_SLV_AXI_CLK 19 30 + #define GCC_PCIE_A_SLV_Q2A_AXI_CLK 20 31 + #define GCC_PCIE_B_AUX_CLK 21 32 + #define GCC_PCIE_B_AUX_CLK_SRC 22 33 + #define GCC_PCIE_B_CFG_AHB_CLK 23 34 + #define GCC_PCIE_B_DTI_QTC_CLK 24 35 + #define GCC_PCIE_B_MSTR_AXI_CLK 25 36 + #define GCC_PCIE_B_PHY_AUX_CLK 26 37 + #define GCC_PCIE_B_PHY_AUX_CLK_SRC 27 38 + #define GCC_PCIE_B_PHY_RCHNG_CLK 28 39 + #define GCC_PCIE_B_PHY_RCHNG_CLK_SRC 29 40 + #define GCC_PCIE_B_PIPE_CLK 30 41 + #define GCC_PCIE_B_PIPE_CLK_SRC 31 42 + #define GCC_PCIE_B_SLV_AXI_CLK 32 43 + #define GCC_PCIE_B_SLV_Q2A_AXI_CLK 33 44 + #define GCC_PCIE_C_AUX_CLK 34 45 + #define GCC_PCIE_C_AUX_CLK_SRC 35 46 + #define GCC_PCIE_C_CFG_AHB_CLK 36 47 + #define GCC_PCIE_C_DTI_QTC_CLK 37 48 + #define GCC_PCIE_C_MSTR_AXI_CLK 38 49 + #define GCC_PCIE_C_PHY_AUX_CLK 39 50 + #define GCC_PCIE_C_PHY_AUX_CLK_SRC 40 51 + #define GCC_PCIE_C_PHY_RCHNG_CLK 41 52 + #define GCC_PCIE_C_PHY_RCHNG_CLK_SRC 42 53 + #define GCC_PCIE_C_PIPE_CLK 43 54 + #define GCC_PCIE_C_PIPE_CLK_SRC 44 55 + #define GCC_PCIE_C_SLV_AXI_CLK 45 56 + #define GCC_PCIE_C_SLV_Q2A_AXI_CLK 46 57 + #define GCC_PCIE_D_AUX_CLK 47 58 + #define GCC_PCIE_D_AUX_CLK_SRC 48 59 + #define GCC_PCIE_D_CFG_AHB_CLK 49 60 + #define GCC_PCIE_D_DTI_QTC_CLK 50 61 + #define GCC_PCIE_D_MSTR_AXI_CLK 51 62 + #define GCC_PCIE_D_PHY_AUX_CLK 52 63 + #define GCC_PCIE_D_PHY_AUX_CLK_SRC 53 64 + #define GCC_PCIE_D_PHY_RCHNG_CLK 54 65 + #define GCC_PCIE_D_PHY_RCHNG_CLK_SRC 55 66 + #define GCC_PCIE_D_PIPE_CLK 56 67 + #define GCC_PCIE_D_PIPE_CLK_SRC 57 68 + #define GCC_PCIE_D_SLV_AXI_CLK 58 69 + #define GCC_PCIE_D_SLV_Q2A_AXI_CLK 59 70 + #define GCC_PCIE_LINK_AHB_CLK 60 71 + #define GCC_PCIE_LINK_XO_CLK 61 72 + #define GCC_PCIE_NOC_ASYNC_BRIDGE_CLK 62 73 + #define GCC_PCIE_NOC_CNOC_SF_QX_CLK 63 74 + #define GCC_PCIE_NOC_M_CFG_CLK 64 75 + #define GCC_PCIE_NOC_M_PDB_CLK 65 76 + #define GCC_PCIE_NOC_MSTR_AXI_CLK 66 77 + #define GCC_PCIE_NOC_PWRCTL_CLK 67 78 + #define GCC_PCIE_NOC_QOSGEN_EXTREF_CLK 68 79 + #define GCC_PCIE_NOC_REFGEN_CLK 69 80 + #define GCC_PCIE_NOC_REFGEN_CLK_SRC 70 81 + #define GCC_PCIE_NOC_S_CFG_CLK 71 82 + #define GCC_PCIE_NOC_S_PDB_CLK 72 83 + #define GCC_PCIE_NOC_SAFETY_CLK 73 84 + #define GCC_PCIE_NOC_SAFETY_CLK_SRC 74 85 + #define GCC_PCIE_NOC_SLAVE_AXI_CLK 75 86 + #define GCC_PCIE_NOC_TSCTR_CLK 76 87 + #define GCC_PCIE_NOC_XO_CLK 77 88 + #define GCC_PDM2_CLK 78 89 + #define GCC_PDM2_CLK_SRC 79 90 + #define GCC_PDM_AHB_CLK 80 91 + #define GCC_PDM_XO4_CLK 81 92 + #define GCC_QUPV3_WRAP3_CORE_2X_CLK 82 93 + #define GCC_QUPV3_WRAP3_CORE_CLK 83 94 + #define GCC_QUPV3_WRAP3_M_CLK 84 95 + #define GCC_QUPV3_WRAP3_QSPI_REF_CLK 85 96 + #define GCC_QUPV3_WRAP3_QSPI_REF_CLK_SRC 86 97 + #define GCC_QUPV3_WRAP3_S0_CLK 87 98 + #define GCC_QUPV3_WRAP3_S0_CLK_SRC 88 99 + #define GCC_QUPV3_WRAP3_S_AHB_CLK 89 100 + #define GCC_SMMU_PCIE_QTC_VOTE_CLK 90 101 + 102 + /* GCC power domains */ 103 + #define GCC_PCIE_A_GDSC 0 104 + #define GCC_PCIE_A_PHY_GDSC 1 105 + #define GCC_PCIE_B_GDSC 2 106 + #define GCC_PCIE_B_PHY_GDSC 3 107 + #define GCC_PCIE_C_GDSC 4 108 + #define GCC_PCIE_C_PHY_GDSC 5 109 + #define GCC_PCIE_D_GDSC 6 110 + #define GCC_PCIE_D_PHY_GDSC 7 111 + #define GCC_PCIE_NOC_GDSC 8 112 + 113 + /* GCC resets */ 114 + #define GCC_PCIE_A_BCR 0 115 + #define GCC_PCIE_A_LINK_DOWN_BCR 1 116 + #define GCC_PCIE_A_NOCSR_COM_PHY_BCR 2 117 + #define GCC_PCIE_A_PHY_BCR 3 118 + #define GCC_PCIE_A_PHY_CFG_AHB_BCR 4 119 + #define GCC_PCIE_A_PHY_COM_BCR 5 120 + #define GCC_PCIE_A_PHY_NOCSR_COM_PHY_BCR 6 121 + #define GCC_PCIE_B_BCR 7 122 + #define GCC_PCIE_B_LINK_DOWN_BCR 8 123 + #define GCC_PCIE_B_NOCSR_COM_PHY_BCR 9 124 + #define GCC_PCIE_B_PHY_BCR 10 125 + #define GCC_PCIE_B_PHY_CFG_AHB_BCR 11 126 + #define GCC_PCIE_B_PHY_COM_BCR 12 127 + #define GCC_PCIE_B_PHY_NOCSR_COM_PHY_BCR 13 128 + #define GCC_PCIE_C_BCR 14 129 + #define GCC_PCIE_C_LINK_DOWN_BCR 15 130 + #define GCC_PCIE_C_NOCSR_COM_PHY_BCR 16 131 + #define GCC_PCIE_C_PHY_BCR 17 132 + #define GCC_PCIE_C_PHY_CFG_AHB_BCR 18 133 + #define GCC_PCIE_C_PHY_COM_BCR 19 134 + #define GCC_PCIE_C_PHY_NOCSR_COM_PHY_BCR 20 135 + #define GCC_PCIE_D_BCR 21 136 + #define GCC_PCIE_D_LINK_DOWN_BCR 22 137 + #define GCC_PCIE_D_NOCSR_COM_PHY_BCR 23 138 + #define GCC_PCIE_D_PHY_BCR 24 139 + #define GCC_PCIE_D_PHY_CFG_AHB_BCR 25 140 + #define GCC_PCIE_D_PHY_COM_BCR 26 141 + #define GCC_PCIE_D_PHY_NOCSR_COM_PHY_BCR 27 142 + #define GCC_PCIE_NOC_BCR 28 143 + #define GCC_PDM_BCR 29 144 + #define GCC_QUPV3_WRAPPER_3_BCR 30 145 + #define GCC_TCSR_PCIE_BCR 31 146 + 147 + #endif

+124

include/dt-bindings/clock/qcom,nord-negcc.h

··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 + /* 3 + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 + */ 5 + 6 + #ifndef _DT_BINDINGS_CLK_QCOM_NE_GCC_NORD_H 7 + #define _DT_BINDINGS_CLK_QCOM_NE_GCC_NORD_H 8 + 9 + /* NE_GCC clocks */ 10 + #define NE_GCC_AGGRE_NOC_UFS_PHY_AXI_CLK 0 11 + #define NE_GCC_AGGRE_NOC_USB2_AXI_CLK 1 12 + #define NE_GCC_AGGRE_NOC_USB3_PRIM_AXI_CLK 2 13 + #define NE_GCC_AGGRE_NOC_USB3_SEC_AXI_CLK 3 14 + #define NE_GCC_AHB2PHY_CLK 4 15 + #define NE_GCC_CNOC_USB2_AXI_CLK 5 16 + #define NE_GCC_CNOC_USB3_PRIM_AXI_CLK 6 17 + #define NE_GCC_CNOC_USB3_SEC_AXI_CLK 7 18 + #define NE_GCC_FRQ_MEASURE_REF_CLK 8 19 + #define NE_GCC_GP1_CLK 9 20 + #define NE_GCC_GP1_CLK_SRC 10 21 + #define NE_GCC_GP2_CLK 11 22 + #define NE_GCC_GP2_CLK_SRC 12 23 + #define NE_GCC_GPLL0 13 24 + #define NE_GCC_GPLL0_OUT_EVEN 14 25 + #define NE_GCC_GPLL2 15 26 + #define NE_GCC_GPU_2_CFG_CLK 16 27 + #define NE_GCC_GPU_2_GPLL0_CLK_SRC 17 28 + #define NE_GCC_GPU_2_GPLL0_DIV_CLK_SRC 18 29 + #define NE_GCC_GPU_2_HSCNOC_GFX_CLK 19 30 + #define NE_GCC_GPU_2_SMMU_VOTE_CLK 20 31 + #define NE_GCC_QUPV3_WRAP2_CORE_2X_CLK 21 32 + #define NE_GCC_QUPV3_WRAP2_CORE_CLK 22 33 + #define NE_GCC_QUPV3_WRAP2_M_AHB_CLK 23 34 + #define NE_GCC_QUPV3_WRAP2_S0_CLK 24 35 + #define NE_GCC_QUPV3_WRAP2_S0_CLK_SRC 25 36 + #define NE_GCC_QUPV3_WRAP2_S1_CLK 26 37 + #define NE_GCC_QUPV3_WRAP2_S1_CLK_SRC 27 38 + #define NE_GCC_QUPV3_WRAP2_S2_CLK 28 39 + #define NE_GCC_QUPV3_WRAP2_S2_CLK_SRC 29 40 + #define NE_GCC_QUPV3_WRAP2_S3_CLK 30 41 + #define NE_GCC_QUPV3_WRAP2_S3_CLK_SRC 31 42 + #define NE_GCC_QUPV3_WRAP2_S4_CLK 32 43 + #define NE_GCC_QUPV3_WRAP2_S4_CLK_SRC 33 44 + #define NE_GCC_QUPV3_WRAP2_S5_CLK 34 45 + #define NE_GCC_QUPV3_WRAP2_S5_CLK_SRC 35 46 + #define NE_GCC_QUPV3_WRAP2_S6_CLK 36 47 + #define NE_GCC_QUPV3_WRAP2_S6_CLK_SRC 37 48 + #define NE_GCC_QUPV3_WRAP2_S_AHB_CLK 38 49 + #define NE_GCC_SDCC4_APPS_CLK 39 50 + #define NE_GCC_SDCC4_APPS_CLK_SRC 40 51 + #define NE_GCC_SDCC4_AXI_CLK 41 52 + #define NE_GCC_UFS_PHY_AHB_CLK 42 53 + #define NE_GCC_UFS_PHY_AXI_CLK 43 54 + #define NE_GCC_UFS_PHY_AXI_CLK_SRC 44 55 + #define NE_GCC_UFS_PHY_ICE_CORE_CLK 45 56 + #define NE_GCC_UFS_PHY_ICE_CORE_CLK_SRC 46 57 + #define NE_GCC_UFS_PHY_PHY_AUX_CLK 47 58 + #define NE_GCC_UFS_PHY_PHY_AUX_CLK_SRC 48 59 + #define NE_GCC_UFS_PHY_RX_SYMBOL_0_CLK 49 60 + #define NE_GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 50 61 + #define NE_GCC_UFS_PHY_RX_SYMBOL_1_CLK 51 62 + #define NE_GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 52 63 + #define NE_GCC_UFS_PHY_TX_SYMBOL_0_CLK 53 64 + #define NE_GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 54 65 + #define NE_GCC_UFS_PHY_UNIPRO_CORE_CLK 55 66 + #define NE_GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 56 67 + #define NE_GCC_USB20_MASTER_CLK 57 68 + #define NE_GCC_USB20_MASTER_CLK_SRC 58 69 + #define NE_GCC_USB20_MOCK_UTMI_CLK 59 70 + #define NE_GCC_USB20_MOCK_UTMI_CLK_SRC 60 71 + #define NE_GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC 61 72 + #define NE_GCC_USB20_SLEEP_CLK 62 73 + #define NE_GCC_USB31_PRIM_ATB_CLK 63 74 + #define NE_GCC_USB31_PRIM_EUD_AHB_CLK 64 75 + #define NE_GCC_USB31_PRIM_MASTER_CLK 65 76 + #define NE_GCC_USB31_PRIM_MASTER_CLK_SRC 66 77 + #define NE_GCC_USB31_PRIM_MOCK_UTMI_CLK 67 78 + #define NE_GCC_USB31_PRIM_MOCK_UTMI_CLK_SRC 68 79 + #define NE_GCC_USB31_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 69 80 + #define NE_GCC_USB31_PRIM_SLEEP_CLK 70 81 + #define NE_GCC_USB31_SEC_ATB_CLK 71 82 + #define NE_GCC_USB31_SEC_EUD_AHB_CLK 72 83 + #define NE_GCC_USB31_SEC_MASTER_CLK 73 84 + #define NE_GCC_USB31_SEC_MASTER_CLK_SRC 74 85 + #define NE_GCC_USB31_SEC_MOCK_UTMI_CLK 75 86 + #define NE_GCC_USB31_SEC_MOCK_UTMI_CLK_SRC 76 87 + #define NE_GCC_USB31_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 77 88 + #define NE_GCC_USB31_SEC_SLEEP_CLK 78 89 + #define NE_GCC_USB3_PRIM_PHY_AUX_CLK 79 90 + #define NE_GCC_USB3_PRIM_PHY_AUX_CLK_SRC 80 91 + #define NE_GCC_USB3_PRIM_PHY_COM_AUX_CLK 81 92 + #define NE_GCC_USB3_PRIM_PHY_PIPE_CLK 82 93 + #define NE_GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 83 94 + #define NE_GCC_USB3_SEC_PHY_AUX_CLK 84 95 + #define NE_GCC_USB3_SEC_PHY_AUX_CLK_SRC 85 96 + #define NE_GCC_USB3_SEC_PHY_COM_AUX_CLK 86 97 + #define NE_GCC_USB3_SEC_PHY_PIPE_CLK 87 98 + #define NE_GCC_USB3_SEC_PHY_PIPE_CLK_SRC 88 99 + 100 + /* NE_GCC power domains */ 101 + #define NE_GCC_UFS_MEM_PHY_GDSC 0 102 + #define NE_GCC_UFS_PHY_GDSC 1 103 + #define NE_GCC_USB20_PRIM_GDSC 2 104 + #define NE_GCC_USB31_PRIM_GDSC 3 105 + #define NE_GCC_USB31_SEC_GDSC 4 106 + #define NE_GCC_USB3_PHY_GDSC 5 107 + #define NE_GCC_USB3_SEC_PHY_GDSC 6 108 + 109 + /* NE_GCC resets */ 110 + #define NE_GCC_GPU_2_BCR 0 111 + #define NE_GCC_QUPV3_WRAPPER_2_BCR 1 112 + #define NE_GCC_SDCC4_BCR 2 113 + #define NE_GCC_UFS_PHY_BCR 3 114 + #define NE_GCC_USB20_PRIM_BCR 4 115 + #define NE_GCC_USB31_PRIM_BCR 5 116 + #define NE_GCC_USB31_SEC_BCR 6 117 + #define NE_GCC_USB3_DP_PHY_PRIM_BCR 7 118 + #define NE_GCC_USB3_DP_PHY_SEC_BCR 8 119 + #define NE_GCC_USB3_PHY_PRIM_BCR 9 120 + #define NE_GCC_USB3_PHY_SEC_BCR 10 121 + #define NE_GCC_USB3PHY_PHY_PRIM_BCR 11 122 + #define NE_GCC_USB3PHY_PHY_SEC_BCR 12 123 + 124 + #endif

+69

include/dt-bindings/clock/qcom,nord-nwgcc.h

··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 + /* 3 + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 + */ 5 + 6 + #ifndef _DT_BINDINGS_CLK_QCOM_NW_GCC_NORD_H 7 + #define _DT_BINDINGS_CLK_QCOM_NW_GCC_NORD_H 8 + 9 + /* NW_GCC clocks */ 10 + #define NW_GCC_ACMU_MUX_CLK 0 11 + #define NW_GCC_CAMERA_AHB_CLK 1 12 + #define NW_GCC_CAMERA_HF_AXI_CLK 2 13 + #define NW_GCC_CAMERA_SF_AXI_CLK 3 14 + #define NW_GCC_CAMERA_TRIG_CLK 4 15 + #define NW_GCC_CAMERA_XO_CLK 5 16 + #define NW_GCC_DISP_0_AHB_CLK 6 17 + #define NW_GCC_DISP_0_HF_AXI_CLK 7 18 + #define NW_GCC_DISP_0_TRIG_CLK 8 19 + #define NW_GCC_DISP_1_AHB_CLK 9 20 + #define NW_GCC_DISP_1_HF_AXI_CLK 10 21 + #define NW_GCC_DISP_1_TRIG_CLK 11 22 + #define NW_GCC_DPRX0_AXI_HF_CLK 12 23 + #define NW_GCC_DPRX0_CFG_AHB_CLK 13 24 + #define NW_GCC_DPRX1_AXI_HF_CLK 14 25 + #define NW_GCC_DPRX1_CFG_AHB_CLK 15 26 + #define NW_GCC_EVA_AHB_CLK 16 27 + #define NW_GCC_EVA_AXI0_CLK 17 28 + #define NW_GCC_EVA_AXI0C_CLK 18 29 + #define NW_GCC_EVA_TRIG_CLK 19 30 + #define NW_GCC_EVA_XO_CLK 20 31 + #define NW_GCC_FRQ_MEASURE_REF_CLK 21 32 + #define NW_GCC_GP1_CLK 22 33 + #define NW_GCC_GP1_CLK_SRC 23 34 + #define NW_GCC_GP2_CLK 24 35 + #define NW_GCC_GP2_CLK_SRC 25 36 + #define NW_GCC_GPLL0 26 37 + #define NW_GCC_GPLL0_OUT_EVEN 27 38 + #define NW_GCC_GPU_2_CFG_AHB_CLK 28 39 + #define NW_GCC_GPU_2_GPLL0_CLK_SRC 29 40 + #define NW_GCC_GPU_2_GPLL0_DIV_CLK_SRC 30 41 + #define NW_GCC_GPU_2_HSCNOC_GFX_CLK 31 42 + #define NW_GCC_GPU_CFG_AHB_CLK 32 43 + #define NW_GCC_GPU_GPLL0_CLK_SRC 33 44 + #define NW_GCC_GPU_GPLL0_DIV_CLK_SRC 34 45 + #define NW_GCC_GPU_HSCNOC_GFX_CLK 35 46 + #define NW_GCC_GPU_SMMU_VOTE_CLK 36 47 + #define NW_GCC_HSCNOC_GPU_2_AXI_CLK 37 48 + #define NW_GCC_HSCNOC_GPU_AXI_CLK 38 49 + #define NW_GCC_MMU_1_TCU_VOTE_CLK 39 50 + #define NW_GCC_VIDEO_AHB_CLK 40 51 + #define NW_GCC_VIDEO_AXI0_CLK 41 52 + #define NW_GCC_VIDEO_AXI0C_CLK 42 53 + #define NW_GCC_VIDEO_AXI1_CLK 43 54 + #define NW_GCC_VIDEO_XO_CLK 44 55 + 56 + /* NW_GCC power domains */ 57 + 58 + /* NW_GCC resets */ 59 + #define NW_GCC_CAMERA_BCR 0 60 + #define NW_GCC_DISPLAY_0_BCR 1 61 + #define NW_GCC_DISPLAY_1_BCR 2 62 + #define NW_GCC_DPRX0_BCR 3 63 + #define NW_GCC_DPRX1_BCR 4 64 + #define NW_GCC_EVA_BCR 5 65 + #define NW_GCC_GPU_2_BCR 6 66 + #define NW_GCC_GPU_BCR 7 67 + #define NW_GCC_VIDEO_BCR 8 68 + 69 + #endif

+98

include/dt-bindings/clock/qcom,nord-segcc.h

··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 + /* 3 + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 + */ 5 + 6 + #ifndef _DT_BINDINGS_CLK_QCOM_SE_GCC_NORD_H 7 + #define _DT_BINDINGS_CLK_QCOM_SE_GCC_NORD_H 8 + 9 + /* SE_GCC clocks */ 10 + #define SE_GCC_EEE_EMAC0_CLK 0 11 + #define SE_GCC_EEE_EMAC0_CLK_SRC 1 12 + #define SE_GCC_EEE_EMAC1_CLK 2 13 + #define SE_GCC_EEE_EMAC1_CLK_SRC 3 14 + #define SE_GCC_EMAC0_AXI_CLK 4 15 + #define SE_GCC_EMAC0_CC_SGMIIPHY_RX_CLK 5 16 + #define SE_GCC_EMAC0_CC_SGMIIPHY_TX_CLK 6 17 + #define SE_GCC_EMAC0_PHY_AUX_CLK 7 18 + #define SE_GCC_EMAC0_PHY_AUX_CLK_SRC 8 19 + #define SE_GCC_EMAC0_PTP_CLK 9 20 + #define SE_GCC_EMAC0_PTP_CLK_SRC 10 21 + #define SE_GCC_EMAC0_RGMII_CLK 11 22 + #define SE_GCC_EMAC0_RGMII_CLK_SRC 12 23 + #define SE_GCC_EMAC0_RPCS_RX_CLK 13 24 + #define SE_GCC_EMAC0_RPCS_TX_CLK 14 25 + #define SE_GCC_EMAC0_XGXS_RX_CLK 15 26 + #define SE_GCC_EMAC0_XGXS_TX_CLK 16 27 + #define SE_GCC_EMAC1_AXI_CLK 17 28 + #define SE_GCC_EMAC1_CC_SGMIIPHY_RX_CLK 18 29 + #define SE_GCC_EMAC1_CC_SGMIIPHY_TX_CLK 19 30 + #define SE_GCC_EMAC1_PHY_AUX_CLK 20 31 + #define SE_GCC_EMAC1_PHY_AUX_CLK_SRC 21 32 + #define SE_GCC_EMAC1_PTP_CLK 22 33 + #define SE_GCC_EMAC1_PTP_CLK_SRC 23 34 + #define SE_GCC_EMAC1_RGMII_CLK 24 35 + #define SE_GCC_EMAC1_RGMII_CLK_SRC 25 36 + #define SE_GCC_EMAC1_RPCS_RX_CLK 26 37 + #define SE_GCC_EMAC1_RPCS_TX_CLK 27 38 + #define SE_GCC_EMAC1_XGXS_RX_CLK 28 39 + #define SE_GCC_EMAC1_XGXS_TX_CLK 29 40 + #define SE_GCC_FRQ_MEASURE_REF_CLK 30 41 + #define SE_GCC_GP1_CLK 31 42 + #define SE_GCC_GP1_CLK_SRC 32 43 + #define SE_GCC_GP2_CLK 33 44 + #define SE_GCC_GP2_CLK_SRC 34 45 + #define SE_GCC_GPLL0 35 46 + #define SE_GCC_GPLL0_OUT_EVEN 36 47 + #define SE_GCC_GPLL2 37 48 + #define SE_GCC_GPLL4 38 49 + #define SE_GCC_GPLL5 39 50 + #define SE_GCC_MMU_2_TCU_VOTE_CLK 40 51 + #define SE_GCC_QUPV3_WRAP0_CORE_2X_CLK 41 52 + #define SE_GCC_QUPV3_WRAP0_CORE_CLK 42 53 + #define SE_GCC_QUPV3_WRAP0_M_AHB_CLK 43 54 + #define SE_GCC_QUPV3_WRAP0_S0_CLK 44 55 + #define SE_GCC_QUPV3_WRAP0_S0_CLK_SRC 45 56 + #define SE_GCC_QUPV3_WRAP0_S1_CLK 46 57 + #define SE_GCC_QUPV3_WRAP0_S1_CLK_SRC 47 58 + #define SE_GCC_QUPV3_WRAP0_S2_CLK 48 59 + #define SE_GCC_QUPV3_WRAP0_S2_CLK_SRC 49 60 + #define SE_GCC_QUPV3_WRAP0_S3_CLK 50 61 + #define SE_GCC_QUPV3_WRAP0_S3_CLK_SRC 51 62 + #define SE_GCC_QUPV3_WRAP0_S4_CLK 52 63 + #define SE_GCC_QUPV3_WRAP0_S4_CLK_SRC 53 64 + #define SE_GCC_QUPV3_WRAP0_S5_CLK 54 65 + #define SE_GCC_QUPV3_WRAP0_S5_CLK_SRC 55 66 + #define SE_GCC_QUPV3_WRAP0_S6_CLK 56 67 + #define SE_GCC_QUPV3_WRAP0_S6_CLK_SRC 57 68 + #define SE_GCC_QUPV3_WRAP0_S_AHB_CLK 58 69 + #define SE_GCC_QUPV3_WRAP1_CORE_2X_CLK 59 70 + #define SE_GCC_QUPV3_WRAP1_CORE_CLK 60 71 + #define SE_GCC_QUPV3_WRAP1_M_AHB_CLK 61 72 + #define SE_GCC_QUPV3_WRAP1_S0_CLK 62 73 + #define SE_GCC_QUPV3_WRAP1_S0_CLK_SRC 63 74 + #define SE_GCC_QUPV3_WRAP1_S1_CLK 64 75 + #define SE_GCC_QUPV3_WRAP1_S1_CLK_SRC 65 76 + #define SE_GCC_QUPV3_WRAP1_S2_CLK 66 77 + #define SE_GCC_QUPV3_WRAP1_S2_CLK_SRC 67 78 + #define SE_GCC_QUPV3_WRAP1_S3_CLK 68 79 + #define SE_GCC_QUPV3_WRAP1_S3_CLK_SRC 69 80 + #define SE_GCC_QUPV3_WRAP1_S4_CLK 70 81 + #define SE_GCC_QUPV3_WRAP1_S4_CLK_SRC 71 82 + #define SE_GCC_QUPV3_WRAP1_S5_CLK 72 83 + #define SE_GCC_QUPV3_WRAP1_S5_CLK_SRC 73 84 + #define SE_GCC_QUPV3_WRAP1_S6_CLK 74 85 + #define SE_GCC_QUPV3_WRAP1_S6_CLK_SRC 75 86 + #define SE_GCC_QUPV3_WRAP1_S_AHB_CLK 76 87 + 88 + /* SE_GCC power domains */ 89 + #define SE_GCC_EMAC0_GDSC 0 90 + #define SE_GCC_EMAC1_GDSC 1 91 + 92 + /* SE_GCC resets */ 93 + #define SE_GCC_EMAC0_BCR 0 94 + #define SE_GCC_EMAC1_BCR 1 95 + #define SE_GCC_QUPV3_WRAPPER_0_BCR 2 96 + #define SE_GCC_QUPV3_WRAPPER_1_BCR 3 97 + 98 + #endif

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