tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'dmaengine-fix-5.8-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine into master

Pull dmaengine fixes from Vinod Koul:

- update dmaengine tree location to kernel.org

- dmatest fix for completing threads

- driver fixes for k3dma, fsl-dma, idxd, ,tegra, and few other drivers

* tag 'dmaengine-fix-5.8-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine: (21 commits)
dmaengine: ioat setting ioat timeout as module parameter
dmaengine: fsl-edma: fix wrong tcd endianness for big-endian cpu
dmaengine: dmatest: stop completed threads when running without set channel
dmaengine: fsl-edma-common: correct DSIZE_32BYTE
dmaengine: dw: Initialize channel before each transfer
dmaengine: idxd: fix misc interrupt handler thread unmasking
dmaengine: idxd: cleanup workqueue config after disabling
dmaengine: tegra210-adma: Fix runtime PM imbalance on error
dmaengine: mcf-edma: Fix NULL pointer exception in mcf_edma_tx_handler
dmaengine: fsl-edma: Fix NULL pointer exception in fsl_edma_tx_handler
dmaengine: fsl-edma: Add lockdep assert for exported function
dmaengine: idxd: fix hw descriptor fields for delta record
dmaengine: ti: k3-udma: add missing put_device() call in of_xudma_dev_get()
dmaengine: sh: usb-dmac: set tx_result parameters
dmaengine: ti: k3-udma: Fix delayed_work usage for tx drain workaround
dmaengine: idxd: fix cdev locking for open and release
dmaengine: imx-sdma: Fix: Remove 'always true' comparison
MAINTAINERS: switch dmaengine tree to kernel.org
dmaengine: ti: k3-udma: Fix the running channel handling in alloc_chan_resources
dmaengine: ti: k3-udma: Fix cleanup code for alloc_chan_resources
...

Linus Torvalds 0665a4e9 6cbba1f9

+128 -60
+1 -1
MAINTAINERS
··· 5112 5112 L: dmaengine@vger.kernel.org 5113 5113 S: Maintained 5114 5114 Q: https://patchwork.kernel.org/project/linux-dmaengine/list/ 5115 - T: git git://git.infradead.org/users/vkoul/slave-dma.git 5115 + T: git git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine.git 5116 5116 F: Documentation/devicetree/bindings/dma/ 5117 5117 F: Documentation/driver-api/dmaengine/ 5118 5118 F: drivers/dma/
+2
drivers/dma/dmatest.c
··· 1176 1176 } else if (dmatest_run) { 1177 1177 if (!is_threaded_test_pending(info)) { 1178 1178 pr_info("No channels configured, continue with any\n"); 1179 + if (!is_threaded_test_run(info)) 1180 + stop_threaded_test(info); 1179 1181 add_threaded_test(info); 1180 1182 } 1181 1183 start_threaded_tests(info);
-12
drivers/dma/dw/core.c
··· 118 118 { 119 119 struct dw_dma *dw = to_dw_dma(dwc->chan.device); 120 120 121 - if (test_bit(DW_DMA_IS_INITIALIZED, &dwc->flags)) 122 - return; 123 - 124 121 dw->initialize_chan(dwc); 125 122 126 123 /* Enable interrupts */ 127 124 channel_set_bit(dw, MASK.XFER, dwc->mask); 128 125 channel_set_bit(dw, MASK.ERROR, dwc->mask); 129 - 130 - set_bit(DW_DMA_IS_INITIALIZED, &dwc->flags); 131 126 } 132 127 133 128 /*----------------------------------------------------------------------*/ ··· 949 954 950 955 void do_dw_dma_off(struct dw_dma *dw) 951 956 { 952 - unsigned int i; 953 - 954 957 dma_writel(dw, CFG, 0); 955 958 956 959 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); ··· 959 966 960 967 while (dma_readl(dw, CFG) & DW_CFG_DMA_EN) 961 968 cpu_relax(); 962 - 963 - for (i = 0; i < dw->dma.chancnt; i++) 964 - clear_bit(DW_DMA_IS_INITIALIZED, &dw->chan[i].flags); 965 969 } 966 970 967 971 void do_dw_dma_on(struct dw_dma *dw) ··· 1021 1031 1022 1032 /* Clear custom channel configuration */ 1023 1033 memset(&dwc->dws, 0, sizeof(struct dw_dma_slave)); 1024 - 1025 - clear_bit(DW_DMA_IS_INITIALIZED, &dwc->flags); 1026 1034 1027 1035 /* Disable interrupts */ 1028 1036 channel_clear_bit(dw, MASK.XFER, dwc->mask);
+16 -12
drivers/dma/fsl-edma-common.c
··· 352 352 /* 353 353 * TCD parameters are stored in struct fsl_edma_hw_tcd in little 354 354 * endian format. However, we need to load the TCD registers in 355 - * big- or little-endian obeying the eDMA engine model endian. 355 + * big- or little-endian obeying the eDMA engine model endian, 356 + * and this is performed from specific edma_write functions 356 357 */ 357 358 edma_writew(edma, 0, &regs->tcd[ch].csr); 358 - edma_writel(edma, le32_to_cpu(tcd->saddr), &regs->tcd[ch].saddr); 359 - edma_writel(edma, le32_to_cpu(tcd->daddr), &regs->tcd[ch].daddr); 360 359 361 - edma_writew(edma, le16_to_cpu(tcd->attr), &regs->tcd[ch].attr); 362 - edma_writew(edma, le16_to_cpu(tcd->soff), &regs->tcd[ch].soff); 360 + edma_writel(edma, (s32)tcd->saddr, &regs->tcd[ch].saddr); 361 + edma_writel(edma, (s32)tcd->daddr, &regs->tcd[ch].daddr); 363 362 364 - edma_writel(edma, le32_to_cpu(tcd->nbytes), &regs->tcd[ch].nbytes); 365 - edma_writel(edma, le32_to_cpu(tcd->slast), &regs->tcd[ch].slast); 363 + edma_writew(edma, (s16)tcd->attr, &regs->tcd[ch].attr); 364 + edma_writew(edma, tcd->soff, &regs->tcd[ch].soff); 366 365 367 - edma_writew(edma, le16_to_cpu(tcd->citer), &regs->tcd[ch].citer); 368 - edma_writew(edma, le16_to_cpu(tcd->biter), &regs->tcd[ch].biter); 369 - edma_writew(edma, le16_to_cpu(tcd->doff), &regs->tcd[ch].doff); 366 + edma_writel(edma, (s32)tcd->nbytes, &regs->tcd[ch].nbytes); 367 + edma_writel(edma, (s32)tcd->slast, &regs->tcd[ch].slast); 370 368 371 - edma_writel(edma, le32_to_cpu(tcd->dlast_sga), 369 + edma_writew(edma, (s16)tcd->citer, &regs->tcd[ch].citer); 370 + edma_writew(edma, (s16)tcd->biter, &regs->tcd[ch].biter); 371 + edma_writew(edma, (s16)tcd->doff, &regs->tcd[ch].doff); 372 + 373 + edma_writel(edma, (s32)tcd->dlast_sga, 372 374 &regs->tcd[ch].dlast_sga); 373 375 374 - edma_writew(edma, le16_to_cpu(tcd->csr), &regs->tcd[ch].csr); 376 + edma_writew(edma, (s16)tcd->csr, &regs->tcd[ch].csr); 375 377 } 376 378 377 379 static inline ··· 590 588 void fsl_edma_xfer_desc(struct fsl_edma_chan *fsl_chan) 591 589 { 592 590 struct virt_dma_desc *vdesc; 591 + 592 + lockdep_assert_held(&fsl_chan->vchan.lock); 593 593 594 594 vdesc = vchan_next_desc(&fsl_chan->vchan); 595 595 if (!vdesc)
+1 -1
drivers/dma/fsl-edma-common.h
··· 33 33 #define EDMA_TCD_ATTR_DSIZE_16BIT BIT(0) 34 34 #define EDMA_TCD_ATTR_DSIZE_32BIT BIT(1) 35 35 #define EDMA_TCD_ATTR_DSIZE_64BIT (BIT(0) | BIT(1)) 36 - #define EDMA_TCD_ATTR_DSIZE_32BYTE (BIT(3) | BIT(0)) 36 + #define EDMA_TCD_ATTR_DSIZE_32BYTE (BIT(2) | BIT(0)) 37 37 #define EDMA_TCD_ATTR_SSIZE_8BIT 0 38 38 #define EDMA_TCD_ATTR_SSIZE_16BIT (EDMA_TCD_ATTR_DSIZE_16BIT << 8) 39 39 #define EDMA_TCD_ATTR_SSIZE_32BIT (EDMA_TCD_ATTR_DSIZE_32BIT << 8)
+7
drivers/dma/fsl-edma.c
··· 45 45 fsl_chan = &fsl_edma->chans[ch]; 46 46 47 47 spin_lock(&fsl_chan->vchan.lock); 48 + 49 + if (!fsl_chan->edesc) { 50 + /* terminate_all called before */ 51 + spin_unlock(&fsl_chan->vchan.lock); 52 + continue; 53 + } 54 + 48 55 if (!fsl_chan->edesc->iscyclic) { 49 56 list_del(&fsl_chan->edesc->vdesc.node); 50 57 vchan_cookie_complete(&fsl_chan->edesc->vdesc);
+16 -3
drivers/dma/idxd/cdev.c
··· 74 74 struct idxd_device *idxd; 75 75 struct idxd_wq *wq; 76 76 struct device *dev; 77 + int rc = 0; 77 78 78 79 wq = inode_wq(inode); 79 80 idxd = wq->idxd; ··· 82 81 83 82 dev_dbg(dev, "%s called: %d\n", __func__, idxd_wq_refcount(wq)); 84 83 85 - if (idxd_wq_refcount(wq) > 0 && wq_dedicated(wq)) 86 - return -EBUSY; 87 - 88 84 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 89 85 if (!ctx) 90 86 return -ENOMEM; 91 87 88 + mutex_lock(&wq->wq_lock); 89 + 90 + if (idxd_wq_refcount(wq) > 0 && wq_dedicated(wq)) { 91 + rc = -EBUSY; 92 + goto failed; 93 + } 94 + 92 95 ctx->wq = wq; 93 96 filp->private_data = ctx; 94 97 idxd_wq_get(wq); 98 + mutex_unlock(&wq->wq_lock); 95 99 return 0; 100 + 101 + failed: 102 + mutex_unlock(&wq->wq_lock); 103 + kfree(ctx); 104 + return rc; 96 105 } 97 106 98 107 static int idxd_cdev_release(struct inode *node, struct file *filep) ··· 116 105 filep->private_data = NULL; 117 106 118 107 kfree(ctx); 108 + mutex_lock(&wq->wq_lock); 119 109 idxd_wq_put(wq); 110 + mutex_unlock(&wq->wq_lock); 120 111 return 0; 121 112 } 122 113
+25
drivers/dma/idxd/device.c
··· 320 320 devm_iounmap(dev, wq->dportal); 321 321 } 322 322 323 + void idxd_wq_disable_cleanup(struct idxd_wq *wq) 324 + { 325 + struct idxd_device *idxd = wq->idxd; 326 + struct device *dev = &idxd->pdev->dev; 327 + int i, wq_offset; 328 + 329 + lockdep_assert_held(&idxd->dev_lock); 330 + memset(&wq->wqcfg, 0, sizeof(wq->wqcfg)); 331 + wq->type = IDXD_WQT_NONE; 332 + wq->size = 0; 333 + wq->group = NULL; 334 + wq->threshold = 0; 335 + wq->priority = 0; 336 + clear_bit(WQ_FLAG_DEDICATED, &wq->flags); 337 + memset(wq->name, 0, WQ_NAME_SIZE); 338 + 339 + for (i = 0; i < 8; i++) { 340 + wq_offset = idxd->wqcfg_offset + wq->id * 32 + i * sizeof(u32); 341 + iowrite32(0, idxd->reg_base + wq_offset); 342 + dev_dbg(dev, "WQ[%d][%d][%#x]: %#x\n", 343 + wq->id, i, wq_offset, 344 + ioread32(idxd->reg_base + wq_offset)); 345 + } 346 + } 347 + 323 348 /* Device control bits */ 324 349 static inline bool idxd_is_enabled(struct idxd_device *idxd) 325 350 {
+1
drivers/dma/idxd/idxd.h
··· 290 290 int idxd_wq_disable(struct idxd_wq *wq); 291 291 int idxd_wq_map_portal(struct idxd_wq *wq); 292 292 void idxd_wq_unmap_portal(struct idxd_wq *wq); 293 + void idxd_wq_disable_cleanup(struct idxd_wq *wq); 293 294 294 295 /* submission */ 295 296 int idxd_submit_desc(struct idxd_wq *wq, struct idxd_desc *desc);
+2 -1
drivers/dma/idxd/irq.c
··· 141 141 142 142 iowrite32(cause, idxd->reg_base + IDXD_INTCAUSE_OFFSET); 143 143 if (!err) 144 - return IRQ_HANDLED; 144 + goto out; 145 145 146 146 gensts.bits = ioread32(idxd->reg_base + IDXD_GENSTATS_OFFSET); 147 147 if (gensts.state == IDXD_DEVICE_STATE_HALT) { ··· 162 162 spin_unlock_bh(&idxd->dev_lock); 163 163 } 164 164 165 + out: 165 166 idxd_unmask_msix_vector(idxd, irq_entry->id); 166 167 return IRQ_HANDLED; 167 168 }
+5
drivers/dma/idxd/sysfs.c
··· 315 315 idxd_unregister_dma_device(idxd); 316 316 spin_lock_irqsave(&idxd->dev_lock, flags); 317 317 rc = idxd_device_disable(idxd); 318 + for (i = 0; i < idxd->max_wqs; i++) { 319 + struct idxd_wq *wq = &idxd->wqs[i]; 320 + 321 + idxd_wq_disable_cleanup(wq); 322 + } 318 323 spin_unlock_irqrestore(&idxd->dev_lock, flags); 319 324 module_put(THIS_MODULE); 320 325 if (rc < 0)
+4 -7
drivers/dma/imx-sdma.c
··· 1331 1331 1332 1332 sdma_channel_synchronize(chan); 1333 1333 1334 - if (sdmac->event_id0 >= 0) 1335 - sdma_event_disable(sdmac, sdmac->event_id0); 1334 + sdma_event_disable(sdmac, sdmac->event_id0); 1336 1335 if (sdmac->event_id1) 1337 1336 sdma_event_disable(sdmac, sdmac->event_id1); 1338 1337 ··· 1631 1632 memcpy(&sdmac->slave_config, dmaengine_cfg, sizeof(*dmaengine_cfg)); 1632 1633 1633 1634 /* Set ENBLn earlier to make sure dma request triggered after that */ 1634 - if (sdmac->event_id0 >= 0) { 1635 - if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events) 1636 - return -EINVAL; 1637 - sdma_event_enable(sdmac, sdmac->event_id0); 1638 - } 1635 + if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events) 1636 + return -EINVAL; 1637 + sdma_event_enable(sdmac, sdmac->event_id0); 1639 1638 1640 1639 if (sdmac->event_id1) { 1641 1640 if (sdmac->event_id1 >= sdmac->sdma->drvdata->num_events)
+12
drivers/dma/ioat/dma.c
··· 26 26 27 27 #include "../dmaengine.h" 28 28 29 + int completion_timeout = 200; 30 + module_param(completion_timeout, int, 0644); 31 + MODULE_PARM_DESC(completion_timeout, 32 + "set ioat completion timeout [msec] (default 200 [msec])"); 33 + int idle_timeout = 2000; 34 + module_param(idle_timeout, int, 0644); 35 + MODULE_PARM_DESC(idle_timeout, 36 + "set ioat idel timeout [msec] (default 2000 [msec])"); 37 + 38 + #define IDLE_TIMEOUT msecs_to_jiffies(idle_timeout) 39 + #define COMPLETION_TIMEOUT msecs_to_jiffies(completion_timeout) 40 + 29 41 static char *chanerr_str[] = { 30 42 "DMA Transfer Source Address Error", 31 43 "DMA Transfer Destination Address Error",
-2
drivers/dma/ioat/dma.h
··· 104 104 #define IOAT_RUN 5 105 105 #define IOAT_CHAN_ACTIVE 6 106 106 struct timer_list timer; 107 - #define COMPLETION_TIMEOUT msecs_to_jiffies(100) 108 - #define IDLE_TIMEOUT msecs_to_jiffies(2000) 109 107 #define RESET_DELAY msecs_to_jiffies(100) 110 108 struct ioatdma_device *ioat_dma; 111 109 dma_addr_t completion_dma;
+7
drivers/dma/mcf-edma.c
··· 35 35 mcf_chan = &mcf_edma->chans[ch]; 36 36 37 37 spin_lock(&mcf_chan->vchan.lock); 38 + 39 + if (!mcf_chan->edesc) { 40 + /* terminate_all called before */ 41 + spin_unlock(&mcf_chan->vchan.lock); 42 + continue; 43 + } 44 + 38 45 if (!mcf_chan->edesc->iscyclic) { 39 46 list_del(&mcf_chan->edesc->vdesc.node); 40 47 vchan_cookie_complete(&mcf_chan->edesc->vdesc);
+2
drivers/dma/sh/usb-dmac.c
··· 586 586 desc->residue = usb_dmac_get_current_residue(chan, desc, 587 587 desc->sg_index - 1); 588 588 desc->done_cookie = desc->vd.tx.cookie; 589 + desc->vd.tx_result.result = DMA_TRANS_NOERROR; 590 + desc->vd.tx_result.residue = desc->residue; 589 591 vchan_cookie_complete(&desc->vd); 590 592 591 593 /* Restart the next transfer if this driver has a next desc */
+4 -1
drivers/dma/tegra210-adma.c
··· 658 658 659 659 ret = pm_runtime_get_sync(tdc2dev(tdc)); 660 660 if (ret < 0) { 661 + pm_runtime_put_noidle(tdc2dev(tdc)); 661 662 free_irq(tdc->irq, tdc); 662 663 return ret; 663 664 } ··· 870 869 pm_runtime_enable(&pdev->dev); 871 870 872 871 ret = pm_runtime_get_sync(&pdev->dev); 873 - if (ret < 0) 872 + if (ret < 0) { 873 + pm_runtime_put_noidle(&pdev->dev); 874 874 goto rpm_disable; 875 + } 875 876 876 877 ret = tegra_adma_init(tdma); 877 878 if (ret)
+1
drivers/dma/ti/k3-udma-private.c
··· 42 42 ud = platform_get_drvdata(pdev); 43 43 if (!ud) { 44 44 pr_debug("UDMA has not been probed\n"); 45 + put_device(&pdev->dev); 45 46 return ERR_PTR(-EPROBE_DEFER); 46 47 } 47 48
+19 -20
drivers/dma/ti/k3-udma.c
··· 1753 1753 dev_err(ud->ddev.dev, 1754 1754 "Descriptor pool allocation failed\n"); 1755 1755 uc->use_dma_pool = false; 1756 - return -ENOMEM; 1756 + ret = -ENOMEM; 1757 + goto err_cleanup; 1757 1758 } 1758 1759 } 1759 1760 ··· 1774 1773 1775 1774 ret = udma_get_chan_pair(uc); 1776 1775 if (ret) 1777 - return ret; 1776 + goto err_cleanup; 1778 1777 1779 1778 ret = udma_alloc_tx_resources(uc); 1780 - if (ret) 1781 - return ret; 1779 + if (ret) { 1780 + udma_put_rchan(uc); 1781 + goto err_cleanup; 1782 + } 1782 1783 1783 1784 ret = udma_alloc_rx_resources(uc); 1784 1785 if (ret) { 1785 1786 udma_free_tx_resources(uc); 1786 - return ret; 1787 + goto err_cleanup; 1787 1788 } 1788 1789 1789 1790 uc->config.src_thread = ud->psil_base + uc->tchan->id; ··· 1803 1800 uc->id); 1804 1801 1805 1802 ret = udma_alloc_tx_resources(uc); 1806 - if (ret) { 1807 - uc->config.remote_thread_id = -1; 1808 - return ret; 1809 - } 1803 + if (ret) 1804 + goto err_cleanup; 1810 1805 1811 1806 uc->config.src_thread = ud->psil_base + uc->tchan->id; 1812 1807 uc->config.dst_thread = uc->config.remote_thread_id; ··· 1821 1820 uc->id); 1822 1821 1823 1822 ret = udma_alloc_rx_resources(uc); 1824 - if (ret) { 1825 - uc->config.remote_thread_id = -1; 1826 - return ret; 1827 - } 1823 + if (ret) 1824 + goto err_cleanup; 1828 1825 1829 1826 uc->config.src_thread = uc->config.remote_thread_id; 1830 1827 uc->config.dst_thread = (ud->psil_base + uc->rchan->id) | ··· 1837 1838 /* Can not happen */ 1838 1839 dev_err(uc->ud->dev, "%s: chan%d invalid direction (%u)\n", 1839 1840 __func__, uc->id, uc->config.dir); 1840 - return -EINVAL; 1841 + ret = -EINVAL; 1842 + goto err_cleanup; 1843 + 1841 1844 } 1842 1845 1843 1846 /* check if the channel configuration was successful */ ··· 1848 1847 1849 1848 if (udma_is_chan_running(uc)) { 1850 1849 dev_warn(ud->dev, "chan%d: is running!\n", uc->id); 1851 - udma_stop(uc); 1850 + udma_reset_chan(uc, false); 1852 1851 if (udma_is_chan_running(uc)) { 1853 1852 dev_err(ud->dev, "chan%d: won't stop!\n", uc->id); 1854 1853 ret = -EBUSY; ··· 1907 1906 1908 1907 udma_reset_rings(uc); 1909 1908 1910 - INIT_DELAYED_WORK_ONSTACK(&uc->tx_drain.work, 1911 - udma_check_tx_completion); 1912 1909 return 0; 1913 1910 1914 1911 err_irq_free: ··· 1918 1919 err_res_free: 1919 1920 udma_free_tx_resources(uc); 1920 1921 udma_free_rx_resources(uc); 1921 - 1922 + err_cleanup: 1922 1923 udma_reset_uchan(uc); 1923 1924 1924 1925 if (uc->use_dma_pool) { ··· 3018 3019 } 3019 3020 3020 3021 cancel_delayed_work_sync(&uc->tx_drain.work); 3021 - destroy_delayed_work_on_stack(&uc->tx_drain.work); 3022 3022 3023 3023 if (uc->irq_num_ring > 0) { 3024 3024 free_irq(uc->irq_num_ring, uc); ··· 3591 3593 return ret; 3592 3594 } 3593 3595 3594 - ret = of_property_read_u32(navss_node, "ti,udma-atype", &ud->atype); 3596 + ret = of_property_read_u32(dev->of_node, "ti,udma-atype", &ud->atype); 3595 3597 if (!ret && ud->atype > 2) { 3596 3598 dev_err(dev, "Invalid atype: %u\n", ud->atype); 3597 3599 return -EINVAL; ··· 3709 3711 tasklet_init(&uc->vc.task, udma_vchan_complete, 3710 3712 (unsigned long)&uc->vc); 3711 3713 init_completion(&uc->teardown_completed); 3714 + INIT_DELAYED_WORK(&uc->tx_drain.work, udma_check_tx_completion); 3712 3715 } 3713 3716 3714 3717 ret = dma_async_device_register(&ud->ddev);
+3
include/uapi/linux/idxd.h
··· 110 110 uint16_t rsvd1; 111 111 union { 112 112 uint8_t expected_res; 113 + /* create delta record */ 113 114 struct { 114 115 uint64_t delta_addr; 115 116 uint32_t max_delta_size; 117 + uint32_t delt_rsvd; 118 + uint8_t expected_res_mask; 116 119 }; 117 120 uint32_t delta_rec_size; 118 121 uint64_t dest2;