Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
ASoC: fsl: add bitcount and timestamp controls
Merge series from Shengjiu Wang <shengjiu.wang@nxp.com>:
The SAI and XCVR have the timestamp counters and bit counters, which can
be used by software to track the progress of the transmitter and receiver.
They can also be used to calculate the relative frequency of the bit clock
against the bus interface clock.
+331
+66
sound/soc/fsl/fsl_sai.c
+66
sound/soc/fsl/fsl_sai.c
···
41
41
.list = fsl_sai_rates,
42
42
};
43
43
44
+
static const char * const inc_mode[] = {
45
+
"On enabled and bitcount increment", "On enabled"
46
+
};
47
+
48
+
static SOC_ENUM_SINGLE_DECL(transmit_tstmp_enum,
49
+
FSL_SAI_TTCTL, FSL_SAI_xTCTL_TSINC_SHIFT, inc_mode);
50
+
static SOC_ENUM_SINGLE_DECL(receive_tstmp_enum,
51
+
FSL_SAI_RTCTL, FSL_SAI_xTCTL_TSINC_SHIFT, inc_mode);
52
+
53
+
static const struct snd_kcontrol_new fsl_sai_timestamp_ctrls[] = {
54
+
FSL_ASOC_SINGLE_EXT("Transmit Timestamp Control Switch", FSL_SAI_TTCTL,
55
+
FSL_SAI_xTCTL_TSEN_SHIFT, 1, 0,
56
+
fsl_asoc_get_volsw, fsl_asoc_put_volsw),
57
+
FSL_ASOC_ENUM_EXT("Transmit Timestamp Increment", transmit_tstmp_enum,
58
+
fsl_asoc_get_enum_double, fsl_asoc_put_enum_double),
59
+
FSL_ASOC_SINGLE_EXT("Transmit Timestamp Reset Switch", FSL_SAI_TTCTL,
60
+
FSL_SAI_xTCTL_RTSC_SHIFT, 1, 0,
61
+
fsl_asoc_get_volsw, fsl_asoc_put_volsw),
62
+
FSL_ASOC_SINGLE_EXT("Transmit Bit Counter Reset Switch", FSL_SAI_TTCTL,
63
+
FSL_SAI_xTCTL_RBC_SHIFT, 1, 0,
64
+
fsl_asoc_get_volsw, fsl_asoc_put_volsw),
65
+
FSL_ASOC_SINGLE_XR_SX_EXT_RO("Transmit Timestamp Counter", FSL_SAI_TTCTN,
66
+
1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx),
67
+
FSL_ASOC_SINGLE_XR_SX_EXT_RO("Transmit Bit Counter", FSL_SAI_TBCTN,
68
+
1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx),
69
+
FSL_ASOC_SINGLE_XR_SX_EXT_RO("Transmit Latched Timestamp Counter", FSL_SAI_TTCAP,
70
+
1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx),
71
+
FSL_ASOC_SINGLE_EXT("Receive Timestamp Control Switch", FSL_SAI_RTCTL,
72
+
FSL_SAI_xTCTL_TSEN_SHIFT, 1, 0,
73
+
fsl_asoc_get_volsw, fsl_asoc_put_volsw),
74
+
FSL_ASOC_ENUM_EXT("Receive Timestamp Increment", receive_tstmp_enum,
75
+
fsl_asoc_get_enum_double, fsl_asoc_put_enum_double),
76
+
FSL_ASOC_SINGLE_EXT("Receive Timestamp Reset Switch", FSL_SAI_RTCTL,
77
+
FSL_SAI_xTCTL_RTSC_SHIFT, 1, 0,
78
+
fsl_asoc_get_volsw, fsl_asoc_put_volsw),
79
+
FSL_ASOC_SINGLE_EXT("Receive Bit Counter Reset Switch", FSL_SAI_RTCTL,
80
+
FSL_SAI_xTCTL_RBC_SHIFT, 1, 0,
81
+
fsl_asoc_get_volsw, fsl_asoc_put_volsw),
82
+
FSL_ASOC_SINGLE_XR_SX_EXT_RO("Receive Timestamp Counter", FSL_SAI_RTCTN,
83
+
1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx),
84
+
FSL_ASOC_SINGLE_XR_SX_EXT_RO("Receive Bit Counter", FSL_SAI_RBCTN,
85
+
1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx),
86
+
FSL_ASOC_SINGLE_XR_SX_EXT_RO("Receive Latched Timestamp Counter", FSL_SAI_RTCAP,
87
+
1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx),
88
+
};
89
+
44
90
/**
45
91
* fsl_sai_dir_is_synced - Check if stream is synced by the opposite stream
46
92
*
···
1056
1010
return 0;
1057
1011
}
1058
1012
1013
+
static int fsl_sai_component_probe(struct snd_soc_component *component)
1014
+
{
1015
+
struct fsl_sai *sai = snd_soc_component_get_drvdata(component);
1016
+
1017
+
if (sai->verid.feature & FSL_SAI_VERID_TSTMP_EN)
1018
+
snd_soc_add_component_controls(component, fsl_sai_timestamp_ctrls,
1019
+
ARRAY_SIZE(fsl_sai_timestamp_ctrls));
1020
+
1021
+
return 0;
1022
+
}
1023
+
1059
1024
static struct snd_soc_dai_driver fsl_sai_dai_template[] = {
1060
1025
{
1061
1026
.name = "sai-tx-rx",
···
1120
1063
1121
1064
static const struct snd_soc_component_driver fsl_component = {
1122
1065
.name = "fsl-sai",
1066
+
.probe = fsl_sai_component_probe,
1123
1067
.resume = fsl_sai_dai_resume,
1124
1068
.legacy_dai_naming = 1,
1125
1069
};
···
1269
1211
case FSL_SAI_RDR5:
1270
1212
case FSL_SAI_RDR6:
1271
1213
case FSL_SAI_RDR7:
1214
+
case FSL_SAI_TTCTN:
1215
+
case FSL_SAI_RTCTN:
1216
+
case FSL_SAI_TTCTL:
1217
+
case FSL_SAI_TBCTN:
1218
+
case FSL_SAI_TTCAP:
1219
+
case FSL_SAI_RTCTL:
1220
+
case FSL_SAI_RBCTN:
1221
+
case FSL_SAI_RTCAP:
1272
1222
return true;
1273
1223
default:
1274
1224
return false;
+4
sound/soc/fsl/fsl_sai.h
+4
sound/soc/fsl/fsl_sai.h
···
196
196
#define FSL_SAI_MDIV_MASK 0xFFFFF
197
197
198
198
/* SAI timestamp and bitcounter */
199
+
#define FSL_SAI_xTCTL_TSEN_SHIFT 0
199
200
#define FSL_SAI_xTCTL_TSEN BIT(0)
201
+
#define FSL_SAI_xTCTL_TSINC_SHIFT 1
200
202
#define FSL_SAI_xTCTL_TSINC BIT(1)
203
+
#define FSL_SAI_xTCTL_RTSC_SHIFT 8
201
204
#define FSL_SAI_xTCTL_RTSC BIT(8)
205
+
#define FSL_SAI_xTCTL_RBC_SHIFT 9
202
206
#define FSL_SAI_xTCTL_RBC BIT(9)
203
207
204
208
/* SAI type */
+131
sound/soc/fsl/fsl_utils.c
+131
sound/soc/fsl/fsl_utils.c
···
10
10
#include <linux/clk-provider.h>
11
11
#include <linux/module.h>
12
12
#include <linux/of_address.h>
13
+
#include <linux/pm_runtime.h>
13
14
#include <sound/soc.h>
14
15
15
16
#include "fsl_utils.h"
···
197
196
}
198
197
}
199
198
EXPORT_SYMBOL(fsl_asoc_constrain_rates);
199
+
200
+
/*
201
+
* Below functions are used by mixer interface to avoid accessing registers
202
+
* which are volatile at pm runtime suspend state (cache_only is enabled).
203
+
*/
204
+
int fsl_asoc_get_xr_sx(struct snd_kcontrol *kcontrol,
205
+
struct snd_ctl_elem_value *ucontrol)
206
+
{
207
+
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
208
+
int ret = 0;
209
+
210
+
ret = pm_runtime_resume_and_get(component->dev);
211
+
if (ret)
212
+
return ret;
213
+
214
+
ret = snd_soc_get_xr_sx(kcontrol, ucontrol);
215
+
216
+
pm_runtime_put_autosuspend(component->dev);
217
+
218
+
return ret;
219
+
}
220
+
EXPORT_SYMBOL_GPL(fsl_asoc_get_xr_sx);
221
+
222
+
int fsl_asoc_put_xr_sx(struct snd_kcontrol *kcontrol,
223
+
struct snd_ctl_elem_value *ucontrol)
224
+
{
225
+
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
226
+
int ret = 0;
227
+
228
+
ret = pm_runtime_resume_and_get(component->dev);
229
+
if (ret)
230
+
return ret;
231
+
232
+
ret = snd_soc_put_xr_sx(kcontrol, ucontrol);
233
+
/*
234
+
* As this function only used by the SNDRV_CTL_ELEM_ACCESS_VOLATILE
235
+
* case. return 0 to avoid control event notification.
236
+
*/
237
+
if (ret > 0)
238
+
ret = 0;
239
+
240
+
pm_runtime_put_autosuspend(component->dev);
241
+
242
+
return ret;
243
+
}
244
+
EXPORT_SYMBOL_GPL(fsl_asoc_put_xr_sx);
245
+
246
+
int fsl_asoc_get_enum_double(struct snd_kcontrol *kcontrol,
247
+
struct snd_ctl_elem_value *ucontrol)
248
+
{
249
+
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
250
+
int ret = 0;
251
+
252
+
ret = pm_runtime_resume_and_get(component->dev);
253
+
if (ret)
254
+
return ret;
255
+
256
+
ret = snd_soc_get_enum_double(kcontrol, ucontrol);
257
+
258
+
pm_runtime_put_autosuspend(component->dev);
259
+
260
+
return ret;
261
+
}
262
+
EXPORT_SYMBOL_GPL(fsl_asoc_get_enum_double);
263
+
264
+
int fsl_asoc_put_enum_double(struct snd_kcontrol *kcontrol,
265
+
struct snd_ctl_elem_value *ucontrol)
266
+
{
267
+
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
268
+
int ret = 0;
269
+
270
+
ret = pm_runtime_resume_and_get(component->dev);
271
+
if (ret)
272
+
return ret;
273
+
274
+
ret = snd_soc_put_enum_double(kcontrol, ucontrol);
275
+
/*
276
+
* As this function only used by the SNDRV_CTL_ELEM_ACCESS_VOLATILE
277
+
* case. return 0 to avoid control event notification.
278
+
*/
279
+
if (ret > 0)
280
+
ret = 0;
281
+
282
+
pm_runtime_put_autosuspend(component->dev);
283
+
284
+
return ret;
285
+
}
286
+
EXPORT_SYMBOL_GPL(fsl_asoc_put_enum_double);
287
+
288
+
int fsl_asoc_get_volsw(struct snd_kcontrol *kcontrol,
289
+
struct snd_ctl_elem_value *ucontrol)
290
+
{
291
+
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
292
+
int ret = 0;
293
+
294
+
ret = pm_runtime_resume_and_get(component->dev);
295
+
if (ret)
296
+
return ret;
297
+
298
+
ret = snd_soc_get_volsw(kcontrol, ucontrol);
299
+
300
+
pm_runtime_put_autosuspend(component->dev);
301
+
302
+
return ret;
303
+
}
304
+
EXPORT_SYMBOL_GPL(fsl_asoc_get_volsw);
305
+
306
+
int fsl_asoc_put_volsw(struct snd_kcontrol *kcontrol,
307
+
struct snd_ctl_elem_value *ucontrol)
308
+
{
309
+
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
310
+
int ret = 0;
311
+
312
+
ret = pm_runtime_resume_and_get(component->dev);
313
+
if (ret)
314
+
return ret;
315
+
316
+
ret = snd_soc_put_volsw(kcontrol, ucontrol);
317
+
/*
318
+
* As this function only used by the SNDRV_CTL_ELEM_ACCESS_VOLATILE
319
+
* case. return 0 to avoid control event notification.
320
+
*/
321
+
if (ret > 0)
322
+
ret = 0;
323
+
324
+
pm_runtime_put_autosuspend(component->dev);
325
+
326
+
return ret;
327
+
}
328
+
EXPORT_SYMBOL_GPL(fsl_asoc_put_volsw);
200
329
201
330
MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
202
331
MODULE_DESCRIPTION("Freescale ASoC utility code");
+48
sound/soc/fsl/fsl_utils.h
+48
sound/soc/fsl/fsl_utils.h
···
31
31
const struct snd_pcm_hw_constraint_list *original_constr,
32
32
struct clk *pll8k_clk, struct clk *pll11k_clk,
33
33
struct clk *ext_clk, int *target_rates);
34
+
35
+
/* Similar to SOC_SINGLE_XR_SX, but it is for read only registers. */
36
+
#define FSL_ASOC_SINGLE_XR_SX_EXT_RO(xname, xregbase, xregcount, xnbits, \
37
+
xmin, xmax, xinvert, xhandler_get) \
38
+
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
39
+
.access = SNDRV_CTL_ELEM_ACCESS_READ | \
40
+
SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
41
+
.info = snd_soc_info_xr_sx, .get = xhandler_get, \
42
+
.private_value = (unsigned long)&(struct soc_mreg_control) \
43
+
{.regbase = xregbase, .regcount = xregcount, .nbits = xnbits, \
44
+
.invert = xinvert, .min = xmin, .max = xmax} }
45
+
46
+
/* Similar to SOC_SINGLE_EXT, but it is for volatile register. */
47
+
#define FSL_ASOC_SINGLE_EXT(xname, xreg, xshift, xmax, xinvert,\
48
+
xhandler_get, xhandler_put) \
49
+
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
50
+
.access = SNDRV_CTL_ELEM_ACCESS_VOLATILE | \
51
+
SNDRV_CTL_ELEM_ACCESS_READWRITE, \
52
+
.info = snd_soc_info_volsw, \
53
+
.get = xhandler_get, .put = xhandler_put, \
54
+
.private_value = SOC_SINGLE_VALUE(xreg, xshift, 0, xmax, xinvert, 0) }
55
+
56
+
#define FSL_ASOC_ENUM_EXT(xname, xenum, xhandler_get, xhandler_put) \
57
+
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
58
+
.access = SNDRV_CTL_ELEM_ACCESS_VOLATILE | \
59
+
SNDRV_CTL_ELEM_ACCESS_READWRITE, \
60
+
.info = snd_soc_info_enum_double, \
61
+
.get = xhandler_get, .put = xhandler_put, \
62
+
.private_value = (unsigned long)&xenum }
63
+
64
+
int fsl_asoc_get_xr_sx(struct snd_kcontrol *kcontrol,
65
+
struct snd_ctl_elem_value *ucontrol);
66
+
67
+
int fsl_asoc_put_xr_sx(struct snd_kcontrol *kcontrol,
68
+
struct snd_ctl_elem_value *ucontrol);
69
+
70
+
int fsl_asoc_get_enum_double(struct snd_kcontrol *kcontrol,
71
+
struct snd_ctl_elem_value *ucontrol);
72
+
73
+
int fsl_asoc_put_enum_double(struct snd_kcontrol *kcontrol,
74
+
struct snd_ctl_elem_value *ucontrol);
75
+
76
+
int fsl_asoc_get_volsw(struct snd_kcontrol *kcontrol,
77
+
struct snd_ctl_elem_value *ucontrol);
78
+
79
+
int fsl_asoc_put_volsw(struct snd_kcontrol *kcontrol,
80
+
struct snd_ctl_elem_value *ucontrol);
81
+
34
82
#endif /* _FSL_UTILS_H */
+64
sound/soc/fsl/fsl_xcvr.c
+64
sound/soc/fsl/fsl_xcvr.c
···
62
62
u32 spdif_constr_rates_list[SPDIF_NUM_RATES];
63
63
};
64
64
65
+
static const char * const inc_mode[] = {
66
+
"On enabled and bitcount increment", "On enabled"
67
+
};
68
+
69
+
static SOC_ENUM_SINGLE_DECL(transmit_tstmp_enum,
70
+
FSL_XCVR_TX_DPTH_CNTR_CTRL,
71
+
FSL_XCVR_TX_DPTH_CNTR_CTRL_TSINC_SHIFT, inc_mode);
72
+
static SOC_ENUM_SINGLE_DECL(receive_tstmp_enum,
73
+
FSL_XCVR_RX_DPTH_CNTR_CTRL,
74
+
FSL_XCVR_RX_DPTH_CNTR_CTRL_TSINC_SHIFT, inc_mode);
75
+
76
+
static const struct snd_kcontrol_new fsl_xcvr_timestamp_ctrls[] = {
77
+
FSL_ASOC_SINGLE_EXT("Transmit Timestamp Control Switch", FSL_XCVR_TX_DPTH_CNTR_CTRL,
78
+
FSL_XCVR_TX_DPTH_CNTR_CTRL_TSEN_SHIFT, 1, 0,
79
+
fsl_asoc_get_volsw, fsl_asoc_put_volsw),
80
+
FSL_ASOC_ENUM_EXT("Transmit Timestamp Increment", transmit_tstmp_enum,
81
+
fsl_asoc_get_enum_double, fsl_asoc_put_enum_double),
82
+
FSL_ASOC_SINGLE_EXT("Transmit Timestamp Reset Switch", FSL_XCVR_TX_DPTH_CNTR_CTRL,
83
+
FSL_XCVR_TX_DPTH_CNTR_CTRL_RTSC_SHIFT, 1, 0,
84
+
fsl_asoc_get_volsw, fsl_asoc_put_volsw),
85
+
FSL_ASOC_SINGLE_EXT("Transmit Bit Counter Reset Switch", FSL_XCVR_TX_DPTH_CNTR_CTRL,
86
+
FSL_XCVR_TX_DPTH_CNTR_CTRL_RBC_SHIFT, 1, 0,
87
+
fsl_asoc_get_volsw, fsl_asoc_put_volsw),
88
+
FSL_ASOC_SINGLE_XR_SX_EXT_RO("Transmit Timestamp Counter", FSL_XCVR_TX_DPTH_TSCR,
89
+
1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx),
90
+
FSL_ASOC_SINGLE_XR_SX_EXT_RO("Transmit Bit Counter", FSL_XCVR_TX_DPTH_BCR,
91
+
1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx),
92
+
FSL_ASOC_SINGLE_XR_SX_EXT_RO("Transmit Bit Count Timestamp", FSL_XCVR_TX_DPTH_BCTR,
93
+
1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx),
94
+
FSL_ASOC_SINGLE_XR_SX_EXT_RO("Transmit Latched Timestamp Counter", FSL_XCVR_TX_DPTH_BCRR,
95
+
1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx),
96
+
FSL_ASOC_SINGLE_EXT("Receive Timestamp Control Switch", FSL_XCVR_RX_DPTH_CNTR_CTRL,
97
+
FSL_XCVR_RX_DPTH_CNTR_CTRL_TSEN_SHIFT, 1, 0,
98
+
fsl_asoc_get_volsw, fsl_asoc_put_volsw),
99
+
FSL_ASOC_ENUM_EXT("Receive Timestamp Increment", receive_tstmp_enum,
100
+
fsl_asoc_get_enum_double, fsl_asoc_put_enum_double),
101
+
FSL_ASOC_SINGLE_EXT("Receive Timestamp Reset Switch", FSL_XCVR_RX_DPTH_CNTR_CTRL,
102
+
FSL_XCVR_RX_DPTH_CNTR_CTRL_RTSC_SHIFT, 1, 0,
103
+
fsl_asoc_get_volsw, fsl_asoc_put_volsw),
104
+
FSL_ASOC_SINGLE_EXT("Receive Bit Counter Reset Switch", FSL_XCVR_RX_DPTH_CNTR_CTRL,
105
+
FSL_XCVR_RX_DPTH_CNTR_CTRL_RBC_SHIFT, 1, 0,
106
+
fsl_asoc_get_volsw, fsl_asoc_put_volsw),
107
+
FSL_ASOC_SINGLE_XR_SX_EXT_RO("Receive Timestamp Counter", FSL_XCVR_RX_DPTH_TSCR,
108
+
1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx),
109
+
FSL_ASOC_SINGLE_XR_SX_EXT_RO("Receive Bit Counter", FSL_XCVR_RX_DPTH_BCR,
110
+
1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx),
111
+
FSL_ASOC_SINGLE_XR_SX_EXT_RO("Receive Bit Count Timestamp", FSL_XCVR_RX_DPTH_BCTR,
112
+
1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx),
113
+
FSL_ASOC_SINGLE_XR_SX_EXT_RO("Receive Latched Timestamp Counter", FSL_XCVR_RX_DPTH_BCRR,
114
+
1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx),
115
+
};
116
+
65
117
static const struct fsl_xcvr_pll_conf {
66
118
u8 mfi; /* min=0x18, max=0x38 */
67
119
u32 mfn; /* signed int, 2's compl., min=0x3FFF0000, max=0x00010000 */
···
1122
1070
},
1123
1071
};
1124
1072
1073
+
static int fsl_xcvr_component_probe(struct snd_soc_component *component)
1074
+
{
1075
+
struct fsl_xcvr *xcvr = snd_soc_component_get_drvdata(component);
1076
+
1077
+
snd_soc_component_init_regmap(component, xcvr->regmap);
1078
+
1079
+
return 0;
1080
+
}
1081
+
1125
1082
static const struct snd_soc_component_driver fsl_xcvr_comp = {
1126
1083
.name = "fsl-xcvr-dai",
1084
+
.probe = fsl_xcvr_component_probe,
1085
+
.controls = fsl_xcvr_timestamp_ctrls,
1086
+
.num_controls = ARRAY_SIZE(fsl_xcvr_timestamp_ctrls),
1127
1087
.legacy_dai_naming = 1,
1128
1088
};
1129
1089
+18
sound/soc/fsl/fsl_xcvr.h
+18
sound/soc/fsl/fsl_xcvr.h
···
233
233
#define FSL_XCVR_TX_DPTH_CTRL_CLK_RATIO BIT(29)
234
234
#define FSL_XCVR_TX_DPTH_CTRL_TM_NO_PRE_BME GENMASK(31, 30)
235
235
236
+
#define FSL_XCVR_RX_DPTH_CNTR_CTRL_TSEN_SHIFT 0
237
+
#define FSL_XCVR_RX_DPTH_CNTR_CTRL_TSEN BIT(0)
238
+
#define FSL_XCVR_RX_DPTH_CNTR_CTRL_TSINC_SHIFT 1
239
+
#define FSL_XCVR_RX_DPTH_CNTR_CTRL_TSINC BIT(1)
240
+
#define FSL_XCVR_RX_DPTH_CNTR_CTRL_RBC_SHIFT 8
241
+
#define FSL_XCVR_RX_DPTH_CNTR_CTRL_RBC BIT(8)
242
+
#define FSL_XCVR_RX_DPTH_CNTR_CTRL_RTSC_SHIFT 9
243
+
#define FSL_XCVR_RX_DPTH_CNTR_CTRL_RTSC BIT(9)
244
+
245
+
#define FSL_XCVR_TX_DPTH_CNTR_CTRL_TSEN_SHIFT 0
246
+
#define FSL_XCVR_TX_DPTH_CNTR_CTRL_TSEN BIT(0)
247
+
#define FSL_XCVR_TX_DPTH_CNTR_CTRL_TSINC_SHIFT 1
248
+
#define FSL_XCVR_TX_DPTH_CNTR_CTRL_TSINC BIT(1)
249
+
#define FSL_XCVR_TX_DPTH_CNTR_CTRL_RBC_SHIFT 8
250
+
#define FSL_XCVR_TX_DPTH_CNTR_CTRL_RBC BIT(8)
251
+
#define FSL_XCVR_TX_DPTH_CNTR_CTRL_RTSC_SHIFT 9
252
+
#define FSL_XCVR_TX_DPTH_CNTR_CTRL_RTSC BIT(9)
253
+
236
254
#define FSL_XCVR_PHY_AI_CTRL_AI_RESETN BIT(15)
237
255
#define FSL_XCVR_PHY_AI_CTRL_AI_RWB BIT(31)
238
256