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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
clk: qcom: gcc-sm6115: Override default Alpha PLL regs
The DEFAULT and BRAMMO PLL offsets are non-standard in downstream, but
currently only BRAMMO ones are overridden. Override DEFAULT ones too.
A very similar thing is happening in gcc-qcm2290 driver.
Fixes: cbe63bfdc54f ("clk: qcom: Add Global Clock controller (GCC) driver for SM6115")
Signed-off-by: Adam Skladowski <a_skl39@protonmail.com>
Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220830075620.974009-2-iskren.chernev@gmail.com
authored by
Adam Skladowski
and committed by
Bjorn Andersson
068a0605
16fb89f9
+30
-16
+30
-16
drivers/clk/qcom/gcc-sm6115.c
+30
-16
drivers/clk/qcom/gcc-sm6115.c
···
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{ 750000000, 1500000000, 1 },
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};
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+
static const u8 clk_alpha_pll_regs_offset[][PLL_OFF_MAX_REGS] = {
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[CLK_ALPHA_PLL_TYPE_DEFAULT] = {
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[PLL_OFF_L_VAL] = 0x04,
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[PLL_OFF_ALPHA_VAL] = 0x08,
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[PLL_OFF_ALPHA_VAL_U] = 0x0c,
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[PLL_OFF_TEST_CTL] = 0x10,
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[PLL_OFF_TEST_CTL_U] = 0x14,
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[PLL_OFF_USER_CTL] = 0x18,
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[PLL_OFF_USER_CTL_U] = 0x1c,
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[PLL_OFF_CONFIG_CTL] = 0x20,
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[PLL_OFF_STATUS] = 0x24,
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},
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};
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+
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static struct clk_alpha_pll gpll0 = {
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.offset = 0x0,
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.vco_table = default_vco,
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.num_vco = ARRAY_SIZE(default_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.clkr = {
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.enable_reg = 0x79000,
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.enable_mask = BIT(0),
···
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.post_div_table = post_div_table_gpll0_out_aux2,
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.num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_aux2),
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.width = 4,
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gpll0_out_aux2",
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.parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
···
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.post_div_table = post_div_table_gpll0_out_main,
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.num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_main),
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.width = 4,
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gpll0_out_main",
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.parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
···
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.offset = 0xa000,
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.vco_table = gpll10_vco,
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.num_vco = ARRAY_SIZE(gpll10_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.clkr = {
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.enable_reg = 0x79000,
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.enable_mask = BIT(10),
···
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.post_div_table = post_div_table_gpll10_out_main,
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.num_post_div = ARRAY_SIZE(post_div_table_gpll10_out_main),
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.width = 4,
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gpll10_out_main",
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.parent_hws = (const struct clk_hw *[]){ &gpll10.clkr.hw },
···
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.vco_table = default_vco,
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.num_vco = ARRAY_SIZE(default_vco),
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.flags = SUPPORTS_DYNAMIC_UPDATE,
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.clkr = {
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.enable_reg = 0x79000,
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.enable_mask = BIT(11),
···
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.post_div_table = post_div_table_gpll11_out_main,
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.num_post_div = ARRAY_SIZE(post_div_table_gpll11_out_main),
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.width = 4,
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gpll11_out_main",
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.parent_hws = (const struct clk_hw *[]){ &gpll11.clkr.hw },
···
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.offset = 0x3000,
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.vco_table = default_vco,
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.num_vco = ARRAY_SIZE(default_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.clkr = {
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.enable_reg = 0x79000,
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.enable_mask = BIT(3),
···
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.offset = 0x4000,
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.vco_table = default_vco,
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.num_vco = ARRAY_SIZE(default_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.clkr = {
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.enable_reg = 0x79000,
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.enable_mask = BIT(4),
···
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.post_div_table = post_div_table_gpll4_out_main,
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.num_post_div = ARRAY_SIZE(post_div_table_gpll4_out_main),
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.width = 4,
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gpll4_out_main",
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.parent_hws = (const struct clk_hw *[]){ &gpll4.clkr.hw },
···
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.offset = 0x6000,
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.vco_table = default_vco,
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.num_vco = ARRAY_SIZE(default_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.clkr = {
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.enable_reg = 0x79000,
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.enable_mask = BIT(6),
···
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.post_div_table = post_div_table_gpll6_out_main,
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.num_post_div = ARRAY_SIZE(post_div_table_gpll6_out_main),
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.width = 4,
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gpll6_out_main",
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.parent_hws = (const struct clk_hw *[]){ &gpll6.clkr.hw },
···
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.offset = 0x7000,
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.vco_table = default_vco,
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.num_vco = ARRAY_SIZE(default_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.clkr = {
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.enable_reg = 0x79000,
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.enable_mask = BIT(7),
···
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.post_div_table = post_div_table_gpll7_out_main,
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.num_post_div = ARRAY_SIZE(post_div_table_gpll7_out_main),
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.width = 4,
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gpll7_out_main",
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.parent_hws = (const struct clk_hw *[]){ &gpll7.clkr.hw },
···
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.offset = 0x8000,
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.vco_table = default_vco,
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.num_vco = ARRAY_SIZE(default_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.flags = SUPPORTS_DYNAMIC_UPDATE,
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.clkr = {
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.enable_reg = 0x79000,
···
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.post_div_table = post_div_table_gpll8_out_main,
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.num_post_div = ARRAY_SIZE(post_div_table_gpll8_out_main),
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.width = 4,
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gpll8_out_main",
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.parent_hws = (const struct clk_hw *[]){ &gpll8.clkr.hw },