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pinctrl: qcom: Drop redundant intr_target_reg on modern SoCs

On all Qualcomm TLMM generations from APQ8084 onwards, the interrupt
target routing bits are located in the same register as the interrupt
configuration bits (intr_cfg_reg). Only five older SoCs — APQ8064,
IPQ8064, MDM9615, MSM8660 and MSM8960 — have a genuinely separate
interrupt target routing register at a different offset (0x400 + 0x4 * id).

Replace MSM_ACCESSOR(intr_target) with a custom accessor that falls back
to intr_cfg_reg when intr_target_reg is zero. Apply the same fallback in
the SCM path. Drop the now-redundant .intr_target_reg initializer from
all SoC drivers where it duplicated intr_cfg_reg, keeping it only in
the five drivers where it genuinely differs.

Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>

authored by

Mukesh Ojha and committed by
Linus Walleij 0720208b fe8933c5

+23 -138
-2
drivers/pinctrl/qcom/pinctrl-apq8084.c
··· 343 343 .io_reg = 0x1004 + 0x10 * id, \ 344 344 .intr_cfg_reg = 0x1008 + 0x10 * id, \ 345 345 .intr_status_reg = 0x100c + 0x10 * id, \ 346 - .intr_target_reg = 0x1008 + 0x10 * id, \ 347 346 .mux_bit = 2, \ 348 347 .pull_bit = 0, \ 349 348 .drv_bit = 6, \ ··· 369 370 .io_reg = 0, \ 370 371 .intr_cfg_reg = 0, \ 371 372 .intr_status_reg = 0, \ 372 - .intr_target_reg = 0, \ 373 373 .mux_bit = -1, \ 374 374 .pull_bit = pull, \ 375 375 .drv_bit = drv, \
-3
drivers/pinctrl/qcom/pinctrl-eliza.c
··· 34 34 .io_reg = 0x4 + REG_SIZE * id, \ 35 35 .intr_cfg_reg = 0x8 + REG_SIZE * id, \ 36 36 .intr_status_reg = 0xc + REG_SIZE * id, \ 37 - .intr_target_reg = 0x8 + REG_SIZE * id, \ 38 37 .mux_bit = 2, \ 39 38 .pull_bit = 0, \ 40 39 .drv_bit = 6, \ ··· 63 64 .io_reg = 0, \ 64 65 .intr_cfg_reg = 0, \ 65 66 .intr_status_reg = 0, \ 66 - .intr_target_reg = 0, \ 67 67 .mux_bit = -1, \ 68 68 .pull_bit = pull, \ 69 69 .drv_bit = drv, \ ··· 87 89 .io_reg = io, \ 88 90 .intr_cfg_reg = 0, \ 89 91 .intr_status_reg = 0, \ 90 - .intr_target_reg = 0, \ 91 92 .mux_bit = -1, \ 92 93 .pull_bit = 3, \ 93 94 .drv_bit = 0, \
-3
drivers/pinctrl/qcom/pinctrl-glymur.c
··· 21 21 .io_reg = 0x4 + REG_SIZE * id, \ 22 22 .intr_cfg_reg = 0x8 + REG_SIZE * id, \ 23 23 .intr_status_reg = 0xc + REG_SIZE * id, \ 24 - .intr_target_reg = 0x8 + REG_SIZE * id, \ 25 24 .mux_bit = 2, \ 26 25 .pull_bit = 0, \ 27 26 .drv_bit = 6, \ ··· 63 64 .io_reg = 0, \ 64 65 .intr_cfg_reg = 0, \ 65 66 .intr_status_reg = 0, \ 66 - .intr_target_reg = 0, \ 67 67 .mux_bit = -1, \ 68 68 .pull_bit = pull, \ 69 69 .drv_bit = drv, \ ··· 87 89 .io_reg = io, \ 88 90 .intr_cfg_reg = 0, \ 89 91 .intr_status_reg = 0, \ 90 - .intr_target_reg = 0, \ 91 92 .mux_bit = -1, \ 92 93 .pull_bit = 3, \ 93 94 .drv_bit = 0, \
-1
drivers/pinctrl/qcom/pinctrl-ipq4019.c
··· 242 242 .io_reg = 0x4 + 0x1000 * id, \ 243 243 .intr_cfg_reg = 0x8 + 0x1000 * id, \ 244 244 .intr_status_reg = 0xc + 0x1000 * id, \ 245 - .intr_target_reg = 0x8 + 0x1000 * id, \ 246 245 .mux_bit = 2, \ 247 246 .pull_bit = 0, \ 248 247 .drv_bit = 6, \
-1
drivers/pinctrl/qcom/pinctrl-ipq5018.c
··· 32 32 .io_reg = 0x4 + REG_SIZE * id, \ 33 33 .intr_cfg_reg = 0x8 + REG_SIZE * id, \ 34 34 .intr_status_reg = 0xc + REG_SIZE * id, \ 35 - .intr_target_reg = 0x8 + REG_SIZE * id, \ 36 35 .mux_bit = 2, \ 37 36 .pull_bit = 0, \ 38 37 .drv_bit = 6, \
-1
drivers/pinctrl/qcom/pinctrl-ipq5332.c
··· 32 32 .io_reg = 0x4 + REG_SIZE * id, \ 33 33 .intr_cfg_reg = 0x8 + REG_SIZE * id, \ 34 34 .intr_status_reg = 0xc + REG_SIZE * id, \ 35 - .intr_target_reg = 0x8 + REG_SIZE * id, \ 36 35 .mux_bit = 2, \ 37 36 .pull_bit = 0, \ 38 37 .drv_bit = 6, \
-1
drivers/pinctrl/qcom/pinctrl-ipq5424.c
··· 33 33 .io_reg = 0x4 + REG_SIZE * id, \ 34 34 .intr_cfg_reg = 0x8 + REG_SIZE * id, \ 35 35 .intr_status_reg = 0xc + REG_SIZE * id, \ 36 - .intr_target_reg = 0x8 + REG_SIZE * id, \ 37 36 .mux_bit = 2, \ 38 37 .pull_bit = 0, \ 39 38 .drv_bit = 6, \
-1
drivers/pinctrl/qcom/pinctrl-ipq6018.c
··· 32 32 .io_reg = 0x4 + REG_SIZE * id, \ 33 33 .intr_cfg_reg = 0x8 + REG_SIZE * id, \ 34 34 .intr_status_reg = 0xc + REG_SIZE * id, \ 35 - .intr_target_reg = 0x8 + REG_SIZE * id, \ 36 35 .mux_bit = 2, \ 37 36 .pull_bit = 0, \ 38 37 .drv_bit = 6, \
-1
drivers/pinctrl/qcom/pinctrl-ipq8074.c
··· 32 32 .io_reg = 0x4 + REG_SIZE * id, \ 33 33 .intr_cfg_reg = 0x8 + REG_SIZE * id, \ 34 34 .intr_status_reg = 0xc + REG_SIZE * id, \ 35 - .intr_target_reg = 0x8 + REG_SIZE * id, \ 36 35 .mux_bit = 2, \ 37 36 .pull_bit = 0, \ 38 37 .drv_bit = 6, \
-1
drivers/pinctrl/qcom/pinctrl-ipq9574.c
··· 32 32 .io_reg = 0x4 + REG_SIZE * id, \ 33 33 .intr_cfg_reg = 0x8 + REG_SIZE * id, \ 34 34 .intr_status_reg = 0xc + REG_SIZE * id, \ 35 - .intr_target_reg = 0x8 + REG_SIZE * id, \ 36 35 .mux_bit = 2, \ 37 36 .pull_bit = 0, \ 38 37 .drv_bit = 6, \
-3
drivers/pinctrl/qcom/pinctrl-kaanapali.c
··· 34 34 .io_reg = 0x4 + REG_SIZE * id, \ 35 35 .intr_cfg_reg = 0x8 + REG_SIZE * id, \ 36 36 .intr_status_reg = 0xc + REG_SIZE * id, \ 37 - .intr_target_reg = 0x8 + REG_SIZE * id, \ 38 37 .mux_bit = 2, \ 39 38 .pull_bit = 0, \ 40 39 .drv_bit = 6, \ ··· 63 64 .io_reg = 0, \ 64 65 .intr_cfg_reg = 0, \ 65 66 .intr_status_reg = 0, \ 66 - .intr_target_reg = 0, \ 67 67 .mux_bit = -1, \ 68 68 .pull_bit = pull, \ 69 69 .drv_bit = drv, \ ··· 87 89 .io_reg = io, \ 88 90 .intr_cfg_reg = 0, \ 89 91 .intr_status_reg = 0, \ 90 - .intr_target_reg = 0, \ 91 92 .mux_bit = -1, \ 92 93 .pull_bit = 3, \ 93 94 .drv_bit = 0, \
-2
drivers/pinctrl/qcom/pinctrl-mdm9607.c
··· 225 225 .io_reg = 0x4 + 0x1000 * id, \ 226 226 .intr_cfg_reg = 0x8 + 0x1000 * id, \ 227 227 .intr_status_reg = 0xc + 0x1000 * id, \ 228 - .intr_target_reg = 0x8 + 0x1000 * id, \ 229 228 .mux_bit = 2, \ 230 229 .pull_bit = 0, \ 231 230 .drv_bit = 6, \ ··· 250 251 .io_reg = 0, \ 251 252 .intr_cfg_reg = 0, \ 252 253 .intr_status_reg = 0, \ 253 - .intr_target_reg = 0, \ 254 254 .mux_bit = -1, \ 255 255 .pull_bit = pull, \ 256 256 .drv_bit = drv, \
-3
drivers/pinctrl/qcom/pinctrl-milos.c
··· 36 36 .io_reg = 0x4 + REG_SIZE * id, \ 37 37 .intr_cfg_reg = 0x8 + REG_SIZE * id, \ 38 38 .intr_status_reg = 0xc + REG_SIZE * id, \ 39 - .intr_target_reg = 0x8 + REG_SIZE * id, \ 40 39 .mux_bit = 2, \ 41 40 .pull_bit = 0, \ 42 41 .drv_bit = 6, \ ··· 66 67 .io_reg = 0, \ 67 68 .intr_cfg_reg = 0, \ 68 69 .intr_status_reg = 0, \ 69 - .intr_target_reg = 0, \ 70 70 .mux_bit = -1, \ 71 71 .pull_bit = pull, \ 72 72 .drv_bit = drv, \ ··· 90 92 .io_reg = io, \ 91 93 .intr_cfg_reg = 0, \ 92 94 .intr_status_reg = 0, \ 93 - .intr_target_reg = 0, \ 94 95 .mux_bit = -1, \ 95 96 .pull_bit = 3, \ 96 97 .drv_bit = 0, \
+18 -2
drivers/pinctrl/qcom/pinctrl-msm.c
··· 98 98 MSM_ACCESSOR(io) 99 99 MSM_ACCESSOR(intr_cfg) 100 100 MSM_ACCESSOR(intr_status) 101 - MSM_ACCESSOR(intr_target) 101 + 102 + static u32 msm_readl_intr_target(struct msm_pinctrl *pctrl, 103 + const struct msm_pingroup *g) 104 + { 105 + u32 reg = g->intr_target_reg ? g->intr_target_reg : g->intr_cfg_reg; 106 + 107 + return readl(pctrl->regs[g->tile] + reg); 108 + } 109 + 110 + static void msm_writel_intr_target(u32 val, struct msm_pinctrl *pctrl, 111 + const struct msm_pingroup *g) 112 + { 113 + u32 reg = g->intr_target_reg ? g->intr_target_reg : g->intr_cfg_reg; 114 + 115 + writel(val, pctrl->regs[g->tile] + reg); 116 + } 102 117 103 118 static void msm_ack_intr_status(struct msm_pinctrl *pctrl, 104 119 const struct msm_pingroup *g) ··· 1093 1078 intr_target_mask = GENMASK(g->intr_target_width - 1, 0); 1094 1079 1095 1080 if (pctrl->intr_target_use_scm) { 1096 - u32 addr = pctrl->phys_base[0] + g->intr_target_reg; 1081 + u32 reg = g->intr_target_reg ? g->intr_target_reg : g->intr_cfg_reg; 1082 + u32 addr = pctrl->phys_base[0] + reg; 1097 1083 int ret; 1098 1084 1099 1085 qcom_scm_io_readl(addr, &val);
+5 -1
drivers/pinctrl/qcom/pinctrl-msm.h
··· 52 52 * @intr_cfg_reg: Offset of the register holding interrupt configuration bits. 53 53 * @intr_status_reg: Offset of the register holding the status bits for this group. 54 54 * @intr_target_reg: Offset of the register specifying routing of the interrupts 55 - * from this group. 55 + * from this group. On most SoCs this register is the same as 56 + * @intr_cfg_reg; leaving this field as zero causes the driver 57 + * to fall back to @intr_cfg_reg automatically. Only set this 58 + * explicitly on older SoCs where the interrupt target routing 59 + * lives in a separate register (e.g. APQ8064, MSM8960). 56 60 * @mux_bit: Offset in @ctl_reg for the pinmux function selection. 57 61 * @pull_bit: Offset in @ctl_reg for the bias configuration. 58 62 * @drv_bit: Offset in @ctl_reg for the drive strength configuration.
-2
drivers/pinctrl/qcom/pinctrl-msm8226.c
··· 282 282 .io_reg = 0x1004 + 0x10 * id, \ 283 283 .intr_cfg_reg = 0x1008 + 0x10 * id, \ 284 284 .intr_status_reg = 0x100c + 0x10 * id, \ 285 - .intr_target_reg = 0x1008 + 0x10 * id, \ 286 285 .mux_bit = 2, \ 287 286 .pull_bit = 0, \ 288 287 .drv_bit = 6, \ ··· 307 308 .io_reg = 0, \ 308 309 .intr_cfg_reg = 0, \ 309 310 .intr_status_reg = 0, \ 310 - .intr_target_reg = 0, \ 311 311 .mux_bit = -1, \ 312 312 .pull_bit = pull, \ 313 313 .drv_bit = drv, \
-2
drivers/pinctrl/qcom/pinctrl-msm8909.c
··· 33 33 .io_reg = 0x4 + REG_SIZE * id, \ 34 34 .intr_cfg_reg = 0x8 + REG_SIZE * id, \ 35 35 .intr_status_reg = 0xc + REG_SIZE * id, \ 36 - .intr_target_reg = 0x8 + REG_SIZE * id, \ 37 36 .mux_bit = 2, \ 38 37 .pull_bit = 0, \ 39 38 .drv_bit = 6, \ ··· 58 59 .io_reg = 0, \ 59 60 .intr_cfg_reg = 0, \ 60 61 .intr_status_reg = 0, \ 61 - .intr_target_reg = 0, \ 62 62 .mux_bit = -1, \ 63 63 .pull_bit = pull, \ 64 64 .drv_bit = drv, \
-2
drivers/pinctrl/qcom/pinctrl-msm8916.c
··· 307 307 .io_reg = 0x4 + 0x1000 * id, \ 308 308 .intr_cfg_reg = 0x8 + 0x1000 * id, \ 309 309 .intr_status_reg = 0xc + 0x1000 * id, \ 310 - .intr_target_reg = 0x8 + 0x1000 * id, \ 311 310 .mux_bit = 2, \ 312 311 .pull_bit = 0, \ 313 312 .drv_bit = 6, \ ··· 332 333 .io_reg = 0, \ 333 334 .intr_cfg_reg = 0, \ 334 335 .intr_status_reg = 0, \ 335 - .intr_target_reg = 0, \ 336 336 .mux_bit = -1, \ 337 337 .pull_bit = pull, \ 338 338 .drv_bit = drv, \
-2
drivers/pinctrl/qcom/pinctrl-msm8917.c
··· 333 333 .io_reg = 0x4 + 0x1000 * id, \ 334 334 .intr_cfg_reg = 0x8 + 0x1000 * id, \ 335 335 .intr_status_reg = 0xc + 0x1000 * id, \ 336 - .intr_target_reg = 0x8 + 0x1000 * id, \ 337 336 .mux_bit = 2, \ 338 337 .pull_bit = 0, \ 339 338 .drv_bit = 6, \ ··· 358 359 .io_reg = 0, \ 359 360 .intr_cfg_reg = 0, \ 360 361 .intr_status_reg = 0, \ 361 - .intr_target_reg = 0, \ 362 362 .mux_bit = -1, \ 363 363 .pull_bit = pull, \ 364 364 .drv_bit = drv, \
-2
drivers/pinctrl/qcom/pinctrl-msm8953.c
··· 29 29 .io_reg = 0x4 + 0x1000 * id, \ 30 30 .intr_cfg_reg = 0x8 + 0x1000 * id, \ 31 31 .intr_status_reg = 0xc + 0x1000 * id, \ 32 - .intr_target_reg = 0x8 + 0x1000 * id, \ 33 32 .mux_bit = 2, \ 34 33 .pull_bit = 0, \ 35 34 .drv_bit = 6, \ ··· 54 55 .io_reg = 0, \ 55 56 .intr_cfg_reg = 0, \ 56 57 .intr_status_reg = 0, \ 57 - .intr_target_reg = 0, \ 58 58 .mux_bit = -1, \ 59 59 .pull_bit = pull, \ 60 60 .drv_bit = drv, \
-2
drivers/pinctrl/qcom/pinctrl-msm8976.c
··· 35 35 .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \ 36 36 .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \ 37 37 .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \ 38 - .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \ 39 38 .mux_bit = 2, \ 40 39 .pull_bit = 0, \ 41 40 .drv_bit = 6, \ ··· 60 61 .io_reg = 0, \ 61 62 .intr_cfg_reg = 0, \ 62 63 .intr_status_reg = 0, \ 63 - .intr_target_reg = 0, \ 64 64 .mux_bit = -1, \ 65 65 .pull_bit = pull, \ 66 66 .drv_bit = drv, \
-2
drivers/pinctrl/qcom/pinctrl-msm8994.c
··· 33 33 .io_reg = 0x1004 + 0x10 * id, \ 34 34 .intr_cfg_reg = 0x1008 + 0x10 * id, \ 35 35 .intr_status_reg = 0x100c + 0x10 * id, \ 36 - .intr_target_reg = 0x1008 + 0x10 * id, \ 37 36 .mux_bit = 2, \ 38 37 .pull_bit = 0, \ 39 38 .drv_bit = 6, \ ··· 58 59 .io_reg = 0, \ 59 60 .intr_cfg_reg = 0, \ 60 61 .intr_status_reg = 0, \ 61 - .intr_target_reg = 0, \ 62 62 .mux_bit = -1, \ 63 63 .pull_bit = pull, \ 64 64 .drv_bit = drv, \
-2
drivers/pinctrl/qcom/pinctrl-msm8996.c
··· 33 33 .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \ 34 34 .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \ 35 35 .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \ 36 - .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \ 37 36 .mux_bit = 2, \ 38 37 .pull_bit = 0, \ 39 38 .drv_bit = 6, \ ··· 58 59 .io_reg = 0, \ 59 60 .intr_cfg_reg = 0, \ 60 61 .intr_status_reg = 0, \ 61 - .intr_target_reg = 0, \ 62 62 .mux_bit = -1, \ 63 63 .pull_bit = pull, \ 64 64 .drv_bit = drv, \
-3
drivers/pinctrl/qcom/pinctrl-msm8998.c
··· 35 35 .io_reg = base + 0x4 + 0x1000 * id, \ 36 36 .intr_cfg_reg = base + 0x8 + 0x1000 * id, \ 37 37 .intr_status_reg = base + 0xc + 0x1000 * id, \ 38 - .intr_target_reg = base + 0x8 + 0x1000 * id, \ 39 38 .mux_bit = 2, \ 40 39 .pull_bit = 0, \ 41 40 .drv_bit = 6, \ ··· 60 61 .io_reg = 0, \ 61 62 .intr_cfg_reg = 0, \ 62 63 .intr_status_reg = 0, \ 63 - .intr_target_reg = 0, \ 64 64 .mux_bit = -1, \ 65 65 .pull_bit = pull, \ 66 66 .drv_bit = drv, \ ··· 84 86 .io_reg = offset + 0x4, \ 85 87 .intr_cfg_reg = 0, \ 86 88 .intr_status_reg = 0, \ 87 - .intr_target_reg = 0, \ 88 89 .mux_bit = -1, \ 89 90 .pull_bit = 3, \ 90 91 .drv_bit = 0, \
-3
drivers/pinctrl/qcom/pinctrl-msm8x74.c
··· 344 344 .io_reg = 0x1004 + 0x10 * id, \ 345 345 .intr_cfg_reg = 0x1008 + 0x10 * id, \ 346 346 .intr_status_reg = 0x100c + 0x10 * id, \ 347 - .intr_target_reg = 0x1008 + 0x10 * id, \ 348 347 .mux_bit = 2, \ 349 348 .pull_bit = 0, \ 350 349 .drv_bit = 6, \ ··· 369 370 .io_reg = 0, \ 370 371 .intr_cfg_reg = 0, \ 371 372 .intr_status_reg = 0, \ 372 - .intr_target_reg = 0, \ 373 373 .mux_bit = -1, \ 374 374 .pull_bit = pull, \ 375 375 .drv_bit = drv, \ ··· 399 401 .io_reg = 0, \ 400 402 .intr_cfg_reg = 0, \ 401 403 .intr_status_reg = 0, \ 402 - .intr_target_reg = 0, \ 403 404 .mux_bit = 25, \ 404 405 .pull_bit = -1, \ 405 406 .drv_bit = -1, \
-3
drivers/pinctrl/qcom/pinctrl-qcm2290.c
··· 33 33 .io_reg = 0x4 + REG_SIZE * id, \ 34 34 .intr_cfg_reg = 0x8 + REG_SIZE * id, \ 35 35 .intr_status_reg = 0xc + REG_SIZE * id, \ 36 - .intr_target_reg = 0x8 + REG_SIZE * id, \ 37 36 .mux_bit = 2, \ 38 37 .pull_bit = 0, \ 39 38 .drv_bit = 6, \ ··· 60 61 .io_reg = 0, \ 61 62 .intr_cfg_reg = 0, \ 62 63 .intr_status_reg = 0, \ 63 - .intr_target_reg = 0, \ 64 64 .mux_bit = -1, \ 65 65 .pull_bit = pull, \ 66 66 .drv_bit = drv, \ ··· 84 86 .io_reg = offset + 0x4, \ 85 87 .intr_cfg_reg = 0, \ 86 88 .intr_status_reg = 0, \ 87 - .intr_target_reg = 0, \ 88 89 .mux_bit = -1, \ 89 90 .pull_bit = 3, \ 90 91 .drv_bit = 0, \
-2
drivers/pinctrl/qcom/pinctrl-qcs404.c
··· 43 43 .io_reg = 0x1000 * id + 0x4, \ 44 44 .intr_cfg_reg = 0x1000 * id + 0x8, \ 45 45 .intr_status_reg = 0x1000 * id + 0xc, \ 46 - .intr_target_reg = 0x1000 * id + 0x8, \ 47 46 .tile = _tile, \ 48 47 .mux_bit = 2, \ 49 48 .pull_bit = 0, \ ··· 69 70 .io_reg = 0, \ 70 71 .intr_cfg_reg = 0, \ 71 72 .intr_status_reg = 0, \ 72 - .intr_target_reg = 0, \ 73 73 .tile = SOUTH, \ 74 74 .mux_bit = -1, \ 75 75 .pull_bit = pull, \
-3
drivers/pinctrl/qcom/pinctrl-qcs615.c
··· 43 43 .io_reg = 0x1000 * id + 0x4, \ 44 44 .intr_cfg_reg = 0x1000 * id + 0x8, \ 45 45 .intr_status_reg = 0x1000 * id + 0xc, \ 46 - .intr_target_reg = 0x1000 * id + 0x8, \ 47 46 .tile = _tile, \ 48 47 .mux_bit = 2, \ 49 48 .pull_bit = 0, \ ··· 69 70 .io_reg = 0, \ 70 71 .intr_cfg_reg = 0, \ 71 72 .intr_status_reg = 0, \ 72 - .intr_target_reg = 0, \ 73 73 .tile = _tile, \ 74 74 .mux_bit = -1, \ 75 75 .pull_bit = pull, \ ··· 94 96 .io_reg = offset + 0x4, \ 95 97 .intr_cfg_reg = 0, \ 96 98 .intr_status_reg = 0, \ 97 - .intr_target_reg = 0, \ 98 99 .tile = WEST, \ 99 100 .mux_bit = -1, \ 100 101 .pull_bit = 3, \
-3
drivers/pinctrl/qcom/pinctrl-qcs8300.c
··· 34 34 .io_reg = 0x4 + REG_SIZE * id, \ 35 35 .intr_cfg_reg = 0x8 + REG_SIZE * id, \ 36 36 .intr_status_reg = 0xc + REG_SIZE * id, \ 37 - .intr_target_reg = 0x8 + REG_SIZE * id, \ 38 37 .mux_bit = 2, \ 39 38 .pull_bit = 0, \ 40 39 .drv_bit = 6, \ ··· 61 62 .io_reg = 0, \ 62 63 .intr_cfg_reg = 0, \ 63 64 .intr_status_reg = 0, \ 64 - .intr_target_reg = 0, \ 65 65 .mux_bit = -1, \ 66 66 .pull_bit = pull, \ 67 67 .drv_bit = drv, \ ··· 85 87 .io_reg = offset + 0x4, \ 86 88 .intr_cfg_reg = 0, \ 87 89 .intr_status_reg = 0, \ 88 - .intr_target_reg = 0, \ 89 90 .mux_bit = -1, \ 90 91 .pull_bit = 3, \ 91 92 .drv_bit = 0, \
-1
drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
··· 106 106 groups[gpio].io_reg = 0x04 + 0x10000 * gpio; 107 107 groups[gpio].intr_cfg_reg = 0x08 + 0x10000 * gpio; 108 108 groups[gpio].intr_status_reg = 0x0c + 0x10000 * gpio; 109 - groups[gpio].intr_target_reg = 0x08 + 0x10000 * gpio; 110 109 111 110 groups[gpio].mux_bit = 2; 112 111 groups[gpio].pull_bit = 0;
-3
drivers/pinctrl/qcom/pinctrl-qdu1000.c
··· 35 35 .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \ 36 36 .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \ 37 37 .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \ 38 - .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \ 39 38 .mux_bit = 2, \ 40 39 .pull_bit = 0, \ 41 40 .drv_bit = 6, \ ··· 60 61 .io_reg = 0, \ 61 62 .intr_cfg_reg = 0, \ 62 63 .intr_status_reg = 0, \ 63 - .intr_target_reg = 0, \ 64 64 .mux_bit = -1, \ 65 65 .pull_bit = pull, \ 66 66 .drv_bit = drv, \ ··· 84 86 .io_reg = offset + 0x4, \ 85 87 .intr_cfg_reg = 0, \ 86 88 .intr_status_reg = 0, \ 87 - .intr_target_reg = 0, \ 88 89 .mux_bit = -1, \ 89 90 .pull_bit = 3, \ 90 91 .drv_bit = 0, \
-3
drivers/pinctrl/qcom/pinctrl-sa8775p.c
··· 34 34 .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \ 35 35 .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \ 36 36 .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \ 37 - .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \ 38 37 .mux_bit = 2, \ 39 38 .pull_bit = 0, \ 40 39 .drv_bit = 6, \ ··· 62 63 .io_reg = 0, \ 63 64 .intr_cfg_reg = 0, \ 64 65 .intr_status_reg = 0, \ 65 - .intr_target_reg = 0, \ 66 66 .mux_bit = -1, \ 67 67 .pull_bit = pull, \ 68 68 .drv_bit = drv, \ ··· 86 88 .io_reg = offset + 0x4, \ 87 89 .intr_cfg_reg = 0, \ 88 90 .intr_status_reg = 0, \ 89 - .intr_target_reg = 0, \ 90 91 .mux_bit = -1, \ 91 92 .pull_bit = 3, \ 92 93 .drv_bit = 0, \
-2
drivers/pinctrl/qcom/pinctrl-sar2130p.c
··· 34 34 .io_reg = 0x4 + REG_SIZE * id, \ 35 35 .intr_cfg_reg = 0x8 + REG_SIZE * id, \ 36 36 .intr_status_reg = 0xc + REG_SIZE * id, \ 37 - .intr_target_reg = 0x8 + REG_SIZE * id, \ 38 37 .mux_bit = 2, \ 39 38 .pull_bit = 0, \ 40 39 .drv_bit = 6, \ ··· 61 62 .io_reg = 0, \ 62 63 .intr_cfg_reg = 0, \ 63 64 .intr_status_reg = 0, \ 64 - .intr_target_reg = 0, \ 65 65 .mux_bit = -1, \ 66 66 .pull_bit = pull, \ 67 67 .drv_bit = drv, \
-3
drivers/pinctrl/qcom/pinctrl-sc7180.c
··· 41 41 .io_reg = 0x1000 * id + 0x4, \ 42 42 .intr_cfg_reg = 0x1000 * id + 0x8, \ 43 43 .intr_status_reg = 0x1000 * id + 0xc, \ 44 - .intr_target_reg = 0x1000 * id + 0x8, \ 45 44 .tile = _tile, \ 46 45 .mux_bit = 2, \ 47 46 .pull_bit = 0, \ ··· 67 68 .io_reg = 0, \ 68 69 .intr_cfg_reg = 0, \ 69 70 .intr_status_reg = 0, \ 70 - .intr_target_reg = 0, \ 71 71 .tile = SOUTH, \ 72 72 .mux_bit = -1, \ 73 73 .pull_bit = pull, \ ··· 92 94 .io_reg = offset + 0x4, \ 93 95 .intr_cfg_reg = 0, \ 94 96 .intr_status_reg = 0, \ 95 - .intr_target_reg = 0, \ 96 97 .tile = SOUTH, \ 97 98 .mux_bit = -1, \ 98 99 .pull_bit = 3, \
-3
drivers/pinctrl/qcom/pinctrl-sc7280.c
··· 31 31 .io_reg = 0x1000 * id + 0x4, \ 32 32 .intr_cfg_reg = 0x1000 * id + 0x8, \ 33 33 .intr_status_reg = 0x1000 * id + 0xc, \ 34 - .intr_target_reg = 0x1000 * id + 0x8, \ 35 34 .mux_bit = 2, \ 36 35 .pull_bit = 0, \ 37 36 .drv_bit = 6, \ ··· 58 59 .io_reg = 0, \ 59 60 .intr_cfg_reg = 0, \ 60 61 .intr_status_reg = 0, \ 61 - .intr_target_reg = 0, \ 62 62 .mux_bit = -1, \ 63 63 .pull_bit = pull, \ 64 64 .drv_bit = drv, \ ··· 82 84 .io_reg = offset + 0x4, \ 83 85 .intr_cfg_reg = 0, \ 84 86 .intr_status_reg = 0, \ 85 - .intr_target_reg = 0, \ 86 87 .mux_bit = -1, \ 87 88 .pull_bit = 3, \ 88 89 .drv_bit = 0, \
-3
drivers/pinctrl/qcom/pinctrl-sc8180x.c
··· 60 60 .io_reg = REG_SIZE * id + 0x4 + offset, \ 61 61 .intr_cfg_reg = REG_SIZE * id + 0x8 + offset, \ 62 62 .intr_status_reg = REG_SIZE * id + 0xc + offset,\ 63 - .intr_target_reg = REG_SIZE * id + 0x8 + offset,\ 64 63 .tile = _tile, \ 65 64 .mux_bit = 2, \ 66 65 .pull_bit = 0, \ ··· 89 90 .io_reg = 0, \ 90 91 .intr_cfg_reg = 0, \ 91 92 .intr_status_reg = 0, \ 92 - .intr_target_reg = 0, \ 93 93 .tile = EAST, \ 94 94 .mux_bit = -1, \ 95 95 .pull_bit = pull, \ ··· 114 116 .io_reg = 0xb6004, \ 115 117 .intr_cfg_reg = 0, \ 116 118 .intr_status_reg = 0, \ 117 - .intr_target_reg = 0, \ 118 119 .tile = SOUTH, \ 119 120 .mux_bit = -1, \ 120 121 .pull_bit = 3, \
-3
drivers/pinctrl/qcom/pinctrl-sc8280xp.c
··· 31 31 .io_reg = 0x4 + REG_SIZE * id, \ 32 32 .intr_cfg_reg = 0x8 + REG_SIZE * id, \ 33 33 .intr_status_reg = 0xc + REG_SIZE * id, \ 34 - .intr_target_reg = 0x8 + REG_SIZE * id, \ 35 34 .mux_bit = 2, \ 36 35 .pull_bit = 0, \ 37 36 .drv_bit = 6, \ ··· 58 59 .io_reg = 0, \ 59 60 .intr_cfg_reg = 0, \ 60 61 .intr_status_reg = 0, \ 61 - .intr_target_reg = 0, \ 62 62 .mux_bit = -1, \ 63 63 .pull_bit = pull, \ 64 64 .drv_bit = drv, \ ··· 82 84 .io_reg = offset + 0x4, \ 83 85 .intr_cfg_reg = 0, \ 84 86 .intr_status_reg = 0, \ 85 - .intr_target_reg = 0, \ 86 87 .mux_bit = -1, \ 87 88 .pull_bit = 3, \ 88 89 .drv_bit = 0, \
-2
drivers/pinctrl/qcom/pinctrl-sdm660.c
··· 46 46 .io_reg = 0x4 + REG_SIZE * id, \ 47 47 .intr_cfg_reg = 0x8 + REG_SIZE * id, \ 48 48 .intr_status_reg = 0xc + REG_SIZE * id, \ 49 - .intr_target_reg = 0x8 + REG_SIZE * id, \ 50 49 .tile = _tile, \ 51 50 .mux_bit = 2, \ 52 51 .pull_bit = 0, \ ··· 72 73 .io_reg = 0, \ 73 74 .intr_cfg_reg = 0, \ 74 75 .intr_status_reg = 0, \ 75 - .intr_target_reg = 0, \ 76 76 .tile = NORTH, \ 77 77 .mux_bit = -1, \ 78 78 .pull_bit = pull, \
-4
drivers/pinctrl/qcom/pinctrl-sdm670.c
··· 37 37 .io_reg = base + 0x4 + REG_SIZE * id, \ 38 38 .intr_cfg_reg = base + 0x8 + REG_SIZE * id, \ 39 39 .intr_status_reg = base + 0xc + REG_SIZE * id, \ 40 - .intr_target_reg = base + 0x8 + REG_SIZE * id, \ 41 40 .mux_bit = 2, \ 42 41 .pull_bit = 0, \ 43 42 .drv_bit = 6, \ ··· 66 67 .io_reg = 0, \ 67 68 .intr_cfg_reg = 0, \ 68 69 .intr_status_reg = 0, \ 69 - .intr_target_reg = 0, \ 70 70 .mux_bit = -1, \ 71 71 .pull_bit = -1, \ 72 72 .drv_bit = -1, \ ··· 90 92 .io_reg = 0, \ 91 93 .intr_cfg_reg = 0, \ 92 94 .intr_status_reg = 0, \ 93 - .intr_target_reg = 0, \ 94 95 .mux_bit = -1, \ 95 96 .pull_bit = pull, \ 96 97 .drv_bit = drv, \ ··· 114 117 .io_reg = offset + 0x4, \ 115 118 .intr_cfg_reg = 0, \ 116 119 .intr_status_reg = 0, \ 117 - .intr_target_reg = 0, \ 118 120 .mux_bit = -1, \ 119 121 .pull_bit = 3, \ 120 122 .drv_bit = 0, \
-3
drivers/pinctrl/qcom/pinctrl-sdm845.c
··· 37 37 .io_reg = base + 0x4 + REG_SIZE * id, \ 38 38 .intr_cfg_reg = base + 0x8 + REG_SIZE * id, \ 39 39 .intr_status_reg = base + 0xc + REG_SIZE * id, \ 40 - .intr_target_reg = base + 0x8 + REG_SIZE * id, \ 41 40 .mux_bit = 2, \ 42 41 .pull_bit = 0, \ 43 42 .drv_bit = 6, \ ··· 62 63 .io_reg = 0, \ 63 64 .intr_cfg_reg = 0, \ 64 65 .intr_status_reg = 0, \ 65 - .intr_target_reg = 0, \ 66 66 .mux_bit = -1, \ 67 67 .pull_bit = pull, \ 68 68 .drv_bit = drv, \ ··· 86 88 .io_reg = offset + 0x4, \ 87 89 .intr_cfg_reg = 0, \ 88 90 .intr_status_reg = 0, \ 89 - .intr_target_reg = 0, \ 90 91 .mux_bit = -1, \ 91 92 .pull_bit = 3, \ 92 93 .drv_bit = 0, \
-2
drivers/pinctrl/qcom/pinctrl-sdx55.c
··· 33 33 .io_reg = 0x4 + REG_SIZE * id, \ 34 34 .intr_cfg_reg = 0x8 + REG_SIZE * id, \ 35 35 .intr_status_reg = 0xc + REG_SIZE * id, \ 36 - .intr_target_reg = 0x8 + REG_SIZE * id, \ 37 36 .mux_bit = 2, \ 38 37 .pull_bit = 0, \ 39 38 .drv_bit = 6, \ ··· 58 59 .io_reg = 0, \ 59 60 .intr_cfg_reg = 0, \ 60 61 .intr_status_reg = 0, \ 61 - .intr_target_reg = 0, \ 62 62 .mux_bit = -1, \ 63 63 .pull_bit = pull, \ 64 64 .drv_bit = drv, \
-3
drivers/pinctrl/qcom/pinctrl-sdx65.c
··· 33 33 .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \ 34 34 .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \ 35 35 .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \ 36 - .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \ 37 36 .mux_bit = 2, \ 38 37 .pull_bit = 0, \ 39 38 .drv_bit = 6, \ ··· 58 59 .io_reg = 0, \ 59 60 .intr_cfg_reg = 0, \ 60 61 .intr_status_reg = 0, \ 61 - .intr_target_reg = 0, \ 62 62 .mux_bit = -1, \ 63 63 .pull_bit = pull, \ 64 64 .drv_bit = drv, \ ··· 82 84 .io_reg = offset + 0x4, \ 83 85 .intr_cfg_reg = 0, \ 84 86 .intr_status_reg = 0, \ 85 - .intr_target_reg = 0, \ 86 87 .mux_bit = -1, \ 87 88 .pull_bit = 3, \ 88 89 .drv_bit = 0, \
-2
drivers/pinctrl/qcom/pinctrl-sdx75.c
··· 19 19 .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \ 20 20 .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \ 21 21 .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \ 22 - .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \ 23 22 .mux_bit = 2, \ 24 23 .pull_bit = 0, \ 25 24 .drv_bit = 6, \ ··· 59 60 .io_reg = 0, \ 60 61 .intr_cfg_reg = 0, \ 61 62 .intr_status_reg = 0, \ 62 - .intr_target_reg = 0, \ 63 63 .mux_bit = -1, \ 64 64 .pull_bit = pull, \ 65 65 .drv_bit = drv, \
-3
drivers/pinctrl/qcom/pinctrl-sm4450.c
··· 33 33 .io_reg = 0x4 + REG_SIZE * id, \ 34 34 .intr_cfg_reg = 0x8 + REG_SIZE * id, \ 35 35 .intr_status_reg = 0xc + REG_SIZE * id, \ 36 - .intr_target_reg = 0x8 + REG_SIZE * id, \ 37 36 .mux_bit = 2, \ 38 37 .pull_bit = 0, \ 39 38 .drv_bit = 6, \ ··· 60 61 .io_reg = 0, \ 61 62 .intr_cfg_reg = 0, \ 62 63 .intr_status_reg = 0, \ 63 - .intr_target_reg = 0, \ 64 64 .mux_bit = -1, \ 65 65 .pull_bit = pull, \ 66 66 .drv_bit = drv, \ ··· 84 86 .io_reg = offset + 0x4, \ 85 87 .intr_cfg_reg = 0, \ 86 88 .intr_status_reg = 0, \ 87 - .intr_target_reg = 0, \ 88 89 .mux_bit = -1, \ 89 90 .pull_bit = 3, \ 90 91 .drv_bit = 0, \
-3
drivers/pinctrl/qcom/pinctrl-sm6115.c
··· 43 43 .io_reg = 0x4 + 0x1000 * id, \ 44 44 .intr_cfg_reg = 0x8 + 0x1000 * id, \ 45 45 .intr_status_reg = 0xc + 0x1000 * id, \ 46 - .intr_target_reg = 0x8 + 0x1000 * id, \ 47 46 .tile = _tile, \ 48 47 .mux_bit = 2, \ 49 48 .pull_bit = 0, \ ··· 69 70 .io_reg = 0, \ 70 71 .intr_cfg_reg = 0, \ 71 72 .intr_status_reg = 0, \ 72 - .intr_target_reg = 0, \ 73 73 .tile = _tile, \ 74 74 .mux_bit = -1, \ 75 75 .pull_bit = pull, \ ··· 94 96 .io_reg = offset + 0x4, \ 95 97 .intr_cfg_reg = 0, \ 96 98 .intr_status_reg = 0, \ 97 - .intr_target_reg = 0, \ 98 99 .tile = WEST, \ 99 100 .mux_bit = -1, \ 100 101 .pull_bit = 3, \
-3
drivers/pinctrl/qcom/pinctrl-sm6125.c
··· 40 40 .io_reg = 0x4 + 0x1000 * id, \ 41 41 .intr_cfg_reg = 0x8 + 0x1000 * id, \ 42 42 .intr_status_reg = 0xc + 0x1000 * id, \ 43 - .intr_target_reg = 0x8 + 0x1000 * id, \ 44 43 .tile = _tile, \ 45 44 .mux_bit = 2, \ 46 45 .pull_bit = 0, \ ··· 66 67 .io_reg = 0, \ 67 68 .intr_cfg_reg = 0, \ 68 69 .intr_status_reg = 0, \ 69 - .intr_target_reg = 0, \ 70 70 .tile = _tile, \ 71 71 .mux_bit = -1, \ 72 72 .pull_bit = pull, \ ··· 91 93 .io_reg = offset + 0x4, \ 92 94 .intr_cfg_reg = 0, \ 93 95 .intr_status_reg = 0, \ 94 - .intr_target_reg = 0, \ 95 96 .tile = WEST, \ 96 97 .mux_bit = -1, \ 97 98 .pull_bit = 3, \
-3
drivers/pinctrl/qcom/pinctrl-sm6350.c
··· 33 33 .io_reg = 0x4 + REG_SIZE * id, \ 34 34 .intr_cfg_reg = 0x8 + REG_SIZE * id, \ 35 35 .intr_status_reg = 0xc + REG_SIZE * id, \ 36 - .intr_target_reg = 0x8 + REG_SIZE * id, \ 37 36 .mux_bit = 2, \ 38 37 .pull_bit = 0, \ 39 38 .drv_bit = 6, \ ··· 58 59 .io_reg = 0, \ 59 60 .intr_cfg_reg = 0, \ 60 61 .intr_status_reg = 0, \ 61 - .intr_target_reg = 0, \ 62 62 .mux_bit = -1, \ 63 63 .pull_bit = pull, \ 64 64 .drv_bit = drv, \ ··· 82 84 .io_reg = offset + 0x4, \ 83 85 .intr_cfg_reg = 0, \ 84 86 .intr_status_reg = 0, \ 85 - .intr_target_reg = 0, \ 86 87 .mux_bit = -1, \ 87 88 .pull_bit = 3, \ 88 89 .drv_bit = 0, \
-3
drivers/pinctrl/qcom/pinctrl-sm6375.c
··· 34 34 .io_reg = REG_SIZE * id + 0x4, \ 35 35 .intr_cfg_reg = REG_SIZE * id + 0x8, \ 36 36 .intr_status_reg = REG_SIZE * id + 0xc, \ 37 - .intr_target_reg = REG_SIZE * id + 0x8, \ 38 37 .mux_bit = 2, \ 39 38 .pull_bit = 0, \ 40 39 .drv_bit = 6, \ ··· 61 62 .io_reg = 0, \ 62 63 .intr_cfg_reg = 0, \ 63 64 .intr_status_reg = 0, \ 64 - .intr_target_reg = 0, \ 65 65 .mux_bit = -1, \ 66 66 .pull_bit = pull, \ 67 67 .drv_bit = drv, \ ··· 85 87 .io_reg = offset + 0x4, \ 86 88 .intr_cfg_reg = 0, \ 87 89 .intr_status_reg = 0, \ 88 - .intr_target_reg = 0, \ 89 90 .mux_bit = -1, \ 90 91 .pull_bit = 3, \ 91 92 .drv_bit = 0, \
-3
drivers/pinctrl/qcom/pinctrl-sm7150.c
··· 47 47 .io_reg = 0x4 + REG_SIZE * id, \ 48 48 .intr_cfg_reg = 0x8 + REG_SIZE * id, \ 49 49 .intr_status_reg = 0xc + REG_SIZE * id, \ 50 - .intr_target_reg = 0x8 + REG_SIZE * id, \ 51 50 .tile = _tile, \ 52 51 .mux_bit = 2, \ 53 52 .pull_bit = 0, \ ··· 73 74 .io_reg = 0, \ 74 75 .intr_cfg_reg = 0, \ 75 76 .intr_status_reg = 0, \ 76 - .intr_target_reg = 0, \ 77 77 .tile = _tile, \ 78 78 .mux_bit = -1, \ 79 79 .pull_bit = pull, \ ··· 98 100 .io_reg = offset + 0x4, \ 99 101 .intr_cfg_reg = 0, \ 100 102 .intr_status_reg = 0, \ 101 - .intr_target_reg = 0, \ 102 103 .tile = WEST, \ 103 104 .mux_bit = -1, \ 104 105 .pull_bit = 3, \
-3
drivers/pinctrl/qcom/pinctrl-sm8150.c
··· 43 43 .io_reg = 0x1000 * id + 0x4, \ 44 44 .intr_cfg_reg = 0x1000 * id + 0x8, \ 45 45 .intr_status_reg = 0x1000 * id + 0xc, \ 46 - .intr_target_reg = 0x1000 * id + 0x8, \ 47 46 .tile = _tile, \ 48 47 .mux_bit = 2, \ 49 48 .pull_bit = 0, \ ··· 69 70 .io_reg = 0, \ 70 71 .intr_cfg_reg = 0, \ 71 72 .intr_status_reg = 0, \ 72 - .intr_target_reg = 0, \ 73 73 .tile = NORTH, \ 74 74 .mux_bit = -1, \ 75 75 .pull_bit = pull, \ ··· 94 96 .io_reg = offset + 0x4, \ 95 97 .intr_cfg_reg = 0, \ 96 98 .intr_status_reg = 0, \ 97 - .intr_target_reg = 0, \ 98 99 .tile = SOUTH, \ 99 100 .mux_bit = -1, \ 100 101 .pull_bit = 3, \
-3
drivers/pinctrl/qcom/pinctrl-sm8250.c
··· 44 44 .io_reg = REG_SIZE * id + 0x4, \ 45 45 .intr_cfg_reg = REG_SIZE * id + 0x8, \ 46 46 .intr_status_reg = REG_SIZE * id + 0xc, \ 47 - .intr_target_reg = REG_SIZE * id + 0x8, \ 48 47 .tile = _tile, \ 49 48 .mux_bit = 2, \ 50 49 .pull_bit = 0, \ ··· 72 73 .io_reg = 0, \ 73 74 .intr_cfg_reg = 0, \ 74 75 .intr_status_reg = 0, \ 75 - .intr_target_reg = 0, \ 76 76 .tile = NORTH, \ 77 77 .mux_bit = -1, \ 78 78 .pull_bit = pull, \ ··· 97 99 .io_reg = offset + 0x4, \ 98 100 .intr_cfg_reg = 0, \ 99 101 .intr_status_reg = 0, \ 100 - .intr_target_reg = 0, \ 101 102 .tile = SOUTH, \ 102 103 .mux_bit = -1, \ 103 104 .pull_bit = 3, \
-3
drivers/pinctrl/qcom/pinctrl-sm8350.c
··· 34 34 .io_reg = REG_SIZE * id + 0x4, \ 35 35 .intr_cfg_reg = REG_SIZE * id + 0x8, \ 36 36 .intr_status_reg = REG_SIZE * id + 0xc, \ 37 - .intr_target_reg = REG_SIZE * id + 0x8, \ 38 37 .mux_bit = 2, \ 39 38 .pull_bit = 0, \ 40 39 .drv_bit = 6, \ ··· 59 60 .io_reg = 0, \ 60 61 .intr_cfg_reg = 0, \ 61 62 .intr_status_reg = 0, \ 62 - .intr_target_reg = 0, \ 63 63 .mux_bit = -1, \ 64 64 .pull_bit = pull, \ 65 65 .drv_bit = drv, \ ··· 83 85 .io_reg = offset + 0x4, \ 84 86 .intr_cfg_reg = 0, \ 85 87 .intr_status_reg = 0, \ 86 - .intr_target_reg = 0, \ 87 88 .mux_bit = -1, \ 88 89 .pull_bit = 3, \ 89 90 .drv_bit = 0, \
-3
drivers/pinctrl/qcom/pinctrl-sm8450.c
··· 34 34 .io_reg = 0x4 + REG_SIZE * id, \ 35 35 .intr_cfg_reg = 0x8 + REG_SIZE * id, \ 36 36 .intr_status_reg = 0xc + REG_SIZE * id, \ 37 - .intr_target_reg = 0x8 + REG_SIZE * id, \ 38 37 .mux_bit = 2, \ 39 38 .pull_bit = 0, \ 40 39 .drv_bit = 6, \ ··· 61 62 .io_reg = 0, \ 62 63 .intr_cfg_reg = 0, \ 63 64 .intr_status_reg = 0, \ 64 - .intr_target_reg = 0, \ 65 65 .mux_bit = -1, \ 66 66 .pull_bit = pull, \ 67 67 .drv_bit = drv, \ ··· 85 87 .io_reg = offset + 0x4, \ 86 88 .intr_cfg_reg = 0, \ 87 89 .intr_status_reg = 0, \ 88 - .intr_target_reg = 0, \ 89 90 .mux_bit = -1, \ 90 91 .pull_bit = 3, \ 91 92 .drv_bit = 0, \
-3
drivers/pinctrl/qcom/pinctrl-sm8550.c
··· 35 35 .io_reg = 0x4 + REG_SIZE * id, \ 36 36 .intr_cfg_reg = 0x8 + REG_SIZE * id, \ 37 37 .intr_status_reg = 0xc + REG_SIZE * id, \ 38 - .intr_target_reg = 0x8 + REG_SIZE * id, \ 39 38 .mux_bit = 2, \ 40 39 .pull_bit = 0, \ 41 40 .drv_bit = 6, \ ··· 63 64 .io_reg = 0, \ 64 65 .intr_cfg_reg = 0, \ 65 66 .intr_status_reg = 0, \ 66 - .intr_target_reg = 0, \ 67 67 .mux_bit = -1, \ 68 68 .pull_bit = pull, \ 69 69 .drv_bit = drv, \ ··· 87 89 .io_reg = offset + 0x4, \ 88 90 .intr_cfg_reg = 0, \ 89 91 .intr_status_reg = 0, \ 90 - .intr_target_reg = 0, \ 91 92 .mux_bit = -1, \ 92 93 .pull_bit = 3, \ 93 94 .drv_bit = 0, \
-3
drivers/pinctrl/qcom/pinctrl-sm8650.c
··· 36 36 .io_reg = 0x4 + REG_SIZE * id, \ 37 37 .intr_cfg_reg = 0x8 + REG_SIZE * id, \ 38 38 .intr_status_reg = 0xc + REG_SIZE * id, \ 39 - .intr_target_reg = 0x8 + REG_SIZE * id, \ 40 39 .mux_bit = 2, \ 41 40 .pull_bit = 0, \ 42 41 .drv_bit = 6, \ ··· 66 67 .io_reg = 0, \ 67 68 .intr_cfg_reg = 0, \ 68 69 .intr_status_reg = 0, \ 69 - .intr_target_reg = 0, \ 70 70 .mux_bit = -1, \ 71 71 .pull_bit = pull, \ 72 72 .drv_bit = drv, \ ··· 90 92 .io_reg = io, \ 91 93 .intr_cfg_reg = 0, \ 92 94 .intr_status_reg = 0, \ 93 - .intr_target_reg = 0, \ 94 95 .mux_bit = -1, \ 95 96 .pull_bit = 3, \ 96 97 .drv_bit = 0, \
-3
drivers/pinctrl/qcom/pinctrl-sm8750.c
··· 35 35 .io_reg = 0x4 + REG_SIZE * id, \ 36 36 .intr_cfg_reg = 0x8 + REG_SIZE * id, \ 37 37 .intr_status_reg = 0xc + REG_SIZE * id, \ 38 - .intr_target_reg = 0x8 + REG_SIZE * id, \ 39 38 .mux_bit = 2, \ 40 39 .pull_bit = 0, \ 41 40 .drv_bit = 6, \ ··· 64 65 .io_reg = 0, \ 65 66 .intr_cfg_reg = 0, \ 66 67 .intr_status_reg = 0, \ 67 - .intr_target_reg = 0, \ 68 68 .mux_bit = -1, \ 69 69 .pull_bit = pull, \ 70 70 .drv_bit = drv, \ ··· 88 90 .io_reg = io, \ 89 91 .intr_cfg_reg = 0, \ 90 92 .intr_status_reg = 0, \ 91 - .intr_target_reg = 0, \ 92 93 .mux_bit = -1, \ 93 94 .pull_bit = 3, \ 94 95 .drv_bit = 0, \
-3
drivers/pinctrl/qcom/pinctrl-x1e80100.c
··· 33 33 .io_reg = 0x4 + REG_SIZE * id, \ 34 34 .intr_cfg_reg = 0x8 + REG_SIZE * id, \ 35 35 .intr_status_reg = 0xc + REG_SIZE * id, \ 36 - .intr_target_reg = 0x8 + REG_SIZE * id, \ 37 36 .mux_bit = 2, \ 38 37 .pull_bit = 0, \ 39 38 .drv_bit = 6, \ ··· 61 62 .io_reg = 0, \ 62 63 .intr_cfg_reg = 0, \ 63 64 .intr_status_reg = 0, \ 64 - .intr_target_reg = 0, \ 65 65 .mux_bit = -1, \ 66 66 .pull_bit = pull, \ 67 67 .drv_bit = drv, \ ··· 85 87 .io_reg = offset + 0x4, \ 86 88 .intr_cfg_reg = 0, \ 87 89 .intr_status_reg = 0, \ 88 - .intr_target_reg = 0, \ 89 90 .mux_bit = -1, \ 90 91 .pull_bit = 3, \ 91 92 .drv_bit = 0, \