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amd-xgbe: Add support for 10 Mbps speed

Add the necessary changes to support 10 Mbps speed for BaseT and SFP
port modes. This is supported in MAC ver >= 30H.

Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com>
Link: https://lore.kernel.org/r/20230109101819.747572-1-Raju.Rangoju@amd.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>

authored by

Raju Rangoju and committed by
Paolo Abeni 07445f3c cbdbb58b

+126 -10
+3
drivers/net/ethernet/amd/xgbe/xgbe-dev.c
··· 807 807 unsigned int ss; 808 808 809 809 switch (speed) { 810 + case SPEED_10: 811 + ss = 0x07; 812 + break; 810 813 case SPEED_1000: 811 814 ss = 0x03; 812 815 break;
+24
drivers/net/ethernet/amd/xgbe/xgbe-mdio.c
··· 274 274 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SGMII_1000); 275 275 } 276 276 277 + static void xgbe_sgmii_10_mode(struct xgbe_prv_data *pdata) 278 + { 279 + /* Set MAC to 10M speed */ 280 + pdata->hw_if.set_speed(pdata, SPEED_10); 281 + 282 + /* Call PHY implementation support to complete rate change */ 283 + pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SGMII_10); 284 + } 285 + 277 286 static void xgbe_sgmii_100_mode(struct xgbe_prv_data *pdata) 278 287 { 279 288 /* Set MAC to 1G speed */ ··· 314 305 break; 315 306 case XGBE_MODE_KR: 316 307 xgbe_kr_mode(pdata); 308 + break; 309 + case XGBE_MODE_SGMII_10: 310 + xgbe_sgmii_10_mode(pdata); 317 311 break; 318 312 case XGBE_MODE_SGMII_100: 319 313 xgbe_sgmii_100_mode(pdata); ··· 1086 1074 static const char *xgbe_phy_speed_string(int speed) 1087 1075 { 1088 1076 switch (speed) { 1077 + case SPEED_10: 1078 + return "10Mbps"; 1089 1079 case SPEED_100: 1090 1080 return "100Mbps"; 1091 1081 case SPEED_1000: ··· 1175 1161 case XGBE_MODE_KX_1000: 1176 1162 case XGBE_MODE_KX_2500: 1177 1163 case XGBE_MODE_KR: 1164 + case XGBE_MODE_SGMII_10: 1178 1165 case XGBE_MODE_SGMII_100: 1179 1166 case XGBE_MODE_SGMII_1000: 1180 1167 case XGBE_MODE_X: ··· 1237 1222 xgbe_set_mode(pdata, XGBE_MODE_SGMII_1000); 1238 1223 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_100)) { 1239 1224 xgbe_set_mode(pdata, XGBE_MODE_SGMII_100); 1225 + } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_10)) { 1226 + xgbe_set_mode(pdata, XGBE_MODE_SGMII_10); 1240 1227 } else { 1241 1228 enable_irq(pdata->an_irq); 1242 1229 ret = -EINVAL; ··· 1318 1301 mode = xgbe_phy_status_aneg(pdata); 1319 1302 1320 1303 switch (mode) { 1304 + case XGBE_MODE_SGMII_10: 1305 + pdata->phy.speed = SPEED_10; 1306 + break; 1321 1307 case XGBE_MODE_SGMII_100: 1322 1308 pdata->phy.speed = SPEED_100; 1323 1309 break; ··· 1463 1443 xgbe_sgmii_1000_mode(pdata); 1464 1444 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_100)) { 1465 1445 xgbe_sgmii_100_mode(pdata); 1446 + } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_10)) { 1447 + xgbe_sgmii_10_mode(pdata); 1466 1448 } else { 1467 1449 ret = -EINVAL; 1468 1450 goto err_irq; ··· 1562 1540 return SPEED_1000; 1563 1541 else if (XGBE_ADV(lks, 100baseT_Full)) 1564 1542 return SPEED_100; 1543 + else if (XGBE_ADV(lks, 10baseT_Full)) 1544 + return SPEED_10; 1565 1545 1566 1546 return SPEED_UNKNOWN; 1567 1547 }
+97 -10
drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c
··· 124 124 #include "xgbe.h" 125 125 #include "xgbe-common.h" 126 126 127 + #define XGBE_PHY_PORT_SPEED_10 BIT(0) 127 128 #define XGBE_PHY_PORT_SPEED_100 BIT(1) 128 129 #define XGBE_PHY_PORT_SPEED_1000 BIT(2) 129 130 #define XGBE_PHY_PORT_SPEED_2500 BIT(3) ··· 760 759 XGBE_SET_SUP(lks, Pause); 761 760 XGBE_SET_SUP(lks, Asym_Pause); 762 761 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T) { 762 + if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10) 763 + XGBE_SET_SUP(lks, 10baseT_Full); 763 764 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) 764 765 XGBE_SET_SUP(lks, 100baseT_Full); 765 766 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ··· 1545 1542 xgbe_phy_phydev_flowctrl(pdata); 1546 1543 1547 1544 switch (pdata->an_status & XGBE_SGMII_AN_LINK_SPEED) { 1545 + case XGBE_SGMII_AN_LINK_SPEED_10: 1546 + if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) { 1547 + XGBE_SET_LP_ADV(lks, 10baseT_Full); 1548 + mode = XGBE_MODE_SGMII_10; 1549 + } else { 1550 + /* Half-duplex not supported */ 1551 + XGBE_SET_LP_ADV(lks, 10baseT_Half); 1552 + mode = XGBE_MODE_UNKNOWN; 1553 + } 1554 + break; 1548 1555 case XGBE_SGMII_AN_LINK_SPEED_100: 1549 1556 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) { 1550 1557 XGBE_SET_LP_ADV(lks, 100baseT_Full); ··· 1671 1658 switch (phy_data->sfp_base) { 1672 1659 case XGBE_SFP_BASE_1000_T: 1673 1660 if (phy_data->phydev && 1674 - (phy_data->phydev->speed == SPEED_100)) 1661 + (phy_data->phydev->speed == SPEED_10)) 1662 + mode = XGBE_MODE_SGMII_10; 1663 + else if (phy_data->phydev && 1664 + (phy_data->phydev->speed == SPEED_100)) 1675 1665 mode = XGBE_MODE_SGMII_100; 1676 1666 else 1677 1667 mode = XGBE_MODE_SGMII_1000; ··· 1689 1673 break; 1690 1674 default: 1691 1675 if (phy_data->phydev && 1692 - (phy_data->phydev->speed == SPEED_100)) 1676 + (phy_data->phydev->speed == SPEED_10)) 1677 + mode = XGBE_MODE_SGMII_10; 1678 + else if (phy_data->phydev && 1679 + (phy_data->phydev->speed == SPEED_100)) 1693 1680 mode = XGBE_MODE_SGMII_100; 1694 1681 else 1695 1682 mode = XGBE_MODE_SGMII_1000; ··· 2146 2127 netif_dbg(pdata, link, pdata->netdev, "100MbE SGMII mode set\n"); 2147 2128 } 2148 2129 2130 + static void xgbe_phy_sgmii_10_mode(struct xgbe_prv_data *pdata) 2131 + { 2132 + struct xgbe_phy_data *phy_data = pdata->phy_data; 2133 + 2134 + xgbe_phy_set_redrv_mode(pdata); 2135 + 2136 + /* 10M/SGMII */ 2137 + xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_1G, XGBE_MB_SUBCMD_10MBITS); 2138 + 2139 + phy_data->cur_mode = XGBE_MODE_SGMII_10; 2140 + 2141 + netif_dbg(pdata, link, pdata->netdev, "10MbE SGMII mode set\n"); 2142 + } 2143 + 2149 2144 static void xgbe_phy_kr_mode(struct xgbe_prv_data *pdata) 2150 2145 { 2151 2146 struct xgbe_phy_data *phy_data = pdata->phy_data; ··· 2218 2185 return xgbe_phy_cur_mode(pdata); 2219 2186 2220 2187 switch (xgbe_phy_cur_mode(pdata)) { 2188 + case XGBE_MODE_SGMII_10: 2221 2189 case XGBE_MODE_SGMII_100: 2222 2190 case XGBE_MODE_SGMII_1000: 2223 2191 return XGBE_MODE_KR; ··· 2286 2252 int speed) 2287 2253 { 2288 2254 switch (speed) { 2255 + case SPEED_10: 2256 + return XGBE_MODE_SGMII_10; 2289 2257 case SPEED_100: 2290 2258 return XGBE_MODE_SGMII_100; 2291 2259 case SPEED_1000: ··· 2305 2269 int speed) 2306 2270 { 2307 2271 switch (speed) { 2272 + case SPEED_10: 2273 + return XGBE_MODE_SGMII_10; 2308 2274 case SPEED_100: 2309 2275 return XGBE_MODE_SGMII_100; 2310 2276 case SPEED_1000: ··· 2381 2343 case XGBE_MODE_KR: 2382 2344 xgbe_phy_kr_mode(pdata); 2383 2345 break; 2346 + case XGBE_MODE_SGMII_10: 2347 + xgbe_phy_sgmii_10_mode(pdata); 2348 + break; 2384 2349 case XGBE_MODE_SGMII_100: 2385 2350 xgbe_phy_sgmii_100_mode(pdata); 2386 2351 break; ··· 2440 2399 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 2441 2400 2442 2401 switch (mode) { 2402 + case XGBE_MODE_SGMII_10: 2403 + return xgbe_phy_check_mode(pdata, mode, 2404 + XGBE_ADV(lks, 10baseT_Full)); 2443 2405 case XGBE_MODE_SGMII_100: 2444 2406 return xgbe_phy_check_mode(pdata, mode, 2445 2407 XGBE_ADV(lks, 100baseT_Full)); ··· 2472 2428 return false; 2473 2429 return xgbe_phy_check_mode(pdata, mode, 2474 2430 XGBE_ADV(lks, 1000baseX_Full)); 2431 + case XGBE_MODE_SGMII_10: 2432 + if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T) 2433 + return false; 2434 + return xgbe_phy_check_mode(pdata, mode, 2435 + XGBE_ADV(lks, 10baseT_Full)); 2475 2436 case XGBE_MODE_SGMII_100: 2476 2437 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T) 2477 2438 return false; ··· 2569 2520 } 2570 2521 } 2571 2522 2572 - static bool xgbe_phy_valid_speed_baset_mode(struct xgbe_phy_data *phy_data, 2523 + static bool xgbe_phy_valid_speed_baset_mode(struct xgbe_prv_data *pdata, 2573 2524 int speed) 2574 2525 { 2526 + struct xgbe_phy_data *phy_data = pdata->phy_data; 2527 + unsigned int ver; 2528 + 2575 2529 switch (speed) { 2530 + case SPEED_10: 2531 + /* Supported in ver >= 30H */ 2532 + ver = XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER); 2533 + return (ver >= 0x30) ? true : false; 2576 2534 case SPEED_100: 2577 2535 case SPEED_1000: 2578 2536 return true; ··· 2592 2536 } 2593 2537 } 2594 2538 2595 - static bool xgbe_phy_valid_speed_sfp_mode(struct xgbe_phy_data *phy_data, 2539 + static bool xgbe_phy_valid_speed_sfp_mode(struct xgbe_prv_data *pdata, 2596 2540 int speed) 2597 2541 { 2542 + struct xgbe_phy_data *phy_data = pdata->phy_data; 2543 + unsigned int ver; 2544 + 2598 2545 switch (speed) { 2546 + case SPEED_10: 2547 + /* Supported in ver >= 30H */ 2548 + ver = XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER); 2549 + return (ver >= 0x30) && (phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000); 2599 2550 case SPEED_100: 2600 2551 return (phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000); 2601 2552 case SPEED_1000: ··· 2649 2586 case XGBE_PORT_MODE_1000BASE_T: 2650 2587 case XGBE_PORT_MODE_NBASE_T: 2651 2588 case XGBE_PORT_MODE_10GBASE_T: 2652 - return xgbe_phy_valid_speed_baset_mode(phy_data, speed); 2589 + return xgbe_phy_valid_speed_baset_mode(pdata, speed); 2653 2590 case XGBE_PORT_MODE_1000BASE_X: 2654 2591 case XGBE_PORT_MODE_10GBASE_R: 2655 2592 return xgbe_phy_valid_speed_basex_mode(phy_data, speed); 2656 2593 case XGBE_PORT_MODE_SFP: 2657 - return xgbe_phy_valid_speed_sfp_mode(phy_data, speed); 2594 + return xgbe_phy_valid_speed_sfp_mode(pdata, speed); 2658 2595 default: 2659 2596 return false; 2660 2597 } ··· 2925 2862 static bool xgbe_phy_port_mode_mismatch(struct xgbe_prv_data *pdata) 2926 2863 { 2927 2864 struct xgbe_phy_data *phy_data = pdata->phy_data; 2865 + unsigned int ver; 2866 + 2867 + /* 10 Mbps speed is not supported in ver < 30H */ 2868 + ver = XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER); 2869 + if (ver < 0x30 && (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10)) 2870 + return true; 2928 2871 2929 2872 switch (phy_data->port_mode) { 2930 2873 case XGBE_PORT_MODE_BACKPLANE: ··· 2944 2875 return false; 2945 2876 break; 2946 2877 case XGBE_PORT_MODE_1000BASE_T: 2947 - if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) || 2878 + if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10) || 2879 + (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) || 2948 2880 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)) 2949 2881 return false; 2950 2882 break; ··· 2954 2884 return false; 2955 2885 break; 2956 2886 case XGBE_PORT_MODE_NBASE_T: 2957 - if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) || 2887 + if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10) || 2888 + (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) || 2958 2889 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) || 2959 2890 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500)) 2960 2891 return false; 2961 2892 break; 2962 2893 case XGBE_PORT_MODE_10GBASE_T: 2963 - if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) || 2894 + if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10) || 2895 + (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) || 2964 2896 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) || 2965 2897 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)) 2966 2898 return false; ··· 2972 2900 return false; 2973 2901 break; 2974 2902 case XGBE_PORT_MODE_SFP: 2975 - if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) || 2903 + if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10) || 2904 + (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) || 2976 2905 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) || 2977 2906 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)) 2978 2907 return false; ··· 3342 3269 XGBE_SET_SUP(lks, Pause); 3343 3270 XGBE_SET_SUP(lks, Asym_Pause); 3344 3271 XGBE_SET_SUP(lks, TP); 3272 + if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10) { 3273 + XGBE_SET_SUP(lks, 10baseT_Full); 3274 + phy_data->start_mode = XGBE_MODE_SGMII_10; 3275 + } 3345 3276 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) { 3346 3277 XGBE_SET_SUP(lks, 100baseT_Full); 3347 3278 phy_data->start_mode = XGBE_MODE_SGMII_100; ··· 3376 3299 XGBE_SET_SUP(lks, Pause); 3377 3300 XGBE_SET_SUP(lks, Asym_Pause); 3378 3301 XGBE_SET_SUP(lks, TP); 3302 + if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10) { 3303 + XGBE_SET_SUP(lks, 10baseT_Full); 3304 + phy_data->start_mode = XGBE_MODE_SGMII_10; 3305 + } 3379 3306 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) { 3380 3307 XGBE_SET_SUP(lks, 100baseT_Full); 3381 3308 phy_data->start_mode = XGBE_MODE_SGMII_100; ··· 3402 3321 XGBE_SET_SUP(lks, Pause); 3403 3322 XGBE_SET_SUP(lks, Asym_Pause); 3404 3323 XGBE_SET_SUP(lks, TP); 3324 + if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10) { 3325 + XGBE_SET_SUP(lks, 10baseT_Full); 3326 + phy_data->start_mode = XGBE_MODE_SGMII_10; 3327 + } 3405 3328 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) { 3406 3329 XGBE_SET_SUP(lks, 100baseT_Full); 3407 3330 phy_data->start_mode = XGBE_MODE_SGMII_100; ··· 3446 3361 XGBE_SET_SUP(lks, Asym_Pause); 3447 3362 XGBE_SET_SUP(lks, TP); 3448 3363 XGBE_SET_SUP(lks, FIBRE); 3364 + if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10) 3365 + phy_data->start_mode = XGBE_MODE_SGMII_10; 3449 3366 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) 3450 3367 phy_data->start_mode = XGBE_MODE_SGMII_100; 3451 3368 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
+2
drivers/net/ethernet/amd/xgbe/xgbe.h
··· 293 293 294 294 #define XGBE_SGMII_AN_LINK_STATUS BIT(1) 295 295 #define XGBE_SGMII_AN_LINK_SPEED (BIT(2) | BIT(3)) 296 + #define XGBE_SGMII_AN_LINK_SPEED_10 0x00 296 297 #define XGBE_SGMII_AN_LINK_SPEED_100 0x04 297 298 #define XGBE_SGMII_AN_LINK_SPEED_1000 0x08 298 299 #define XGBE_SGMII_AN_LINK_DUPLEX BIT(4) ··· 595 594 XGBE_MODE_KX_2500, 596 595 XGBE_MODE_KR, 597 596 XGBE_MODE_X, 597 + XGBE_MODE_SGMII_10, 598 598 XGBE_MODE_SGMII_100, 599 599 XGBE_MODE_SGMII_1000, 600 600 XGBE_MODE_SFI,