Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'soc-ep93xx-dt-6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC update from Arnd Bergmann:
"Convert ep93xx to devicetree
This concludes a long journey towards replacing the old board files
with devictree description on the Cirrus Logic EP93xx platform.
Nikita Shubin has been working on this for a long time, for details
see the last post on
https://lore.kernel.org/lkml/20240909-ep93xx-v12-0-e86ab2423d4b@maquefel.me/"
* tag 'soc-ep93xx-dt-6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (47 commits)
dt-bindings: gpio: ep9301: Add missing "#interrupt-cells" to examples
MAINTAINERS: Update EP93XX ARM ARCHITECTURE maintainer
soc: ep93xx: drop reference to removed EP93XX_SOC_COMMON config
net: cirrus: use u8 for addr to calm down sparse
dmaengine: cirrus: use snprintf() to calm down gcc 13.3.0
dmaengine: ep93xx: Fix a NULL vs IS_ERR() check in probe()
pinctrl: ep93xx: Fix raster pins typo
spi: ep93xx: update kerneldoc comments for ep93xx_spi
clk: ep93xx: Fix off by one in ep93xx_div_recalc_rate()
clk: ep93xx: add module license
dmaengine: cirrus: remove platform code
ASoC: cirrus: edb93xx: Delete driver
ARM: ep93xx: soc: drop defines
ARM: ep93xx: delete all boardfiles
ata: pata_ep93xx: remove legacy pinctrl use
pwm: ep93xx: drop legacy pinctrl
ARM: ep93xx: DT for the Cirrus ep93xx SoC platforms
ARM: dts: ep93xx: Add EDB9302 DT
ARM: dts: ep93xx: add ts7250 board
ARM: dts: add Cirrus EP93XX SoC .dtsi
...
+5130
-4559
+38
Documentation/devicetree/bindings/arm/cirrus/cirrus,ep9301.yaml
+38
Documentation/devicetree/bindings/arm/cirrus/cirrus,ep9301.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/arm/cirrus/cirrus,ep9301.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Cirrus Logic EP93xx platforms
8
+
9
+
description:
10
+
The EP93xx SoC is a ARMv4T-based with 200 MHz ARM9 CPU.
11
+
12
+
maintainers:
13
+
- Alexander Sverdlin <alexander.sverdlin@gmail.com>
14
+
- Nikita Shubin <nikita.shubin@maquefel.me>
15
+
16
+
properties:
17
+
$nodename:
18
+
const: '/'
19
+
compatible:
20
+
oneOf:
21
+
- description: The TS-7250 is a compact, full-featured Single Board
22
+
Computer (SBC) based upon the Cirrus EP9302 ARM9 CPU
23
+
items:
24
+
- const: technologic,ts7250
25
+
- const: cirrus,ep9301
26
+
27
+
- description: The Liebherr BK3 is a derivate from ts7250 board
28
+
items:
29
+
- const: liebherr,bk3
30
+
- const: cirrus,ep9301
31
+
32
+
- description: EDB302 is an evaluation board by Cirrus Logic,
33
+
based on a Cirrus Logic EP9302 CPU
34
+
items:
35
+
- const: cirrus,edb9302
36
+
- const: cirrus,ep9301
37
+
38
+
additionalProperties: true
+42
Documentation/devicetree/bindings/ata/cirrus,ep9312-pata.yaml
+42
Documentation/devicetree/bindings/ata/cirrus,ep9312-pata.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/ata/cirrus,ep9312-pata.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Cirrus Logic EP9312 PATA controller
8
+
9
+
maintainers:
10
+
- Damien Le Moal <dlemoal@kernel.org>
11
+
12
+
properties:
13
+
compatible:
14
+
oneOf:
15
+
- const: cirrus,ep9312-pata
16
+
- items:
17
+
- const: cirrus,ep9315-pata
18
+
- const: cirrus,ep9312-pata
19
+
20
+
reg:
21
+
maxItems: 1
22
+
23
+
interrupts:
24
+
maxItems: 1
25
+
26
+
required:
27
+
- compatible
28
+
- reg
29
+
- interrupts
30
+
31
+
additionalProperties: false
32
+
33
+
examples:
34
+
- |
35
+
ide@800a0000 {
36
+
compatible = "cirrus,ep9312-pata";
37
+
reg = <0x800a0000 0x38>;
38
+
interrupt-parent = <&vic1>;
39
+
interrupts = <8>;
40
+
pinctrl-names = "default";
41
+
pinctrl-0 = <&ide_default_pins>;
42
+
};
+84
Documentation/devicetree/bindings/dma/cirrus,ep9301-dma-m2m.yaml
+84
Documentation/devicetree/bindings/dma/cirrus,ep9301-dma-m2m.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/dma/cirrus,ep9301-dma-m2m.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Cirrus Logic ep93xx SoC DMA controller
8
+
9
+
maintainers:
10
+
- Alexander Sverdlin <alexander.sverdlin@gmail.com>
11
+
- Nikita Shubin <nikita.shubin@maquefel.me>
12
+
13
+
allOf:
14
+
- $ref: dma-controller.yaml#
15
+
16
+
properties:
17
+
compatible:
18
+
oneOf:
19
+
- const: cirrus,ep9301-dma-m2m
20
+
- items:
21
+
- enum:
22
+
- cirrus,ep9302-dma-m2m
23
+
- cirrus,ep9307-dma-m2m
24
+
- cirrus,ep9312-dma-m2m
25
+
- cirrus,ep9315-dma-m2m
26
+
- const: cirrus,ep9301-dma-m2m
27
+
28
+
reg:
29
+
items:
30
+
- description: m2m0 channel registers
31
+
- description: m2m1 channel registers
32
+
33
+
clocks:
34
+
items:
35
+
- description: m2m0 channel gate clock
36
+
- description: m2m1 channel gate clock
37
+
38
+
clock-names:
39
+
items:
40
+
- const: m2m0
41
+
- const: m2m1
42
+
43
+
interrupts:
44
+
items:
45
+
- description: m2m0 channel interrupt
46
+
- description: m2m1 channel interrupt
47
+
48
+
'#dma-cells':
49
+
const: 2
50
+
description: |
51
+
The first cell is the unique device channel number as indicated by this
52
+
table for ep93xx:
53
+
54
+
10: SPI controller
55
+
11: IDE controller
56
+
57
+
The second cell is the DMA direction line number:
58
+
59
+
1: Memory to device
60
+
2: Device to memory
61
+
62
+
required:
63
+
- compatible
64
+
- reg
65
+
- clocks
66
+
- clock-names
67
+
- interrupts
68
+
69
+
additionalProperties: false
70
+
71
+
examples:
72
+
- |
73
+
#include <dt-bindings/clock/cirrus,ep9301-syscon.h>
74
+
dma-controller@80000100 {
75
+
compatible = "cirrus,ep9301-dma-m2m";
76
+
reg = <0x80000100 0x0040>,
77
+
<0x80000140 0x0040>;
78
+
clocks = <&syscon EP93XX_CLK_M2M0>,
79
+
<&syscon EP93XX_CLK_M2M1>;
80
+
clock-names = "m2m0", "m2m1";
81
+
interrupt-parent = <&vic0>;
82
+
interrupts = <17>, <18>;
83
+
#dma-cells = <2>;
84
+
};
+144
Documentation/devicetree/bindings/dma/cirrus,ep9301-dma-m2p.yaml
+144
Documentation/devicetree/bindings/dma/cirrus,ep9301-dma-m2p.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/dma/cirrus,ep9301-dma-m2p.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Cirrus Logic ep93xx SoC M2P DMA controller
8
+
9
+
maintainers:
10
+
- Alexander Sverdlin <alexander.sverdlin@gmail.com>
11
+
- Nikita Shubin <nikita.shubin@maquefel.me>
12
+
13
+
allOf:
14
+
- $ref: dma-controller.yaml#
15
+
16
+
properties:
17
+
compatible:
18
+
oneOf:
19
+
- const: cirrus,ep9301-dma-m2p
20
+
- items:
21
+
- enum:
22
+
- cirrus,ep9302-dma-m2p
23
+
- cirrus,ep9307-dma-m2p
24
+
- cirrus,ep9312-dma-m2p
25
+
- cirrus,ep9315-dma-m2p
26
+
- const: cirrus,ep9301-dma-m2p
27
+
28
+
reg:
29
+
items:
30
+
- description: m2p0 channel registers
31
+
- description: m2p1 channel registers
32
+
- description: m2p2 channel registers
33
+
- description: m2p3 channel registers
34
+
- description: m2p4 channel registers
35
+
- description: m2p5 channel registers
36
+
- description: m2p6 channel registers
37
+
- description: m2p7 channel registers
38
+
- description: m2p8 channel registers
39
+
- description: m2p9 channel registers
40
+
41
+
clocks:
42
+
items:
43
+
- description: m2p0 channel gate clock
44
+
- description: m2p1 channel gate clock
45
+
- description: m2p2 channel gate clock
46
+
- description: m2p3 channel gate clock
47
+
- description: m2p4 channel gate clock
48
+
- description: m2p5 channel gate clock
49
+
- description: m2p6 channel gate clock
50
+
- description: m2p7 channel gate clock
51
+
- description: m2p8 channel gate clock
52
+
- description: m2p9 channel gate clock
53
+
54
+
clock-names:
55
+
items:
56
+
- const: m2p0
57
+
- const: m2p1
58
+
- const: m2p2
59
+
- const: m2p3
60
+
- const: m2p4
61
+
- const: m2p5
62
+
- const: m2p6
63
+
- const: m2p7
64
+
- const: m2p8
65
+
- const: m2p9
66
+
67
+
interrupts:
68
+
items:
69
+
- description: m2p0 channel interrupt
70
+
- description: m2p1 channel interrupt
71
+
- description: m2p2 channel interrupt
72
+
- description: m2p3 channel interrupt
73
+
- description: m2p4 channel interrupt
74
+
- description: m2p5 channel interrupt
75
+
- description: m2p6 channel interrupt
76
+
- description: m2p7 channel interrupt
77
+
- description: m2p8 channel interrupt
78
+
- description: m2p9 channel interrupt
79
+
80
+
'#dma-cells':
81
+
const: 2
82
+
description: |
83
+
The first cell is the unique device channel number as indicated by this
84
+
table for ep93xx:
85
+
86
+
0: I2S channel 1
87
+
1: I2S channel 2 (unused)
88
+
2: AC97 channel 1 (unused)
89
+
3: AC97 channel 2 (unused)
90
+
4: AC97 channel 3 (unused)
91
+
5: I2S channel 3 (unused)
92
+
6: UART1 (unused)
93
+
7: UART2 (unused)
94
+
8: UART3 (unused)
95
+
9: IRDA (unused)
96
+
97
+
The second cell is the DMA direction line number:
98
+
99
+
1: Memory to device
100
+
2: Device to memory
101
+
102
+
required:
103
+
- compatible
104
+
- reg
105
+
- clocks
106
+
- clock-names
107
+
- interrupts
108
+
109
+
additionalProperties: false
110
+
111
+
examples:
112
+
- |
113
+
#include <dt-bindings/clock/cirrus,ep9301-syscon.h>
114
+
dma-controller@80000000 {
115
+
compatible = "cirrus,ep9301-dma-m2p";
116
+
reg = <0x80000000 0x0040>,
117
+
<0x80000040 0x0040>,
118
+
<0x80000080 0x0040>,
119
+
<0x800000c0 0x0040>,
120
+
<0x80000240 0x0040>,
121
+
<0x80000200 0x0040>,
122
+
<0x800002c0 0x0040>,
123
+
<0x80000280 0x0040>,
124
+
<0x80000340 0x0040>,
125
+
<0x80000300 0x0040>;
126
+
clocks = <&syscon EP93XX_CLK_M2P0>,
127
+
<&syscon EP93XX_CLK_M2P1>,
128
+
<&syscon EP93XX_CLK_M2P2>,
129
+
<&syscon EP93XX_CLK_M2P3>,
130
+
<&syscon EP93XX_CLK_M2P4>,
131
+
<&syscon EP93XX_CLK_M2P5>,
132
+
<&syscon EP93XX_CLK_M2P6>,
133
+
<&syscon EP93XX_CLK_M2P7>,
134
+
<&syscon EP93XX_CLK_M2P8>,
135
+
<&syscon EP93XX_CLK_M2P9>;
136
+
clock-names = "m2p0", "m2p1",
137
+
"m2p2", "m2p3",
138
+
"m2p4", "m2p5",
139
+
"m2p6", "m2p7",
140
+
"m2p8", "m2p9";
141
+
interrupt-parent = <&vic0>;
142
+
interrupts = <7>, <8>, <9>, <10>, <11>, <12>, <13>, <14>, <15>, <16>;
143
+
#dma-cells = <2>;
144
+
};
+6
-3
Documentation/devicetree/bindings/gpio/gpio-ep9301.yaml
+6
-3
Documentation/devicetree/bindings/gpio/gpio-ep9301.yaml
···
73
73
reg-names = "data", "dir", "intr";
74
74
gpio-controller;
75
75
#gpio-cells = <2>;
76
-
interrupt-controller;
77
-
interrupt-parent = <&vic1>;
78
-
interrupts = <27>;
76
+
interrupt-controller;
77
+
#interrupt-cells = <2>;
78
+
interrupt-parent = <&vic1>;
79
+
interrupts = <27>;
79
80
};
80
81
81
82
gpio@80840004 {
···
88
87
gpio-controller;
89
88
#gpio-cells = <2>;
90
89
interrupt-controller;
90
+
#interrupt-cells = <2>;
91
91
interrupt-parent = <&vic1>;
92
92
interrupts = <27>;
93
93
};
···
129
127
gpio-controller;
130
128
#gpio-cells = <2>;
131
129
interrupt-controller;
130
+
#interrupt-cells = <2>;
132
131
interrupts-extended = <&vic0 19>, <&vic0 20>,
133
132
<&vic0 21>, <&vic0 22>,
134
133
<&vic1 15>, <&vic1 16>,
+87
Documentation/devicetree/bindings/input/cirrus,ep9307-keypad.yaml
+87
Documentation/devicetree/bindings/input/cirrus,ep9307-keypad.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/input/cirrus,ep9307-keypad.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Cirrus ep93xx keypad
8
+
9
+
maintainers:
10
+
- Alexander Sverdlin <alexander.sverdlin@gmail.com>
11
+
12
+
allOf:
13
+
- $ref: /schemas/input/matrix-keymap.yaml#
14
+
15
+
description:
16
+
The KPP is designed to interface with a keypad matrix with 2-point contact
17
+
or 3-point contact keys. The KPP is designed to simplify the software task
18
+
of scanning a keypad matrix. The KPP is capable of detecting, debouncing,
19
+
and decoding one or multiple keys pressed simultaneously on a keypad.
20
+
21
+
properties:
22
+
compatible:
23
+
oneOf:
24
+
- const: cirrus,ep9307-keypad
25
+
- items:
26
+
- enum:
27
+
- cirrus,ep9312-keypad
28
+
- cirrus,ep9315-keypad
29
+
- const: cirrus,ep9307-keypad
30
+
31
+
reg:
32
+
maxItems: 1
33
+
34
+
interrupts:
35
+
maxItems: 1
36
+
37
+
clocks:
38
+
maxItems: 1
39
+
40
+
debounce-delay-ms:
41
+
description: |
42
+
Time in microseconds that key must be pressed or
43
+
released for state change interrupt to trigger.
44
+
45
+
cirrus,prescale:
46
+
description: row/column counter pre-scaler load value
47
+
$ref: /schemas/types.yaml#/definitions/uint16
48
+
maximum: 1023
49
+
50
+
required:
51
+
- compatible
52
+
- reg
53
+
- interrupts
54
+
- clocks
55
+
- linux,keymap
56
+
57
+
unevaluatedProperties: false
58
+
59
+
examples:
60
+
- |
61
+
#include <dt-bindings/input/input.h>
62
+
#include <dt-bindings/clock/cirrus,ep9301-syscon.h>
63
+
keypad@800f0000 {
64
+
compatible = "cirrus,ep9307-keypad";
65
+
reg = <0x800f0000 0x0c>;
66
+
interrupt-parent = <&vic0>;
67
+
interrupts = <29>;
68
+
clocks = <&eclk EP93XX_CLK_KEYPAD>;
69
+
pinctrl-names = "default";
70
+
pinctrl-0 = <&keypad_default_pins>;
71
+
linux,keymap = <KEY_UP>,
72
+
<KEY_DOWN>,
73
+
<KEY_VOLUMEDOWN>,
74
+
<KEY_HOME>,
75
+
<KEY_RIGHT>,
76
+
<KEY_LEFT>,
77
+
<KEY_ENTER>,
78
+
<KEY_VOLUMEUP>,
79
+
<KEY_F6>,
80
+
<KEY_F8>,
81
+
<KEY_F9>,
82
+
<KEY_F10>,
83
+
<KEY_F1>,
84
+
<KEY_F2>,
85
+
<KEY_F3>,
86
+
<KEY_POWER>;
87
+
};
+45
Documentation/devicetree/bindings/mtd/technologic,nand.yaml
+45
Documentation/devicetree/bindings/mtd/technologic,nand.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/mtd/technologic,nand.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Technologic Systems NAND controller
8
+
9
+
maintainers:
10
+
- Nikita Shubin <nikita.shubin@maquefel.me>
11
+
12
+
allOf:
13
+
- $ref: nand-controller.yaml
14
+
15
+
properties:
16
+
compatible:
17
+
oneOf:
18
+
- const: technologic,ts7200-nand
19
+
- items:
20
+
- enum:
21
+
- technologic,ts7300-nand
22
+
- technologic,ts7260-nand
23
+
- technologic,ts7250-nand
24
+
- const: technologic,ts7200-nand
25
+
26
+
reg:
27
+
maxItems: 1
28
+
29
+
required:
30
+
- compatible
31
+
- reg
32
+
33
+
unevaluatedProperties: false
34
+
35
+
examples:
36
+
- |
37
+
nand-controller@60000000 {
38
+
compatible = "technologic,ts7200-nand";
39
+
reg = <0x60000000 0x8000000>;
40
+
#address-cells = <1>;
41
+
#size-cells = <0>;
42
+
nand@0 {
43
+
reg = <0>;
44
+
};
45
+
};
+59
Documentation/devicetree/bindings/net/cirrus,ep9301-eth.yaml
+59
Documentation/devicetree/bindings/net/cirrus,ep9301-eth.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/net/cirrus,ep9301-eth.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: EP93xx SoC Ethernet Controller
8
+
9
+
maintainers:
10
+
- Alexander Sverdlin <alexander.sverdlin@gmail.com>
11
+
- Nikita Shubin <nikita.shubin@maquefel.me>
12
+
13
+
allOf:
14
+
- $ref: ethernet-controller.yaml#
15
+
16
+
properties:
17
+
compatible:
18
+
oneOf:
19
+
- const: cirrus,ep9301-eth
20
+
- items:
21
+
- enum:
22
+
- cirrus,ep9302-eth
23
+
- cirrus,ep9307-eth
24
+
- cirrus,ep9312-eth
25
+
- cirrus,ep9315-eth
26
+
- const: cirrus,ep9301-eth
27
+
28
+
reg:
29
+
items:
30
+
- description: The physical base address and size of IO range
31
+
32
+
interrupts:
33
+
items:
34
+
- description: Combined signal for various interrupt events
35
+
36
+
phy-handle: true
37
+
38
+
mdio:
39
+
$ref: mdio.yaml#
40
+
unevaluatedProperties: false
41
+
description: optional node for embedded MDIO controller
42
+
43
+
required:
44
+
- compatible
45
+
- reg
46
+
- interrupts
47
+
- phy-handle
48
+
49
+
additionalProperties: false
50
+
51
+
examples:
52
+
- |
53
+
ethernet@80010000 {
54
+
compatible = "cirrus,ep9301-eth";
55
+
reg = <0x80010000 0x10000>;
56
+
interrupt-parent = <&vic1>;
57
+
interrupts = <7>;
58
+
phy-handle = <&phy0>;
59
+
};
+53
Documentation/devicetree/bindings/pwm/cirrus,ep9301-pwm.yaml
+53
Documentation/devicetree/bindings/pwm/cirrus,ep9301-pwm.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pwm/cirrus,ep9301-pwm.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Cirrus Logic ep93xx PWM controller
8
+
9
+
maintainers:
10
+
- Alexander Sverdlin <alexander.sverdlin@gmail.com>
11
+
- Nikita Shubin <nikita.shubin@maquefel.me>
12
+
13
+
allOf:
14
+
- $ref: pwm.yaml#
15
+
16
+
properties:
17
+
compatible:
18
+
oneOf:
19
+
- const: cirrus,ep9301-pwm
20
+
- items:
21
+
- enum:
22
+
- cirrus,ep9302-pwm
23
+
- cirrus,ep9307-pwm
24
+
- cirrus,ep9312-pwm
25
+
- cirrus,ep9315-pwm
26
+
- const: cirrus,ep9301-pwm
27
+
28
+
reg:
29
+
maxItems: 1
30
+
31
+
clocks:
32
+
items:
33
+
- description: SoC PWM clock
34
+
35
+
"#pwm-cells":
36
+
const: 3
37
+
38
+
required:
39
+
- compatible
40
+
- reg
41
+
- clocks
42
+
43
+
unevaluatedProperties: false
44
+
45
+
examples:
46
+
- |
47
+
#include <dt-bindings/clock/cirrus,ep9301-syscon.h>
48
+
pwm@80910000 {
49
+
compatible = "cirrus,ep9301-pwm";
50
+
reg = <0x80910000 0x10>;
51
+
clocks = <&syscon EP93XX_CLK_PWM>;
52
+
#pwm-cells = <3>;
53
+
};
+94
Documentation/devicetree/bindings/soc/cirrus/cirrus,ep9301-syscon.yaml
+94
Documentation/devicetree/bindings/soc/cirrus/cirrus,ep9301-syscon.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/soc/cirrus/cirrus,ep9301-syscon.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Cirrus Logic EP93xx Platforms System Controller
8
+
9
+
maintainers:
10
+
- Alexander Sverdlin <alexander.sverdlin@gmail.com>
11
+
- Nikita Shubin <nikita.shubin@maquefel.me>
12
+
13
+
description: |
14
+
Central resources are controlled by a set of software-locked registers,
15
+
which can be used to prevent accidental accesses. Syscon generates
16
+
the various bus and peripheral clocks and controls the system startup
17
+
configuration.
18
+
19
+
The System Controller (Syscon) provides:
20
+
- Clock control
21
+
- Power management
22
+
- System configuration management
23
+
24
+
Syscon registers are common for all EP93xx SoC's, through some actual peripheral
25
+
may be missing depending on actual SoC model.
26
+
27
+
properties:
28
+
compatible:
29
+
oneOf:
30
+
- items:
31
+
- enum:
32
+
- cirrus,ep9302-syscon
33
+
- cirrus,ep9307-syscon
34
+
- cirrus,ep9312-syscon
35
+
- cirrus,ep9315-syscon
36
+
- const: cirrus,ep9301-syscon
37
+
- const: syscon
38
+
- items:
39
+
- const: cirrus,ep9301-syscon
40
+
- const: syscon
41
+
42
+
reg:
43
+
maxItems: 1
44
+
45
+
"#clock-cells":
46
+
const: 1
47
+
48
+
clocks:
49
+
items:
50
+
- description: reference clock
51
+
52
+
patternProperties:
53
+
'^pins-':
54
+
type: object
55
+
description: pin node
56
+
$ref: /schemas/pinctrl/pinmux-node.yaml
57
+
58
+
properties:
59
+
function:
60
+
enum: [ spi, ac97, i2s, pwm, keypad, pata, lcd, gpio ]
61
+
62
+
groups:
63
+
enum: [ ssp, ac97, i2s_on_ssp, i2s_on_ac97, pwm1, gpio1agrp,
64
+
gpio2agrp, gpio3agrp, gpio4agrp, gpio6agrp, gpio7agrp,
65
+
rasteronsdram0grp, rasteronsdram3grp, keypadgrp, idegrp ]
66
+
67
+
required:
68
+
- function
69
+
- groups
70
+
71
+
unevaluatedProperties: false
72
+
73
+
required:
74
+
- compatible
75
+
- reg
76
+
- "#clock-cells"
77
+
- clocks
78
+
79
+
additionalProperties: false
80
+
81
+
examples:
82
+
- |
83
+
syscon@80930000 {
84
+
compatible = "cirrus,ep9301-syscon", "syscon";
85
+
reg = <0x80930000 0x1000>;
86
+
87
+
#clock-cells = <1>;
88
+
clocks = <&xtali>;
89
+
90
+
spi_default_pins: pins-spi {
91
+
function = "spi";
92
+
groups = "ssp";
93
+
};
94
+
};
+16
Documentation/devicetree/bindings/sound/cirrus,ep9301-i2s.yaml
+16
Documentation/devicetree/bindings/sound/cirrus,ep9301-i2s.yaml
···
40
40
- const: sclk
41
41
- const: lrclk
42
42
43
+
dmas:
44
+
items:
45
+
- description: out DMA channel
46
+
- description: in DMA channel
47
+
48
+
dma-names:
49
+
items:
50
+
- const: tx
51
+
- const: rx
52
+
53
+
port:
54
+
$ref: audio-graph-port.yaml#
55
+
unevaluatedProperties: false
56
+
43
57
required:
44
58
- compatible
45
59
- '#sound-dai-cells'
···
75
61
<&syscon 30>,
76
62
<&syscon 31>;
77
63
clock-names = "mclk", "sclk", "lrclk";
64
+
dmas = <&dma0 0 1>, <&dma0 0 2>;
65
+
dma-names = "tx", "rx";
78
66
};
79
67
80
68
...
+70
Documentation/devicetree/bindings/spi/cirrus,ep9301-spi.yaml
+70
Documentation/devicetree/bindings/spi/cirrus,ep9301-spi.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/spi/cirrus,ep9301-spi.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: EP93xx SoC SPI controller
8
+
9
+
maintainers:
10
+
- Alexander Sverdlin <alexander.sverdlin@gmail.com>
11
+
- Nikita Shubin <nikita.shubin@maquefel.me>
12
+
13
+
allOf:
14
+
- $ref: spi-controller.yaml#
15
+
16
+
properties:
17
+
compatible:
18
+
oneOf:
19
+
- const: cirrus,ep9301-spi
20
+
- items:
21
+
- enum:
22
+
- cirrus,ep9302-spi
23
+
- cirrus,ep9307-spi
24
+
- cirrus,ep9312-spi
25
+
- cirrus,ep9315-spi
26
+
- const: cirrus,ep9301-spi
27
+
28
+
reg:
29
+
items:
30
+
- description: SPI registers region
31
+
32
+
interrupts:
33
+
maxItems: 1
34
+
35
+
clocks:
36
+
items:
37
+
- description: SPI Controller reference clock source
38
+
39
+
dmas:
40
+
items:
41
+
- description: rx DMA channel
42
+
- description: tx DMA channel
43
+
44
+
dma-names:
45
+
items:
46
+
- const: rx
47
+
- const: tx
48
+
49
+
required:
50
+
- compatible
51
+
- reg
52
+
- interrupts
53
+
- clocks
54
+
55
+
unevaluatedProperties: false
56
+
57
+
examples:
58
+
- |
59
+
#include <dt-bindings/gpio/gpio.h>
60
+
#include <dt-bindings/clock/cirrus,ep9301-syscon.h>
61
+
spi@808a0000 {
62
+
compatible = "cirrus,ep9301-spi";
63
+
reg = <0x808a0000 0x18>;
64
+
interrupt-parent = <&vic1>;
65
+
interrupts = <21>;
66
+
clocks = <&syscon EP93XX_CLK_SPI>;
67
+
dmas = <&dma1 10 2>, <&dma1 10 1>;
68
+
dma-names = "rx", "tx";
69
+
cs-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
70
+
};
+1
MAINTAINERS
+1
MAINTAINERS
···
2272
2272
ARM/CIRRUS LOGIC EP93XX ARM ARCHITECTURE
2273
2273
M: Hartley Sweeten <hsweeten@visionengravers.com>
2274
2274
M: Alexander Sverdlin <alexander.sverdlin@gmail.com>
2275
+
M: Nikita Shubin <nikita.shubin@maquefel.me>
2275
2276
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
2276
2277
S: Maintained
2277
2278
F: Documentation/devicetree/bindings/iio/adc/cirrus,ep9301-adc.yaml
-1
arch/arm/Makefile
-1
arch/arm/Makefile
···
183
183
machine-$(CONFIG_ARCH_DAVINCI) += davinci
184
184
machine-$(CONFIG_ARCH_DIGICOLOR) += digicolor
185
185
machine-$(CONFIG_ARCH_DOVE) += dove
186
-
machine-$(CONFIG_ARCH_EP93XX) += ep93xx
187
186
machine-$(CONFIG_ARCH_EXYNOS) += exynos
188
187
machine-$(CONFIG_ARCH_FOOTBRIDGE) += footbridge
189
188
machine-$(CONFIG_ARCH_GEMINI) += gemini
+4
arch/arm/boot/dts/cirrus/Makefile
+4
arch/arm/boot/dts/cirrus/Makefile
+125
arch/arm/boot/dts/cirrus/ep93xx-bk3.dts
+125
arch/arm/boot/dts/cirrus/ep93xx-bk3.dts
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Device Tree file for Liebherr controller BK3.1 based on Cirrus EP9302 SoC
4
+
*/
5
+
/dts-v1/;
6
+
#include "ep93xx.dtsi"
7
+
8
+
/ {
9
+
model = "Liebherr controller BK3.1";
10
+
compatible = "liebherr,bk3", "cirrus,ep9301";
11
+
#address-cells = <1>;
12
+
#size-cells = <1>;
13
+
14
+
chosen {
15
+
};
16
+
17
+
memory@0 {
18
+
device_type = "memory";
19
+
/* should be set from ATAGS */
20
+
reg = <0x00000000 0x02000000>,
21
+
<0x000530c0 0x01fdd000>;
22
+
};
23
+
24
+
leds {
25
+
compatible = "gpio-leds";
26
+
led-0 {
27
+
label = "grled";
28
+
gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
29
+
linux,default-trigger = "heartbeat";
30
+
function = LED_FUNCTION_HEARTBEAT;
31
+
};
32
+
33
+
led-1 {
34
+
label = "rdled";
35
+
gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>;
36
+
function = LED_FUNCTION_FAULT;
37
+
};
38
+
};
39
+
};
40
+
41
+
&ebi {
42
+
nand-controller@60000000 {
43
+
compatible = "technologic,ts7200-nand";
44
+
reg = <0x60000000 0x8000000>;
45
+
#address-cells = <1>;
46
+
#size-cells = <0>;
47
+
48
+
nand@0 {
49
+
reg = <0>;
50
+
partitions {
51
+
compatible = "fixed-partitions";
52
+
#address-cells = <1>;
53
+
#size-cells = <1>;
54
+
55
+
partition@0 {
56
+
label = "System";
57
+
reg = <0x00000000 0x01e00000>;
58
+
read-only;
59
+
};
60
+
61
+
partition@1e00000 {
62
+
label = "Data";
63
+
reg = <0x01e00000 0x05f20000>;
64
+
};
65
+
66
+
partition@7d20000 {
67
+
label = "RedBoot";
68
+
reg = <0x07d20000 0x002e0000>;
69
+
read-only;
70
+
};
71
+
};
72
+
};
73
+
};
74
+
};
75
+
76
+
ð0 {
77
+
phy-handle = <&phy0>;
78
+
};
79
+
80
+
&i2s {
81
+
dmas = <&dma0 0 1>, <&dma0 0 2>;
82
+
dma-names = "tx", "rx";
83
+
pinctrl-names = "default";
84
+
pinctrl-0 = <&i2s_on_ac97_pins>;
85
+
status = "okay";
86
+
};
87
+
88
+
&gpio1 {
89
+
/* PWM */
90
+
gpio-ranges = <&syscon 6 163 1>;
91
+
};
92
+
93
+
&gpio4 {
94
+
gpio-ranges = <&syscon 0 97 2>;
95
+
status = "okay";
96
+
};
97
+
98
+
&gpio6 {
99
+
gpio-ranges = <&syscon 0 87 2>;
100
+
status = "okay";
101
+
};
102
+
103
+
&gpio7 {
104
+
gpio-ranges = <&syscon 2 199 4>;
105
+
status = "okay";
106
+
};
107
+
108
+
&mdio0 {
109
+
phy0: ethernet-phy@1 {
110
+
reg = <1>;
111
+
device_type = "ethernet-phy";
112
+
};
113
+
};
114
+
115
+
&uart0 {
116
+
status = "okay";
117
+
};
118
+
119
+
&uart1 {
120
+
status = "okay";
121
+
};
122
+
123
+
&usb0 {
124
+
status = "okay";
125
+
};
+181
arch/arm/boot/dts/cirrus/ep93xx-edb9302.dts
+181
arch/arm/boot/dts/cirrus/ep93xx-edb9302.dts
···
1
+
// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
/*
3
+
* Device Tree file for Cirrus Logic EDB9302 board based on EP9302 SoC
4
+
*/
5
+
/dts-v1/;
6
+
#include "ep93xx.dtsi"
7
+
8
+
/ {
9
+
#address-cells = <1>;
10
+
#size-cells = <1>;
11
+
compatible = "cirrus,edb9302", "cirrus,ep9301";
12
+
model = "cirrus,edb9302";
13
+
14
+
chosen {
15
+
};
16
+
17
+
memory@0 {
18
+
device_type = "memory";
19
+
/* should be set from ATAGS */
20
+
reg = <0x0000000 0x800000>,
21
+
<0x1000000 0x800000>,
22
+
<0x4000000 0x800000>,
23
+
<0x5000000 0x800000>;
24
+
};
25
+
26
+
sound {
27
+
compatible = "audio-graph-card2";
28
+
label = "EDB93XX";
29
+
links = <&i2s_port>;
30
+
};
31
+
32
+
leds {
33
+
compatible = "gpio-leds";
34
+
led-0 {
35
+
label = "grled";
36
+
gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
37
+
linux,default-trigger = "heartbeat";
38
+
function = LED_FUNCTION_HEARTBEAT;
39
+
};
40
+
41
+
led-1 {
42
+
label = "rdled";
43
+
gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>;
44
+
function = LED_FUNCTION_FAULT;
45
+
};
46
+
};
47
+
};
48
+
49
+
&adc {
50
+
status = "okay";
51
+
};
52
+
53
+
&ebi {
54
+
flash@60000000 {
55
+
compatible = "cfi-flash";
56
+
reg = <0x60000000 0x1000000>;
57
+
bank-width = <2>;
58
+
};
59
+
};
60
+
61
+
ð0 {
62
+
phy-handle = <&phy0>;
63
+
};
64
+
65
+
&gpio0 {
66
+
gpio-ranges = <&syscon 0 153 1>,
67
+
<&syscon 1 152 1>,
68
+
<&syscon 2 151 1>,
69
+
<&syscon 3 148 1>,
70
+
<&syscon 4 147 1>,
71
+
<&syscon 5 146 1>,
72
+
<&syscon 6 145 1>,
73
+
<&syscon 7 144 1>;
74
+
};
75
+
76
+
&gpio1 {
77
+
gpio-ranges = <&syscon 0 143 1>,
78
+
<&syscon 1 142 1>,
79
+
<&syscon 2 141 1>,
80
+
<&syscon 3 140 1>,
81
+
<&syscon 4 165 1>,
82
+
<&syscon 5 164 1>,
83
+
<&syscon 6 163 1>,
84
+
<&syscon 7 160 1>;
85
+
};
86
+
87
+
&gpio2 {
88
+
gpio-ranges = <&syscon 0 115 1>;
89
+
};
90
+
91
+
/* edb9302 doesn't have GPIO Port D present */
92
+
&gpio3 {
93
+
status = "disabled";
94
+
};
95
+
96
+
&gpio4 {
97
+
gpio-ranges = <&syscon 0 97 2>;
98
+
};
99
+
100
+
&gpio5 {
101
+
gpio-ranges = <&syscon 1 170 1>,
102
+
<&syscon 2 169 1>,
103
+
<&syscon 3 168 1>;
104
+
};
105
+
106
+
&gpio6 {
107
+
gpio-ranges = <&syscon 0 87 2>;
108
+
};
109
+
110
+
&gpio7 {
111
+
gpio-ranges = <&syscon 2 199 4>;
112
+
};
113
+
114
+
&i2s {
115
+
pinctrl-names = "default";
116
+
pinctrl-0 = <&i2s_on_ac97_pins>;
117
+
status = "okay";
118
+
i2s_port: port {
119
+
i2s_ep: endpoint {
120
+
system-clock-direction-out;
121
+
frame-master;
122
+
bitclock-master;
123
+
mclk-fs = <256>;
124
+
dai-format = "i2s";
125
+
convert-channels = <2>;
126
+
convert-sample-format = "s32_le";
127
+
remote-endpoint = <&codec_ep>;
128
+
};
129
+
};
130
+
};
131
+
132
+
&mdio0 {
133
+
phy0: ethernet-phy@1 {
134
+
reg = <1>;
135
+
device_type = "ethernet-phy";
136
+
};
137
+
};
138
+
139
+
&spi0 {
140
+
cs-gpios = <&gpio0 6 GPIO_ACTIVE_LOW
141
+
&gpio0 7 GPIO_ACTIVE_LOW>;
142
+
dmas = <&dma1 10 2>, <&dma1 10 1>;
143
+
dma-names = "rx", "tx";
144
+
status = "okay";
145
+
146
+
cs4271: codec@0 {
147
+
compatible = "cirrus,cs4271";
148
+
reg = <0>;
149
+
#sound-dai-cells = <0>;
150
+
spi-max-frequency = <6000000>;
151
+
spi-cpol;
152
+
spi-cpha;
153
+
reset-gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
154
+
port {
155
+
codec_ep: endpoint {
156
+
remote-endpoint = <&i2s_ep>;
157
+
};
158
+
};
159
+
};
160
+
161
+
at25f1024: eeprom@1 {
162
+
compatible = "atmel,at25";
163
+
reg = <1>;
164
+
address-width = <8>;
165
+
size = <0x20000>;
166
+
pagesize = <256>;
167
+
spi-max-frequency = <20000000>;
168
+
};
169
+
};
170
+
171
+
&uart0 {
172
+
status = "okay";
173
+
};
174
+
175
+
&uart1 {
176
+
status = "okay";
177
+
};
178
+
179
+
&usb0 {
180
+
status = "okay";
181
+
};
+145
arch/arm/boot/dts/cirrus/ep93xx-ts7250.dts
+145
arch/arm/boot/dts/cirrus/ep93xx-ts7250.dts
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Device Tree file for Technologic Systems ts7250 board based on Cirrus EP9302 SoC
4
+
*/
5
+
/dts-v1/;
6
+
#include "ep93xx.dtsi"
7
+
8
+
/ {
9
+
compatible = "technologic,ts7250", "cirrus,ep9301";
10
+
model = "TS-7250 SBC";
11
+
#address-cells = <1>;
12
+
#size-cells = <1>;
13
+
14
+
chosen {
15
+
};
16
+
17
+
memory@0 {
18
+
device_type = "memory";
19
+
/* should be set from ATAGS */
20
+
reg = <0x00000000 0x02000000>,
21
+
<0x000530c0 0x01fdd000>;
22
+
};
23
+
24
+
leds {
25
+
compatible = "gpio-leds";
26
+
led-0 {
27
+
label = "grled";
28
+
gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
29
+
linux,default-trigger = "heartbeat";
30
+
function = LED_FUNCTION_HEARTBEAT;
31
+
};
32
+
33
+
led-1 {
34
+
label = "rdled";
35
+
gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>;
36
+
function = LED_FUNCTION_FAULT;
37
+
};
38
+
};
39
+
};
40
+
41
+
&ebi {
42
+
nand-controller@60000000 {
43
+
compatible = "technologic,ts7200-nand";
44
+
reg = <0x60000000 0x8000000>;
45
+
#address-cells = <1>;
46
+
#size-cells = <0>;
47
+
48
+
nand@0 {
49
+
reg = <0>;
50
+
partitions {
51
+
compatible = "fixed-partitions";
52
+
#address-cells = <1>;
53
+
#size-cells = <1>;
54
+
55
+
partition@0 {
56
+
label = "TS-BOOTROM";
57
+
reg = <0x00000000 0x00020000>;
58
+
read-only;
59
+
};
60
+
61
+
partition@20000 {
62
+
label = "Linux";
63
+
reg = <0x00020000 0x07d00000>;
64
+
};
65
+
66
+
partition@7d20000 {
67
+
label = "RedBoot";
68
+
reg = <0x07d20000 0x002e0000>;
69
+
read-only;
70
+
};
71
+
};
72
+
};
73
+
};
74
+
75
+
rtc@10800000 {
76
+
compatible = "st,m48t86";
77
+
reg = <0x10800000 0x1>,
78
+
<0x11700000 0x1>;
79
+
};
80
+
81
+
watchdog@23800000 {
82
+
compatible = "technologic,ts7200-wdt";
83
+
reg = <0x23800000 0x01>,
84
+
<0x23c00000 0x01>;
85
+
timeout-sec = <30>;
86
+
};
87
+
};
88
+
89
+
ð0 {
90
+
phy-handle = <&phy0>;
91
+
};
92
+
93
+
&gpio1 {
94
+
/* PWM */
95
+
gpio-ranges = <&syscon 6 163 1>;
96
+
};
97
+
98
+
/* ts7250 doesn't have GPIO Port D present */
99
+
&gpio3 {
100
+
status = "disabled";
101
+
};
102
+
103
+
&gpio4 {
104
+
gpio-ranges = <&syscon 0 97 2>;
105
+
};
106
+
107
+
&gpio6 {
108
+
gpio-ranges = <&syscon 0 87 2>;
109
+
};
110
+
111
+
&gpio7 {
112
+
gpio-ranges = <&syscon 2 199 4>;
113
+
};
114
+
115
+
&spi0 {
116
+
cs-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
117
+
dmas = <&dma1 10 2>, <&dma1 10 1>;
118
+
dma-names = "rx", "tx";
119
+
status = "okay";
120
+
121
+
tmp122: temperature-sensor@0 {
122
+
compatible = "ti,tmp122";
123
+
reg = <0>;
124
+
spi-max-frequency = <2000000>;
125
+
};
126
+
};
127
+
128
+
&mdio0 {
129
+
phy0: ethernet-phy@1 {
130
+
reg = <1>;
131
+
device_type = "ethernet-phy";
132
+
};
133
+
};
134
+
135
+
&uart0 {
136
+
status = "okay";
137
+
};
138
+
139
+
&uart1 {
140
+
status = "okay";
141
+
};
142
+
143
+
&usb0 {
144
+
status = "okay";
145
+
};
+444
arch/arm/boot/dts/cirrus/ep93xx.dtsi
+444
arch/arm/boot/dts/cirrus/ep93xx.dtsi
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Device Tree file for Cirrus Logic systems EP93XX SoC
4
+
*/
5
+
#include <dt-bindings/gpio/gpio.h>
6
+
#include <dt-bindings/leds/common.h>
7
+
#include <dt-bindings/input/input.h>
8
+
#include <dt-bindings/clock/cirrus,ep9301-syscon.h>
9
+
/ {
10
+
soc: soc {
11
+
compatible = "simple-bus";
12
+
ranges;
13
+
#address-cells = <1>;
14
+
#size-cells = <1>;
15
+
16
+
syscon: syscon@80930000 {
17
+
compatible = "cirrus,ep9301-syscon", "syscon";
18
+
reg = <0x80930000 0x1000>;
19
+
20
+
#clock-cells = <1>;
21
+
clocks = <&xtali>;
22
+
23
+
spi_default_pins: pins-spi {
24
+
function = "spi";
25
+
groups = "ssp";
26
+
};
27
+
28
+
ac97_default_pins: pins-ac97 {
29
+
function = "ac97";
30
+
groups = "ac97";
31
+
};
32
+
33
+
i2s_on_ssp_pins: pins-i2sonssp {
34
+
function = "i2s";
35
+
groups = "i2s_on_ssp";
36
+
};
37
+
38
+
i2s_on_ac97_pins: pins-i2sonac97 {
39
+
function = "i2s";
40
+
groups = "i2s_on_ac97";
41
+
};
42
+
43
+
gpio1_default_pins: pins-gpio1 {
44
+
function = "gpio";
45
+
groups = "gpio1agrp";
46
+
};
47
+
48
+
pwm1_default_pins: pins-pwm1 {
49
+
function = "pwm";
50
+
groups = "pwm1";
51
+
};
52
+
53
+
gpio2_default_pins: pins-gpio2 {
54
+
function = "gpio";
55
+
groups = "gpio2agrp";
56
+
};
57
+
58
+
gpio3_default_pins: pins-gpio3 {
59
+
function = "gpio";
60
+
groups = "gpio3agrp";
61
+
};
62
+
63
+
keypad_default_pins: pins-keypad {
64
+
function = "keypad";
65
+
groups = "keypadgrp";
66
+
};
67
+
68
+
gpio4_default_pins: pins-gpio4 {
69
+
function = "gpio";
70
+
groups = "gpio4agrp";
71
+
};
72
+
73
+
gpio6_default_pins: pins-gpio6 {
74
+
function = "gpio";
75
+
groups = "gpio6agrp";
76
+
};
77
+
78
+
gpio7_default_pins: pins-gpio7 {
79
+
function = "gpio";
80
+
groups = "gpio7agrp";
81
+
};
82
+
83
+
ide_default_pins: pins-ide {
84
+
function = "pata";
85
+
groups = "idegrp";
86
+
};
87
+
88
+
lcd_on_dram0_pins: pins-rasteronsdram0 {
89
+
function = "lcd";
90
+
groups = "rasteronsdram0grp";
91
+
};
92
+
93
+
lcd_on_dram3_pins: pins-rasteronsdram3 {
94
+
function = "lcd";
95
+
groups = "rasteronsdram3grp";
96
+
};
97
+
};
98
+
99
+
adc: adc@80900000 {
100
+
compatible = "cirrus,ep9301-adc";
101
+
reg = <0x80900000 0x28>;
102
+
clocks = <&syscon EP93XX_CLK_ADC>;
103
+
interrupt-parent = <&vic0>;
104
+
interrupts = <30>;
105
+
status = "disabled";
106
+
};
107
+
108
+
/*
109
+
* The EP93XX expansion bus is a set of up to 7 each up to 16MB
110
+
* windows in the 256MB space from 0x50000000 to 0x5fffffff.
111
+
* But since we don't require to setup it in any way, we can
112
+
* represent it as a simple-bus.
113
+
*/
114
+
ebi: bus@80080000 {
115
+
compatible = "simple-bus";
116
+
reg = <0x80080000 0x20>;
117
+
native-endian;
118
+
#address-cells = <1>;
119
+
#size-cells = <1>;
120
+
ranges;
121
+
};
122
+
123
+
dma0: dma-controller@80000000 {
124
+
compatible = "cirrus,ep9301-dma-m2p";
125
+
reg = <0x80000000 0x0040>,
126
+
<0x80000040 0x0040>,
127
+
<0x80000080 0x0040>,
128
+
<0x800000c0 0x0040>,
129
+
<0x80000240 0x0040>,
130
+
<0x80000200 0x0040>,
131
+
<0x800002c0 0x0040>,
132
+
<0x80000280 0x0040>,
133
+
<0x80000340 0x0040>,
134
+
<0x80000300 0x0040>;
135
+
clocks = <&syscon EP93XX_CLK_M2P0>,
136
+
<&syscon EP93XX_CLK_M2P1>,
137
+
<&syscon EP93XX_CLK_M2P2>,
138
+
<&syscon EP93XX_CLK_M2P3>,
139
+
<&syscon EP93XX_CLK_M2P4>,
140
+
<&syscon EP93XX_CLK_M2P5>,
141
+
<&syscon EP93XX_CLK_M2P6>,
142
+
<&syscon EP93XX_CLK_M2P7>,
143
+
<&syscon EP93XX_CLK_M2P8>,
144
+
<&syscon EP93XX_CLK_M2P9>;
145
+
clock-names = "m2p0", "m2p1",
146
+
"m2p2", "m2p3",
147
+
"m2p4", "m2p5",
148
+
"m2p6", "m2p7",
149
+
"m2p8", "m2p9";
150
+
interrupt-parent = <&vic0>;
151
+
interrupts = <7>, <8>, <9>, <10>, <11>,
152
+
<12>, <13>, <14>, <15>, <16>;
153
+
#dma-cells = <2>;
154
+
};
155
+
156
+
dma1: dma-controller@80000100 {
157
+
compatible = "cirrus,ep9301-dma-m2m";
158
+
reg = <0x80000100 0x0040>,
159
+
<0x80000140 0x0040>;
160
+
clocks = <&syscon EP93XX_CLK_M2M0>,
161
+
<&syscon EP93XX_CLK_M2M1>;
162
+
clock-names = "m2m0", "m2m1";
163
+
interrupt-parent = <&vic0>;
164
+
interrupts = <17>, <18>;
165
+
#dma-cells = <2>;
166
+
};
167
+
168
+
eth0: ethernet@80010000 {
169
+
compatible = "cirrus,ep9301-eth";
170
+
reg = <0x80010000 0x10000>;
171
+
interrupt-parent = <&vic1>;
172
+
interrupts = <7>;
173
+
mdio0: mdio {
174
+
#address-cells = <1>;
175
+
#size-cells = <0>;
176
+
};
177
+
};
178
+
179
+
gpio0: gpio@80840000 {
180
+
compatible = "cirrus,ep9301-gpio";
181
+
reg = <0x80840000 0x04>,
182
+
<0x80840010 0x04>,
183
+
<0x80840090 0x1c>;
184
+
reg-names = "data", "dir", "intr";
185
+
gpio-controller;
186
+
#gpio-cells = <2>;
187
+
interrupt-controller;
188
+
#interrupt-cells = <2>;
189
+
interrupt-parent = <&vic1>;
190
+
interrupts = <27>;
191
+
};
192
+
193
+
gpio1: gpio@80840004 {
194
+
compatible = "cirrus,ep9301-gpio";
195
+
reg = <0x80840004 0x04>,
196
+
<0x80840014 0x04>,
197
+
<0x808400ac 0x1c>;
198
+
reg-names = "data", "dir", "intr";
199
+
gpio-controller;
200
+
#gpio-cells = <2>;
201
+
interrupt-controller;
202
+
#interrupt-cells = <2>;
203
+
interrupt-parent = <&vic1>;
204
+
interrupts = <27>;
205
+
};
206
+
207
+
gpio2: gpio@80840008 {
208
+
compatible = "cirrus,ep9301-gpio";
209
+
reg = <0x80840008 0x04>,
210
+
<0x80840018 0x04>;
211
+
reg-names = "data", "dir";
212
+
gpio-controller;
213
+
#gpio-cells = <2>;
214
+
pinctrl-names = "default";
215
+
pinctrl-0 = <&gpio2_default_pins>;
216
+
};
217
+
218
+
gpio3: gpio@8084000c {
219
+
compatible = "cirrus,ep9301-gpio";
220
+
reg = <0x8084000c 0x04>,
221
+
<0x8084001c 0x04>;
222
+
reg-names = "data", "dir";
223
+
gpio-controller;
224
+
#gpio-cells = <2>;
225
+
pinctrl-names = "default";
226
+
pinctrl-0 = <&gpio3_default_pins>;
227
+
};
228
+
229
+
gpio4: gpio@80840020 {
230
+
compatible = "cirrus,ep9301-gpio";
231
+
reg = <0x80840020 0x04>,
232
+
<0x80840024 0x04>;
233
+
reg-names = "data", "dir";
234
+
gpio-controller;
235
+
#gpio-cells = <2>;
236
+
pinctrl-names = "default";
237
+
pinctrl-0 = <&gpio4_default_pins>;
238
+
};
239
+
240
+
gpio5: gpio@80840030 {
241
+
compatible = "cirrus,ep9301-gpio";
242
+
reg = <0x80840030 0x04>,
243
+
<0x80840034 0x04>,
244
+
<0x8084004c 0x1c>;
245
+
reg-names = "data", "dir", "intr";
246
+
gpio-controller;
247
+
#gpio-cells = <2>;
248
+
interrupt-controller;
249
+
#interrupt-cells = <2>;
250
+
interrupts-extended = <&vic0 19>, <&vic0 20>,
251
+
<&vic0 21>, <&vic0 22>,
252
+
<&vic1 15>, <&vic1 16>,
253
+
<&vic1 17>, <&vic1 18>;
254
+
};
255
+
256
+
gpio6: gpio@80840038 {
257
+
compatible = "cirrus,ep9301-gpio";
258
+
reg = <0x80840038 0x04>,
259
+
<0x8084003c 0x04>;
260
+
reg-names = "data", "dir";
261
+
gpio-controller;
262
+
#gpio-cells = <2>;
263
+
pinctrl-names = "default";
264
+
pinctrl-0 = <&gpio6_default_pins>;
265
+
};
266
+
267
+
gpio7: gpio@80840040 {
268
+
compatible = "cirrus,ep9301-gpio";
269
+
reg = <0x80840040 0x04>,
270
+
<0x80840044 0x04>;
271
+
reg-names = "data", "dir";
272
+
gpio-controller;
273
+
#gpio-cells = <2>;
274
+
pinctrl-names = "default";
275
+
pinctrl-0 = <&gpio7_default_pins>;
276
+
};
277
+
278
+
i2s: i2s@80820000 {
279
+
compatible = "cirrus,ep9301-i2s";
280
+
reg = <0x80820000 0x100>;
281
+
#sound-dai-cells = <0>;
282
+
interrupt-parent = <&vic1>;
283
+
interrupts = <28>;
284
+
clocks = <&syscon EP93XX_CLK_I2S_MCLK>,
285
+
<&syscon EP93XX_CLK_I2S_SCLK>,
286
+
<&syscon EP93XX_CLK_I2S_LRCLK>;
287
+
clock-names = "mclk", "sclk", "lrclk";
288
+
dmas = <&dma0 0 1>, <&dma0 0 2>;
289
+
dma-names = "tx", "rx";
290
+
status = "disabled";
291
+
};
292
+
293
+
ide: ide@800a0000 {
294
+
compatible = "cirrus,ep9312-pata";
295
+
reg = <0x800a0000 0x38>;
296
+
interrupt-parent = <&vic1>;
297
+
interrupts = <8>;
298
+
pinctrl-names = "default";
299
+
pinctrl-0 = <&ide_default_pins>;
300
+
status = "disabled";
301
+
};
302
+
303
+
vic0: interrupt-controller@800b0000 {
304
+
compatible = "arm,pl192-vic";
305
+
reg = <0x800b0000 0x1000>;
306
+
interrupt-controller;
307
+
#interrupt-cells = <1>;
308
+
valid-mask = <0x7ffffffc>;
309
+
valid-wakeup-mask = <0x0>;
310
+
};
311
+
312
+
vic1: interrupt-controller@800c0000 {
313
+
compatible = "arm,pl192-vic";
314
+
reg = <0x800c0000 0x1000>;
315
+
interrupt-controller;
316
+
#interrupt-cells = <1>;
317
+
valid-mask = <0x1fffffff>;
318
+
valid-wakeup-mask = <0x0>;
319
+
};
320
+
321
+
keypad: keypad@800f0000 {
322
+
compatible = "cirrus,ep9307-keypad";
323
+
reg = <0x800f0000 0x0c>;
324
+
interrupt-parent = <&vic0>;
325
+
interrupts = <29>;
326
+
clocks = <&syscon EP93XX_CLK_KEYPAD>;
327
+
pinctrl-names = "default";
328
+
pinctrl-0 = <&keypad_default_pins>;
329
+
linux,keymap = <KEY_UP>,
330
+
<KEY_DOWN>,
331
+
<KEY_VOLUMEDOWN>,
332
+
<KEY_HOME>,
333
+
<KEY_RIGHT>,
334
+
<KEY_LEFT>,
335
+
<KEY_ENTER>,
336
+
<KEY_VOLUMEUP>,
337
+
<KEY_F6>,
338
+
<KEY_F8>,
339
+
<KEY_F9>,
340
+
<KEY_F10>,
341
+
<KEY_F1>,
342
+
<KEY_F2>,
343
+
<KEY_F3>,
344
+
<KEY_POWER>;
345
+
};
346
+
347
+
pwm0: pwm@80910000 {
348
+
compatible = "cirrus,ep9301-pwm";
349
+
reg = <0x80910000 0x10>;
350
+
clocks = <&syscon EP93XX_CLK_PWM>;
351
+
#pwm-cells = <3>;
352
+
status = "disabled";
353
+
};
354
+
355
+
pwm1: pwm@80910020 {
356
+
compatible = "cirrus,ep9301-pwm";
357
+
reg = <0x80910020 0x10>;
358
+
clocks = <&syscon EP93XX_CLK_PWM>;
359
+
#pwm-cells = <3>;
360
+
pinctrl-names = "default";
361
+
pinctrl-0 = <&pwm1_default_pins>;
362
+
status = "disabled";
363
+
};
364
+
365
+
rtc0: rtc@80920000 {
366
+
compatible = "cirrus,ep9301-rtc";
367
+
reg = <0x80920000 0x100>;
368
+
};
369
+
370
+
spi0: spi@808a0000 {
371
+
compatible = "cirrus,ep9301-spi";
372
+
reg = <0x808a0000 0x18>;
373
+
#address-cells = <1>;
374
+
#size-cells = <0>;
375
+
interrupt-parent = <&vic1>;
376
+
interrupts = <21>;
377
+
clocks = <&syscon EP93XX_CLK_SPI>;
378
+
pinctrl-names = "default";
379
+
pinctrl-0 = <&spi_default_pins>;
380
+
status = "disabled";
381
+
};
382
+
383
+
timer: timer@80810000 {
384
+
compatible = "cirrus,ep9301-timer";
385
+
reg = <0x80810000 0x100>;
386
+
interrupt-parent = <&vic1>;
387
+
interrupts = <19>;
388
+
};
389
+
390
+
uart0: serial@808c0000 {
391
+
compatible = "arm,pl011", "arm,primecell";
392
+
reg = <0x808c0000 0x1000>;
393
+
arm,primecell-periphid = <0x00041010>;
394
+
clocks = <&syscon EP93XX_CLK_UART1>, <&syscon EP93XX_CLK_UART>;
395
+
clock-names = "uartclk", "apb_pclk";
396
+
interrupt-parent = <&vic1>;
397
+
interrupts = <20>;
398
+
status = "disabled";
399
+
};
400
+
401
+
uart1: uart@808d0000 {
402
+
compatible = "arm,primecell";
403
+
reg = <0x808d0000 0x1000>;
404
+
arm,primecell-periphid = <0x00041010>;
405
+
clocks = <&syscon EP93XX_CLK_UART2>, <&syscon EP93XX_CLK_UART>;
406
+
clock-names = "apb:uart2", "apb_pclk";
407
+
interrupt-parent = <&vic1>;
408
+
interrupts = <22>;
409
+
status = "disabled";
410
+
};
411
+
412
+
uart2: uart@808b0000 {
413
+
compatible = "arm,primecell";
414
+
reg = <0x808b0000 0x1000>;
415
+
arm,primecell-periphid = <0x00041010>;
416
+
clocks = <&syscon EP93XX_CLK_UART3>, <&syscon EP93XX_CLK_UART>;
417
+
clock-names = "apb:uart3", "apb_pclk";
418
+
interrupt-parent = <&vic1>;
419
+
interrupts = <23>;
420
+
status = "disabled";
421
+
};
422
+
423
+
usb0: usb@80020000 {
424
+
compatible = "generic-ohci";
425
+
reg = <0x80020000 0x10000>;
426
+
interrupt-parent = <&vic1>;
427
+
interrupts = <24>;
428
+
clocks = <&syscon EP93XX_CLK_USB>;
429
+
status = "disabled";
430
+
};
431
+
432
+
watchdog0: watchdog@80940000 {
433
+
compatible = "cirrus,ep9301-wdt";
434
+
reg = <0x80940000 0x08>;
435
+
};
436
+
};
437
+
438
+
xtali: oscillator {
439
+
compatible = "fixed-clock";
440
+
#clock-cells = <0>;
441
+
clock-frequency = <14745600>;
442
+
clock-output-names = "xtali";
443
+
};
444
+
};
+10
-10
arch/arm/mach-ep93xx/Kconfig
+10
-10
arch/arm/mach-ep93xx/Kconfig
···
3
3
bool "EP93xx-based"
4
4
depends on ATAGS
5
5
depends on ARCH_MULTI_V4T
6
+
# CONFIG_ARCH_MULTI_V7 is not set
6
7
depends on CPU_LITTLE_ENDIAN
8
+
select ARCH_HAS_RESET_CONTROLLER
7
9
select ARCH_SPARSEMEM_ENABLE
8
10
select ARM_AMBA
9
11
select ARM_VIC
12
+
select ARM_APPENDED_DTB # Old Redboot bootloaders deployed
13
+
select ARM_ATAG_DTB_COMPAT # we need this to update dt memory node
14
+
select COMMON_CLK_EP93XX
15
+
select EP93XX_TIMER
10
16
select CLKSRC_MMIO
11
17
select CPU_ARM920T
12
18
select GPIOLIB
19
+
select PINCTRL
20
+
select PINCTRL_EP93XX
13
21
help
14
22
This enables support for the Cirrus EP93xx series of CPUs.
15
23
16
24
if ARCH_EP93XX
17
25
18
-
menu "Cirrus EP93xx Implementation Options"
19
-
20
-
config EP93XX_SOC_COMMON
21
-
bool
22
-
default y
23
-
select SOC_BUS
24
-
select LEDS_GPIO_REGISTER
25
-
26
-
comment "EP93xx Platforms"
26
+
# menu "EP93xx Platforms"
27
27
28
28
config MACH_BK3
29
29
bool "Support Liebherr BK3.1"
···
103
103
Say 'Y' here if you want your kernel to support the
104
104
Vision Engraving Systems EP9307 SoM.
105
105
106
-
endmenu
106
+
# endmenu
107
107
108
108
endif
-11
arch/arm/mach-ep93xx/Makefile
-11
arch/arm/mach-ep93xx/Makefile
···
1
-
# SPDX-License-Identifier: GPL-2.0
2
-
#
3
-
# Makefile for the linux kernel.
4
-
#
5
-
obj-y := core.o clock.o timer-ep93xx.o
6
-
7
-
obj-$(CONFIG_EP93XX_DMA) += dma.o
8
-
9
-
obj-$(CONFIG_MACH_EDB93XX) += edb93xx.o
10
-
obj-$(CONFIG_MACH_TS72XX) += ts72xx.o
11
-
obj-$(CONFIG_MACH_VISION_EP9307)+= vision_ep9307.o
-733
arch/arm/mach-ep93xx/clock.c
-733
arch/arm/mach-ep93xx/clock.c
···
1
-
// SPDX-License-Identifier: GPL-2.0-or-later
2
-
/*
3
-
* arch/arm/mach-ep93xx/clock.c
4
-
* Clock control for Cirrus EP93xx chips.
5
-
*
6
-
* Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
7
-
*/
8
-
9
-
#define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt
10
-
11
-
#include <linux/kernel.h>
12
-
#include <linux/clk.h>
13
-
#include <linux/err.h>
14
-
#include <linux/module.h>
15
-
#include <linux/string.h>
16
-
#include <linux/io.h>
17
-
#include <linux/spinlock.h>
18
-
#include <linux/clkdev.h>
19
-
#include <linux/clk-provider.h>
20
-
#include <linux/soc/cirrus/ep93xx.h>
21
-
22
-
#include "hardware.h"
23
-
24
-
#include <asm/div64.h>
25
-
26
-
#include "soc.h"
27
-
28
-
static DEFINE_SPINLOCK(clk_lock);
29
-
30
-
static char fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };
31
-
static char hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 };
32
-
static char pclk_divisors[] = { 1, 2, 4, 8 };
33
-
34
-
static char adc_divisors[] = { 16, 4 };
35
-
static char sclk_divisors[] = { 2, 4 };
36
-
static char lrclk_divisors[] = { 32, 64, 128 };
37
-
38
-
static const char * const mux_parents[] = {
39
-
"xtali",
40
-
"pll1",
41
-
"pll2"
42
-
};
43
-
44
-
/*
45
-
* PLL rate = 14.7456 MHz * (X1FBD + 1) * (X2FBD + 1) / (X2IPD + 1) / 2^PS
46
-
*/
47
-
static unsigned long calc_pll_rate(unsigned long long rate, u32 config_word)
48
-
{
49
-
int i;
50
-
51
-
rate *= ((config_word >> 11) & 0x1f) + 1; /* X1FBD */
52
-
rate *= ((config_word >> 5) & 0x3f) + 1; /* X2FBD */
53
-
do_div(rate, (config_word & 0x1f) + 1); /* X2IPD */
54
-
for (i = 0; i < ((config_word >> 16) & 3); i++) /* PS */
55
-
rate >>= 1;
56
-
57
-
return (unsigned long)rate;
58
-
}
59
-
60
-
struct clk_psc {
61
-
struct clk_hw hw;
62
-
void __iomem *reg;
63
-
u8 bit_idx;
64
-
u32 mask;
65
-
u8 shift;
66
-
u8 width;
67
-
char *div;
68
-
u8 num_div;
69
-
spinlock_t *lock;
70
-
};
71
-
72
-
#define to_clk_psc(_hw) container_of(_hw, struct clk_psc, hw)
73
-
74
-
static int ep93xx_clk_is_enabled(struct clk_hw *hw)
75
-
{
76
-
struct clk_psc *psc = to_clk_psc(hw);
77
-
u32 val = readl(psc->reg);
78
-
79
-
return (val & BIT(psc->bit_idx)) ? 1 : 0;
80
-
}
81
-
82
-
static int ep93xx_clk_enable(struct clk_hw *hw)
83
-
{
84
-
struct clk_psc *psc = to_clk_psc(hw);
85
-
unsigned long flags = 0;
86
-
u32 val;
87
-
88
-
if (psc->lock)
89
-
spin_lock_irqsave(psc->lock, flags);
90
-
91
-
val = __raw_readl(psc->reg);
92
-
val |= BIT(psc->bit_idx);
93
-
94
-
ep93xx_syscon_swlocked_write(val, psc->reg);
95
-
96
-
if (psc->lock)
97
-
spin_unlock_irqrestore(psc->lock, flags);
98
-
99
-
return 0;
100
-
}
101
-
102
-
static void ep93xx_clk_disable(struct clk_hw *hw)
103
-
{
104
-
struct clk_psc *psc = to_clk_psc(hw);
105
-
unsigned long flags = 0;
106
-
u32 val;
107
-
108
-
if (psc->lock)
109
-
spin_lock_irqsave(psc->lock, flags);
110
-
111
-
val = __raw_readl(psc->reg);
112
-
val &= ~BIT(psc->bit_idx);
113
-
114
-
ep93xx_syscon_swlocked_write(val, psc->reg);
115
-
116
-
if (psc->lock)
117
-
spin_unlock_irqrestore(psc->lock, flags);
118
-
}
119
-
120
-
static const struct clk_ops clk_ep93xx_gate_ops = {
121
-
.enable = ep93xx_clk_enable,
122
-
.disable = ep93xx_clk_disable,
123
-
.is_enabled = ep93xx_clk_is_enabled,
124
-
};
125
-
126
-
static struct clk_hw *ep93xx_clk_register_gate(const char *name,
127
-
const char *parent_name,
128
-
void __iomem *reg,
129
-
u8 bit_idx)
130
-
{
131
-
struct clk_init_data init;
132
-
struct clk_psc *psc;
133
-
struct clk *clk;
134
-
135
-
psc = kzalloc(sizeof(*psc), GFP_KERNEL);
136
-
if (!psc)
137
-
return ERR_PTR(-ENOMEM);
138
-
139
-
init.name = name;
140
-
init.ops = &clk_ep93xx_gate_ops;
141
-
init.flags = CLK_SET_RATE_PARENT;
142
-
init.parent_names = (parent_name ? &parent_name : NULL);
143
-
init.num_parents = (parent_name ? 1 : 0);
144
-
145
-
psc->reg = reg;
146
-
psc->bit_idx = bit_idx;
147
-
psc->hw.init = &init;
148
-
psc->lock = &clk_lock;
149
-
150
-
clk = clk_register(NULL, &psc->hw);
151
-
if (IS_ERR(clk)) {
152
-
kfree(psc);
153
-
return ERR_CAST(clk);
154
-
}
155
-
156
-
return &psc->hw;
157
-
}
158
-
159
-
static u8 ep93xx_mux_get_parent(struct clk_hw *hw)
160
-
{
161
-
struct clk_psc *psc = to_clk_psc(hw);
162
-
u32 val = __raw_readl(psc->reg);
163
-
164
-
if (!(val & EP93XX_SYSCON_CLKDIV_ESEL))
165
-
return 0;
166
-
167
-
if (!(val & EP93XX_SYSCON_CLKDIV_PSEL))
168
-
return 1;
169
-
170
-
return 2;
171
-
}
172
-
173
-
static int ep93xx_mux_set_parent_lock(struct clk_hw *hw, u8 index)
174
-
{
175
-
struct clk_psc *psc = to_clk_psc(hw);
176
-
unsigned long flags = 0;
177
-
u32 val;
178
-
179
-
if (index >= ARRAY_SIZE(mux_parents))
180
-
return -EINVAL;
181
-
182
-
if (psc->lock)
183
-
spin_lock_irqsave(psc->lock, flags);
184
-
185
-
val = __raw_readl(psc->reg);
186
-
val &= ~(EP93XX_SYSCON_CLKDIV_ESEL | EP93XX_SYSCON_CLKDIV_PSEL);
187
-
188
-
189
-
if (index != 0) {
190
-
val |= EP93XX_SYSCON_CLKDIV_ESEL;
191
-
val |= (index - 1) ? EP93XX_SYSCON_CLKDIV_PSEL : 0;
192
-
}
193
-
194
-
ep93xx_syscon_swlocked_write(val, psc->reg);
195
-
196
-
if (psc->lock)
197
-
spin_unlock_irqrestore(psc->lock, flags);
198
-
199
-
return 0;
200
-
}
201
-
202
-
static bool is_best(unsigned long rate, unsigned long now,
203
-
unsigned long best)
204
-
{
205
-
return abs(rate - now) < abs(rate - best);
206
-
}
207
-
208
-
static int ep93xx_mux_determine_rate(struct clk_hw *hw,
209
-
struct clk_rate_request *req)
210
-
{
211
-
unsigned long rate = req->rate;
212
-
struct clk *best_parent = NULL;
213
-
unsigned long __parent_rate;
214
-
unsigned long best_rate = 0, actual_rate, mclk_rate;
215
-
unsigned long best_parent_rate;
216
-
int __div = 0, __pdiv = 0;
217
-
int i;
218
-
219
-
/*
220
-
* Try the two pll's and the external clock
221
-
* Because the valid predividers are 2, 2.5 and 3, we multiply
222
-
* all the clocks by 2 to avoid floating point math.
223
-
*
224
-
* This is based on the algorithm in the ep93xx raster guide:
225
-
* http://be-a-maverick.com/en/pubs/appNote/AN269REV1.pdf
226
-
*
227
-
*/
228
-
for (i = 0; i < ARRAY_SIZE(mux_parents); i++) {
229
-
struct clk *parent = clk_get_sys(mux_parents[i], NULL);
230
-
231
-
__parent_rate = clk_get_rate(parent);
232
-
mclk_rate = __parent_rate * 2;
233
-
234
-
/* Try each predivider value */
235
-
for (__pdiv = 4; __pdiv <= 6; __pdiv++) {
236
-
__div = mclk_rate / (rate * __pdiv);
237
-
if (__div < 2 || __div > 127)
238
-
continue;
239
-
240
-
actual_rate = mclk_rate / (__pdiv * __div);
241
-
if (is_best(rate, actual_rate, best_rate)) {
242
-
best_rate = actual_rate;
243
-
best_parent_rate = __parent_rate;
244
-
best_parent = parent;
245
-
}
246
-
}
247
-
}
248
-
249
-
if (!best_parent)
250
-
return -EINVAL;
251
-
252
-
req->best_parent_rate = best_parent_rate;
253
-
req->best_parent_hw = __clk_get_hw(best_parent);
254
-
req->rate = best_rate;
255
-
256
-
return 0;
257
-
}
258
-
259
-
static unsigned long ep93xx_ddiv_recalc_rate(struct clk_hw *hw,
260
-
unsigned long parent_rate)
261
-
{
262
-
struct clk_psc *psc = to_clk_psc(hw);
263
-
unsigned long rate = 0;
264
-
u32 val = __raw_readl(psc->reg);
265
-
int __pdiv = ((val >> EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) & 0x03);
266
-
int __div = val & 0x7f;
267
-
268
-
if (__div > 0)
269
-
rate = (parent_rate * 2) / ((__pdiv + 3) * __div);
270
-
271
-
return rate;
272
-
}
273
-
274
-
static int ep93xx_ddiv_set_rate(struct clk_hw *hw, unsigned long rate,
275
-
unsigned long parent_rate)
276
-
{
277
-
struct clk_psc *psc = to_clk_psc(hw);
278
-
int pdiv = 0, div = 0;
279
-
unsigned long best_rate = 0, actual_rate, mclk_rate;
280
-
int __div = 0, __pdiv = 0;
281
-
u32 val;
282
-
283
-
mclk_rate = parent_rate * 2;
284
-
285
-
for (__pdiv = 4; __pdiv <= 6; __pdiv++) {
286
-
__div = mclk_rate / (rate * __pdiv);
287
-
if (__div < 2 || __div > 127)
288
-
continue;
289
-
290
-
actual_rate = mclk_rate / (__pdiv * __div);
291
-
if (is_best(rate, actual_rate, best_rate)) {
292
-
pdiv = __pdiv - 3;
293
-
div = __div;
294
-
best_rate = actual_rate;
295
-
}
296
-
}
297
-
298
-
if (!best_rate)
299
-
return -EINVAL;
300
-
301
-
val = __raw_readl(psc->reg);
302
-
303
-
/* Clear old dividers */
304
-
val &= ~0x37f;
305
-
306
-
/* Set the new pdiv and div bits for the new clock rate */
307
-
val |= (pdiv << EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) | div;
308
-
ep93xx_syscon_swlocked_write(val, psc->reg);
309
-
310
-
return 0;
311
-
}
312
-
313
-
static const struct clk_ops clk_ddiv_ops = {
314
-
.enable = ep93xx_clk_enable,
315
-
.disable = ep93xx_clk_disable,
316
-
.is_enabled = ep93xx_clk_is_enabled,
317
-
.get_parent = ep93xx_mux_get_parent,
318
-
.set_parent = ep93xx_mux_set_parent_lock,
319
-
.determine_rate = ep93xx_mux_determine_rate,
320
-
.recalc_rate = ep93xx_ddiv_recalc_rate,
321
-
.set_rate = ep93xx_ddiv_set_rate,
322
-
};
323
-
324
-
static struct clk_hw *clk_hw_register_ddiv(const char *name,
325
-
void __iomem *reg,
326
-
u8 bit_idx)
327
-
{
328
-
struct clk_init_data init;
329
-
struct clk_psc *psc;
330
-
struct clk *clk;
331
-
332
-
psc = kzalloc(sizeof(*psc), GFP_KERNEL);
333
-
if (!psc)
334
-
return ERR_PTR(-ENOMEM);
335
-
336
-
init.name = name;
337
-
init.ops = &clk_ddiv_ops;
338
-
init.flags = 0;
339
-
init.parent_names = mux_parents;
340
-
init.num_parents = ARRAY_SIZE(mux_parents);
341
-
342
-
psc->reg = reg;
343
-
psc->bit_idx = bit_idx;
344
-
psc->lock = &clk_lock;
345
-
psc->hw.init = &init;
346
-
347
-
clk = clk_register(NULL, &psc->hw);
348
-
if (IS_ERR(clk)) {
349
-
kfree(psc);
350
-
return ERR_CAST(clk);
351
-
}
352
-
return &psc->hw;
353
-
}
354
-
355
-
static unsigned long ep93xx_div_recalc_rate(struct clk_hw *hw,
356
-
unsigned long parent_rate)
357
-
{
358
-
struct clk_psc *psc = to_clk_psc(hw);
359
-
u32 val = __raw_readl(psc->reg);
360
-
u8 index = (val & psc->mask) >> psc->shift;
361
-
362
-
if (index > psc->num_div)
363
-
return 0;
364
-
365
-
return DIV_ROUND_UP_ULL(parent_rate, psc->div[index]);
366
-
}
367
-
368
-
static long ep93xx_div_round_rate(struct clk_hw *hw, unsigned long rate,
369
-
unsigned long *parent_rate)
370
-
{
371
-
struct clk_psc *psc = to_clk_psc(hw);
372
-
unsigned long best = 0, now, maxdiv;
373
-
int i;
374
-
375
-
maxdiv = psc->div[psc->num_div - 1];
376
-
377
-
for (i = 0; i < psc->num_div; i++) {
378
-
if ((rate * psc->div[i]) == *parent_rate)
379
-
return DIV_ROUND_UP_ULL((u64)*parent_rate, psc->div[i]);
380
-
381
-
now = DIV_ROUND_UP_ULL((u64)*parent_rate, psc->div[i]);
382
-
383
-
if (is_best(rate, now, best))
384
-
best = now;
385
-
}
386
-
387
-
if (!best)
388
-
best = DIV_ROUND_UP_ULL(*parent_rate, maxdiv);
389
-
390
-
return best;
391
-
}
392
-
393
-
static int ep93xx_div_set_rate(struct clk_hw *hw, unsigned long rate,
394
-
unsigned long parent_rate)
395
-
{
396
-
struct clk_psc *psc = to_clk_psc(hw);
397
-
u32 val = __raw_readl(psc->reg) & ~psc->mask;
398
-
int i;
399
-
400
-
for (i = 0; i < psc->num_div; i++)
401
-
if (rate == parent_rate / psc->div[i]) {
402
-
val |= i << psc->shift;
403
-
break;
404
-
}
405
-
406
-
if (i == psc->num_div)
407
-
return -EINVAL;
408
-
409
-
ep93xx_syscon_swlocked_write(val, psc->reg);
410
-
411
-
return 0;
412
-
}
413
-
414
-
static const struct clk_ops ep93xx_div_ops = {
415
-
.enable = ep93xx_clk_enable,
416
-
.disable = ep93xx_clk_disable,
417
-
.is_enabled = ep93xx_clk_is_enabled,
418
-
.recalc_rate = ep93xx_div_recalc_rate,
419
-
.round_rate = ep93xx_div_round_rate,
420
-
.set_rate = ep93xx_div_set_rate,
421
-
};
422
-
423
-
static struct clk_hw *clk_hw_register_div(const char *name,
424
-
const char *parent_name,
425
-
void __iomem *reg,
426
-
u8 enable_bit,
427
-
u8 shift,
428
-
u8 width,
429
-
char *clk_divisors,
430
-
u8 num_div)
431
-
{
432
-
struct clk_init_data init;
433
-
struct clk_psc *psc;
434
-
struct clk *clk;
435
-
436
-
psc = kzalloc(sizeof(*psc), GFP_KERNEL);
437
-
if (!psc)
438
-
return ERR_PTR(-ENOMEM);
439
-
440
-
init.name = name;
441
-
init.ops = &ep93xx_div_ops;
442
-
init.flags = 0;
443
-
init.parent_names = (parent_name ? &parent_name : NULL);
444
-
init.num_parents = 1;
445
-
446
-
psc->reg = reg;
447
-
psc->bit_idx = enable_bit;
448
-
psc->mask = GENMASK(shift + width - 1, shift);
449
-
psc->shift = shift;
450
-
psc->div = clk_divisors;
451
-
psc->num_div = num_div;
452
-
psc->lock = &clk_lock;
453
-
psc->hw.init = &init;
454
-
455
-
clk = clk_register(NULL, &psc->hw);
456
-
if (IS_ERR(clk)) {
457
-
kfree(psc);
458
-
return ERR_CAST(clk);
459
-
}
460
-
return &psc->hw;
461
-
}
462
-
463
-
struct ep93xx_gate {
464
-
unsigned int bit;
465
-
const char *dev_id;
466
-
const char *con_id;
467
-
};
468
-
469
-
static struct ep93xx_gate ep93xx_uarts[] = {
470
-
{EP93XX_SYSCON_DEVCFG_U1EN, "apb:uart1", NULL},
471
-
{EP93XX_SYSCON_DEVCFG_U2EN, "apb:uart2", NULL},
472
-
{EP93XX_SYSCON_DEVCFG_U3EN, "apb:uart3", NULL},
473
-
};
474
-
475
-
static void __init ep93xx_uart_clock_init(void)
476
-
{
477
-
unsigned int i;
478
-
struct clk_hw *hw;
479
-
u32 value;
480
-
unsigned int clk_uart_div;
481
-
482
-
value = __raw_readl(EP93XX_SYSCON_PWRCNT);
483
-
if (value & EP93XX_SYSCON_PWRCNT_UARTBAUD)
484
-
clk_uart_div = 1;
485
-
else
486
-
clk_uart_div = 2;
487
-
488
-
hw = clk_hw_register_fixed_factor(NULL, "uart", "xtali", 0, 1, clk_uart_div);
489
-
490
-
/* parenting uart gate clocks to uart clock */
491
-
for (i = 0; i < ARRAY_SIZE(ep93xx_uarts); i++) {
492
-
hw = ep93xx_clk_register_gate(ep93xx_uarts[i].dev_id,
493
-
"uart",
494
-
EP93XX_SYSCON_DEVCFG,
495
-
ep93xx_uarts[i].bit);
496
-
497
-
clk_hw_register_clkdev(hw, NULL, ep93xx_uarts[i].dev_id);
498
-
}
499
-
}
500
-
501
-
static struct ep93xx_gate ep93xx_dmas[] = {
502
-
{EP93XX_SYSCON_PWRCNT_DMA_M2P0, NULL, "m2p0"},
503
-
{EP93XX_SYSCON_PWRCNT_DMA_M2P1, NULL, "m2p1"},
504
-
{EP93XX_SYSCON_PWRCNT_DMA_M2P2, NULL, "m2p2"},
505
-
{EP93XX_SYSCON_PWRCNT_DMA_M2P3, NULL, "m2p3"},
506
-
{EP93XX_SYSCON_PWRCNT_DMA_M2P4, NULL, "m2p4"},
507
-
{EP93XX_SYSCON_PWRCNT_DMA_M2P5, NULL, "m2p5"},
508
-
{EP93XX_SYSCON_PWRCNT_DMA_M2P6, NULL, "m2p6"},
509
-
{EP93XX_SYSCON_PWRCNT_DMA_M2P7, NULL, "m2p7"},
510
-
{EP93XX_SYSCON_PWRCNT_DMA_M2P8, NULL, "m2p8"},
511
-
{EP93XX_SYSCON_PWRCNT_DMA_M2P9, NULL, "m2p9"},
512
-
{EP93XX_SYSCON_PWRCNT_DMA_M2M0, NULL, "m2m0"},
513
-
{EP93XX_SYSCON_PWRCNT_DMA_M2M1, NULL, "m2m1"},
514
-
};
515
-
516
-
static void __init ep93xx_dma_clock_init(void)
517
-
{
518
-
unsigned int i;
519
-
struct clk_hw *hw;
520
-
int ret;
521
-
522
-
for (i = 0; i < ARRAY_SIZE(ep93xx_dmas); i++) {
523
-
hw = clk_hw_register_gate(NULL, ep93xx_dmas[i].con_id,
524
-
"hclk", 0,
525
-
EP93XX_SYSCON_PWRCNT,
526
-
ep93xx_dmas[i].bit,
527
-
0,
528
-
&clk_lock);
529
-
530
-
ret = clk_hw_register_clkdev(hw, ep93xx_dmas[i].con_id, NULL);
531
-
if (ret)
532
-
pr_err("%s: failed to register lookup %s\n",
533
-
__func__, ep93xx_dmas[i].con_id);
534
-
}
535
-
}
536
-
537
-
static int __init ep93xx_clock_init(void)
538
-
{
539
-
u32 value;
540
-
struct clk_hw *hw;
541
-
unsigned long clk_pll1_rate;
542
-
unsigned long clk_f_rate;
543
-
unsigned long clk_h_rate;
544
-
unsigned long clk_p_rate;
545
-
unsigned long clk_pll2_rate;
546
-
unsigned int clk_f_div;
547
-
unsigned int clk_h_div;
548
-
unsigned int clk_p_div;
549
-
unsigned int clk_usb_div;
550
-
unsigned long clk_spi_div;
551
-
552
-
hw = clk_hw_register_fixed_rate(NULL, "xtali", NULL, 0, EP93XX_EXT_CLK_RATE);
553
-
clk_hw_register_clkdev(hw, NULL, "xtali");
554
-
555
-
/* Determine the bootloader configured pll1 rate */
556
-
value = __raw_readl(EP93XX_SYSCON_CLKSET1);
557
-
if (!(value & EP93XX_SYSCON_CLKSET1_NBYP1))
558
-
clk_pll1_rate = EP93XX_EXT_CLK_RATE;
559
-
else
560
-
clk_pll1_rate = calc_pll_rate(EP93XX_EXT_CLK_RATE, value);
561
-
562
-
hw = clk_hw_register_fixed_rate(NULL, "pll1", "xtali", 0, clk_pll1_rate);
563
-
clk_hw_register_clkdev(hw, NULL, "pll1");
564
-
565
-
/* Initialize the pll1 derived clocks */
566
-
clk_f_div = fclk_divisors[(value >> 25) & 0x7];
567
-
clk_h_div = hclk_divisors[(value >> 20) & 0x7];
568
-
clk_p_div = pclk_divisors[(value >> 18) & 0x3];
569
-
570
-
hw = clk_hw_register_fixed_factor(NULL, "fclk", "pll1", 0, 1, clk_f_div);
571
-
clk_f_rate = clk_get_rate(hw->clk);
572
-
hw = clk_hw_register_fixed_factor(NULL, "hclk", "pll1", 0, 1, clk_h_div);
573
-
clk_h_rate = clk_get_rate(hw->clk);
574
-
hw = clk_hw_register_fixed_factor(NULL, "pclk", "hclk", 0, 1, clk_p_div);
575
-
clk_p_rate = clk_get_rate(hw->clk);
576
-
577
-
clk_hw_register_clkdev(hw, "apb_pclk", NULL);
578
-
579
-
ep93xx_dma_clock_init();
580
-
581
-
/* Determine the bootloader configured pll2 rate */
582
-
value = __raw_readl(EP93XX_SYSCON_CLKSET2);
583
-
if (!(value & EP93XX_SYSCON_CLKSET2_NBYP2))
584
-
clk_pll2_rate = EP93XX_EXT_CLK_RATE;
585
-
else if (value & EP93XX_SYSCON_CLKSET2_PLL2_EN)
586
-
clk_pll2_rate = calc_pll_rate(EP93XX_EXT_CLK_RATE, value);
587
-
else
588
-
clk_pll2_rate = 0;
589
-
590
-
hw = clk_hw_register_fixed_rate(NULL, "pll2", "xtali", 0, clk_pll2_rate);
591
-
clk_hw_register_clkdev(hw, NULL, "pll2");
592
-
593
-
/* Initialize the pll2 derived clocks */
594
-
/*
595
-
* These four bits set the divide ratio between the PLL2
596
-
* output and the USB clock.
597
-
* 0000 - Divide by 1
598
-
* 0001 - Divide by 2
599
-
* 0010 - Divide by 3
600
-
* 0011 - Divide by 4
601
-
* 0100 - Divide by 5
602
-
* 0101 - Divide by 6
603
-
* 0110 - Divide by 7
604
-
* 0111 - Divide by 8
605
-
* 1000 - Divide by 9
606
-
* 1001 - Divide by 10
607
-
* 1010 - Divide by 11
608
-
* 1011 - Divide by 12
609
-
* 1100 - Divide by 13
610
-
* 1101 - Divide by 14
611
-
* 1110 - Divide by 15
612
-
* 1111 - Divide by 1
613
-
* On power-on-reset these bits are reset to 0000b.
614
-
*/
615
-
clk_usb_div = (((value >> 28) & 0xf) + 1);
616
-
hw = clk_hw_register_fixed_factor(NULL, "usb_clk", "pll2", 0, 1, clk_usb_div);
617
-
hw = clk_hw_register_gate(NULL, "ohci-platform",
618
-
"usb_clk", 0,
619
-
EP93XX_SYSCON_PWRCNT,
620
-
EP93XX_SYSCON_PWRCNT_USH_EN,
621
-
0,
622
-
&clk_lock);
623
-
clk_hw_register_clkdev(hw, NULL, "ohci-platform");
624
-
625
-
/*
626
-
* EP93xx SSP clock rate was doubled in version E2. For more information
627
-
* see:
628
-
* http://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf
629
-
*/
630
-
clk_spi_div = 1;
631
-
if (ep93xx_chip_revision() < EP93XX_CHIP_REV_E2)
632
-
clk_spi_div = 2;
633
-
hw = clk_hw_register_fixed_factor(NULL, "ep93xx-spi.0", "xtali", 0, 1, clk_spi_div);
634
-
clk_hw_register_clkdev(hw, NULL, "ep93xx-spi.0");
635
-
636
-
/* pwm clock */
637
-
hw = clk_hw_register_fixed_factor(NULL, "pwm_clk", "xtali", 0, 1, 1);
638
-
clk_hw_register_clkdev(hw, "pwm_clk", NULL);
639
-
640
-
pr_info("PLL1 running at %ld MHz, PLL2 at %ld MHz\n",
641
-
clk_pll1_rate / 1000000, clk_pll2_rate / 1000000);
642
-
pr_info("FCLK %ld MHz, HCLK %ld MHz, PCLK %ld MHz\n",
643
-
clk_f_rate / 1000000, clk_h_rate / 1000000,
644
-
clk_p_rate / 1000000);
645
-
646
-
ep93xx_uart_clock_init();
647
-
648
-
/* touchscreen/adc clock */
649
-
hw = clk_hw_register_div("ep93xx-adc",
650
-
"xtali",
651
-
EP93XX_SYSCON_KEYTCHCLKDIV,
652
-
EP93XX_SYSCON_KEYTCHCLKDIV_TSEN,
653
-
EP93XX_SYSCON_KEYTCHCLKDIV_ADIV,
654
-
1,
655
-
adc_divisors,
656
-
ARRAY_SIZE(adc_divisors));
657
-
658
-
clk_hw_register_clkdev(hw, NULL, "ep93xx-adc");
659
-
660
-
/* keypad clock */
661
-
hw = clk_hw_register_div("ep93xx-keypad",
662
-
"xtali",
663
-
EP93XX_SYSCON_KEYTCHCLKDIV,
664
-
EP93XX_SYSCON_KEYTCHCLKDIV_KEN,
665
-
EP93XX_SYSCON_KEYTCHCLKDIV_KDIV,
666
-
1,
667
-
adc_divisors,
668
-
ARRAY_SIZE(adc_divisors));
669
-
670
-
clk_hw_register_clkdev(hw, NULL, "ep93xx-keypad");
671
-
672
-
/* On reset PDIV and VDIV is set to zero, while PDIV zero
673
-
* means clock disable, VDIV shouldn't be zero.
674
-
* So i set both dividers to minimum.
675
-
*/
676
-
/* ENA - Enable CLK divider. */
677
-
/* PDIV - 00 - Disable clock */
678
-
/* VDIV - at least 2 */
679
-
/* Check and enable video clk registers */
680
-
value = __raw_readl(EP93XX_SYSCON_VIDCLKDIV);
681
-
value |= (1 << EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) | 2;
682
-
ep93xx_syscon_swlocked_write(value, EP93XX_SYSCON_VIDCLKDIV);
683
-
684
-
/* check and enable i2s clk registers */
685
-
value = __raw_readl(EP93XX_SYSCON_I2SCLKDIV);
686
-
value |= (1 << EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) | 2;
687
-
ep93xx_syscon_swlocked_write(value, EP93XX_SYSCON_I2SCLKDIV);
688
-
689
-
/* video clk */
690
-
hw = clk_hw_register_ddiv("ep93xx-fb",
691
-
EP93XX_SYSCON_VIDCLKDIV,
692
-
EP93XX_SYSCON_CLKDIV_ENABLE);
693
-
694
-
clk_hw_register_clkdev(hw, NULL, "ep93xx-fb");
695
-
696
-
/* i2s clk */
697
-
hw = clk_hw_register_ddiv("mclk",
698
-
EP93XX_SYSCON_I2SCLKDIV,
699
-
EP93XX_SYSCON_CLKDIV_ENABLE);
700
-
701
-
clk_hw_register_clkdev(hw, "mclk", "ep93xx-i2s");
702
-
703
-
/* i2s sclk */
704
-
#define EP93XX_I2SCLKDIV_SDIV_SHIFT 16
705
-
#define EP93XX_I2SCLKDIV_SDIV_WIDTH 1
706
-
hw = clk_hw_register_div("sclk",
707
-
"mclk",
708
-
EP93XX_SYSCON_I2SCLKDIV,
709
-
EP93XX_SYSCON_I2SCLKDIV_SENA,
710
-
EP93XX_I2SCLKDIV_SDIV_SHIFT,
711
-
EP93XX_I2SCLKDIV_SDIV_WIDTH,
712
-
sclk_divisors,
713
-
ARRAY_SIZE(sclk_divisors));
714
-
715
-
clk_hw_register_clkdev(hw, "sclk", "ep93xx-i2s");
716
-
717
-
/* i2s lrclk */
718
-
#define EP93XX_I2SCLKDIV_LRDIV32_SHIFT 17
719
-
#define EP93XX_I2SCLKDIV_LRDIV32_WIDTH 3
720
-
hw = clk_hw_register_div("lrclk",
721
-
"sclk",
722
-
EP93XX_SYSCON_I2SCLKDIV,
723
-
EP93XX_SYSCON_I2SCLKDIV_SENA,
724
-
EP93XX_I2SCLKDIV_LRDIV32_SHIFT,
725
-
EP93XX_I2SCLKDIV_LRDIV32_WIDTH,
726
-
lrclk_divisors,
727
-
ARRAY_SIZE(lrclk_divisors));
728
-
729
-
clk_hw_register_clkdev(hw, "lrclk", "ep93xx-i2s");
730
-
731
-
return 0;
732
-
}
733
-
postcore_initcall(ep93xx_clock_init);
-1018
arch/arm/mach-ep93xx/core.c
-1018
arch/arm/mach-ep93xx/core.c
···
1
-
// SPDX-License-Identifier: GPL-2.0-or-later
2
-
/*
3
-
* arch/arm/mach-ep93xx/core.c
4
-
* Core routines for Cirrus EP93xx chips.
5
-
*
6
-
* Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
7
-
* Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org>
8
-
*
9
-
* Thanks go to Michael Burian and Ray Lehtiniemi for their key
10
-
* role in the ep93xx linux community.
11
-
*/
12
-
13
-
#define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt
14
-
15
-
#include <linux/kernel.h>
16
-
#include <linux/init.h>
17
-
#include <linux/platform_device.h>
18
-
#include <linux/interrupt.h>
19
-
#include <linux/dma-mapping.h>
20
-
#include <linux/sys_soc.h>
21
-
#include <linux/irq.h>
22
-
#include <linux/io.h>
23
-
#include <linux/gpio.h>
24
-
#include <linux/leds.h>
25
-
#include <linux/uaccess.h>
26
-
#include <linux/termios.h>
27
-
#include <linux/amba/bus.h>
28
-
#include <linux/amba/serial.h>
29
-
#include <linux/mtd/physmap.h>
30
-
#include <linux/i2c.h>
31
-
#include <linux/gpio/machine.h>
32
-
#include <linux/spi/spi.h>
33
-
#include <linux/export.h>
34
-
#include <linux/irqchip/arm-vic.h>
35
-
#include <linux/reboot.h>
36
-
#include <linux/usb/ohci_pdriver.h>
37
-
#include <linux/random.h>
38
-
39
-
#include "hardware.h"
40
-
#include <linux/platform_data/video-ep93xx.h>
41
-
#include <linux/platform_data/keypad-ep93xx.h>
42
-
#include <linux/platform_data/spi-ep93xx.h>
43
-
#include <linux/soc/cirrus/ep93xx.h>
44
-
45
-
#include "gpio-ep93xx.h"
46
-
47
-
#include <asm/mach/arch.h>
48
-
#include <asm/mach/map.h>
49
-
50
-
#include "soc.h"
51
-
#include "irqs.h"
52
-
53
-
/*************************************************************************
54
-
* Static I/O mappings that are needed for all EP93xx platforms
55
-
*************************************************************************/
56
-
static struct map_desc ep93xx_io_desc[] __initdata = {
57
-
{
58
-
.virtual = EP93XX_AHB_VIRT_BASE,
59
-
.pfn = __phys_to_pfn(EP93XX_AHB_PHYS_BASE),
60
-
.length = EP93XX_AHB_SIZE,
61
-
.type = MT_DEVICE,
62
-
}, {
63
-
.virtual = EP93XX_APB_VIRT_BASE,
64
-
.pfn = __phys_to_pfn(EP93XX_APB_PHYS_BASE),
65
-
.length = EP93XX_APB_SIZE,
66
-
.type = MT_DEVICE,
67
-
},
68
-
};
69
-
70
-
void __init ep93xx_map_io(void)
71
-
{
72
-
iotable_init(ep93xx_io_desc, ARRAY_SIZE(ep93xx_io_desc));
73
-
}
74
-
75
-
/*************************************************************************
76
-
* EP93xx IRQ handling
77
-
*************************************************************************/
78
-
void __init ep93xx_init_irq(void)
79
-
{
80
-
vic_init(EP93XX_VIC1_BASE, IRQ_EP93XX_VIC0, EP93XX_VIC1_VALID_IRQ_MASK, 0);
81
-
vic_init(EP93XX_VIC2_BASE, IRQ_EP93XX_VIC1, EP93XX_VIC2_VALID_IRQ_MASK, 0);
82
-
}
83
-
84
-
85
-
/*************************************************************************
86
-
* EP93xx System Controller Software Locked register handling
87
-
*************************************************************************/
88
-
89
-
/*
90
-
* syscon_swlock prevents anything else from writing to the syscon
91
-
* block while a software locked register is being written.
92
-
*/
93
-
static DEFINE_SPINLOCK(syscon_swlock);
94
-
95
-
void ep93xx_syscon_swlocked_write(unsigned int val, void __iomem *reg)
96
-
{
97
-
unsigned long flags;
98
-
99
-
spin_lock_irqsave(&syscon_swlock, flags);
100
-
101
-
__raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
102
-
__raw_writel(val, reg);
103
-
104
-
spin_unlock_irqrestore(&syscon_swlock, flags);
105
-
}
106
-
107
-
void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits)
108
-
{
109
-
unsigned long flags;
110
-
unsigned int val;
111
-
112
-
spin_lock_irqsave(&syscon_swlock, flags);
113
-
114
-
val = __raw_readl(EP93XX_SYSCON_DEVCFG);
115
-
val &= ~clear_bits;
116
-
val |= set_bits;
117
-
__raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
118
-
__raw_writel(val, EP93XX_SYSCON_DEVCFG);
119
-
120
-
spin_unlock_irqrestore(&syscon_swlock, flags);
121
-
}
122
-
123
-
/**
124
-
* ep93xx_chip_revision() - returns the EP93xx chip revision
125
-
*
126
-
* See "platform.h" for more information.
127
-
*/
128
-
unsigned int ep93xx_chip_revision(void)
129
-
{
130
-
unsigned int v;
131
-
132
-
v = __raw_readl(EP93XX_SYSCON_SYSCFG);
133
-
v &= EP93XX_SYSCON_SYSCFG_REV_MASK;
134
-
v >>= EP93XX_SYSCON_SYSCFG_REV_SHIFT;
135
-
return v;
136
-
}
137
-
EXPORT_SYMBOL_GPL(ep93xx_chip_revision);
138
-
139
-
/*************************************************************************
140
-
* EP93xx GPIO
141
-
*************************************************************************/
142
-
static struct resource ep93xx_gpio_resource[] = {
143
-
DEFINE_RES_MEM(EP93XX_GPIO_PHYS_BASE, 0xcc),
144
-
DEFINE_RES_IRQ(IRQ_EP93XX_GPIO_AB),
145
-
DEFINE_RES_IRQ(IRQ_EP93XX_GPIO0MUX),
146
-
DEFINE_RES_IRQ(IRQ_EP93XX_GPIO1MUX),
147
-
DEFINE_RES_IRQ(IRQ_EP93XX_GPIO2MUX),
148
-
DEFINE_RES_IRQ(IRQ_EP93XX_GPIO3MUX),
149
-
DEFINE_RES_IRQ(IRQ_EP93XX_GPIO4MUX),
150
-
DEFINE_RES_IRQ(IRQ_EP93XX_GPIO5MUX),
151
-
DEFINE_RES_IRQ(IRQ_EP93XX_GPIO6MUX),
152
-
DEFINE_RES_IRQ(IRQ_EP93XX_GPIO7MUX),
153
-
};
154
-
155
-
static struct platform_device ep93xx_gpio_device = {
156
-
.name = "gpio-ep93xx",
157
-
.id = -1,
158
-
.num_resources = ARRAY_SIZE(ep93xx_gpio_resource),
159
-
.resource = ep93xx_gpio_resource,
160
-
};
161
-
162
-
/*************************************************************************
163
-
* EP93xx peripheral handling
164
-
*************************************************************************/
165
-
#define EP93XX_UART_MCR_OFFSET (0x0100)
166
-
167
-
static void ep93xx_uart_set_mctrl(struct amba_device *dev,
168
-
void __iomem *base, unsigned int mctrl)
169
-
{
170
-
unsigned int mcr;
171
-
172
-
mcr = 0;
173
-
if (mctrl & TIOCM_RTS)
174
-
mcr |= 2;
175
-
if (mctrl & TIOCM_DTR)
176
-
mcr |= 1;
177
-
178
-
__raw_writel(mcr, base + EP93XX_UART_MCR_OFFSET);
179
-
}
180
-
181
-
static struct amba_pl010_data ep93xx_uart_data = {
182
-
.set_mctrl = ep93xx_uart_set_mctrl,
183
-
};
184
-
185
-
static AMBA_APB_DEVICE(uart1, "apb:uart1", 0x00041010, EP93XX_UART1_PHYS_BASE,
186
-
{ IRQ_EP93XX_UART1 }, &ep93xx_uart_data);
187
-
188
-
static AMBA_APB_DEVICE(uart2, "apb:uart2", 0x00041010, EP93XX_UART2_PHYS_BASE,
189
-
{ IRQ_EP93XX_UART2 }, NULL);
190
-
191
-
static AMBA_APB_DEVICE(uart3, "apb:uart3", 0x00041010, EP93XX_UART3_PHYS_BASE,
192
-
{ IRQ_EP93XX_UART3 }, &ep93xx_uart_data);
193
-
194
-
static struct resource ep93xx_rtc_resource[] = {
195
-
DEFINE_RES_MEM(EP93XX_RTC_PHYS_BASE, 0x10c),
196
-
};
197
-
198
-
static struct platform_device ep93xx_rtc_device = {
199
-
.name = "ep93xx-rtc",
200
-
.id = -1,
201
-
.num_resources = ARRAY_SIZE(ep93xx_rtc_resource),
202
-
.resource = ep93xx_rtc_resource,
203
-
};
204
-
205
-
/*************************************************************************
206
-
* EP93xx OHCI USB Host
207
-
*************************************************************************/
208
-
209
-
static struct clk *ep93xx_ohci_host_clock;
210
-
211
-
static int ep93xx_ohci_power_on(struct platform_device *pdev)
212
-
{
213
-
if (!ep93xx_ohci_host_clock) {
214
-
ep93xx_ohci_host_clock = devm_clk_get(&pdev->dev, NULL);
215
-
if (IS_ERR(ep93xx_ohci_host_clock))
216
-
return PTR_ERR(ep93xx_ohci_host_clock);
217
-
}
218
-
219
-
return clk_prepare_enable(ep93xx_ohci_host_clock);
220
-
}
221
-
222
-
static void ep93xx_ohci_power_off(struct platform_device *pdev)
223
-
{
224
-
clk_disable(ep93xx_ohci_host_clock);
225
-
}
226
-
227
-
static struct usb_ohci_pdata ep93xx_ohci_pdata = {
228
-
.power_on = ep93xx_ohci_power_on,
229
-
.power_off = ep93xx_ohci_power_off,
230
-
.power_suspend = ep93xx_ohci_power_off,
231
-
};
232
-
233
-
static struct resource ep93xx_ohci_resources[] = {
234
-
DEFINE_RES_MEM(EP93XX_USB_PHYS_BASE, 0x1000),
235
-
DEFINE_RES_IRQ(IRQ_EP93XX_USB),
236
-
};
237
-
238
-
static u64 ep93xx_ohci_dma_mask = DMA_BIT_MASK(32);
239
-
240
-
static struct platform_device ep93xx_ohci_device = {
241
-
.name = "ohci-platform",
242
-
.id = -1,
243
-
.num_resources = ARRAY_SIZE(ep93xx_ohci_resources),
244
-
.resource = ep93xx_ohci_resources,
245
-
.dev = {
246
-
.dma_mask = &ep93xx_ohci_dma_mask,
247
-
.coherent_dma_mask = DMA_BIT_MASK(32),
248
-
.platform_data = &ep93xx_ohci_pdata,
249
-
},
250
-
};
251
-
252
-
/*************************************************************************
253
-
* EP93xx physmap'ed flash
254
-
*************************************************************************/
255
-
static struct physmap_flash_data ep93xx_flash_data;
256
-
257
-
static struct resource ep93xx_flash_resource = {
258
-
.flags = IORESOURCE_MEM,
259
-
};
260
-
261
-
static struct platform_device ep93xx_flash = {
262
-
.name = "physmap-flash",
263
-
.id = 0,
264
-
.dev = {
265
-
.platform_data = &ep93xx_flash_data,
266
-
},
267
-
.num_resources = 1,
268
-
.resource = &ep93xx_flash_resource,
269
-
};
270
-
271
-
/**
272
-
* ep93xx_register_flash() - Register the external flash device.
273
-
* @width: bank width in octets
274
-
* @start: resource start address
275
-
* @size: resource size
276
-
*/
277
-
void __init ep93xx_register_flash(unsigned int width,
278
-
resource_size_t start, resource_size_t size)
279
-
{
280
-
ep93xx_flash_data.width = width;
281
-
282
-
ep93xx_flash_resource.start = start;
283
-
ep93xx_flash_resource.end = start + size - 1;
284
-
285
-
platform_device_register(&ep93xx_flash);
286
-
}
287
-
288
-
289
-
/*************************************************************************
290
-
* EP93xx ethernet peripheral handling
291
-
*************************************************************************/
292
-
static struct ep93xx_eth_data ep93xx_eth_data;
293
-
294
-
static struct resource ep93xx_eth_resource[] = {
295
-
DEFINE_RES_MEM(EP93XX_ETHERNET_PHYS_BASE, 0x10000),
296
-
DEFINE_RES_IRQ(IRQ_EP93XX_ETHERNET),
297
-
};
298
-
299
-
static u64 ep93xx_eth_dma_mask = DMA_BIT_MASK(32);
300
-
301
-
static struct platform_device ep93xx_eth_device = {
302
-
.name = "ep93xx-eth",
303
-
.id = -1,
304
-
.dev = {
305
-
.platform_data = &ep93xx_eth_data,
306
-
.coherent_dma_mask = DMA_BIT_MASK(32),
307
-
.dma_mask = &ep93xx_eth_dma_mask,
308
-
},
309
-
.num_resources = ARRAY_SIZE(ep93xx_eth_resource),
310
-
.resource = ep93xx_eth_resource,
311
-
};
312
-
313
-
/**
314
-
* ep93xx_register_eth - Register the built-in ethernet platform device.
315
-
* @data: platform specific ethernet configuration (__initdata)
316
-
* @copy_addr: flag indicating that the MAC address should be copied
317
-
* from the IndAd registers (as programmed by the bootloader)
318
-
*/
319
-
void __init ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_addr)
320
-
{
321
-
if (copy_addr)
322
-
memcpy_fromio(data->dev_addr, EP93XX_ETHERNET_BASE + 0x50, 6);
323
-
324
-
ep93xx_eth_data = *data;
325
-
platform_device_register(&ep93xx_eth_device);
326
-
}
327
-
328
-
329
-
/*************************************************************************
330
-
* EP93xx i2c peripheral handling
331
-
*************************************************************************/
332
-
333
-
/* All EP93xx devices use the same two GPIO pins for I2C bit-banging */
334
-
static struct gpiod_lookup_table ep93xx_i2c_gpiod_table = {
335
-
.dev_id = "i2c-gpio.0",
336
-
.table = {
337
-
/* Use local offsets on gpiochip/port "G" */
338
-
GPIO_LOOKUP_IDX("G", 1, NULL, 0,
339
-
GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
340
-
GPIO_LOOKUP_IDX("G", 0, NULL, 1,
341
-
GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
342
-
{ }
343
-
},
344
-
};
345
-
346
-
static struct platform_device ep93xx_i2c_device = {
347
-
.name = "i2c-gpio",
348
-
.id = 0,
349
-
.dev = {
350
-
.platform_data = NULL,
351
-
},
352
-
};
353
-
354
-
/**
355
-
* ep93xx_register_i2c - Register the i2c platform device.
356
-
* @devices: platform specific i2c bus device information (__initdata)
357
-
* @num: the number of devices on the i2c bus
358
-
*/
359
-
void __init ep93xx_register_i2c(struct i2c_board_info *devices, int num)
360
-
{
361
-
/*
362
-
* FIXME: this just sets the two pins as non-opendrain, as no
363
-
* platforms tries to do that anyway. Flag the applicable lines
364
-
* as open drain in the GPIO_LOOKUP above and the driver or
365
-
* gpiolib will handle open drain/open drain emulation as need
366
-
* be. Right now i2c-gpio emulates open drain which is not
367
-
* optimal.
368
-
*/
369
-
__raw_writel((0 << 1) | (0 << 0),
370
-
EP93XX_GPIO_EEDRIVE);
371
-
372
-
i2c_register_board_info(0, devices, num);
373
-
gpiod_add_lookup_table(&ep93xx_i2c_gpiod_table);
374
-
platform_device_register(&ep93xx_i2c_device);
375
-
}
376
-
377
-
/*************************************************************************
378
-
* EP93xx SPI peripheral handling
379
-
*************************************************************************/
380
-
static struct ep93xx_spi_info ep93xx_spi_master_data;
381
-
382
-
static struct resource ep93xx_spi_resources[] = {
383
-
DEFINE_RES_MEM(EP93XX_SPI_PHYS_BASE, 0x18),
384
-
DEFINE_RES_IRQ(IRQ_EP93XX_SSP),
385
-
};
386
-
387
-
static u64 ep93xx_spi_dma_mask = DMA_BIT_MASK(32);
388
-
389
-
static struct platform_device ep93xx_spi_device = {
390
-
.name = "ep93xx-spi",
391
-
.id = 0,
392
-
.dev = {
393
-
.platform_data = &ep93xx_spi_master_data,
394
-
.coherent_dma_mask = DMA_BIT_MASK(32),
395
-
.dma_mask = &ep93xx_spi_dma_mask,
396
-
},
397
-
.num_resources = ARRAY_SIZE(ep93xx_spi_resources),
398
-
.resource = ep93xx_spi_resources,
399
-
};
400
-
401
-
/**
402
-
* ep93xx_register_spi() - registers spi platform device
403
-
* @info: ep93xx board specific spi master info (__initdata)
404
-
* @devices: SPI devices to register (__initdata)
405
-
* @num: number of SPI devices to register
406
-
*
407
-
* This function registers platform device for the EP93xx SPI controller and
408
-
* also makes sure that SPI pins are muxed so that I2S is not using those pins.
409
-
*/
410
-
void __init ep93xx_register_spi(struct ep93xx_spi_info *info,
411
-
struct spi_board_info *devices, int num)
412
-
{
413
-
/*
414
-
* When SPI is used, we need to make sure that I2S is muxed off from
415
-
* SPI pins.
416
-
*/
417
-
ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_I2SONSSP);
418
-
419
-
ep93xx_spi_master_data = *info;
420
-
spi_register_board_info(devices, num);
421
-
platform_device_register(&ep93xx_spi_device);
422
-
}
423
-
424
-
/*************************************************************************
425
-
* EP93xx LEDs
426
-
*************************************************************************/
427
-
static const struct gpio_led ep93xx_led_pins[] __initconst = {
428
-
{
429
-
.name = "platform:grled",
430
-
}, {
431
-
.name = "platform:rdled",
432
-
},
433
-
};
434
-
435
-
static const struct gpio_led_platform_data ep93xx_led_data __initconst = {
436
-
.num_leds = ARRAY_SIZE(ep93xx_led_pins),
437
-
.leds = ep93xx_led_pins,
438
-
};
439
-
440
-
static struct gpiod_lookup_table ep93xx_leds_gpio_table = {
441
-
.dev_id = "leds-gpio",
442
-
.table = {
443
-
/* Use local offsets on gpiochip/port "E" */
444
-
GPIO_LOOKUP_IDX("E", 0, NULL, 0, GPIO_ACTIVE_HIGH),
445
-
GPIO_LOOKUP_IDX("E", 1, NULL, 1, GPIO_ACTIVE_HIGH),
446
-
{ }
447
-
},
448
-
};
449
-
450
-
/*************************************************************************
451
-
* EP93xx pwm peripheral handling
452
-
*************************************************************************/
453
-
static struct resource ep93xx_pwm0_resource[] = {
454
-
DEFINE_RES_MEM(EP93XX_PWM_PHYS_BASE, 0x10),
455
-
};
456
-
457
-
static struct platform_device ep93xx_pwm0_device = {
458
-
.name = "ep93xx-pwm",
459
-
.id = 0,
460
-
.num_resources = ARRAY_SIZE(ep93xx_pwm0_resource),
461
-
.resource = ep93xx_pwm0_resource,
462
-
};
463
-
464
-
static struct resource ep93xx_pwm1_resource[] = {
465
-
DEFINE_RES_MEM(EP93XX_PWM_PHYS_BASE + 0x20, 0x10),
466
-
};
467
-
468
-
static struct platform_device ep93xx_pwm1_device = {
469
-
.name = "ep93xx-pwm",
470
-
.id = 1,
471
-
.num_resources = ARRAY_SIZE(ep93xx_pwm1_resource),
472
-
.resource = ep93xx_pwm1_resource,
473
-
};
474
-
475
-
void __init ep93xx_register_pwm(int pwm0, int pwm1)
476
-
{
477
-
if (pwm0)
478
-
platform_device_register(&ep93xx_pwm0_device);
479
-
480
-
/* NOTE: EP9307 does not have PWMOUT1 (pin EGPIO14) */
481
-
if (pwm1)
482
-
platform_device_register(&ep93xx_pwm1_device);
483
-
}
484
-
485
-
int ep93xx_pwm_acquire_gpio(struct platform_device *pdev)
486
-
{
487
-
int err;
488
-
489
-
if (pdev->id == 0) {
490
-
err = 0;
491
-
} else if (pdev->id == 1) {
492
-
err = gpio_request(EP93XX_GPIO_LINE_EGPIO14,
493
-
dev_name(&pdev->dev));
494
-
if (err)
495
-
return err;
496
-
err = gpio_direction_output(EP93XX_GPIO_LINE_EGPIO14, 0);
497
-
if (err)
498
-
goto fail;
499
-
500
-
/* PWM 1 output on EGPIO[14] */
501
-
ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_PONG);
502
-
} else {
503
-
err = -ENODEV;
504
-
}
505
-
506
-
return err;
507
-
508
-
fail:
509
-
gpio_free(EP93XX_GPIO_LINE_EGPIO14);
510
-
return err;
511
-
}
512
-
EXPORT_SYMBOL(ep93xx_pwm_acquire_gpio);
513
-
514
-
void ep93xx_pwm_release_gpio(struct platform_device *pdev)
515
-
{
516
-
if (pdev->id == 1) {
517
-
gpio_direction_input(EP93XX_GPIO_LINE_EGPIO14);
518
-
gpio_free(EP93XX_GPIO_LINE_EGPIO14);
519
-
520
-
/* EGPIO[14] used for GPIO */
521
-
ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_PONG);
522
-
}
523
-
}
524
-
EXPORT_SYMBOL(ep93xx_pwm_release_gpio);
525
-
526
-
527
-
/*************************************************************************
528
-
* EP93xx video peripheral handling
529
-
*************************************************************************/
530
-
static struct ep93xxfb_mach_info ep93xxfb_data;
531
-
532
-
static struct resource ep93xx_fb_resource[] = {
533
-
DEFINE_RES_MEM(EP93XX_RASTER_PHYS_BASE, 0x800),
534
-
};
535
-
536
-
static struct platform_device ep93xx_fb_device = {
537
-
.name = "ep93xx-fb",
538
-
.id = -1,
539
-
.dev = {
540
-
.platform_data = &ep93xxfb_data,
541
-
.coherent_dma_mask = DMA_BIT_MASK(32),
542
-
.dma_mask = &ep93xx_fb_device.dev.coherent_dma_mask,
543
-
},
544
-
.num_resources = ARRAY_SIZE(ep93xx_fb_resource),
545
-
.resource = ep93xx_fb_resource,
546
-
};
547
-
548
-
/* The backlight use a single register in the framebuffer's register space */
549
-
#define EP93XX_RASTER_REG_BRIGHTNESS 0x20
550
-
551
-
static struct resource ep93xx_bl_resources[] = {
552
-
DEFINE_RES_MEM(EP93XX_RASTER_PHYS_BASE +
553
-
EP93XX_RASTER_REG_BRIGHTNESS, 0x04),
554
-
};
555
-
556
-
static struct platform_device ep93xx_bl_device = {
557
-
.name = "ep93xx-bl",
558
-
.id = -1,
559
-
.num_resources = ARRAY_SIZE(ep93xx_bl_resources),
560
-
.resource = ep93xx_bl_resources,
561
-
};
562
-
563
-
/**
564
-
* ep93xx_register_fb - Register the framebuffer platform device.
565
-
* @data: platform specific framebuffer configuration (__initdata)
566
-
*/
567
-
void __init ep93xx_register_fb(struct ep93xxfb_mach_info *data)
568
-
{
569
-
ep93xxfb_data = *data;
570
-
platform_device_register(&ep93xx_fb_device);
571
-
platform_device_register(&ep93xx_bl_device);
572
-
}
573
-
574
-
575
-
/*************************************************************************
576
-
* EP93xx matrix keypad peripheral handling
577
-
*************************************************************************/
578
-
static struct ep93xx_keypad_platform_data ep93xx_keypad_data;
579
-
580
-
static struct resource ep93xx_keypad_resource[] = {
581
-
DEFINE_RES_MEM(EP93XX_KEY_MATRIX_PHYS_BASE, 0x0c),
582
-
DEFINE_RES_IRQ(IRQ_EP93XX_KEY),
583
-
};
584
-
585
-
static struct platform_device ep93xx_keypad_device = {
586
-
.name = "ep93xx-keypad",
587
-
.id = -1,
588
-
.dev = {
589
-
.platform_data = &ep93xx_keypad_data,
590
-
},
591
-
.num_resources = ARRAY_SIZE(ep93xx_keypad_resource),
592
-
.resource = ep93xx_keypad_resource,
593
-
};
594
-
595
-
/**
596
-
* ep93xx_register_keypad - Register the keypad platform device.
597
-
* @data: platform specific keypad configuration (__initdata)
598
-
*/
599
-
void __init ep93xx_register_keypad(struct ep93xx_keypad_platform_data *data)
600
-
{
601
-
ep93xx_keypad_data = *data;
602
-
platform_device_register(&ep93xx_keypad_device);
603
-
}
604
-
605
-
int ep93xx_keypad_acquire_gpio(struct platform_device *pdev)
606
-
{
607
-
int err;
608
-
int i;
609
-
610
-
for (i = 0; i < 8; i++) {
611
-
err = gpio_request(EP93XX_GPIO_LINE_C(i), dev_name(&pdev->dev));
612
-
if (err)
613
-
goto fail_gpio_c;
614
-
err = gpio_request(EP93XX_GPIO_LINE_D(i), dev_name(&pdev->dev));
615
-
if (err)
616
-
goto fail_gpio_d;
617
-
}
618
-
619
-
/* Enable the keypad controller; GPIO ports C and D used for keypad */
620
-
ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_KEYS |
621
-
EP93XX_SYSCON_DEVCFG_GONK);
622
-
623
-
return 0;
624
-
625
-
fail_gpio_d:
626
-
gpio_free(EP93XX_GPIO_LINE_C(i));
627
-
fail_gpio_c:
628
-
for (--i; i >= 0; --i) {
629
-
gpio_free(EP93XX_GPIO_LINE_C(i));
630
-
gpio_free(EP93XX_GPIO_LINE_D(i));
631
-
}
632
-
return err;
633
-
}
634
-
EXPORT_SYMBOL(ep93xx_keypad_acquire_gpio);
635
-
636
-
void ep93xx_keypad_release_gpio(struct platform_device *pdev)
637
-
{
638
-
int i;
639
-
640
-
for (i = 0; i < 8; i++) {
641
-
gpio_free(EP93XX_GPIO_LINE_C(i));
642
-
gpio_free(EP93XX_GPIO_LINE_D(i));
643
-
}
644
-
645
-
/* Disable the keypad controller; GPIO ports C and D used for GPIO */
646
-
ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_KEYS |
647
-
EP93XX_SYSCON_DEVCFG_GONK);
648
-
}
649
-
EXPORT_SYMBOL(ep93xx_keypad_release_gpio);
650
-
651
-
/*************************************************************************
652
-
* EP93xx I2S audio peripheral handling
653
-
*************************************************************************/
654
-
static struct resource ep93xx_i2s_resource[] = {
655
-
DEFINE_RES_MEM(EP93XX_I2S_PHYS_BASE, 0x100),
656
-
DEFINE_RES_IRQ(IRQ_EP93XX_SAI),
657
-
};
658
-
659
-
static struct platform_device ep93xx_i2s_device = {
660
-
.name = "ep93xx-i2s",
661
-
.id = -1,
662
-
.num_resources = ARRAY_SIZE(ep93xx_i2s_resource),
663
-
.resource = ep93xx_i2s_resource,
664
-
};
665
-
666
-
static struct platform_device ep93xx_pcm_device = {
667
-
.name = "ep93xx-pcm-audio",
668
-
.id = -1,
669
-
};
670
-
671
-
void __init ep93xx_register_i2s(void)
672
-
{
673
-
platform_device_register(&ep93xx_i2s_device);
674
-
platform_device_register(&ep93xx_pcm_device);
675
-
}
676
-
677
-
#define EP93XX_SYSCON_DEVCFG_I2S_MASK (EP93XX_SYSCON_DEVCFG_I2SONSSP | \
678
-
EP93XX_SYSCON_DEVCFG_I2SONAC97)
679
-
680
-
#define EP93XX_I2SCLKDIV_MASK (EP93XX_SYSCON_I2SCLKDIV_ORIDE | \
681
-
EP93XX_SYSCON_I2SCLKDIV_SPOL)
682
-
683
-
int ep93xx_i2s_acquire(void)
684
-
{
685
-
unsigned val;
686
-
687
-
ep93xx_devcfg_set_clear(EP93XX_SYSCON_DEVCFG_I2SONAC97,
688
-
EP93XX_SYSCON_DEVCFG_I2S_MASK);
689
-
690
-
/*
691
-
* This is potentially racy with the clock api for i2s_mclk, sclk and
692
-
* lrclk. Since the i2s driver is the only user of those clocks we
693
-
* rely on it to prevent parallel use of this function and the
694
-
* clock api for the i2s clocks.
695
-
*/
696
-
val = __raw_readl(EP93XX_SYSCON_I2SCLKDIV);
697
-
val &= ~EP93XX_I2SCLKDIV_MASK;
698
-
val |= EP93XX_SYSCON_I2SCLKDIV_ORIDE | EP93XX_SYSCON_I2SCLKDIV_SPOL;
699
-
ep93xx_syscon_swlocked_write(val, EP93XX_SYSCON_I2SCLKDIV);
700
-
701
-
return 0;
702
-
}
703
-
EXPORT_SYMBOL(ep93xx_i2s_acquire);
704
-
705
-
void ep93xx_i2s_release(void)
706
-
{
707
-
ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_I2S_MASK);
708
-
}
709
-
EXPORT_SYMBOL(ep93xx_i2s_release);
710
-
711
-
/*************************************************************************
712
-
* EP93xx AC97 audio peripheral handling
713
-
*************************************************************************/
714
-
static struct resource ep93xx_ac97_resources[] = {
715
-
DEFINE_RES_MEM(EP93XX_AAC_PHYS_BASE, 0xac),
716
-
DEFINE_RES_IRQ(IRQ_EP93XX_AACINTR),
717
-
};
718
-
719
-
static struct platform_device ep93xx_ac97_device = {
720
-
.name = "ep93xx-ac97",
721
-
.id = -1,
722
-
.num_resources = ARRAY_SIZE(ep93xx_ac97_resources),
723
-
.resource = ep93xx_ac97_resources,
724
-
};
725
-
726
-
void __init ep93xx_register_ac97(void)
727
-
{
728
-
/*
729
-
* Make sure that the AC97 pins are not used by I2S.
730
-
*/
731
-
ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_I2SONAC97);
732
-
733
-
platform_device_register(&ep93xx_ac97_device);
734
-
platform_device_register(&ep93xx_pcm_device);
735
-
}
736
-
737
-
/*************************************************************************
738
-
* EP93xx Watchdog
739
-
*************************************************************************/
740
-
static struct resource ep93xx_wdt_resources[] = {
741
-
DEFINE_RES_MEM(EP93XX_WATCHDOG_PHYS_BASE, 0x08),
742
-
};
743
-
744
-
static struct platform_device ep93xx_wdt_device = {
745
-
.name = "ep93xx-wdt",
746
-
.id = -1,
747
-
.num_resources = ARRAY_SIZE(ep93xx_wdt_resources),
748
-
.resource = ep93xx_wdt_resources,
749
-
};
750
-
751
-
/*************************************************************************
752
-
* EP93xx IDE
753
-
*************************************************************************/
754
-
static struct resource ep93xx_ide_resources[] = {
755
-
DEFINE_RES_MEM(EP93XX_IDE_PHYS_BASE, 0x38),
756
-
DEFINE_RES_IRQ(IRQ_EP93XX_EXT3),
757
-
};
758
-
759
-
static struct platform_device ep93xx_ide_device = {
760
-
.name = "ep93xx-ide",
761
-
.id = -1,
762
-
.dev = {
763
-
.dma_mask = &ep93xx_ide_device.dev.coherent_dma_mask,
764
-
.coherent_dma_mask = DMA_BIT_MASK(32),
765
-
},
766
-
.num_resources = ARRAY_SIZE(ep93xx_ide_resources),
767
-
.resource = ep93xx_ide_resources,
768
-
};
769
-
770
-
void __init ep93xx_register_ide(void)
771
-
{
772
-
platform_device_register(&ep93xx_ide_device);
773
-
}
774
-
775
-
int ep93xx_ide_acquire_gpio(struct platform_device *pdev)
776
-
{
777
-
int err;
778
-
int i;
779
-
780
-
err = gpio_request(EP93XX_GPIO_LINE_EGPIO2, dev_name(&pdev->dev));
781
-
if (err)
782
-
return err;
783
-
err = gpio_request(EP93XX_GPIO_LINE_EGPIO15, dev_name(&pdev->dev));
784
-
if (err)
785
-
goto fail_egpio15;
786
-
for (i = 2; i < 8; i++) {
787
-
err = gpio_request(EP93XX_GPIO_LINE_E(i), dev_name(&pdev->dev));
788
-
if (err)
789
-
goto fail_gpio_e;
790
-
}
791
-
for (i = 4; i < 8; i++) {
792
-
err = gpio_request(EP93XX_GPIO_LINE_G(i), dev_name(&pdev->dev));
793
-
if (err)
794
-
goto fail_gpio_g;
795
-
}
796
-
for (i = 0; i < 8; i++) {
797
-
err = gpio_request(EP93XX_GPIO_LINE_H(i), dev_name(&pdev->dev));
798
-
if (err)
799
-
goto fail_gpio_h;
800
-
}
801
-
802
-
/* GPIO ports E[7:2], G[7:4] and H used by IDE */
803
-
ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_EONIDE |
804
-
EP93XX_SYSCON_DEVCFG_GONIDE |
805
-
EP93XX_SYSCON_DEVCFG_HONIDE);
806
-
return 0;
807
-
808
-
fail_gpio_h:
809
-
for (--i; i >= 0; --i)
810
-
gpio_free(EP93XX_GPIO_LINE_H(i));
811
-
i = 8;
812
-
fail_gpio_g:
813
-
for (--i; i >= 4; --i)
814
-
gpio_free(EP93XX_GPIO_LINE_G(i));
815
-
i = 8;
816
-
fail_gpio_e:
817
-
for (--i; i >= 2; --i)
818
-
gpio_free(EP93XX_GPIO_LINE_E(i));
819
-
gpio_free(EP93XX_GPIO_LINE_EGPIO15);
820
-
fail_egpio15:
821
-
gpio_free(EP93XX_GPIO_LINE_EGPIO2);
822
-
return err;
823
-
}
824
-
EXPORT_SYMBOL(ep93xx_ide_acquire_gpio);
825
-
826
-
void ep93xx_ide_release_gpio(struct platform_device *pdev)
827
-
{
828
-
int i;
829
-
830
-
for (i = 2; i < 8; i++)
831
-
gpio_free(EP93XX_GPIO_LINE_E(i));
832
-
for (i = 4; i < 8; i++)
833
-
gpio_free(EP93XX_GPIO_LINE_G(i));
834
-
for (i = 0; i < 8; i++)
835
-
gpio_free(EP93XX_GPIO_LINE_H(i));
836
-
gpio_free(EP93XX_GPIO_LINE_EGPIO15);
837
-
gpio_free(EP93XX_GPIO_LINE_EGPIO2);
838
-
839
-
840
-
/* GPIO ports E[7:2], G[7:4] and H used by GPIO */
841
-
ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_EONIDE |
842
-
EP93XX_SYSCON_DEVCFG_GONIDE |
843
-
EP93XX_SYSCON_DEVCFG_HONIDE);
844
-
}
845
-
EXPORT_SYMBOL(ep93xx_ide_release_gpio);
846
-
847
-
/*************************************************************************
848
-
* EP93xx ADC
849
-
*************************************************************************/
850
-
static struct resource ep93xx_adc_resources[] = {
851
-
DEFINE_RES_MEM(EP93XX_ADC_PHYS_BASE, 0x28),
852
-
DEFINE_RES_IRQ(IRQ_EP93XX_TOUCH),
853
-
};
854
-
855
-
static struct platform_device ep93xx_adc_device = {
856
-
.name = "ep93xx-adc",
857
-
.id = -1,
858
-
.num_resources = ARRAY_SIZE(ep93xx_adc_resources),
859
-
.resource = ep93xx_adc_resources,
860
-
};
861
-
862
-
void __init ep93xx_register_adc(void)
863
-
{
864
-
/* Power up ADC, deactivate Touch Screen Controller */
865
-
ep93xx_devcfg_set_clear(EP93XX_SYSCON_DEVCFG_TIN,
866
-
EP93XX_SYSCON_DEVCFG_ADCPD);
867
-
868
-
platform_device_register(&ep93xx_adc_device);
869
-
}
870
-
871
-
/*************************************************************************
872
-
* EP93xx Security peripheral
873
-
*************************************************************************/
874
-
875
-
/*
876
-
* The Maverick Key is 256 bits of micro fuses blown at the factory during
877
-
* manufacturing to uniquely identify a part.
878
-
*
879
-
* See: http://arm.cirrus.com/forum/viewtopic.php?t=486&highlight=maverick+key
880
-
*/
881
-
#define EP93XX_SECURITY_REG(x) (EP93XX_SECURITY_BASE + (x))
882
-
#define EP93XX_SECURITY_SECFLG EP93XX_SECURITY_REG(0x2400)
883
-
#define EP93XX_SECURITY_FUSEFLG EP93XX_SECURITY_REG(0x2410)
884
-
#define EP93XX_SECURITY_UNIQID EP93XX_SECURITY_REG(0x2440)
885
-
#define EP93XX_SECURITY_UNIQCHK EP93XX_SECURITY_REG(0x2450)
886
-
#define EP93XX_SECURITY_UNIQVAL EP93XX_SECURITY_REG(0x2460)
887
-
#define EP93XX_SECURITY_SECID1 EP93XX_SECURITY_REG(0x2500)
888
-
#define EP93XX_SECURITY_SECID2 EP93XX_SECURITY_REG(0x2504)
889
-
#define EP93XX_SECURITY_SECCHK1 EP93XX_SECURITY_REG(0x2520)
890
-
#define EP93XX_SECURITY_SECCHK2 EP93XX_SECURITY_REG(0x2524)
891
-
#define EP93XX_SECURITY_UNIQID2 EP93XX_SECURITY_REG(0x2700)
892
-
#define EP93XX_SECURITY_UNIQID3 EP93XX_SECURITY_REG(0x2704)
893
-
#define EP93XX_SECURITY_UNIQID4 EP93XX_SECURITY_REG(0x2708)
894
-
#define EP93XX_SECURITY_UNIQID5 EP93XX_SECURITY_REG(0x270c)
895
-
896
-
static char ep93xx_soc_id[33];
897
-
898
-
static const char __init *ep93xx_get_soc_id(void)
899
-
{
900
-
unsigned int id, id2, id3, id4, id5;
901
-
902
-
if (__raw_readl(EP93XX_SECURITY_UNIQVAL) != 1)
903
-
return "bad Hamming code";
904
-
905
-
id = __raw_readl(EP93XX_SECURITY_UNIQID);
906
-
id2 = __raw_readl(EP93XX_SECURITY_UNIQID2);
907
-
id3 = __raw_readl(EP93XX_SECURITY_UNIQID3);
908
-
id4 = __raw_readl(EP93XX_SECURITY_UNIQID4);
909
-
id5 = __raw_readl(EP93XX_SECURITY_UNIQID5);
910
-
911
-
if (id != id2)
912
-
return "invalid";
913
-
914
-
/* Toss the unique ID into the entropy pool */
915
-
add_device_randomness(&id2, 4);
916
-
add_device_randomness(&id3, 4);
917
-
add_device_randomness(&id4, 4);
918
-
add_device_randomness(&id5, 4);
919
-
920
-
snprintf(ep93xx_soc_id, sizeof(ep93xx_soc_id),
921
-
"%08x%08x%08x%08x", id2, id3, id4, id5);
922
-
923
-
return ep93xx_soc_id;
924
-
}
925
-
926
-
static const char __init *ep93xx_get_soc_rev(void)
927
-
{
928
-
int rev = ep93xx_chip_revision();
929
-
930
-
switch (rev) {
931
-
case EP93XX_CHIP_REV_D0:
932
-
return "D0";
933
-
case EP93XX_CHIP_REV_D1:
934
-
return "D1";
935
-
case EP93XX_CHIP_REV_E0:
936
-
return "E0";
937
-
case EP93XX_CHIP_REV_E1:
938
-
return "E1";
939
-
case EP93XX_CHIP_REV_E2:
940
-
return "E2";
941
-
default:
942
-
return "unknown";
943
-
}
944
-
}
945
-
946
-
static const char __init *ep93xx_get_machine_name(void)
947
-
{
948
-
return kasprintf(GFP_KERNEL,"%s", machine_desc->name);
949
-
}
950
-
951
-
static struct device __init *ep93xx_init_soc(void)
952
-
{
953
-
struct soc_device_attribute *soc_dev_attr;
954
-
struct soc_device *soc_dev;
955
-
956
-
soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
957
-
if (!soc_dev_attr)
958
-
return NULL;
959
-
960
-
soc_dev_attr->machine = ep93xx_get_machine_name();
961
-
soc_dev_attr->family = "Cirrus Logic EP93xx";
962
-
soc_dev_attr->revision = ep93xx_get_soc_rev();
963
-
soc_dev_attr->soc_id = ep93xx_get_soc_id();
964
-
965
-
soc_dev = soc_device_register(soc_dev_attr);
966
-
if (IS_ERR(soc_dev)) {
967
-
kfree(soc_dev_attr->machine);
968
-
kfree(soc_dev_attr);
969
-
return NULL;
970
-
}
971
-
972
-
return soc_device_to_device(soc_dev);
973
-
}
974
-
975
-
struct device __init *ep93xx_init_devices(void)
976
-
{
977
-
struct device *parent;
978
-
979
-
/* Disallow access to MaverickCrunch initially */
980
-
ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_CPENA);
981
-
982
-
/* Default all ports to GPIO */
983
-
ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_KEYS |
984
-
EP93XX_SYSCON_DEVCFG_GONK |
985
-
EP93XX_SYSCON_DEVCFG_EONIDE |
986
-
EP93XX_SYSCON_DEVCFG_GONIDE |
987
-
EP93XX_SYSCON_DEVCFG_HONIDE);
988
-
989
-
parent = ep93xx_init_soc();
990
-
991
-
/* Get the GPIO working early, other devices need it */
992
-
platform_device_register(&ep93xx_gpio_device);
993
-
994
-
amba_device_register(&uart1_device, &iomem_resource);
995
-
amba_device_register(&uart2_device, &iomem_resource);
996
-
amba_device_register(&uart3_device, &iomem_resource);
997
-
998
-
platform_device_register(&ep93xx_rtc_device);
999
-
platform_device_register(&ep93xx_ohci_device);
1000
-
platform_device_register(&ep93xx_wdt_device);
1001
-
1002
-
gpiod_add_lookup_table(&ep93xx_leds_gpio_table);
1003
-
gpio_led_register_device(-1, &ep93xx_led_data);
1004
-
1005
-
return parent;
1006
-
}
1007
-
1008
-
void ep93xx_restart(enum reboot_mode mode, const char *cmd)
1009
-
{
1010
-
/*
1011
-
* Set then clear the SWRST bit to initiate a software reset
1012
-
*/
1013
-
ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_SWRST);
1014
-
ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_SWRST);
1015
-
1016
-
while (1)
1017
-
;
1018
-
}
-114
arch/arm/mach-ep93xx/dma.c
-114
arch/arm/mach-ep93xx/dma.c
···
1
-
// SPDX-License-Identifier: GPL-2.0-or-later
2
-
/*
3
-
* arch/arm/mach-ep93xx/dma.c
4
-
*
5
-
* Platform support code for the EP93xx dmaengine driver.
6
-
*
7
-
* Copyright (C) 2011 Mika Westerberg
8
-
*
9
-
* This work is based on the original dma-m2p implementation with
10
-
* following copyrights:
11
-
*
12
-
* Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
13
-
* Copyright (C) 2006 Applied Data Systems
14
-
* Copyright (C) 2009 Ryan Mallon <rmallon@gmail.com>
15
-
*/
16
-
17
-
#include <linux/dmaengine.h>
18
-
#include <linux/dma-mapping.h>
19
-
#include <linux/init.h>
20
-
#include <linux/interrupt.h>
21
-
#include <linux/kernel.h>
22
-
#include <linux/platform_device.h>
23
-
24
-
#include <linux/platform_data/dma-ep93xx.h>
25
-
#include "hardware.h"
26
-
27
-
#include "soc.h"
28
-
29
-
#define DMA_CHANNEL(_name, _base, _irq) \
30
-
{ .name = (_name), .base = (_base), .irq = (_irq) }
31
-
32
-
/*
33
-
* DMA M2P channels.
34
-
*
35
-
* On the EP93xx chip the following peripherals my be allocated to the 10
36
-
* Memory to Internal Peripheral (M2P) channels (5 transmit + 5 receive).
37
-
*
38
-
* I2S contains 3 Tx and 3 Rx DMA Channels
39
-
* AAC contains 3 Tx and 3 Rx DMA Channels
40
-
* UART1 contains 1 Tx and 1 Rx DMA Channels
41
-
* UART2 contains 1 Tx and 1 Rx DMA Channels
42
-
* UART3 contains 1 Tx and 1 Rx DMA Channels
43
-
* IrDA contains 1 Tx and 1 Rx DMA Channels
44
-
*
45
-
* Registers are mapped statically in ep93xx_map_io().
46
-
*/
47
-
static struct ep93xx_dma_chan_data ep93xx_dma_m2p_channels[] = {
48
-
DMA_CHANNEL("m2p0", EP93XX_DMA_BASE + 0x0000, IRQ_EP93XX_DMAM2P0),
49
-
DMA_CHANNEL("m2p1", EP93XX_DMA_BASE + 0x0040, IRQ_EP93XX_DMAM2P1),
50
-
DMA_CHANNEL("m2p2", EP93XX_DMA_BASE + 0x0080, IRQ_EP93XX_DMAM2P2),
51
-
DMA_CHANNEL("m2p3", EP93XX_DMA_BASE + 0x00c0, IRQ_EP93XX_DMAM2P3),
52
-
DMA_CHANNEL("m2p4", EP93XX_DMA_BASE + 0x0240, IRQ_EP93XX_DMAM2P4),
53
-
DMA_CHANNEL("m2p5", EP93XX_DMA_BASE + 0x0200, IRQ_EP93XX_DMAM2P5),
54
-
DMA_CHANNEL("m2p6", EP93XX_DMA_BASE + 0x02c0, IRQ_EP93XX_DMAM2P6),
55
-
DMA_CHANNEL("m2p7", EP93XX_DMA_BASE + 0x0280, IRQ_EP93XX_DMAM2P7),
56
-
DMA_CHANNEL("m2p8", EP93XX_DMA_BASE + 0x0340, IRQ_EP93XX_DMAM2P8),
57
-
DMA_CHANNEL("m2p9", EP93XX_DMA_BASE + 0x0300, IRQ_EP93XX_DMAM2P9),
58
-
};
59
-
60
-
static struct ep93xx_dma_platform_data ep93xx_dma_m2p_data = {
61
-
.channels = ep93xx_dma_m2p_channels,
62
-
.num_channels = ARRAY_SIZE(ep93xx_dma_m2p_channels),
63
-
};
64
-
65
-
static u64 ep93xx_dma_m2p_mask = DMA_BIT_MASK(32);
66
-
67
-
static struct platform_device ep93xx_dma_m2p_device = {
68
-
.name = "ep93xx-dma-m2p",
69
-
.id = -1,
70
-
.dev = {
71
-
.platform_data = &ep93xx_dma_m2p_data,
72
-
.dma_mask = &ep93xx_dma_m2p_mask,
73
-
.coherent_dma_mask = DMA_BIT_MASK(32),
74
-
},
75
-
};
76
-
77
-
/*
78
-
* DMA M2M channels.
79
-
*
80
-
* There are 2 M2M channels which support memcpy/memset and in addition simple
81
-
* hardware requests from/to SSP and IDE. We do not implement an external
82
-
* hardware requests.
83
-
*
84
-
* Registers are mapped statically in ep93xx_map_io().
85
-
*/
86
-
static struct ep93xx_dma_chan_data ep93xx_dma_m2m_channels[] = {
87
-
DMA_CHANNEL("m2m0", EP93XX_DMA_BASE + 0x0100, IRQ_EP93XX_DMAM2M0),
88
-
DMA_CHANNEL("m2m1", EP93XX_DMA_BASE + 0x0140, IRQ_EP93XX_DMAM2M1),
89
-
};
90
-
91
-
static struct ep93xx_dma_platform_data ep93xx_dma_m2m_data = {
92
-
.channels = ep93xx_dma_m2m_channels,
93
-
.num_channels = ARRAY_SIZE(ep93xx_dma_m2m_channels),
94
-
};
95
-
96
-
static u64 ep93xx_dma_m2m_mask = DMA_BIT_MASK(32);
97
-
98
-
static struct platform_device ep93xx_dma_m2m_device = {
99
-
.name = "ep93xx-dma-m2m",
100
-
.id = -1,
101
-
.dev = {
102
-
.platform_data = &ep93xx_dma_m2m_data,
103
-
.dma_mask = &ep93xx_dma_m2m_mask,
104
-
.coherent_dma_mask = DMA_BIT_MASK(32),
105
-
},
106
-
};
107
-
108
-
static int __init ep93xx_dma_init(void)
109
-
{
110
-
platform_device_register(&ep93xx_dma_m2p_device);
111
-
platform_device_register(&ep93xx_dma_m2m_device);
112
-
return 0;
113
-
}
114
-
arch_initcall(ep93xx_dma_init);
-368
arch/arm/mach-ep93xx/edb93xx.c
-368
arch/arm/mach-ep93xx/edb93xx.c
···
1
-
// SPDX-License-Identifier: GPL-2.0-or-later
2
-
/*
3
-
* arch/arm/mach-ep93xx/edb93xx.c
4
-
* Cirrus Logic EDB93xx Development Board support.
5
-
*
6
-
* EDB93XX, EDB9301, EDB9307A
7
-
* Copyright (C) 2008-2009 H Hartley Sweeten <hsweeten@visionengravers.com>
8
-
*
9
-
* EDB9302
10
-
* Copyright (C) 2006 George Kashperko <george@chas.com.ua>
11
-
*
12
-
* EDB9302A, EDB9315, EDB9315A
13
-
* Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
14
-
*
15
-
* EDB9307
16
-
* Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org>
17
-
*
18
-
* EDB9312
19
-
* Copyright (C) 2006 Infosys Technologies Limited
20
-
* Toufeeq Hussain <toufeeq_hussain@infosys.com>
21
-
*/
22
-
23
-
#include <linux/kernel.h>
24
-
#include <linux/init.h>
25
-
#include <linux/platform_device.h>
26
-
#include <linux/i2c.h>
27
-
#include <linux/spi/spi.h>
28
-
#include <linux/gpio/machine.h>
29
-
30
-
#include <sound/cs4271.h>
31
-
32
-
#include "hardware.h"
33
-
#include <linux/platform_data/video-ep93xx.h>
34
-
#include <linux/platform_data/spi-ep93xx.h>
35
-
#include "gpio-ep93xx.h"
36
-
37
-
#include <asm/mach-types.h>
38
-
#include <asm/mach/arch.h>
39
-
40
-
#include "soc.h"
41
-
42
-
static void __init edb93xx_register_flash(void)
43
-
{
44
-
if (machine_is_edb9307() || machine_is_edb9312() ||
45
-
machine_is_edb9315()) {
46
-
ep93xx_register_flash(4, EP93XX_CS6_PHYS_BASE, SZ_32M);
47
-
} else {
48
-
ep93xx_register_flash(2, EP93XX_CS6_PHYS_BASE, SZ_16M);
49
-
}
50
-
}
51
-
52
-
static struct ep93xx_eth_data __initdata edb93xx_eth_data = {
53
-
.phy_id = 1,
54
-
};
55
-
56
-
57
-
/*************************************************************************
58
-
* EDB93xx i2c peripheral handling
59
-
*************************************************************************/
60
-
61
-
static struct i2c_board_info __initdata edb93xxa_i2c_board_info[] = {
62
-
{
63
-
I2C_BOARD_INFO("isl1208", 0x6f),
64
-
},
65
-
};
66
-
67
-
static struct i2c_board_info __initdata edb93xx_i2c_board_info[] = {
68
-
{
69
-
I2C_BOARD_INFO("ds1337", 0x68),
70
-
},
71
-
};
72
-
73
-
static void __init edb93xx_register_i2c(void)
74
-
{
75
-
if (machine_is_edb9302a() || machine_is_edb9307a() ||
76
-
machine_is_edb9315a()) {
77
-
ep93xx_register_i2c(edb93xxa_i2c_board_info,
78
-
ARRAY_SIZE(edb93xxa_i2c_board_info));
79
-
} else if (machine_is_edb9302() || machine_is_edb9307()
80
-
|| machine_is_edb9312() || machine_is_edb9315()) {
81
-
ep93xx_register_i2c(edb93xx_i2c_board_info,
82
-
ARRAY_SIZE(edb93xx_i2c_board_info));
83
-
}
84
-
}
85
-
86
-
87
-
/*************************************************************************
88
-
* EDB93xx SPI peripheral handling
89
-
*************************************************************************/
90
-
static struct cs4271_platform_data edb93xx_cs4271_data = {
91
-
/* Intentionally left blank */
92
-
};
93
-
94
-
static struct spi_board_info edb93xx_spi_board_info[] __initdata = {
95
-
{
96
-
.modalias = "cs4271",
97
-
.platform_data = &edb93xx_cs4271_data,
98
-
.max_speed_hz = 6000000,
99
-
.bus_num = 0,
100
-
.chip_select = 0,
101
-
.mode = SPI_MODE_3,
102
-
},
103
-
};
104
-
105
-
static struct gpiod_lookup_table edb93xx_spi_cs_gpio_table = {
106
-
.dev_id = "spi0",
107
-
.table = {
108
-
GPIO_LOOKUP("A", 6, "cs", GPIO_ACTIVE_LOW),
109
-
{ },
110
-
},
111
-
};
112
-
113
-
static struct ep93xx_spi_info edb93xx_spi_info __initdata = {
114
-
/* Intentionally left blank */
115
-
};
116
-
117
-
static struct gpiod_lookup_table edb93xx_cs4272_edb9301_gpio_table = {
118
-
.dev_id = "spi0.0", /* CS0 on SPI0 */
119
-
.table = {
120
-
GPIO_LOOKUP("A", 1, "reset", GPIO_ACTIVE_LOW),
121
-
{ },
122
-
},
123
-
};
124
-
125
-
static struct gpiod_lookup_table edb93xx_cs4272_edb9302_gpio_table = {
126
-
.dev_id = "spi0.0", /* CS0 on SPI0 */
127
-
.table = {
128
-
GPIO_LOOKUP("H", 2, "reset", GPIO_ACTIVE_LOW),
129
-
{ },
130
-
},
131
-
};
132
-
133
-
static struct gpiod_lookup_table edb93xx_cs4272_edb9315_gpio_table = {
134
-
.dev_id = "spi0.0", /* CS0 on SPI0 */
135
-
.table = {
136
-
GPIO_LOOKUP("B", 6, "reset", GPIO_ACTIVE_LOW),
137
-
{ },
138
-
},
139
-
};
140
-
141
-
static void __init edb93xx_register_spi(void)
142
-
{
143
-
if (machine_is_edb9301() || machine_is_edb9302())
144
-
gpiod_add_lookup_table(&edb93xx_cs4272_edb9301_gpio_table);
145
-
else if (machine_is_edb9302a() || machine_is_edb9307a())
146
-
gpiod_add_lookup_table(&edb93xx_cs4272_edb9302_gpio_table);
147
-
else if (machine_is_edb9315a())
148
-
gpiod_add_lookup_table(&edb93xx_cs4272_edb9315_gpio_table);
149
-
150
-
gpiod_add_lookup_table(&edb93xx_spi_cs_gpio_table);
151
-
ep93xx_register_spi(&edb93xx_spi_info, edb93xx_spi_board_info,
152
-
ARRAY_SIZE(edb93xx_spi_board_info));
153
-
}
154
-
155
-
156
-
/*************************************************************************
157
-
* EDB93xx I2S
158
-
*************************************************************************/
159
-
static struct platform_device edb93xx_audio_device = {
160
-
.name = "edb93xx-audio",
161
-
.id = -1,
162
-
};
163
-
164
-
static int __init edb93xx_has_audio(void)
165
-
{
166
-
return (machine_is_edb9301() || machine_is_edb9302() ||
167
-
machine_is_edb9302a() || machine_is_edb9307a() ||
168
-
machine_is_edb9315a());
169
-
}
170
-
171
-
static void __init edb93xx_register_i2s(void)
172
-
{
173
-
if (edb93xx_has_audio()) {
174
-
ep93xx_register_i2s();
175
-
platform_device_register(&edb93xx_audio_device);
176
-
}
177
-
}
178
-
179
-
180
-
/*************************************************************************
181
-
* EDB93xx pwm
182
-
*************************************************************************/
183
-
static void __init edb93xx_register_pwm(void)
184
-
{
185
-
if (machine_is_edb9301() ||
186
-
machine_is_edb9302() || machine_is_edb9302a()) {
187
-
/* EP9301 and EP9302 only have pwm.1 (EGPIO14) */
188
-
ep93xx_register_pwm(0, 1);
189
-
} else if (machine_is_edb9307() || machine_is_edb9307a()) {
190
-
/* EP9307 only has pwm.0 (PWMOUT) */
191
-
ep93xx_register_pwm(1, 0);
192
-
} else {
193
-
/* EP9312 and EP9315 have both */
194
-
ep93xx_register_pwm(1, 1);
195
-
}
196
-
}
197
-
198
-
199
-
/*************************************************************************
200
-
* EDB93xx framebuffer
201
-
*************************************************************************/
202
-
static struct ep93xxfb_mach_info __initdata edb93xxfb_info = {
203
-
.flags = 0,
204
-
};
205
-
206
-
static int __init edb93xx_has_fb(void)
207
-
{
208
-
/* These platforms have an ep93xx with video capability */
209
-
return machine_is_edb9307() || machine_is_edb9307a() ||
210
-
machine_is_edb9312() || machine_is_edb9315() ||
211
-
machine_is_edb9315a();
212
-
}
213
-
214
-
static void __init edb93xx_register_fb(void)
215
-
{
216
-
if (!edb93xx_has_fb())
217
-
return;
218
-
219
-
if (machine_is_edb9307a() || machine_is_edb9315a())
220
-
edb93xxfb_info.flags |= EP93XXFB_USE_SDCSN0;
221
-
else
222
-
edb93xxfb_info.flags |= EP93XXFB_USE_SDCSN3;
223
-
224
-
ep93xx_register_fb(&edb93xxfb_info);
225
-
}
226
-
227
-
228
-
/*************************************************************************
229
-
* EDB93xx IDE
230
-
*************************************************************************/
231
-
static int __init edb93xx_has_ide(void)
232
-
{
233
-
/*
234
-
* Although EDB9312 and EDB9315 do have IDE capability, they have
235
-
* INTRQ line wired as pull-up, which makes using IDE interface
236
-
* problematic.
237
-
*/
238
-
return machine_is_edb9312() || machine_is_edb9315() ||
239
-
machine_is_edb9315a();
240
-
}
241
-
242
-
static void __init edb93xx_register_ide(void)
243
-
{
244
-
if (!edb93xx_has_ide())
245
-
return;
246
-
247
-
ep93xx_register_ide();
248
-
}
249
-
250
-
251
-
static void __init edb93xx_init_machine(void)
252
-
{
253
-
ep93xx_init_devices();
254
-
edb93xx_register_flash();
255
-
ep93xx_register_eth(&edb93xx_eth_data, 1);
256
-
edb93xx_register_i2c();
257
-
edb93xx_register_spi();
258
-
edb93xx_register_i2s();
259
-
edb93xx_register_pwm();
260
-
edb93xx_register_fb();
261
-
edb93xx_register_ide();
262
-
ep93xx_register_adc();
263
-
}
264
-
265
-
266
-
#ifdef CONFIG_MACH_EDB9301
267
-
MACHINE_START(EDB9301, "Cirrus Logic EDB9301 Evaluation Board")
268
-
/* Maintainer: H Hartley Sweeten <hsweeten@visionengravers.com> */
269
-
.atag_offset = 0x100,
270
-
.nr_irqs = NR_EP93XX_IRQS,
271
-
.map_io = ep93xx_map_io,
272
-
.init_irq = ep93xx_init_irq,
273
-
.init_time = ep93xx_timer_init,
274
-
.init_machine = edb93xx_init_machine,
275
-
.restart = ep93xx_restart,
276
-
MACHINE_END
277
-
#endif
278
-
279
-
#ifdef CONFIG_MACH_EDB9302
280
-
MACHINE_START(EDB9302, "Cirrus Logic EDB9302 Evaluation Board")
281
-
/* Maintainer: George Kashperko <george@chas.com.ua> */
282
-
.atag_offset = 0x100,
283
-
.nr_irqs = NR_EP93XX_IRQS,
284
-
.map_io = ep93xx_map_io,
285
-
.init_irq = ep93xx_init_irq,
286
-
.init_time = ep93xx_timer_init,
287
-
.init_machine = edb93xx_init_machine,
288
-
.restart = ep93xx_restart,
289
-
MACHINE_END
290
-
#endif
291
-
292
-
#ifdef CONFIG_MACH_EDB9302A
293
-
MACHINE_START(EDB9302A, "Cirrus Logic EDB9302A Evaluation Board")
294
-
/* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
295
-
.atag_offset = 0x100,
296
-
.nr_irqs = NR_EP93XX_IRQS,
297
-
.map_io = ep93xx_map_io,
298
-
.init_irq = ep93xx_init_irq,
299
-
.init_time = ep93xx_timer_init,
300
-
.init_machine = edb93xx_init_machine,
301
-
.restart = ep93xx_restart,
302
-
MACHINE_END
303
-
#endif
304
-
305
-
#ifdef CONFIG_MACH_EDB9307
306
-
MACHINE_START(EDB9307, "Cirrus Logic EDB9307 Evaluation Board")
307
-
/* Maintainer: Herbert Valerio Riedel <hvr@gnu.org> */
308
-
.atag_offset = 0x100,
309
-
.nr_irqs = NR_EP93XX_IRQS,
310
-
.map_io = ep93xx_map_io,
311
-
.init_irq = ep93xx_init_irq,
312
-
.init_time = ep93xx_timer_init,
313
-
.init_machine = edb93xx_init_machine,
314
-
.restart = ep93xx_restart,
315
-
MACHINE_END
316
-
#endif
317
-
318
-
#ifdef CONFIG_MACH_EDB9307A
319
-
MACHINE_START(EDB9307A, "Cirrus Logic EDB9307A Evaluation Board")
320
-
/* Maintainer: H Hartley Sweeten <hsweeten@visionengravers.com> */
321
-
.atag_offset = 0x100,
322
-
.nr_irqs = NR_EP93XX_IRQS,
323
-
.map_io = ep93xx_map_io,
324
-
.init_irq = ep93xx_init_irq,
325
-
.init_time = ep93xx_timer_init,
326
-
.init_machine = edb93xx_init_machine,
327
-
.restart = ep93xx_restart,
328
-
MACHINE_END
329
-
#endif
330
-
331
-
#ifdef CONFIG_MACH_EDB9312
332
-
MACHINE_START(EDB9312, "Cirrus Logic EDB9312 Evaluation Board")
333
-
/* Maintainer: Toufeeq Hussain <toufeeq_hussain@infosys.com> */
334
-
.atag_offset = 0x100,
335
-
.nr_irqs = NR_EP93XX_IRQS,
336
-
.map_io = ep93xx_map_io,
337
-
.init_irq = ep93xx_init_irq,
338
-
.init_time = ep93xx_timer_init,
339
-
.init_machine = edb93xx_init_machine,
340
-
.restart = ep93xx_restart,
341
-
MACHINE_END
342
-
#endif
343
-
344
-
#ifdef CONFIG_MACH_EDB9315
345
-
MACHINE_START(EDB9315, "Cirrus Logic EDB9315 Evaluation Board")
346
-
/* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
347
-
.atag_offset = 0x100,
348
-
.nr_irqs = NR_EP93XX_IRQS,
349
-
.map_io = ep93xx_map_io,
350
-
.init_irq = ep93xx_init_irq,
351
-
.init_time = ep93xx_timer_init,
352
-
.init_machine = edb93xx_init_machine,
353
-
.restart = ep93xx_restart,
354
-
MACHINE_END
355
-
#endif
356
-
357
-
#ifdef CONFIG_MACH_EDB9315A
358
-
MACHINE_START(EDB9315A, "Cirrus Logic EDB9315A Evaluation Board")
359
-
/* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
360
-
.atag_offset = 0x100,
361
-
.nr_irqs = NR_EP93XX_IRQS,
362
-
.map_io = ep93xx_map_io,
363
-
.init_irq = ep93xx_init_irq,
364
-
.init_time = ep93xx_timer_init,
365
-
.init_machine = edb93xx_init_machine,
366
-
.restart = ep93xx_restart,
367
-
MACHINE_END
368
-
#endif
-38
arch/arm/mach-ep93xx/ep93xx-regs.h
-38
arch/arm/mach-ep93xx/ep93xx-regs.h
···
1
-
/* SPDX-License-Identifier: GPL-2.0 */
2
-
#ifndef __ASM_ARCH_EP93XX_REGS_H
3
-
#define __ASM_ARCH_EP93XX_REGS_H
4
-
5
-
/*
6
-
* EP93xx linux memory map:
7
-
*
8
-
* virt phys size
9
-
* fe800000 5M per-platform mappings
10
-
* fed00000 80800000 2M APB
11
-
* fef00000 80000000 1M AHB
12
-
*/
13
-
14
-
#define EP93XX_AHB_PHYS_BASE 0x80000000
15
-
#define EP93XX_AHB_VIRT_BASE 0xfef00000
16
-
#define EP93XX_AHB_SIZE 0x00100000
17
-
18
-
#define EP93XX_AHB_PHYS(x) (EP93XX_AHB_PHYS_BASE + (x))
19
-
#define EP93XX_AHB_IOMEM(x) IOMEM(EP93XX_AHB_VIRT_BASE + (x))
20
-
21
-
#define EP93XX_APB_PHYS_BASE 0x80800000
22
-
#define EP93XX_APB_VIRT_BASE 0xfed00000
23
-
#define EP93XX_APB_SIZE 0x00200000
24
-
25
-
#define EP93XX_APB_PHYS(x) (EP93XX_APB_PHYS_BASE + (x))
26
-
#define EP93XX_APB_IOMEM(x) IOMEM(EP93XX_APB_VIRT_BASE + (x))
27
-
28
-
/* APB UARTs */
29
-
#define EP93XX_UART1_PHYS_BASE EP93XX_APB_PHYS(0x000c0000)
30
-
#define EP93XX_UART1_BASE EP93XX_APB_IOMEM(0x000c0000)
31
-
32
-
#define EP93XX_UART2_PHYS_BASE EP93XX_APB_PHYS(0x000d0000)
33
-
#define EP93XX_UART2_BASE EP93XX_APB_IOMEM(0x000d0000)
34
-
35
-
#define EP93XX_UART3_PHYS_BASE EP93XX_APB_PHYS(0x000e0000)
36
-
#define EP93XX_UART3_BASE EP93XX_APB_IOMEM(0x000e0000)
37
-
38
-
#endif
-111
arch/arm/mach-ep93xx/gpio-ep93xx.h
-111
arch/arm/mach-ep93xx/gpio-ep93xx.h
···
1
-
/* SPDX-License-Identifier: GPL-2.0 */
2
-
/* Include file for the EP93XX GPIO controller machine specifics */
3
-
4
-
#ifndef __GPIO_EP93XX_H
5
-
#define __GPIO_EP93XX_H
6
-
7
-
#include "ep93xx-regs.h"
8
-
9
-
#define EP93XX_GPIO_PHYS_BASE EP93XX_APB_PHYS(0x00040000)
10
-
#define EP93XX_GPIO_BASE EP93XX_APB_IOMEM(0x00040000)
11
-
#define EP93XX_GPIO_REG(x) (EP93XX_GPIO_BASE + (x))
12
-
#define EP93XX_GPIO_F_INT_STATUS EP93XX_GPIO_REG(0x5c)
13
-
#define EP93XX_GPIO_A_INT_STATUS EP93XX_GPIO_REG(0xa0)
14
-
#define EP93XX_GPIO_B_INT_STATUS EP93XX_GPIO_REG(0xbc)
15
-
#define EP93XX_GPIO_EEDRIVE EP93XX_GPIO_REG(0xc8)
16
-
17
-
/* GPIO port A. */
18
-
#define EP93XX_GPIO_LINE_A(x) ((x) + 0)
19
-
#define EP93XX_GPIO_LINE_EGPIO0 EP93XX_GPIO_LINE_A(0)
20
-
#define EP93XX_GPIO_LINE_EGPIO1 EP93XX_GPIO_LINE_A(1)
21
-
#define EP93XX_GPIO_LINE_EGPIO2 EP93XX_GPIO_LINE_A(2)
22
-
#define EP93XX_GPIO_LINE_EGPIO3 EP93XX_GPIO_LINE_A(3)
23
-
#define EP93XX_GPIO_LINE_EGPIO4 EP93XX_GPIO_LINE_A(4)
24
-
#define EP93XX_GPIO_LINE_EGPIO5 EP93XX_GPIO_LINE_A(5)
25
-
#define EP93XX_GPIO_LINE_EGPIO6 EP93XX_GPIO_LINE_A(6)
26
-
#define EP93XX_GPIO_LINE_EGPIO7 EP93XX_GPIO_LINE_A(7)
27
-
28
-
/* GPIO port B. */
29
-
#define EP93XX_GPIO_LINE_B(x) ((x) + 8)
30
-
#define EP93XX_GPIO_LINE_EGPIO8 EP93XX_GPIO_LINE_B(0)
31
-
#define EP93XX_GPIO_LINE_EGPIO9 EP93XX_GPIO_LINE_B(1)
32
-
#define EP93XX_GPIO_LINE_EGPIO10 EP93XX_GPIO_LINE_B(2)
33
-
#define EP93XX_GPIO_LINE_EGPIO11 EP93XX_GPIO_LINE_B(3)
34
-
#define EP93XX_GPIO_LINE_EGPIO12 EP93XX_GPIO_LINE_B(4)
35
-
#define EP93XX_GPIO_LINE_EGPIO13 EP93XX_GPIO_LINE_B(5)
36
-
#define EP93XX_GPIO_LINE_EGPIO14 EP93XX_GPIO_LINE_B(6)
37
-
#define EP93XX_GPIO_LINE_EGPIO15 EP93XX_GPIO_LINE_B(7)
38
-
39
-
/* GPIO port C. */
40
-
#define EP93XX_GPIO_LINE_C(x) ((x) + 40)
41
-
#define EP93XX_GPIO_LINE_ROW0 EP93XX_GPIO_LINE_C(0)
42
-
#define EP93XX_GPIO_LINE_ROW1 EP93XX_GPIO_LINE_C(1)
43
-
#define EP93XX_GPIO_LINE_ROW2 EP93XX_GPIO_LINE_C(2)
44
-
#define EP93XX_GPIO_LINE_ROW3 EP93XX_GPIO_LINE_C(3)
45
-
#define EP93XX_GPIO_LINE_ROW4 EP93XX_GPIO_LINE_C(4)
46
-
#define EP93XX_GPIO_LINE_ROW5 EP93XX_GPIO_LINE_C(5)
47
-
#define EP93XX_GPIO_LINE_ROW6 EP93XX_GPIO_LINE_C(6)
48
-
#define EP93XX_GPIO_LINE_ROW7 EP93XX_GPIO_LINE_C(7)
49
-
50
-
/* GPIO port D. */
51
-
#define EP93XX_GPIO_LINE_D(x) ((x) + 24)
52
-
#define EP93XX_GPIO_LINE_COL0 EP93XX_GPIO_LINE_D(0)
53
-
#define EP93XX_GPIO_LINE_COL1 EP93XX_GPIO_LINE_D(1)
54
-
#define EP93XX_GPIO_LINE_COL2 EP93XX_GPIO_LINE_D(2)
55
-
#define EP93XX_GPIO_LINE_COL3 EP93XX_GPIO_LINE_D(3)
56
-
#define EP93XX_GPIO_LINE_COL4 EP93XX_GPIO_LINE_D(4)
57
-
#define EP93XX_GPIO_LINE_COL5 EP93XX_GPIO_LINE_D(5)
58
-
#define EP93XX_GPIO_LINE_COL6 EP93XX_GPIO_LINE_D(6)
59
-
#define EP93XX_GPIO_LINE_COL7 EP93XX_GPIO_LINE_D(7)
60
-
61
-
/* GPIO port E. */
62
-
#define EP93XX_GPIO_LINE_E(x) ((x) + 32)
63
-
#define EP93XX_GPIO_LINE_GRLED EP93XX_GPIO_LINE_E(0)
64
-
#define EP93XX_GPIO_LINE_RDLED EP93XX_GPIO_LINE_E(1)
65
-
#define EP93XX_GPIO_LINE_DIORn EP93XX_GPIO_LINE_E(2)
66
-
#define EP93XX_GPIO_LINE_IDECS1n EP93XX_GPIO_LINE_E(3)
67
-
#define EP93XX_GPIO_LINE_IDECS2n EP93XX_GPIO_LINE_E(4)
68
-
#define EP93XX_GPIO_LINE_IDEDA0 EP93XX_GPIO_LINE_E(5)
69
-
#define EP93XX_GPIO_LINE_IDEDA1 EP93XX_GPIO_LINE_E(6)
70
-
#define EP93XX_GPIO_LINE_IDEDA2 EP93XX_GPIO_LINE_E(7)
71
-
72
-
/* GPIO port F. */
73
-
#define EP93XX_GPIO_LINE_F(x) ((x) + 16)
74
-
#define EP93XX_GPIO_LINE_WP EP93XX_GPIO_LINE_F(0)
75
-
#define EP93XX_GPIO_LINE_MCCD1 EP93XX_GPIO_LINE_F(1)
76
-
#define EP93XX_GPIO_LINE_MCCD2 EP93XX_GPIO_LINE_F(2)
77
-
#define EP93XX_GPIO_LINE_MCBVD1 EP93XX_GPIO_LINE_F(3)
78
-
#define EP93XX_GPIO_LINE_MCBVD2 EP93XX_GPIO_LINE_F(4)
79
-
#define EP93XX_GPIO_LINE_VS1 EP93XX_GPIO_LINE_F(5)
80
-
#define EP93XX_GPIO_LINE_READY EP93XX_GPIO_LINE_F(6)
81
-
#define EP93XX_GPIO_LINE_VS2 EP93XX_GPIO_LINE_F(7)
82
-
83
-
/* GPIO port G. */
84
-
#define EP93XX_GPIO_LINE_G(x) ((x) + 48)
85
-
#define EP93XX_GPIO_LINE_EECLK EP93XX_GPIO_LINE_G(0)
86
-
#define EP93XX_GPIO_LINE_EEDAT EP93XX_GPIO_LINE_G(1)
87
-
#define EP93XX_GPIO_LINE_SLA0 EP93XX_GPIO_LINE_G(2)
88
-
#define EP93XX_GPIO_LINE_SLA1 EP93XX_GPIO_LINE_G(3)
89
-
#define EP93XX_GPIO_LINE_DD12 EP93XX_GPIO_LINE_G(4)
90
-
#define EP93XX_GPIO_LINE_DD13 EP93XX_GPIO_LINE_G(5)
91
-
#define EP93XX_GPIO_LINE_DD14 EP93XX_GPIO_LINE_G(6)
92
-
#define EP93XX_GPIO_LINE_DD15 EP93XX_GPIO_LINE_G(7)
93
-
94
-
/* GPIO port H. */
95
-
#define EP93XX_GPIO_LINE_H(x) ((x) + 56)
96
-
#define EP93XX_GPIO_LINE_DD0 EP93XX_GPIO_LINE_H(0)
97
-
#define EP93XX_GPIO_LINE_DD1 EP93XX_GPIO_LINE_H(1)
98
-
#define EP93XX_GPIO_LINE_DD2 EP93XX_GPIO_LINE_H(2)
99
-
#define EP93XX_GPIO_LINE_DD3 EP93XX_GPIO_LINE_H(3)
100
-
#define EP93XX_GPIO_LINE_DD4 EP93XX_GPIO_LINE_H(4)
101
-
#define EP93XX_GPIO_LINE_DD5 EP93XX_GPIO_LINE_H(5)
102
-
#define EP93XX_GPIO_LINE_DD6 EP93XX_GPIO_LINE_H(6)
103
-
#define EP93XX_GPIO_LINE_DD7 EP93XX_GPIO_LINE_H(7)
104
-
105
-
/* maximum value for gpio line identifiers */
106
-
#define EP93XX_GPIO_LINE_MAX EP93XX_GPIO_LINE_H(7)
107
-
108
-
/* maximum value for irq capable line identifiers */
109
-
#define EP93XX_GPIO_LINE_MAX_IRQ EP93XX_GPIO_LINE_F(7)
110
-
111
-
#endif /* __GPIO_EP93XX_H */
-25
arch/arm/mach-ep93xx/hardware.h
-25
arch/arm/mach-ep93xx/hardware.h
···
1
-
/* SPDX-License-Identifier: GPL-2.0 */
2
-
/*
3
-
* arch/arm/mach-ep93xx/include/mach/hardware.h
4
-
*/
5
-
6
-
#ifndef __ASM_ARCH_HARDWARE_H
7
-
#define __ASM_ARCH_HARDWARE_H
8
-
9
-
#include "platform.h"
10
-
11
-
/*
12
-
* The EP93xx has two external crystal oscillators. To generate the
13
-
* required high-frequency clocks, the processor uses two phase-locked-
14
-
* loops (PLLs) to multiply the incoming external clock signal to much
15
-
* higher frequencies that are then divided down by programmable dividers
16
-
* to produce the needed clocks. The PLLs operate independently of one
17
-
* another.
18
-
*/
19
-
#define EP93XX_EXT_CLK_RATE 14745600
20
-
#define EP93XX_EXT_RTC_RATE 32768
21
-
22
-
#define EP93XX_KEYTCHCLK_DIV4 (EP93XX_EXT_CLK_RATE / 4)
23
-
#define EP93XX_KEYTCHCLK_DIV16 (EP93XX_EXT_CLK_RATE / 16)
24
-
25
-
#endif
-76
arch/arm/mach-ep93xx/irqs.h
-76
arch/arm/mach-ep93xx/irqs.h
···
1
-
/* SPDX-License-Identifier: GPL-2.0 */
2
-
#ifndef __ASM_ARCH_IRQS_H
3
-
#define __ASM_ARCH_IRQS_H
4
-
5
-
#define IRQ_EP93XX_VIC0 1
6
-
7
-
#define IRQ_EP93XX_COMMRX (IRQ_EP93XX_VIC0 + 2)
8
-
#define IRQ_EP93XX_COMMTX (IRQ_EP93XX_VIC0 + 3)
9
-
#define IRQ_EP93XX_TIMER1 (IRQ_EP93XX_VIC0 + 4)
10
-
#define IRQ_EP93XX_TIMER2 (IRQ_EP93XX_VIC0 + 5)
11
-
#define IRQ_EP93XX_AACINTR (IRQ_EP93XX_VIC0 + 6)
12
-
#define IRQ_EP93XX_DMAM2P0 (IRQ_EP93XX_VIC0 + 7)
13
-
#define IRQ_EP93XX_DMAM2P1 (IRQ_EP93XX_VIC0 + 8)
14
-
#define IRQ_EP93XX_DMAM2P2 (IRQ_EP93XX_VIC0 + 9)
15
-
#define IRQ_EP93XX_DMAM2P3 (IRQ_EP93XX_VIC0 + 10)
16
-
#define IRQ_EP93XX_DMAM2P4 (IRQ_EP93XX_VIC0 + 11)
17
-
#define IRQ_EP93XX_DMAM2P5 (IRQ_EP93XX_VIC0 + 12)
18
-
#define IRQ_EP93XX_DMAM2P6 (IRQ_EP93XX_VIC0 + 13)
19
-
#define IRQ_EP93XX_DMAM2P7 (IRQ_EP93XX_VIC0 + 14)
20
-
#define IRQ_EP93XX_DMAM2P8 (IRQ_EP93XX_VIC0 + 15)
21
-
#define IRQ_EP93XX_DMAM2P9 (IRQ_EP93XX_VIC0 + 16)
22
-
#define IRQ_EP93XX_DMAM2M0 (IRQ_EP93XX_VIC0 + 17)
23
-
#define IRQ_EP93XX_DMAM2M1 (IRQ_EP93XX_VIC0 + 18)
24
-
#define IRQ_EP93XX_GPIO0MUX (IRQ_EP93XX_VIC0 + 19)
25
-
#define IRQ_EP93XX_GPIO1MUX (IRQ_EP93XX_VIC0 + 20)
26
-
#define IRQ_EP93XX_GPIO2MUX (IRQ_EP93XX_VIC0 + 21)
27
-
#define IRQ_EP93XX_GPIO3MUX (IRQ_EP93XX_VIC0 + 22)
28
-
#define IRQ_EP93XX_UART1RX (IRQ_EP93XX_VIC0 + 23)
29
-
#define IRQ_EP93XX_UART1TX (IRQ_EP93XX_VIC0 + 24)
30
-
#define IRQ_EP93XX_UART2RX (IRQ_EP93XX_VIC0 + 25)
31
-
#define IRQ_EP93XX_UART2TX (IRQ_EP93XX_VIC0 + 26)
32
-
#define IRQ_EP93XX_UART3RX (IRQ_EP93XX_VIC0 + 27)
33
-
#define IRQ_EP93XX_UART3TX (IRQ_EP93XX_VIC0 + 28)
34
-
#define IRQ_EP93XX_KEY (IRQ_EP93XX_VIC0 + 29)
35
-
#define IRQ_EP93XX_TOUCH (IRQ_EP93XX_VIC0 + 30)
36
-
#define EP93XX_VIC1_VALID_IRQ_MASK 0x7ffffffc
37
-
38
-
#define IRQ_EP93XX_VIC1 (IRQ_EP93XX_VIC0 + 32)
39
-
40
-
#define IRQ_EP93XX_EXT0 (IRQ_EP93XX_VIC1 + 0)
41
-
#define IRQ_EP93XX_EXT1 (IRQ_EP93XX_VIC1 + 1)
42
-
#define IRQ_EP93XX_EXT2 (IRQ_EP93XX_VIC1 + 2)
43
-
#define IRQ_EP93XX_64HZ (IRQ_EP93XX_VIC1 + 3)
44
-
#define IRQ_EP93XX_WATCHDOG (IRQ_EP93XX_VIC1 + 4)
45
-
#define IRQ_EP93XX_RTC (IRQ_EP93XX_VIC1 + 5)
46
-
#define IRQ_EP93XX_IRDA (IRQ_EP93XX_VIC1 + 6)
47
-
#define IRQ_EP93XX_ETHERNET (IRQ_EP93XX_VIC1 + 7)
48
-
#define IRQ_EP93XX_EXT3 (IRQ_EP93XX_VIC1 + 8)
49
-
#define IRQ_EP93XX_PROG (IRQ_EP93XX_VIC1 + 9)
50
-
#define IRQ_EP93XX_1HZ (IRQ_EP93XX_VIC1 + 10)
51
-
#define IRQ_EP93XX_VSYNC (IRQ_EP93XX_VIC1 + 11)
52
-
#define IRQ_EP93XX_VIDEO_FIFO (IRQ_EP93XX_VIC1 + 12)
53
-
#define IRQ_EP93XX_SSP1RX (IRQ_EP93XX_VIC1 + 13)
54
-
#define IRQ_EP93XX_SSP1TX (IRQ_EP93XX_VIC1 + 14)
55
-
#define IRQ_EP93XX_GPIO4MUX (IRQ_EP93XX_VIC1 + 15)
56
-
#define IRQ_EP93XX_GPIO5MUX (IRQ_EP93XX_VIC1 + 16)
57
-
#define IRQ_EP93XX_GPIO6MUX (IRQ_EP93XX_VIC1 + 17)
58
-
#define IRQ_EP93XX_GPIO7MUX (IRQ_EP93XX_VIC1 + 18)
59
-
#define IRQ_EP93XX_TIMER3 (IRQ_EP93XX_VIC1 + 19)
60
-
#define IRQ_EP93XX_UART1 (IRQ_EP93XX_VIC1 + 20)
61
-
#define IRQ_EP93XX_SSP (IRQ_EP93XX_VIC1 + 21)
62
-
#define IRQ_EP93XX_UART2 (IRQ_EP93XX_VIC1 + 22)
63
-
#define IRQ_EP93XX_UART3 (IRQ_EP93XX_VIC1 + 23)
64
-
#define IRQ_EP93XX_USB (IRQ_EP93XX_VIC1 + 24)
65
-
#define IRQ_EP93XX_ETHERNET_PME (IRQ_EP93XX_VIC1 + 25)
66
-
#define IRQ_EP93XX_DSP (IRQ_EP93XX_VIC1 + 26)
67
-
#define IRQ_EP93XX_GPIO_AB (IRQ_EP93XX_VIC1 + 27)
68
-
#define IRQ_EP93XX_SAI (IRQ_EP93XX_VIC1 + 28)
69
-
#define EP93XX_VIC2_VALID_IRQ_MASK 0x1fffffff
70
-
71
-
#define NR_EP93XX_IRQS (IRQ_EP93XX_VIC1 + 32 + 24)
72
-
73
-
#define EP93XX_BOARD_IRQ(x) (NR_EP93XX_IRQS + (x))
74
-
#define EP93XX_BOARD_IRQS 32
75
-
76
-
#endif
-42
arch/arm/mach-ep93xx/platform.h
-42
arch/arm/mach-ep93xx/platform.h
···
1
-
/* SPDX-License-Identifier: GPL-2.0 */
2
-
/*
3
-
* arch/arm/mach-ep93xx/include/mach/platform.h
4
-
*/
5
-
6
-
#ifndef __ASSEMBLY__
7
-
8
-
#include <linux/platform_data/eth-ep93xx.h>
9
-
#include <linux/reboot.h>
10
-
11
-
struct device;
12
-
struct i2c_board_info;
13
-
struct spi_board_info;
14
-
struct platform_device;
15
-
struct ep93xxfb_mach_info;
16
-
struct ep93xx_keypad_platform_data;
17
-
struct ep93xx_spi_info;
18
-
19
-
void ep93xx_map_io(void);
20
-
void ep93xx_init_irq(void);
21
-
22
-
void ep93xx_register_flash(unsigned int width,
23
-
resource_size_t start, resource_size_t size);
24
-
25
-
void ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_addr);
26
-
void ep93xx_register_i2c(struct i2c_board_info *devices, int num);
27
-
void ep93xx_register_spi(struct ep93xx_spi_info *info,
28
-
struct spi_board_info *devices, int num);
29
-
void ep93xx_register_fb(struct ep93xxfb_mach_info *data);
30
-
void ep93xx_register_pwm(int pwm0, int pwm1);
31
-
void ep93xx_register_keypad(struct ep93xx_keypad_platform_data *data);
32
-
void ep93xx_register_i2s(void);
33
-
void ep93xx_register_ac97(void);
34
-
void ep93xx_register_ide(void);
35
-
void ep93xx_register_adc(void);
36
-
37
-
struct device *ep93xx_init_devices(void);
38
-
extern void ep93xx_timer_init(void);
39
-
40
-
void ep93xx_restart(enum reboot_mode, const char *);
41
-
42
-
#endif
-212
arch/arm/mach-ep93xx/soc.h
-212
arch/arm/mach-ep93xx/soc.h
···
1
-
/* SPDX-License-Identifier: GPL-2.0-or-later */
2
-
/*
3
-
* arch/arm/mach-ep93xx/soc.h
4
-
*
5
-
* Copyright (C) 2012 Open Kernel Labs <www.ok-labs.com>
6
-
* Copyright (C) 2012 Ryan Mallon <rmallon@gmail.com>
7
-
*/
8
-
9
-
#ifndef _EP93XX_SOC_H
10
-
#define _EP93XX_SOC_H
11
-
12
-
#include "ep93xx-regs.h"
13
-
#include "irqs.h"
14
-
15
-
/*
16
-
* EP93xx Physical Memory Map:
17
-
*
18
-
* The ASDO pin is sampled at system reset to select a synchronous or
19
-
* asynchronous boot configuration. When ASDO is "1" (i.e. pulled-up)
20
-
* the synchronous boot mode is selected. When ASDO is "0" (i.e
21
-
* pulled-down) the asynchronous boot mode is selected.
22
-
*
23
-
* In synchronous boot mode nSDCE3 is decoded starting at physical address
24
-
* 0x00000000 and nCS0 is decoded starting at 0xf0000000. For asynchronous
25
-
* boot mode they are swapped with nCS0 decoded at 0x00000000 ann nSDCE3
26
-
* decoded at 0xf0000000.
27
-
*
28
-
* There is known errata for the EP93xx dealing with External Memory
29
-
* Configurations. Please refer to "AN273: EP93xx Silicon Rev E Design
30
-
* Guidelines" for more information. This document can be found at:
31
-
*
32
-
* http://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf
33
-
*/
34
-
35
-
#define EP93XX_CS0_PHYS_BASE_ASYNC 0x00000000 /* ASDO Pin = 0 */
36
-
#define EP93XX_SDCE3_PHYS_BASE_SYNC 0x00000000 /* ASDO Pin = 1 */
37
-
#define EP93XX_CS1_PHYS_BASE 0x10000000
38
-
#define EP93XX_CS2_PHYS_BASE 0x20000000
39
-
#define EP93XX_CS3_PHYS_BASE 0x30000000
40
-
#define EP93XX_PCMCIA_PHYS_BASE 0x40000000
41
-
#define EP93XX_CS6_PHYS_BASE 0x60000000
42
-
#define EP93XX_CS7_PHYS_BASE 0x70000000
43
-
#define EP93XX_SDCE0_PHYS_BASE 0xc0000000
44
-
#define EP93XX_SDCE1_PHYS_BASE 0xd0000000
45
-
#define EP93XX_SDCE2_PHYS_BASE 0xe0000000
46
-
#define EP93XX_SDCE3_PHYS_BASE_ASYNC 0xf0000000 /* ASDO Pin = 0 */
47
-
#define EP93XX_CS0_PHYS_BASE_SYNC 0xf0000000 /* ASDO Pin = 1 */
48
-
49
-
/* AHB peripherals */
50
-
#define EP93XX_DMA_BASE EP93XX_AHB_IOMEM(0x00000000)
51
-
52
-
#define EP93XX_ETHERNET_PHYS_BASE EP93XX_AHB_PHYS(0x00010000)
53
-
#define EP93XX_ETHERNET_BASE EP93XX_AHB_IOMEM(0x00010000)
54
-
55
-
#define EP93XX_USB_PHYS_BASE EP93XX_AHB_PHYS(0x00020000)
56
-
#define EP93XX_USB_BASE EP93XX_AHB_IOMEM(0x00020000)
57
-
58
-
#define EP93XX_RASTER_PHYS_BASE EP93XX_AHB_PHYS(0x00030000)
59
-
#define EP93XX_RASTER_BASE EP93XX_AHB_IOMEM(0x00030000)
60
-
61
-
#define EP93XX_GRAPHICS_ACCEL_BASE EP93XX_AHB_IOMEM(0x00040000)
62
-
63
-
#define EP93XX_SDRAM_CONTROLLER_BASE EP93XX_AHB_IOMEM(0x00060000)
64
-
65
-
#define EP93XX_PCMCIA_CONTROLLER_BASE EP93XX_AHB_IOMEM(0x00080000)
66
-
67
-
#define EP93XX_BOOT_ROM_BASE EP93XX_AHB_IOMEM(0x00090000)
68
-
69
-
#define EP93XX_IDE_PHYS_BASE EP93XX_AHB_PHYS(0x000a0000)
70
-
#define EP93XX_IDE_BASE EP93XX_AHB_IOMEM(0x000a0000)
71
-
72
-
#define EP93XX_VIC1_BASE EP93XX_AHB_IOMEM(0x000b0000)
73
-
74
-
#define EP93XX_VIC2_BASE EP93XX_AHB_IOMEM(0x000c0000)
75
-
76
-
/* APB peripherals */
77
-
#define EP93XX_TIMER_BASE EP93XX_APB_IOMEM(0x00010000)
78
-
79
-
#define EP93XX_I2S_PHYS_BASE EP93XX_APB_PHYS(0x00020000)
80
-
#define EP93XX_I2S_BASE EP93XX_APB_IOMEM(0x00020000)
81
-
82
-
#define EP93XX_SECURITY_BASE EP93XX_APB_IOMEM(0x00030000)
83
-
84
-
#define EP93XX_AAC_PHYS_BASE EP93XX_APB_PHYS(0x00080000)
85
-
#define EP93XX_AAC_BASE EP93XX_APB_IOMEM(0x00080000)
86
-
87
-
#define EP93XX_SPI_PHYS_BASE EP93XX_APB_PHYS(0x000a0000)
88
-
#define EP93XX_SPI_BASE EP93XX_APB_IOMEM(0x000a0000)
89
-
90
-
#define EP93XX_IRDA_BASE EP93XX_APB_IOMEM(0x000b0000)
91
-
92
-
#define EP93XX_KEY_MATRIX_PHYS_BASE EP93XX_APB_PHYS(0x000f0000)
93
-
#define EP93XX_KEY_MATRIX_BASE EP93XX_APB_IOMEM(0x000f0000)
94
-
95
-
#define EP93XX_ADC_PHYS_BASE EP93XX_APB_PHYS(0x00100000)
96
-
#define EP93XX_ADC_BASE EP93XX_APB_IOMEM(0x00100000)
97
-
#define EP93XX_TOUCHSCREEN_BASE EP93XX_APB_IOMEM(0x00100000)
98
-
99
-
#define EP93XX_PWM_PHYS_BASE EP93XX_APB_PHYS(0x00110000)
100
-
#define EP93XX_PWM_BASE EP93XX_APB_IOMEM(0x00110000)
101
-
102
-
#define EP93XX_RTC_PHYS_BASE EP93XX_APB_PHYS(0x00120000)
103
-
#define EP93XX_RTC_BASE EP93XX_APB_IOMEM(0x00120000)
104
-
105
-
#define EP93XX_WATCHDOG_PHYS_BASE EP93XX_APB_PHYS(0x00140000)
106
-
#define EP93XX_WATCHDOG_BASE EP93XX_APB_IOMEM(0x00140000)
107
-
108
-
/* System controller */
109
-
#define EP93XX_SYSCON_BASE EP93XX_APB_IOMEM(0x00130000)
110
-
#define EP93XX_SYSCON_REG(x) (EP93XX_SYSCON_BASE + (x))
111
-
#define EP93XX_SYSCON_POWER_STATE EP93XX_SYSCON_REG(0x00)
112
-
#define EP93XX_SYSCON_PWRCNT EP93XX_SYSCON_REG(0x04)
113
-
#define EP93XX_SYSCON_PWRCNT_FIR_EN (1<<31)
114
-
#define EP93XX_SYSCON_PWRCNT_UARTBAUD (1<<29)
115
-
#define EP93XX_SYSCON_PWRCNT_USH_EN 28
116
-
#define EP93XX_SYSCON_PWRCNT_DMA_M2M1 27
117
-
#define EP93XX_SYSCON_PWRCNT_DMA_M2M0 26
118
-
#define EP93XX_SYSCON_PWRCNT_DMA_M2P8 25
119
-
#define EP93XX_SYSCON_PWRCNT_DMA_M2P9 24
120
-
#define EP93XX_SYSCON_PWRCNT_DMA_M2P6 23
121
-
#define EP93XX_SYSCON_PWRCNT_DMA_M2P7 22
122
-
#define EP93XX_SYSCON_PWRCNT_DMA_M2P4 21
123
-
#define EP93XX_SYSCON_PWRCNT_DMA_M2P5 20
124
-
#define EP93XX_SYSCON_PWRCNT_DMA_M2P2 19
125
-
#define EP93XX_SYSCON_PWRCNT_DMA_M2P3 18
126
-
#define EP93XX_SYSCON_PWRCNT_DMA_M2P0 17
127
-
#define EP93XX_SYSCON_PWRCNT_DMA_M2P1 16
128
-
#define EP93XX_SYSCON_HALT EP93XX_SYSCON_REG(0x08)
129
-
#define EP93XX_SYSCON_STANDBY EP93XX_SYSCON_REG(0x0c)
130
-
#define EP93XX_SYSCON_CLKSET1 EP93XX_SYSCON_REG(0x20)
131
-
#define EP93XX_SYSCON_CLKSET1_NBYP1 (1<<23)
132
-
#define EP93XX_SYSCON_CLKSET2 EP93XX_SYSCON_REG(0x24)
133
-
#define EP93XX_SYSCON_CLKSET2_NBYP2 (1<<19)
134
-
#define EP93XX_SYSCON_CLKSET2_PLL2_EN (1<<18)
135
-
#define EP93XX_SYSCON_DEVCFG EP93XX_SYSCON_REG(0x80)
136
-
#define EP93XX_SYSCON_DEVCFG_SWRST (1<<31)
137
-
#define EP93XX_SYSCON_DEVCFG_D1ONG (1<<30)
138
-
#define EP93XX_SYSCON_DEVCFG_D0ONG (1<<29)
139
-
#define EP93XX_SYSCON_DEVCFG_IONU2 (1<<28)
140
-
#define EP93XX_SYSCON_DEVCFG_GONK (1<<27)
141
-
#define EP93XX_SYSCON_DEVCFG_TONG (1<<26)
142
-
#define EP93XX_SYSCON_DEVCFG_MONG (1<<25)
143
-
#define EP93XX_SYSCON_DEVCFG_U3EN 24
144
-
#define EP93XX_SYSCON_DEVCFG_CPENA (1<<23)
145
-
#define EP93XX_SYSCON_DEVCFG_A2ONG (1<<22)
146
-
#define EP93XX_SYSCON_DEVCFG_A1ONG (1<<21)
147
-
#define EP93XX_SYSCON_DEVCFG_U2EN 20
148
-
#define EP93XX_SYSCON_DEVCFG_EXVC (1<<19)
149
-
#define EP93XX_SYSCON_DEVCFG_U1EN 18
150
-
#define EP93XX_SYSCON_DEVCFG_TIN (1<<17)
151
-
#define EP93XX_SYSCON_DEVCFG_HC3IN (1<<15)
152
-
#define EP93XX_SYSCON_DEVCFG_HC3EN (1<<14)
153
-
#define EP93XX_SYSCON_DEVCFG_HC1IN (1<<13)
154
-
#define EP93XX_SYSCON_DEVCFG_HC1EN (1<<12)
155
-
#define EP93XX_SYSCON_DEVCFG_HONIDE (1<<11)
156
-
#define EP93XX_SYSCON_DEVCFG_GONIDE (1<<10)
157
-
#define EP93XX_SYSCON_DEVCFG_PONG (1<<9)
158
-
#define EP93XX_SYSCON_DEVCFG_EONIDE (1<<8)
159
-
#define EP93XX_SYSCON_DEVCFG_I2SONSSP (1<<7)
160
-
#define EP93XX_SYSCON_DEVCFG_I2SONAC97 (1<<6)
161
-
#define EP93XX_SYSCON_DEVCFG_RASONP3 (1<<4)
162
-
#define EP93XX_SYSCON_DEVCFG_RAS (1<<3)
163
-
#define EP93XX_SYSCON_DEVCFG_ADCPD (1<<2)
164
-
#define EP93XX_SYSCON_DEVCFG_KEYS (1<<1)
165
-
#define EP93XX_SYSCON_DEVCFG_SHENA (1<<0)
166
-
#define EP93XX_SYSCON_VIDCLKDIV EP93XX_SYSCON_REG(0x84)
167
-
#define EP93XX_SYSCON_CLKDIV_ENABLE 15
168
-
#define EP93XX_SYSCON_CLKDIV_ESEL (1<<14)
169
-
#define EP93XX_SYSCON_CLKDIV_PSEL (1<<13)
170
-
#define EP93XX_SYSCON_CLKDIV_PDIV_SHIFT 8
171
-
#define EP93XX_SYSCON_I2SCLKDIV EP93XX_SYSCON_REG(0x8c)
172
-
#define EP93XX_SYSCON_I2SCLKDIV_SENA 31
173
-
#define EP93XX_SYSCON_I2SCLKDIV_ORIDE (1<<29)
174
-
#define EP93XX_SYSCON_I2SCLKDIV_SPOL (1<<19)
175
-
#define EP93XX_I2SCLKDIV_SDIV (1 << 16)
176
-
#define EP93XX_I2SCLKDIV_LRDIV32 (0 << 17)
177
-
#define EP93XX_I2SCLKDIV_LRDIV64 (1 << 17)
178
-
#define EP93XX_I2SCLKDIV_LRDIV128 (2 << 17)
179
-
#define EP93XX_I2SCLKDIV_LRDIV_MASK (3 << 17)
180
-
#define EP93XX_SYSCON_KEYTCHCLKDIV EP93XX_SYSCON_REG(0x90)
181
-
#define EP93XX_SYSCON_KEYTCHCLKDIV_TSEN 31
182
-
#define EP93XX_SYSCON_KEYTCHCLKDIV_ADIV 16
183
-
#define EP93XX_SYSCON_KEYTCHCLKDIV_KEN 15
184
-
#define EP93XX_SYSCON_KEYTCHCLKDIV_KDIV (1<<0)
185
-
#define EP93XX_SYSCON_SYSCFG EP93XX_SYSCON_REG(0x9c)
186
-
#define EP93XX_SYSCON_SYSCFG_REV_MASK (0xf0000000)
187
-
#define EP93XX_SYSCON_SYSCFG_REV_SHIFT (28)
188
-
#define EP93XX_SYSCON_SYSCFG_SBOOT (1<<8)
189
-
#define EP93XX_SYSCON_SYSCFG_LCSN7 (1<<7)
190
-
#define EP93XX_SYSCON_SYSCFG_LCSN6 (1<<6)
191
-
#define EP93XX_SYSCON_SYSCFG_LASDO (1<<5)
192
-
#define EP93XX_SYSCON_SYSCFG_LEEDA (1<<4)
193
-
#define EP93XX_SYSCON_SYSCFG_LEECLK (1<<3)
194
-
#define EP93XX_SYSCON_SYSCFG_LCSN2 (1<<1)
195
-
#define EP93XX_SYSCON_SYSCFG_LCSN1 (1<<0)
196
-
#define EP93XX_SYSCON_SWLOCK EP93XX_SYSCON_REG(0xc0)
197
-
198
-
/* EP93xx System Controller software locked register write */
199
-
void ep93xx_syscon_swlocked_write(unsigned int val, void __iomem *reg);
200
-
void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits);
201
-
202
-
static inline void ep93xx_devcfg_set_bits(unsigned int bits)
203
-
{
204
-
ep93xx_devcfg_set_clear(bits, 0x00);
205
-
}
206
-
207
-
static inline void ep93xx_devcfg_clear_bits(unsigned int bits)
208
-
{
209
-
ep93xx_devcfg_set_clear(0x00, bits);
210
-
}
211
-
212
-
#endif /* _EP93XX_SOC_H */
-143
arch/arm/mach-ep93xx/timer-ep93xx.c
-143
arch/arm/mach-ep93xx/timer-ep93xx.c
···
1
-
// SPDX-License-Identifier: GPL-2.0
2
-
#include <linux/kernel.h>
3
-
#include <linux/init.h>
4
-
#include <linux/clocksource.h>
5
-
#include <linux/clockchips.h>
6
-
#include <linux/sched_clock.h>
7
-
#include <linux/interrupt.h>
8
-
#include <linux/irq.h>
9
-
#include <linux/io.h>
10
-
#include <asm/mach/time.h>
11
-
#include "soc.h"
12
-
#include "platform.h"
13
-
14
-
/*************************************************************************
15
-
* Timer handling for EP93xx
16
-
*************************************************************************
17
-
* The ep93xx has four internal timers. Timers 1, 2 (both 16 bit) and
18
-
* 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate
19
-
* an interrupt on underflow. Timer 4 (40 bit) counts down at 983.04 kHz,
20
-
* is free-running, and can't generate interrupts.
21
-
*
22
-
* The 508 kHz timers are ideal for use for the timer interrupt, as the
23
-
* most common values of HZ divide 508 kHz nicely. We pick the 32 bit
24
-
* timer (timer 3) to get as long sleep intervals as possible when using
25
-
* CONFIG_NO_HZ.
26
-
*
27
-
* The higher clock rate of timer 4 makes it a better choice than the
28
-
* other timers for use as clock source and for sched_clock(), providing
29
-
* a stable 40 bit time base.
30
-
*************************************************************************
31
-
*/
32
-
#define EP93XX_TIMER_REG(x) (EP93XX_TIMER_BASE + (x))
33
-
#define EP93XX_TIMER1_LOAD EP93XX_TIMER_REG(0x00)
34
-
#define EP93XX_TIMER1_VALUE EP93XX_TIMER_REG(0x04)
35
-
#define EP93XX_TIMER1_CONTROL EP93XX_TIMER_REG(0x08)
36
-
#define EP93XX_TIMER123_CONTROL_ENABLE (1 << 7)
37
-
#define EP93XX_TIMER123_CONTROL_MODE (1 << 6)
38
-
#define EP93XX_TIMER123_CONTROL_CLKSEL (1 << 3)
39
-
#define EP93XX_TIMER1_CLEAR EP93XX_TIMER_REG(0x0c)
40
-
#define EP93XX_TIMER2_LOAD EP93XX_TIMER_REG(0x20)
41
-
#define EP93XX_TIMER2_VALUE EP93XX_TIMER_REG(0x24)
42
-
#define EP93XX_TIMER2_CONTROL EP93XX_TIMER_REG(0x28)
43
-
#define EP93XX_TIMER2_CLEAR EP93XX_TIMER_REG(0x2c)
44
-
#define EP93XX_TIMER4_VALUE_LOW EP93XX_TIMER_REG(0x60)
45
-
#define EP93XX_TIMER4_VALUE_HIGH EP93XX_TIMER_REG(0x64)
46
-
#define EP93XX_TIMER4_VALUE_HIGH_ENABLE (1 << 8)
47
-
#define EP93XX_TIMER3_LOAD EP93XX_TIMER_REG(0x80)
48
-
#define EP93XX_TIMER3_VALUE EP93XX_TIMER_REG(0x84)
49
-
#define EP93XX_TIMER3_CONTROL EP93XX_TIMER_REG(0x88)
50
-
#define EP93XX_TIMER3_CLEAR EP93XX_TIMER_REG(0x8c)
51
-
52
-
#define EP93XX_TIMER123_RATE 508469
53
-
#define EP93XX_TIMER4_RATE 983040
54
-
55
-
static u64 notrace ep93xx_read_sched_clock(void)
56
-
{
57
-
u64 ret;
58
-
59
-
ret = readl(EP93XX_TIMER4_VALUE_LOW);
60
-
ret |= ((u64) (readl(EP93XX_TIMER4_VALUE_HIGH) & 0xff) << 32);
61
-
return ret;
62
-
}
63
-
64
-
static u64 ep93xx_clocksource_read(struct clocksource *c)
65
-
{
66
-
u64 ret;
67
-
68
-
ret = readl(EP93XX_TIMER4_VALUE_LOW);
69
-
ret |= ((u64) (readl(EP93XX_TIMER4_VALUE_HIGH) & 0xff) << 32);
70
-
return (u64) ret;
71
-
}
72
-
73
-
static int ep93xx_clkevt_set_next_event(unsigned long next,
74
-
struct clock_event_device *evt)
75
-
{
76
-
/* Default mode: periodic, off, 508 kHz */
77
-
u32 tmode = EP93XX_TIMER123_CONTROL_MODE |
78
-
EP93XX_TIMER123_CONTROL_CLKSEL;
79
-
80
-
/* Clear timer */
81
-
writel(tmode, EP93XX_TIMER3_CONTROL);
82
-
83
-
/* Set next event */
84
-
writel(next, EP93XX_TIMER3_LOAD);
85
-
writel(tmode | EP93XX_TIMER123_CONTROL_ENABLE,
86
-
EP93XX_TIMER3_CONTROL);
87
-
return 0;
88
-
}
89
-
90
-
91
-
static int ep93xx_clkevt_shutdown(struct clock_event_device *evt)
92
-
{
93
-
/* Disable timer */
94
-
writel(0, EP93XX_TIMER3_CONTROL);
95
-
96
-
return 0;
97
-
}
98
-
99
-
static struct clock_event_device ep93xx_clockevent = {
100
-
.name = "timer1",
101
-
.features = CLOCK_EVT_FEAT_ONESHOT,
102
-
.set_state_shutdown = ep93xx_clkevt_shutdown,
103
-
.set_state_oneshot = ep93xx_clkevt_shutdown,
104
-
.tick_resume = ep93xx_clkevt_shutdown,
105
-
.set_next_event = ep93xx_clkevt_set_next_event,
106
-
.rating = 300,
107
-
};
108
-
109
-
static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id)
110
-
{
111
-
struct clock_event_device *evt = dev_id;
112
-
113
-
/* Writing any value clears the timer interrupt */
114
-
writel(1, EP93XX_TIMER3_CLEAR);
115
-
116
-
evt->event_handler(evt);
117
-
118
-
return IRQ_HANDLED;
119
-
}
120
-
121
-
void __init ep93xx_timer_init(void)
122
-
{
123
-
int irq = IRQ_EP93XX_TIMER3;
124
-
unsigned long flags = IRQF_TIMER | IRQF_IRQPOLL;
125
-
126
-
/* Enable and register clocksource and sched_clock on timer 4 */
127
-
writel(EP93XX_TIMER4_VALUE_HIGH_ENABLE,
128
-
EP93XX_TIMER4_VALUE_HIGH);
129
-
clocksource_mmio_init(NULL, "timer4",
130
-
EP93XX_TIMER4_RATE, 200, 40,
131
-
ep93xx_clocksource_read);
132
-
sched_clock_register(ep93xx_read_sched_clock, 40,
133
-
EP93XX_TIMER4_RATE);
134
-
135
-
/* Set up clockevent on timer 3 */
136
-
if (request_irq(irq, ep93xx_timer_interrupt, flags, "ep93xx timer",
137
-
&ep93xx_clockevent))
138
-
pr_err("Failed to request irq %d (ep93xx timer)\n", irq);
139
-
clockevents_config_and_register(&ep93xx_clockevent,
140
-
EP93XX_TIMER123_RATE,
141
-
1,
142
-
0xffffffffU);
143
-
}
-422
arch/arm/mach-ep93xx/ts72xx.c
-422
arch/arm/mach-ep93xx/ts72xx.c
···
1
-
// SPDX-License-Identifier: GPL-2.0-or-later
2
-
/*
3
-
* arch/arm/mach-ep93xx/ts72xx.c
4
-
* Technologic Systems TS72xx SBC support.
5
-
*
6
-
* Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
7
-
*/
8
-
9
-
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10
-
11
-
#include <linux/kernel.h>
12
-
#include <linux/init.h>
13
-
#include <linux/platform_device.h>
14
-
#include <linux/io.h>
15
-
#include <linux/mtd/platnand.h>
16
-
#include <linux/spi/spi.h>
17
-
#include <linux/spi/flash.h>
18
-
#include <linux/spi/mmc_spi.h>
19
-
#include <linux/mmc/host.h>
20
-
#include <linux/platform_data/spi-ep93xx.h>
21
-
#include <linux/gpio/machine.h>
22
-
23
-
#include "gpio-ep93xx.h"
24
-
#include "hardware.h"
25
-
26
-
#include <asm/mach-types.h>
27
-
#include <asm/mach/map.h>
28
-
#include <asm/mach/arch.h>
29
-
30
-
#include "soc.h"
31
-
#include "ts72xx.h"
32
-
33
-
/*************************************************************************
34
-
* IO map
35
-
*************************************************************************/
36
-
static struct map_desc ts72xx_io_desc[] __initdata = {
37
-
{
38
-
.virtual = (unsigned long)TS72XX_MODEL_VIRT_BASE,
39
-
.pfn = __phys_to_pfn(TS72XX_MODEL_PHYS_BASE),
40
-
.length = TS72XX_MODEL_SIZE,
41
-
.type = MT_DEVICE,
42
-
}, {
43
-
.virtual = (unsigned long)TS72XX_OPTIONS_VIRT_BASE,
44
-
.pfn = __phys_to_pfn(TS72XX_OPTIONS_PHYS_BASE),
45
-
.length = TS72XX_OPTIONS_SIZE,
46
-
.type = MT_DEVICE,
47
-
}, {
48
-
.virtual = (unsigned long)TS72XX_OPTIONS2_VIRT_BASE,
49
-
.pfn = __phys_to_pfn(TS72XX_OPTIONS2_PHYS_BASE),
50
-
.length = TS72XX_OPTIONS2_SIZE,
51
-
.type = MT_DEVICE,
52
-
}, {
53
-
.virtual = (unsigned long)TS72XX_CPLDVER_VIRT_BASE,
54
-
.pfn = __phys_to_pfn(TS72XX_CPLDVER_PHYS_BASE),
55
-
.length = TS72XX_CPLDVER_SIZE,
56
-
.type = MT_DEVICE,
57
-
}
58
-
};
59
-
60
-
static void __init ts72xx_map_io(void)
61
-
{
62
-
ep93xx_map_io();
63
-
iotable_init(ts72xx_io_desc, ARRAY_SIZE(ts72xx_io_desc));
64
-
}
65
-
66
-
67
-
/*************************************************************************
68
-
* NAND flash
69
-
*************************************************************************/
70
-
#define TS72XX_NAND_CONTROL_ADDR_LINE 22 /* 0xN0400000 */
71
-
#define TS72XX_NAND_BUSY_ADDR_LINE 23 /* 0xN0800000 */
72
-
73
-
static void ts72xx_nand_hwcontrol(struct nand_chip *chip,
74
-
int cmd, unsigned int ctrl)
75
-
{
76
-
if (ctrl & NAND_CTRL_CHANGE) {
77
-
void __iomem *addr = chip->legacy.IO_ADDR_R;
78
-
unsigned char bits;
79
-
80
-
addr += (1 << TS72XX_NAND_CONTROL_ADDR_LINE);
81
-
82
-
bits = __raw_readb(addr) & ~0x07;
83
-
bits |= (ctrl & NAND_NCE) << 2; /* bit 0 -> bit 2 */
84
-
bits |= (ctrl & NAND_CLE); /* bit 1 -> bit 1 */
85
-
bits |= (ctrl & NAND_ALE) >> 2; /* bit 2 -> bit 0 */
86
-
87
-
__raw_writeb(bits, addr);
88
-
}
89
-
90
-
if (cmd != NAND_CMD_NONE)
91
-
__raw_writeb(cmd, chip->legacy.IO_ADDR_W);
92
-
}
93
-
94
-
static int ts72xx_nand_device_ready(struct nand_chip *chip)
95
-
{
96
-
void __iomem *addr = chip->legacy.IO_ADDR_R;
97
-
98
-
addr += (1 << TS72XX_NAND_BUSY_ADDR_LINE);
99
-
100
-
return !!(__raw_readb(addr) & 0x20);
101
-
}
102
-
103
-
#define TS72XX_BOOTROM_PART_SIZE (SZ_16K)
104
-
#define TS72XX_REDBOOT_PART_SIZE (SZ_2M + SZ_1M)
105
-
106
-
static struct mtd_partition ts72xx_nand_parts[] = {
107
-
{
108
-
.name = "TS-BOOTROM",
109
-
.offset = 0,
110
-
.size = TS72XX_BOOTROM_PART_SIZE,
111
-
.mask_flags = MTD_WRITEABLE, /* force read-only */
112
-
}, {
113
-
.name = "Linux",
114
-
.offset = MTDPART_OFS_RETAIN,
115
-
.size = TS72XX_REDBOOT_PART_SIZE,
116
-
/* leave so much for last partition */
117
-
}, {
118
-
.name = "RedBoot",
119
-
.offset = MTDPART_OFS_APPEND,
120
-
.size = MTDPART_SIZ_FULL,
121
-
.mask_flags = MTD_WRITEABLE, /* force read-only */
122
-
},
123
-
};
124
-
125
-
static struct platform_nand_data ts72xx_nand_data = {
126
-
.chip = {
127
-
.nr_chips = 1,
128
-
.chip_offset = 0,
129
-
.chip_delay = 15,
130
-
},
131
-
.ctrl = {
132
-
.cmd_ctrl = ts72xx_nand_hwcontrol,
133
-
.dev_ready = ts72xx_nand_device_ready,
134
-
},
135
-
};
136
-
137
-
static struct resource ts72xx_nand_resource[] = {
138
-
{
139
-
.start = 0, /* filled in later */
140
-
.end = 0, /* filled in later */
141
-
.flags = IORESOURCE_MEM,
142
-
},
143
-
};
144
-
145
-
static struct platform_device ts72xx_nand_flash = {
146
-
.name = "gen_nand",
147
-
.id = -1,
148
-
.dev.platform_data = &ts72xx_nand_data,
149
-
.resource = ts72xx_nand_resource,
150
-
.num_resources = ARRAY_SIZE(ts72xx_nand_resource),
151
-
};
152
-
153
-
static void __init ts72xx_register_flash(struct mtd_partition *parts, int n,
154
-
resource_size_t start)
155
-
{
156
-
/*
157
-
* TS7200 has NOR flash all other TS72xx board have NAND flash.
158
-
*/
159
-
if (board_is_ts7200()) {
160
-
ep93xx_register_flash(2, EP93XX_CS6_PHYS_BASE, SZ_16M);
161
-
} else {
162
-
ts72xx_nand_resource[0].start = start;
163
-
ts72xx_nand_resource[0].end = start + SZ_16M - 1;
164
-
165
-
ts72xx_nand_data.chip.partitions = parts;
166
-
ts72xx_nand_data.chip.nr_partitions = n;
167
-
168
-
platform_device_register(&ts72xx_nand_flash);
169
-
}
170
-
}
171
-
172
-
/*************************************************************************
173
-
* RTC M48T86
174
-
*************************************************************************/
175
-
#define TS72XX_RTC_INDEX_PHYS_BASE (EP93XX_CS1_PHYS_BASE + 0x00800000)
176
-
#define TS72XX_RTC_DATA_PHYS_BASE (EP93XX_CS1_PHYS_BASE + 0x01700000)
177
-
178
-
static struct resource ts72xx_rtc_resources[] = {
179
-
DEFINE_RES_MEM(TS72XX_RTC_INDEX_PHYS_BASE, 0x01),
180
-
DEFINE_RES_MEM(TS72XX_RTC_DATA_PHYS_BASE, 0x01),
181
-
};
182
-
183
-
static struct platform_device ts72xx_rtc_device = {
184
-
.name = "rtc-m48t86",
185
-
.id = -1,
186
-
.resource = ts72xx_rtc_resources,
187
-
.num_resources = ARRAY_SIZE(ts72xx_rtc_resources),
188
-
};
189
-
190
-
/*************************************************************************
191
-
* Watchdog (in CPLD)
192
-
*************************************************************************/
193
-
#define TS72XX_WDT_CONTROL_PHYS_BASE (EP93XX_CS2_PHYS_BASE + 0x03800000)
194
-
#define TS72XX_WDT_FEED_PHYS_BASE (EP93XX_CS2_PHYS_BASE + 0x03c00000)
195
-
196
-
static struct resource ts72xx_wdt_resources[] = {
197
-
DEFINE_RES_MEM(TS72XX_WDT_CONTROL_PHYS_BASE, 0x01),
198
-
DEFINE_RES_MEM(TS72XX_WDT_FEED_PHYS_BASE, 0x01),
199
-
};
200
-
201
-
static struct platform_device ts72xx_wdt_device = {
202
-
.name = "ts72xx-wdt",
203
-
.id = -1,
204
-
.resource = ts72xx_wdt_resources,
205
-
.num_resources = ARRAY_SIZE(ts72xx_wdt_resources),
206
-
};
207
-
208
-
/*************************************************************************
209
-
* ETH
210
-
*************************************************************************/
211
-
static struct ep93xx_eth_data __initdata ts72xx_eth_data = {
212
-
.phy_id = 1,
213
-
};
214
-
215
-
/*************************************************************************
216
-
* SPI SD/MMC host
217
-
*************************************************************************/
218
-
#define BK3_EN_SDCARD_PHYS_BASE 0x12400000
219
-
#define BK3_EN_SDCARD_PWR 0x0
220
-
#define BK3_DIS_SDCARD_PWR 0x0C
221
-
static void bk3_mmc_spi_setpower(struct device *dev, unsigned int vdd)
222
-
{
223
-
void __iomem *pwr_sd = ioremap(BK3_EN_SDCARD_PHYS_BASE, SZ_4K);
224
-
225
-
if (!pwr_sd) {
226
-
pr_err("Failed to enable SD card power!");
227
-
return;
228
-
}
229
-
230
-
pr_debug("%s: SD card pwr %s VDD:0x%x\n", __func__,
231
-
!!vdd ? "ON" : "OFF", vdd);
232
-
233
-
if (!!vdd)
234
-
__raw_writeb(BK3_EN_SDCARD_PWR, pwr_sd);
235
-
else
236
-
__raw_writeb(BK3_DIS_SDCARD_PWR, pwr_sd);
237
-
238
-
iounmap(pwr_sd);
239
-
}
240
-
241
-
static struct mmc_spi_platform_data bk3_spi_mmc_data = {
242
-
.detect_delay = 500,
243
-
.powerup_msecs = 100,
244
-
.ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
245
-
.caps = MMC_CAP_NONREMOVABLE,
246
-
.setpower = bk3_mmc_spi_setpower,
247
-
};
248
-
249
-
/*************************************************************************
250
-
* SPI Bus - SD card access
251
-
*************************************************************************/
252
-
static struct spi_board_info bk3_spi_board_info[] __initdata = {
253
-
{
254
-
.modalias = "mmc_spi",
255
-
.platform_data = &bk3_spi_mmc_data,
256
-
.max_speed_hz = 7.4E6,
257
-
.bus_num = 0,
258
-
.chip_select = 0,
259
-
.mode = SPI_MODE_0,
260
-
},
261
-
};
262
-
263
-
/*
264
-
* This is a stub -> the FGPIO[3] pin is not connected on the schematic
265
-
* The all work is performed automatically by !SPI_FRAME (SFRM1) and
266
-
* goes through CPLD
267
-
*/
268
-
static struct gpiod_lookup_table bk3_spi_cs_gpio_table = {
269
-
.dev_id = "spi0",
270
-
.table = {
271
-
GPIO_LOOKUP("F", 3, "cs", GPIO_ACTIVE_LOW),
272
-
{ },
273
-
},
274
-
};
275
-
276
-
static struct ep93xx_spi_info bk3_spi_master __initdata = {
277
-
.use_dma = 1,
278
-
};
279
-
280
-
/*************************************************************************
281
-
* TS72XX support code
282
-
*************************************************************************/
283
-
#if IS_ENABLED(CONFIG_FPGA_MGR_TS73XX)
284
-
285
-
/* Relative to EP93XX_CS1_PHYS_BASE */
286
-
#define TS73XX_FPGA_LOADER_BASE 0x03c00000
287
-
288
-
static struct resource ts73xx_fpga_resources[] = {
289
-
{
290
-
.start = EP93XX_CS1_PHYS_BASE + TS73XX_FPGA_LOADER_BASE,
291
-
.end = EP93XX_CS1_PHYS_BASE + TS73XX_FPGA_LOADER_BASE + 1,
292
-
.flags = IORESOURCE_MEM,
293
-
},
294
-
};
295
-
296
-
static struct platform_device ts73xx_fpga_device = {
297
-
.name = "ts73xx-fpga-mgr",
298
-
.id = -1,
299
-
.resource = ts73xx_fpga_resources,
300
-
.num_resources = ARRAY_SIZE(ts73xx_fpga_resources),
301
-
};
302
-
303
-
#endif
304
-
305
-
/*************************************************************************
306
-
* SPI Bus
307
-
*************************************************************************/
308
-
static struct spi_board_info ts72xx_spi_devices[] __initdata = {
309
-
{
310
-
.modalias = "tmp122",
311
-
.max_speed_hz = 2 * 1000 * 1000,
312
-
.bus_num = 0,
313
-
.chip_select = 0,
314
-
},
315
-
};
316
-
317
-
static struct gpiod_lookup_table ts72xx_spi_cs_gpio_table = {
318
-
.dev_id = "spi0",
319
-
.table = {
320
-
/* DIO_17 */
321
-
GPIO_LOOKUP("F", 2, "cs", GPIO_ACTIVE_LOW),
322
-
{ },
323
-
},
324
-
};
325
-
326
-
static struct ep93xx_spi_info ts72xx_spi_info __initdata = {
327
-
/* Intentionally left blank */
328
-
};
329
-
330
-
static void __init ts72xx_init_machine(void)
331
-
{
332
-
ep93xx_init_devices();
333
-
ts72xx_register_flash(ts72xx_nand_parts, ARRAY_SIZE(ts72xx_nand_parts),
334
-
is_ts9420_installed() ?
335
-
EP93XX_CS7_PHYS_BASE : EP93XX_CS6_PHYS_BASE);
336
-
platform_device_register(&ts72xx_rtc_device);
337
-
platform_device_register(&ts72xx_wdt_device);
338
-
339
-
ep93xx_register_eth(&ts72xx_eth_data, 1);
340
-
#if IS_ENABLED(CONFIG_FPGA_MGR_TS73XX)
341
-
if (board_is_ts7300())
342
-
platform_device_register(&ts73xx_fpga_device);
343
-
#endif
344
-
gpiod_add_lookup_table(&ts72xx_spi_cs_gpio_table);
345
-
ep93xx_register_spi(&ts72xx_spi_info, ts72xx_spi_devices,
346
-
ARRAY_SIZE(ts72xx_spi_devices));
347
-
}
348
-
349
-
MACHINE_START(TS72XX, "Technologic Systems TS-72xx SBC")
350
-
/* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
351
-
.atag_offset = 0x100,
352
-
.nr_irqs = NR_EP93XX_IRQS,
353
-
.map_io = ts72xx_map_io,
354
-
.init_irq = ep93xx_init_irq,
355
-
.init_time = ep93xx_timer_init,
356
-
.init_machine = ts72xx_init_machine,
357
-
.restart = ep93xx_restart,
358
-
MACHINE_END
359
-
360
-
/*************************************************************************
361
-
* EP93xx I2S audio peripheral handling
362
-
*************************************************************************/
363
-
static struct resource ep93xx_i2s_resource[] = {
364
-
DEFINE_RES_MEM(EP93XX_I2S_PHYS_BASE, 0x100),
365
-
DEFINE_RES_IRQ_NAMED(IRQ_EP93XX_SAI, "spilink i2s slave"),
366
-
};
367
-
368
-
static struct platform_device ep93xx_i2s_device = {
369
-
.name = "ep93xx-spilink-i2s",
370
-
.id = -1,
371
-
.num_resources = ARRAY_SIZE(ep93xx_i2s_resource),
372
-
.resource = ep93xx_i2s_resource,
373
-
};
374
-
375
-
/*************************************************************************
376
-
* BK3 support code
377
-
*************************************************************************/
378
-
static struct mtd_partition bk3_nand_parts[] = {
379
-
{
380
-
.name = "System",
381
-
.offset = 0x00000000,
382
-
.size = 0x01e00000,
383
-
}, {
384
-
.name = "Data",
385
-
.offset = 0x01e00000,
386
-
.size = 0x05f20000
387
-
}, {
388
-
.name = "RedBoot",
389
-
.offset = 0x07d20000,
390
-
.size = 0x002e0000,
391
-
.mask_flags = MTD_WRITEABLE, /* force RO */
392
-
},
393
-
};
394
-
395
-
static void __init bk3_init_machine(void)
396
-
{
397
-
ep93xx_init_devices();
398
-
399
-
ts72xx_register_flash(bk3_nand_parts, ARRAY_SIZE(bk3_nand_parts),
400
-
EP93XX_CS6_PHYS_BASE);
401
-
402
-
ep93xx_register_eth(&ts72xx_eth_data, 1);
403
-
404
-
gpiod_add_lookup_table(&bk3_spi_cs_gpio_table);
405
-
ep93xx_register_spi(&bk3_spi_master, bk3_spi_board_info,
406
-
ARRAY_SIZE(bk3_spi_board_info));
407
-
408
-
/* Configure ep93xx's I2S to use AC97 pins */
409
-
ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_I2SONAC97);
410
-
platform_device_register(&ep93xx_i2s_device);
411
-
}
412
-
413
-
MACHINE_START(BK3, "Liebherr controller BK3.1")
414
-
/* Maintainer: Lukasz Majewski <lukma@denx.de> */
415
-
.atag_offset = 0x100,
416
-
.nr_irqs = NR_EP93XX_IRQS,
417
-
.map_io = ts72xx_map_io,
418
-
.init_irq = ep93xx_init_irq,
419
-
.init_time = ep93xx_timer_init,
420
-
.init_machine = bk3_init_machine,
421
-
.restart = ep93xx_restart,
422
-
MACHINE_END
-94
arch/arm/mach-ep93xx/ts72xx.h
-94
arch/arm/mach-ep93xx/ts72xx.h
···
1
-
/* SPDX-License-Identifier: GPL-2.0 */
2
-
/*
3
-
* arch/arm/mach-ep93xx/include/mach/ts72xx.h
4
-
*/
5
-
6
-
/*
7
-
* TS72xx memory map:
8
-
*
9
-
* virt phys size
10
-
* febff000 22000000 4K model number register (bits 0-2)
11
-
* febfe000 22400000 4K options register
12
-
* febfd000 22800000 4K options register #2
13
-
* febfc000 23400000 4K CPLD version register
14
-
*/
15
-
16
-
#ifndef __TS72XX_H_
17
-
#define __TS72XX_H_
18
-
19
-
#define TS72XX_MODEL_PHYS_BASE 0x22000000
20
-
#define TS72XX_MODEL_VIRT_BASE IOMEM(0xfebff000)
21
-
#define TS72XX_MODEL_SIZE 0x00001000
22
-
23
-
#define TS72XX_MODEL_TS7200 0x00
24
-
#define TS72XX_MODEL_TS7250 0x01
25
-
#define TS72XX_MODEL_TS7260 0x02
26
-
#define TS72XX_MODEL_TS7300 0x03
27
-
#define TS72XX_MODEL_TS7400 0x04
28
-
#define TS72XX_MODEL_MASK 0x07
29
-
30
-
31
-
#define TS72XX_OPTIONS_PHYS_BASE 0x22400000
32
-
#define TS72XX_OPTIONS_VIRT_BASE IOMEM(0xfebfe000)
33
-
#define TS72XX_OPTIONS_SIZE 0x00001000
34
-
35
-
#define TS72XX_OPTIONS_COM2_RS485 0x02
36
-
#define TS72XX_OPTIONS_MAX197 0x01
37
-
38
-
39
-
#define TS72XX_OPTIONS2_PHYS_BASE 0x22800000
40
-
#define TS72XX_OPTIONS2_VIRT_BASE IOMEM(0xfebfd000)
41
-
#define TS72XX_OPTIONS2_SIZE 0x00001000
42
-
43
-
#define TS72XX_OPTIONS2_TS9420 0x04
44
-
#define TS72XX_OPTIONS2_TS9420_BOOT 0x02
45
-
46
-
#define TS72XX_CPLDVER_PHYS_BASE 0x23400000
47
-
#define TS72XX_CPLDVER_VIRT_BASE IOMEM(0xfebfc000)
48
-
#define TS72XX_CPLDVER_SIZE 0x00001000
49
-
50
-
#ifndef __ASSEMBLY__
51
-
52
-
static inline int ts72xx_model(void)
53
-
{
54
-
return __raw_readb(TS72XX_MODEL_VIRT_BASE) & TS72XX_MODEL_MASK;
55
-
}
56
-
57
-
static inline int board_is_ts7200(void)
58
-
{
59
-
return ts72xx_model() == TS72XX_MODEL_TS7200;
60
-
}
61
-
62
-
static inline int board_is_ts7250(void)
63
-
{
64
-
return ts72xx_model() == TS72XX_MODEL_TS7250;
65
-
}
66
-
67
-
static inline int board_is_ts7260(void)
68
-
{
69
-
return ts72xx_model() == TS72XX_MODEL_TS7260;
70
-
}
71
-
72
-
static inline int board_is_ts7300(void)
73
-
{
74
-
return ts72xx_model() == TS72XX_MODEL_TS7300;
75
-
}
76
-
77
-
static inline int board_is_ts7400(void)
78
-
{
79
-
return ts72xx_model() == TS72XX_MODEL_TS7400;
80
-
}
81
-
82
-
static inline int is_max197_installed(void)
83
-
{
84
-
return !!(__raw_readb(TS72XX_OPTIONS_VIRT_BASE) &
85
-
TS72XX_OPTIONS_MAX197);
86
-
}
87
-
88
-
static inline int is_ts9420_installed(void)
89
-
{
90
-
return !!(__raw_readb(TS72XX_OPTIONS2_VIRT_BASE) &
91
-
TS72XX_OPTIONS2_TS9420);
92
-
}
93
-
#endif
94
-
#endif /* __TS72XX_H_ */
-319
arch/arm/mach-ep93xx/vision_ep9307.c
-319
arch/arm/mach-ep93xx/vision_ep9307.c
···
1
-
// SPDX-License-Identifier: GPL-2.0-or-later
2
-
/*
3
-
* arch/arm/mach-ep93xx/vision_ep9307.c
4
-
* Vision Engraving Systems EP9307 SoM support.
5
-
*
6
-
* Copyright (C) 2008-2011 Vision Engraving Systems
7
-
* H Hartley Sweeten <hsweeten@visionengravers.com>
8
-
*/
9
-
10
-
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
11
-
12
-
#include <linux/kernel.h>
13
-
#include <linux/init.h>
14
-
#include <linux/platform_device.h>
15
-
#include <linux/irq.h>
16
-
#include <linux/gpio.h>
17
-
#include <linux/gpio/machine.h>
18
-
#include <linux/fb.h>
19
-
#include <linux/io.h>
20
-
#include <linux/mtd/partitions.h>
21
-
#include <linux/i2c.h>
22
-
#include <linux/platform_data/pca953x.h>
23
-
#include <linux/spi/spi.h>
24
-
#include <linux/spi/flash.h>
25
-
#include <linux/spi/mmc_spi.h>
26
-
#include <linux/mmc/host.h>
27
-
28
-
#include <sound/cs4271.h>
29
-
30
-
#include "hardware.h"
31
-
#include <linux/platform_data/video-ep93xx.h>
32
-
#include <linux/platform_data/spi-ep93xx.h>
33
-
#include "gpio-ep93xx.h"
34
-
35
-
#include <asm/mach-types.h>
36
-
#include <asm/mach/map.h>
37
-
#include <asm/mach/arch.h>
38
-
39
-
#include "soc.h"
40
-
41
-
/*************************************************************************
42
-
* Static I/O mappings for the FPGA
43
-
*************************************************************************/
44
-
#define VISION_PHYS_BASE EP93XX_CS7_PHYS_BASE
45
-
#define VISION_VIRT_BASE 0xfebff000
46
-
47
-
static struct map_desc vision_io_desc[] __initdata = {
48
-
{
49
-
.virtual = VISION_VIRT_BASE,
50
-
.pfn = __phys_to_pfn(VISION_PHYS_BASE),
51
-
.length = SZ_4K,
52
-
.type = MT_DEVICE,
53
-
},
54
-
};
55
-
56
-
static void __init vision_map_io(void)
57
-
{
58
-
ep93xx_map_io();
59
-
60
-
iotable_init(vision_io_desc, ARRAY_SIZE(vision_io_desc));
61
-
}
62
-
63
-
/*************************************************************************
64
-
* Ethernet
65
-
*************************************************************************/
66
-
static struct ep93xx_eth_data vision_eth_data __initdata = {
67
-
.phy_id = 1,
68
-
};
69
-
70
-
/*************************************************************************
71
-
* Framebuffer
72
-
*************************************************************************/
73
-
#define VISION_LCD_ENABLE EP93XX_GPIO_LINE_EGPIO1
74
-
75
-
static int vision_lcd_setup(struct platform_device *pdev)
76
-
{
77
-
int err;
78
-
79
-
err = gpio_request_one(VISION_LCD_ENABLE, GPIOF_OUT_INIT_HIGH, dev_name(&pdev->dev));
80
-
if (err)
81
-
return err;
82
-
83
-
ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_RAS |
84
-
EP93XX_SYSCON_DEVCFG_RASONP3 |
85
-
EP93XX_SYSCON_DEVCFG_EXVC);
86
-
87
-
return 0;
88
-
}
89
-
90
-
static void vision_lcd_teardown(struct platform_device *pdev)
91
-
{
92
-
gpio_free(VISION_LCD_ENABLE);
93
-
}
94
-
95
-
static void vision_lcd_blank(int blank_mode, struct fb_info *info)
96
-
{
97
-
if (blank_mode)
98
-
gpio_set_value(VISION_LCD_ENABLE, 0);
99
-
else
100
-
gpio_set_value(VISION_LCD_ENABLE, 1);
101
-
}
102
-
103
-
static struct ep93xxfb_mach_info ep93xxfb_info __initdata = {
104
-
.flags = EP93XXFB_USE_SDCSN0 | EP93XXFB_PCLK_FALLING,
105
-
.setup = vision_lcd_setup,
106
-
.teardown = vision_lcd_teardown,
107
-
.blank = vision_lcd_blank,
108
-
};
109
-
110
-
111
-
/*************************************************************************
112
-
* GPIO Expanders
113
-
*************************************************************************/
114
-
#define PCA9539_74_GPIO_BASE (EP93XX_GPIO_LINE_MAX + 1)
115
-
#define PCA9539_75_GPIO_BASE (PCA9539_74_GPIO_BASE + 16)
116
-
#define PCA9539_76_GPIO_BASE (PCA9539_75_GPIO_BASE + 16)
117
-
#define PCA9539_77_GPIO_BASE (PCA9539_76_GPIO_BASE + 16)
118
-
119
-
static struct pca953x_platform_data pca953x_74_gpio_data = {
120
-
.gpio_base = PCA9539_74_GPIO_BASE,
121
-
.irq_base = EP93XX_BOARD_IRQ(0),
122
-
};
123
-
124
-
static struct pca953x_platform_data pca953x_75_gpio_data = {
125
-
.gpio_base = PCA9539_75_GPIO_BASE,
126
-
.irq_base = -1,
127
-
};
128
-
129
-
static struct pca953x_platform_data pca953x_76_gpio_data = {
130
-
.gpio_base = PCA9539_76_GPIO_BASE,
131
-
.irq_base = -1,
132
-
};
133
-
134
-
static struct pca953x_platform_data pca953x_77_gpio_data = {
135
-
.gpio_base = PCA9539_77_GPIO_BASE,
136
-
.irq_base = -1,
137
-
};
138
-
139
-
/*************************************************************************
140
-
* I2C Bus
141
-
*************************************************************************/
142
-
143
-
static struct i2c_board_info vision_i2c_info[] __initdata = {
144
-
{
145
-
I2C_BOARD_INFO("isl1208", 0x6f),
146
-
.irq = IRQ_EP93XX_EXT1,
147
-
}, {
148
-
I2C_BOARD_INFO("pca9539", 0x74),
149
-
.platform_data = &pca953x_74_gpio_data,
150
-
}, {
151
-
I2C_BOARD_INFO("pca9539", 0x75),
152
-
.platform_data = &pca953x_75_gpio_data,
153
-
}, {
154
-
I2C_BOARD_INFO("pca9539", 0x76),
155
-
.platform_data = &pca953x_76_gpio_data,
156
-
}, {
157
-
I2C_BOARD_INFO("pca9539", 0x77),
158
-
.platform_data = &pca953x_77_gpio_data,
159
-
},
160
-
};
161
-
162
-
/*************************************************************************
163
-
* SPI CS4271 Audio Codec
164
-
*************************************************************************/
165
-
static struct cs4271_platform_data vision_cs4271_data = {
166
-
/* Intentionally left blank */
167
-
};
168
-
169
-
/*************************************************************************
170
-
* SPI Flash
171
-
*************************************************************************/
172
-
static struct mtd_partition vision_spi_flash_partitions[] = {
173
-
{
174
-
.name = "SPI bootstrap",
175
-
.offset = 0,
176
-
.size = SZ_4K,
177
-
}, {
178
-
.name = "Bootstrap config",
179
-
.offset = MTDPART_OFS_APPEND,
180
-
.size = SZ_4K,
181
-
}, {
182
-
.name = "System config",
183
-
.offset = MTDPART_OFS_APPEND,
184
-
.size = MTDPART_SIZ_FULL,
185
-
},
186
-
};
187
-
188
-
static struct flash_platform_data vision_spi_flash_data = {
189
-
.name = "SPI Flash",
190
-
.parts = vision_spi_flash_partitions,
191
-
.nr_parts = ARRAY_SIZE(vision_spi_flash_partitions),
192
-
};
193
-
194
-
/*************************************************************************
195
-
* SPI SD/MMC host
196
-
*************************************************************************/
197
-
static struct mmc_spi_platform_data vision_spi_mmc_data = {
198
-
.detect_delay = 100,
199
-
.powerup_msecs = 100,
200
-
.ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
201
-
.caps2 = MMC_CAP2_RO_ACTIVE_HIGH,
202
-
};
203
-
204
-
static struct gpiod_lookup_table vision_spi_mmc_gpio_table = {
205
-
.dev_id = "mmc_spi.2", /* "mmc_spi @ CS2 */
206
-
.table = {
207
-
/* Card detect */
208
-
GPIO_LOOKUP_IDX("B", 7, NULL, 0, GPIO_ACTIVE_LOW),
209
-
/* Write protect */
210
-
GPIO_LOOKUP_IDX("F", 0, NULL, 1, GPIO_ACTIVE_HIGH),
211
-
{ },
212
-
},
213
-
};
214
-
215
-
/*************************************************************************
216
-
* SPI Bus
217
-
*************************************************************************/
218
-
static struct spi_board_info vision_spi_board_info[] __initdata = {
219
-
{
220
-
.modalias = "cs4271",
221
-
.platform_data = &vision_cs4271_data,
222
-
.max_speed_hz = 6000000,
223
-
.bus_num = 0,
224
-
.chip_select = 0,
225
-
.mode = SPI_MODE_3,
226
-
}, {
227
-
.modalias = "sst25l",
228
-
.platform_data = &vision_spi_flash_data,
229
-
.max_speed_hz = 20000000,
230
-
.bus_num = 0,
231
-
.chip_select = 1,
232
-
.mode = SPI_MODE_3,
233
-
}, {
234
-
.modalias = "mmc_spi",
235
-
.platform_data = &vision_spi_mmc_data,
236
-
.max_speed_hz = 20000000,
237
-
.bus_num = 0,
238
-
.chip_select = 2,
239
-
.mode = SPI_MODE_3,
240
-
},
241
-
};
242
-
243
-
static struct gpiod_lookup_table vision_spi_cs4271_gpio_table = {
244
-
.dev_id = "spi0.0", /* cs4271 @ CS0 */
245
-
.table = {
246
-
/* RESET */
247
-
GPIO_LOOKUP_IDX("H", 2, NULL, 0, GPIO_ACTIVE_LOW),
248
-
{ },
249
-
},
250
-
};
251
-
252
-
static struct gpiod_lookup_table vision_spi_cs_gpio_table = {
253
-
.dev_id = "spi0",
254
-
.table = {
255
-
GPIO_LOOKUP_IDX("A", 6, "cs", 0, GPIO_ACTIVE_LOW),
256
-
GPIO_LOOKUP_IDX("A", 7, "cs", 1, GPIO_ACTIVE_LOW),
257
-
GPIO_LOOKUP_IDX("G", 2, "cs", 2, GPIO_ACTIVE_LOW),
258
-
{ },
259
-
},
260
-
};
261
-
262
-
static struct ep93xx_spi_info vision_spi_master __initdata = {
263
-
.use_dma = 1,
264
-
};
265
-
266
-
/*************************************************************************
267
-
* I2S Audio
268
-
*************************************************************************/
269
-
static struct platform_device vision_audio_device = {
270
-
.name = "edb93xx-audio",
271
-
.id = -1,
272
-
};
273
-
274
-
static void __init vision_register_i2s(void)
275
-
{
276
-
ep93xx_register_i2s();
277
-
platform_device_register(&vision_audio_device);
278
-
}
279
-
280
-
/*************************************************************************
281
-
* Machine Initialization
282
-
*************************************************************************/
283
-
static void __init vision_init_machine(void)
284
-
{
285
-
ep93xx_init_devices();
286
-
ep93xx_register_flash(2, EP93XX_CS6_PHYS_BASE, SZ_64M);
287
-
ep93xx_register_eth(&vision_eth_data, 1);
288
-
ep93xx_register_fb(&ep93xxfb_info);
289
-
ep93xx_register_pwm(1, 0);
290
-
291
-
/*
292
-
* Request the gpio expander's interrupt gpio line now to prevent
293
-
* the kernel from doing a WARN in gpiolib:gpio_ensure_requested().
294
-
*/
295
-
if (gpio_request_one(EP93XX_GPIO_LINE_F(7), GPIOF_IN, "pca9539:74"))
296
-
pr_warn("cannot request interrupt gpio for pca9539:74\n");
297
-
298
-
vision_i2c_info[1].irq = gpio_to_irq(EP93XX_GPIO_LINE_F(7));
299
-
300
-
ep93xx_register_i2c(vision_i2c_info,
301
-
ARRAY_SIZE(vision_i2c_info));
302
-
gpiod_add_lookup_table(&vision_spi_cs4271_gpio_table);
303
-
gpiod_add_lookup_table(&vision_spi_mmc_gpio_table);
304
-
gpiod_add_lookup_table(&vision_spi_cs_gpio_table);
305
-
ep93xx_register_spi(&vision_spi_master, vision_spi_board_info,
306
-
ARRAY_SIZE(vision_spi_board_info));
307
-
vision_register_i2s();
308
-
}
309
-
310
-
MACHINE_START(VISION_EP9307, "Vision Engraving Systems EP9307")
311
-
/* Maintainer: H Hartley Sweeten <hsweeten@visionengravers.com> */
312
-
.atag_offset = 0x100,
313
-
.nr_irqs = NR_EP93XX_IRQS + EP93XX_BOARD_IRQS,
314
-
.map_io = vision_map_io,
315
-
.init_irq = ep93xx_init_irq,
316
-
.init_time = ep93xx_timer_init,
317
-
.init_machine = vision_init_machine,
318
-
.restart = ep93xx_restart,
319
-
MACHINE_END
+48
-57
drivers/ata/pata_ep93xx.c
+48
-57
drivers/ata/pata_ep93xx.c
···
44
44
#include <linux/delay.h>
45
45
#include <linux/dmaengine.h>
46
46
#include <linux/ktime.h>
47
+
#include <linux/mod_devicetable.h>
47
48
48
-
#include <linux/platform_data/dma-ep93xx.h>
49
49
#include <linux/soc/cirrus/ep93xx.h>
50
50
51
51
#define DRV_NAME "ep93xx-ide"
···
126
126
};
127
127
128
128
struct ep93xx_pata_data {
129
-
const struct platform_device *pdev;
129
+
struct platform_device *pdev;
130
130
void __iomem *ide_base;
131
131
struct ata_timing t;
132
132
bool iordy;
···
135
135
unsigned long udma_out_phys;
136
136
137
137
struct dma_chan *dma_rx_channel;
138
-
struct ep93xx_dma_data dma_rx_data;
139
138
struct dma_chan *dma_tx_channel;
140
-
struct ep93xx_dma_data dma_tx_data;
141
139
};
142
140
143
141
static void ep93xx_pata_clear_regs(void __iomem *base)
···
635
637
}
636
638
}
637
639
638
-
static bool ep93xx_pata_dma_filter(struct dma_chan *chan, void *filter_param)
640
+
static int ep93xx_pata_dma_init(struct ep93xx_pata_data *drv_data)
639
641
{
640
-
if (ep93xx_dma_chan_is_m2p(chan))
641
-
return false;
642
-
643
-
chan->private = filter_param;
644
-
return true;
645
-
}
646
-
647
-
static void ep93xx_pata_dma_init(struct ep93xx_pata_data *drv_data)
648
-
{
649
-
const struct platform_device *pdev = drv_data->pdev;
642
+
struct platform_device *pdev = drv_data->pdev;
643
+
struct device *dev = &pdev->dev;
650
644
dma_cap_mask_t mask;
651
645
struct dma_slave_config conf;
646
+
int ret;
652
647
653
648
dma_cap_zero(mask);
654
649
dma_cap_set(DMA_SLAVE, mask);
···
651
660
* to request only one channel, and reprogram it's direction at
652
661
* start of new transfer.
653
662
*/
654
-
drv_data->dma_rx_data.port = EP93XX_DMA_IDE;
655
-
drv_data->dma_rx_data.direction = DMA_DEV_TO_MEM;
656
-
drv_data->dma_rx_data.name = "ep93xx-pata-rx";
657
-
drv_data->dma_rx_channel = dma_request_channel(mask,
658
-
ep93xx_pata_dma_filter, &drv_data->dma_rx_data);
659
-
if (!drv_data->dma_rx_channel)
660
-
return;
663
+
drv_data->dma_rx_channel = dma_request_chan(dev, "rx");
664
+
if (IS_ERR(drv_data->dma_rx_channel))
665
+
return dev_err_probe(dev, PTR_ERR(drv_data->dma_rx_channel),
666
+
"rx DMA setup failed\n");
661
667
662
-
drv_data->dma_tx_data.port = EP93XX_DMA_IDE;
663
-
drv_data->dma_tx_data.direction = DMA_MEM_TO_DEV;
664
-
drv_data->dma_tx_data.name = "ep93xx-pata-tx";
665
-
drv_data->dma_tx_channel = dma_request_channel(mask,
666
-
ep93xx_pata_dma_filter, &drv_data->dma_tx_data);
667
-
if (!drv_data->dma_tx_channel) {
668
-
dma_release_channel(drv_data->dma_rx_channel);
669
-
return;
668
+
drv_data->dma_tx_channel = dma_request_chan(&pdev->dev, "tx");
669
+
if (IS_ERR(drv_data->dma_tx_channel)) {
670
+
ret = dev_err_probe(dev, PTR_ERR(drv_data->dma_tx_channel),
671
+
"tx DMA setup failed\n");
672
+
goto fail_release_rx;
670
673
}
671
674
672
675
/* Configure receive channel direction and source address */
···
668
683
conf.direction = DMA_DEV_TO_MEM;
669
684
conf.src_addr = drv_data->udma_in_phys;
670
685
conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
671
-
if (dmaengine_slave_config(drv_data->dma_rx_channel, &conf)) {
672
-
dev_err(&pdev->dev, "failed to configure rx dma channel\n");
673
-
ep93xx_pata_release_dma(drv_data);
674
-
return;
686
+
ret = dmaengine_slave_config(drv_data->dma_rx_channel, &conf);
687
+
if (ret) {
688
+
dev_err_probe(dev, ret, "failed to configure rx dma channel");
689
+
goto fail_release_dma;
675
690
}
676
691
677
692
/* Configure transmit channel direction and destination address */
···
679
694
conf.direction = DMA_MEM_TO_DEV;
680
695
conf.dst_addr = drv_data->udma_out_phys;
681
696
conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
682
-
if (dmaengine_slave_config(drv_data->dma_tx_channel, &conf)) {
683
-
dev_err(&pdev->dev, "failed to configure tx dma channel\n");
684
-
ep93xx_pata_release_dma(drv_data);
697
+
ret = dmaengine_slave_config(drv_data->dma_tx_channel, &conf);
698
+
if (ret) {
699
+
dev_err_probe(dev, ret, "failed to configure tx dma channel");
700
+
goto fail_release_dma;
685
701
}
702
+
703
+
return 0;
704
+
705
+
fail_release_rx:
706
+
dma_release_channel(drv_data->dma_rx_channel);
707
+
fail_release_dma:
708
+
ep93xx_pata_release_dma(drv_data);
709
+
710
+
return ret;
686
711
}
687
712
688
713
static void ep93xx_pata_dma_start(struct ata_queued_cmd *qc)
···
920
925
void __iomem *ide_base;
921
926
int err;
922
927
923
-
err = ep93xx_ide_acquire_gpio(pdev);
924
-
if (err)
925
-
return err;
926
-
927
928
/* INT[3] (IRQ_EP93XX_EXT3) line connected as pull down */
928
929
irq = platform_get_irq(pdev, 0);
929
-
if (irq < 0) {
930
-
err = irq;
931
-
goto err_rel_gpio;
932
-
}
930
+
if (irq < 0)
931
+
return irq;
933
932
934
933
ide_base = devm_platform_get_and_ioremap_resource(pdev, 0, &mem_res);
935
-
if (IS_ERR(ide_base)) {
936
-
err = PTR_ERR(ide_base);
937
-
goto err_rel_gpio;
938
-
}
934
+
if (IS_ERR(ide_base))
935
+
return PTR_ERR(ide_base);
939
936
940
937
drv_data = devm_kzalloc(&pdev->dev, sizeof(*drv_data), GFP_KERNEL);
941
-
if (!drv_data) {
942
-
err = -ENOMEM;
943
-
goto err_rel_gpio;
944
-
}
938
+
if (!drv_data)
939
+
return -ENOMEM;
945
940
946
941
drv_data->pdev = pdev;
947
942
drv_data->ide_base = ide_base;
948
943
drv_data->udma_in_phys = mem_res->start + IDEUDMADATAIN;
949
944
drv_data->udma_out_phys = mem_res->start + IDEUDMADATAOUT;
950
-
ep93xx_pata_dma_init(drv_data);
945
+
err = ep93xx_pata_dma_init(drv_data);
946
+
if (err)
947
+
return err;
951
948
952
949
/* allocate host */
953
950
host = ata_host_alloc(&pdev->dev, 1);
···
990
1003
991
1004
err_rel_dma:
992
1005
ep93xx_pata_release_dma(drv_data);
993
-
err_rel_gpio:
994
-
ep93xx_ide_release_gpio(pdev);
995
1006
return err;
996
1007
}
997
1008
···
1001
1016
ata_host_detach(host);
1002
1017
ep93xx_pata_release_dma(drv_data);
1003
1018
ep93xx_pata_clear_regs(drv_data->ide_base);
1004
-
ep93xx_ide_release_gpio(pdev);
1005
1019
}
1020
+
1021
+
static const struct of_device_id ep93xx_pata_of_ids[] = {
1022
+
{ .compatible = "cirrus,ep9312-pata" },
1023
+
{ /* sentinel */ }
1024
+
};
1025
+
MODULE_DEVICE_TABLE(of, ep93xx_pata_of_ids);
1006
1026
1007
1027
static struct platform_driver ep93xx_pata_platform_driver = {
1008
1028
.driver = {
1009
1029
.name = DRV_NAME,
1030
+
.of_match_table = ep93xx_pata_of_ids,
1010
1031
},
1011
1032
.probe = ep93xx_pata_probe,
1012
1033
.remove_new = ep93xx_pata_remove,
+8
drivers/clk/Kconfig
+8
drivers/clk/Kconfig
···
218
218
This driver provides the fixed clocks and gates present on Airoha
219
219
ARM silicon.
220
220
221
+
config COMMON_CLK_EP93XX
222
+
tristate "Clock driver for Cirrus Logic ep93xx SoC"
223
+
depends on ARCH_EP93XX || COMPILE_TEST
224
+
select AUXILIARY_BUS
225
+
select REGMAP_MMIO
226
+
help
227
+
This driver supports the SoC clocks on the Cirrus Logic ep93xx.
228
+
221
229
config COMMON_CLK_FSL_FLEXSPI
222
230
tristate "Clock driver for FlexSPI on Layerscape SoCs"
223
231
depends on ARCH_LAYERSCAPE || COMPILE_TEST
+1
drivers/clk/Makefile
+1
drivers/clk/Makefile
···
39
39
obj-$(CONFIG_COMMON_CLK_CDCE925) += clk-cdce925.o
40
40
obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o
41
41
obj-$(CONFIG_COMMON_CLK_CS2000_CP) += clk-cs2000-cp.o
42
+
obj-$(CONFIG_COMMON_CLK_EP93XX) += clk-ep93xx.o
42
43
obj-$(CONFIG_ARCH_SPARX5) += clk-sparx5.o
43
44
obj-$(CONFIG_COMMON_CLK_EN7523) += clk-en7523.o
44
45
obj-$(CONFIG_COMMON_CLK_FIXED_MMIO) += clk-fixed-mmio.o
+850
drivers/clk/clk-ep93xx.c
+850
drivers/clk/clk-ep93xx.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-or-later
2
+
/*
3
+
* Clock control for Cirrus EP93xx chips.
4
+
* Copyright (C) 2021 Nikita Shubin <nikita.shubin@maquefel.me>
5
+
*
6
+
* Based on a rewrite of arch/arm/mach-ep93xx/clock.c:
7
+
* Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
8
+
*/
9
+
#define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt
10
+
11
+
#include <linux/bits.h>
12
+
#include <linux/cleanup.h>
13
+
#include <linux/clk-provider.h>
14
+
#include <linux/math.h>
15
+
#include <linux/platform_device.h>
16
+
#include <linux/regmap.h>
17
+
#include <linux/spinlock.h>
18
+
19
+
#include <linux/soc/cirrus/ep93xx.h>
20
+
#include <dt-bindings/clock/cirrus,ep9301-syscon.h>
21
+
22
+
#include <asm/div64.h>
23
+
24
+
#define EP93XX_EXT_CLK_RATE 14745600
25
+
#define EP93XX_EXT_RTC_RATE 32768
26
+
27
+
#define EP93XX_SYSCON_POWER_STATE 0x00
28
+
#define EP93XX_SYSCON_PWRCNT 0x04
29
+
#define EP93XX_SYSCON_PWRCNT_UARTBAUD BIT(29)
30
+
#define EP93XX_SYSCON_PWRCNT_USH_EN 28
31
+
#define EP93XX_SYSCON_PWRCNT_DMA_M2M1 27
32
+
#define EP93XX_SYSCON_PWRCNT_DMA_M2M0 26
33
+
#define EP93XX_SYSCON_PWRCNT_DMA_M2P8 25
34
+
#define EP93XX_SYSCON_PWRCNT_DMA_M2P9 24
35
+
#define EP93XX_SYSCON_PWRCNT_DMA_M2P6 23
36
+
#define EP93XX_SYSCON_PWRCNT_DMA_M2P7 22
37
+
#define EP93XX_SYSCON_PWRCNT_DMA_M2P4 21
38
+
#define EP93XX_SYSCON_PWRCNT_DMA_M2P5 20
39
+
#define EP93XX_SYSCON_PWRCNT_DMA_M2P2 19
40
+
#define EP93XX_SYSCON_PWRCNT_DMA_M2P3 18
41
+
#define EP93XX_SYSCON_PWRCNT_DMA_M2P0 17
42
+
#define EP93XX_SYSCON_PWRCNT_DMA_M2P1 16
43
+
#define EP93XX_SYSCON_CLKSET1 0x20
44
+
#define EP93XX_SYSCON_CLKSET1_NBYP1 BIT(23)
45
+
#define EP93XX_SYSCON_CLKSET2 0x24
46
+
#define EP93XX_SYSCON_CLKSET2_NBYP2 BIT(19)
47
+
#define EP93XX_SYSCON_CLKSET2_PLL2_EN BIT(18)
48
+
#define EP93XX_SYSCON_DEVCFG 0x80
49
+
#define EP93XX_SYSCON_DEVCFG_U3EN 24
50
+
#define EP93XX_SYSCON_DEVCFG_U2EN 20
51
+
#define EP93XX_SYSCON_DEVCFG_U1EN 18
52
+
#define EP93XX_SYSCON_VIDCLKDIV 0x84
53
+
#define EP93XX_SYSCON_CLKDIV_ENABLE 15
54
+
#define EP93XX_SYSCON_CLKDIV_ESEL BIT(14)
55
+
#define EP93XX_SYSCON_CLKDIV_PSEL BIT(13)
56
+
#define EP93XX_SYSCON_CLKDIV_MASK GENMASK(14, 13)
57
+
#define EP93XX_SYSCON_CLKDIV_PDIV_SHIFT 8
58
+
#define EP93XX_SYSCON_I2SCLKDIV 0x8c
59
+
#define EP93XX_SYSCON_I2SCLKDIV_SENA 31
60
+
#define EP93XX_SYSCON_I2SCLKDIV_ORIDE BIT(29)
61
+
#define EP93XX_SYSCON_I2SCLKDIV_SPOL BIT(19)
62
+
#define EP93XX_SYSCON_KEYTCHCLKDIV 0x90
63
+
#define EP93XX_SYSCON_KEYTCHCLKDIV_TSEN 31
64
+
#define EP93XX_SYSCON_KEYTCHCLKDIV_ADIV 16
65
+
#define EP93XX_SYSCON_KEYTCHCLKDIV_KEN 15
66
+
#define EP93XX_SYSCON_KEYTCHCLKDIV_KDIV 0
67
+
#define EP93XX_SYSCON_CHIPID 0x94
68
+
#define EP93XX_SYSCON_CHIPID_ID 0x9213
69
+
70
+
#define EP93XX_FIXED_CLK_COUNT 21
71
+
72
+
static const char ep93xx_adc_divisors[] = { 16, 4 };
73
+
static const char ep93xx_sclk_divisors[] = { 2, 4 };
74
+
static const char ep93xx_lrclk_divisors[] = { 32, 64, 128 };
75
+
76
+
struct ep93xx_clk {
77
+
struct clk_hw hw;
78
+
u16 idx;
79
+
u16 reg;
80
+
u32 mask;
81
+
u8 bit_idx;
82
+
u8 shift;
83
+
u8 width;
84
+
u8 num_div;
85
+
const char *div;
86
+
};
87
+
88
+
struct ep93xx_clk_priv {
89
+
spinlock_t lock;
90
+
struct ep93xx_regmap_adev *aux_dev;
91
+
struct device *dev;
92
+
void __iomem *base;
93
+
struct regmap *map;
94
+
struct clk_hw *fixed[EP93XX_FIXED_CLK_COUNT];
95
+
struct ep93xx_clk reg[];
96
+
};
97
+
98
+
static struct ep93xx_clk *ep93xx_clk_from(struct clk_hw *hw)
99
+
{
100
+
return container_of(hw, struct ep93xx_clk, hw);
101
+
}
102
+
103
+
static struct ep93xx_clk_priv *ep93xx_priv_from(struct ep93xx_clk *clk)
104
+
{
105
+
return container_of(clk, struct ep93xx_clk_priv, reg[clk->idx]);
106
+
}
107
+
108
+
static void ep93xx_clk_write(struct ep93xx_clk_priv *priv, unsigned int reg, unsigned int val)
109
+
{
110
+
struct ep93xx_regmap_adev *aux = priv->aux_dev;
111
+
112
+
aux->write(aux->map, aux->lock, reg, val);
113
+
}
114
+
115
+
static int ep93xx_clk_is_enabled(struct clk_hw *hw)
116
+
{
117
+
struct ep93xx_clk *clk = ep93xx_clk_from(hw);
118
+
struct ep93xx_clk_priv *priv = ep93xx_priv_from(clk);
119
+
u32 val;
120
+
121
+
regmap_read(priv->map, clk->reg, &val);
122
+
123
+
return !!(val & BIT(clk->bit_idx));
124
+
}
125
+
126
+
static int ep93xx_clk_enable(struct clk_hw *hw)
127
+
{
128
+
struct ep93xx_clk *clk = ep93xx_clk_from(hw);
129
+
struct ep93xx_clk_priv *priv = ep93xx_priv_from(clk);
130
+
u32 val;
131
+
132
+
guard(spinlock_irqsave)(&priv->lock);
133
+
134
+
regmap_read(priv->map, clk->reg, &val);
135
+
val |= BIT(clk->bit_idx);
136
+
137
+
ep93xx_clk_write(priv, clk->reg, val);
138
+
139
+
return 0;
140
+
}
141
+
142
+
static void ep93xx_clk_disable(struct clk_hw *hw)
143
+
{
144
+
struct ep93xx_clk *clk = ep93xx_clk_from(hw);
145
+
struct ep93xx_clk_priv *priv = ep93xx_priv_from(clk);
146
+
u32 val;
147
+
148
+
guard(spinlock_irqsave)(&priv->lock);
149
+
150
+
regmap_read(priv->map, clk->reg, &val);
151
+
val &= ~BIT(clk->bit_idx);
152
+
153
+
ep93xx_clk_write(priv, clk->reg, val);
154
+
}
155
+
156
+
static const struct clk_ops clk_ep93xx_gate_ops = {
157
+
.enable = ep93xx_clk_enable,
158
+
.disable = ep93xx_clk_disable,
159
+
.is_enabled = ep93xx_clk_is_enabled,
160
+
};
161
+
162
+
static int ep93xx_clk_register_gate(struct ep93xx_clk *clk,
163
+
const char *name,
164
+
struct clk_parent_data *parent_data,
165
+
unsigned long flags,
166
+
unsigned int reg,
167
+
u8 bit_idx)
168
+
{
169
+
struct ep93xx_clk_priv *priv = ep93xx_priv_from(clk);
170
+
struct clk_init_data init = { };
171
+
172
+
init.name = name;
173
+
init.ops = &clk_ep93xx_gate_ops;
174
+
init.flags = flags;
175
+
init.parent_data = parent_data;
176
+
init.num_parents = 1;
177
+
178
+
clk->reg = reg;
179
+
clk->bit_idx = bit_idx;
180
+
clk->hw.init = &init;
181
+
182
+
return devm_clk_hw_register(priv->dev, &clk->hw);
183
+
}
184
+
185
+
static u8 ep93xx_mux_get_parent(struct clk_hw *hw)
186
+
{
187
+
struct ep93xx_clk *clk = ep93xx_clk_from(hw);
188
+
struct ep93xx_clk_priv *priv = ep93xx_priv_from(clk);
189
+
u32 val;
190
+
191
+
regmap_read(priv->map, clk->reg, &val);
192
+
193
+
val &= EP93XX_SYSCON_CLKDIV_MASK;
194
+
195
+
switch (val) {
196
+
case EP93XX_SYSCON_CLKDIV_ESEL:
197
+
return 1; /* PLL1 */
198
+
case EP93XX_SYSCON_CLKDIV_MASK:
199
+
return 2; /* PLL2 */
200
+
default:
201
+
return 0; /* XTALI */
202
+
};
203
+
}
204
+
205
+
static int ep93xx_mux_set_parent_lock(struct clk_hw *hw, u8 index)
206
+
{
207
+
struct ep93xx_clk *clk = ep93xx_clk_from(hw);
208
+
struct ep93xx_clk_priv *priv = ep93xx_priv_from(clk);
209
+
u32 val;
210
+
211
+
if (index >= 3)
212
+
return -EINVAL;
213
+
214
+
guard(spinlock_irqsave)(&priv->lock);
215
+
216
+
regmap_read(priv->map, clk->reg, &val);
217
+
val &= ~(EP93XX_SYSCON_CLKDIV_MASK);
218
+
val |= index > 0 ? EP93XX_SYSCON_CLKDIV_ESEL : 0;
219
+
val |= index > 1 ? EP93XX_SYSCON_CLKDIV_PSEL : 0;
220
+
221
+
ep93xx_clk_write(priv, clk->reg, val);
222
+
223
+
return 0;
224
+
}
225
+
226
+
static bool is_best(unsigned long rate, unsigned long now,
227
+
unsigned long best)
228
+
{
229
+
return abs_diff(rate, now) < abs_diff(rate, best);
230
+
}
231
+
232
+
static int ep93xx_mux_determine_rate(struct clk_hw *hw,
233
+
struct clk_rate_request *req)
234
+
{
235
+
unsigned long best_rate = 0, actual_rate, mclk_rate;
236
+
unsigned long rate = req->rate;
237
+
struct clk_hw *parent_best = NULL;
238
+
unsigned long parent_rate_best;
239
+
unsigned long parent_rate;
240
+
int div, pdiv;
241
+
unsigned int i;
242
+
243
+
/*
244
+
* Try the two pll's and the external clock,
245
+
* because the valid predividers are 2, 2.5 and 3, we multiply
246
+
* all the clocks by 2 to avoid floating point math.
247
+
*
248
+
* This is based on the algorithm in the ep93xx raster guide:
249
+
* http://be-a-maverick.com/en/pubs/appNote/AN269REV1.pdf
250
+
*
251
+
*/
252
+
for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
253
+
struct clk_hw *parent = clk_hw_get_parent_by_index(hw, i);
254
+
255
+
parent_rate = clk_hw_get_rate(parent);
256
+
mclk_rate = parent_rate * 2;
257
+
258
+
/* Try each predivider value */
259
+
for (pdiv = 4; pdiv <= 6; pdiv++) {
260
+
div = DIV_ROUND_CLOSEST(mclk_rate, rate * pdiv);
261
+
if (!in_range(div, 1, 127))
262
+
continue;
263
+
264
+
actual_rate = DIV_ROUND_CLOSEST(mclk_rate, pdiv * div);
265
+
if (is_best(rate, actual_rate, best_rate)) {
266
+
best_rate = actual_rate;
267
+
parent_rate_best = parent_rate;
268
+
parent_best = parent;
269
+
}
270
+
}
271
+
}
272
+
273
+
if (!parent_best)
274
+
return -EINVAL;
275
+
276
+
req->best_parent_rate = parent_rate_best;
277
+
req->best_parent_hw = parent_best;
278
+
req->rate = best_rate;
279
+
280
+
return 0;
281
+
}
282
+
283
+
static unsigned long ep93xx_ddiv_recalc_rate(struct clk_hw *hw,
284
+
unsigned long parent_rate)
285
+
{
286
+
struct ep93xx_clk *clk = ep93xx_clk_from(hw);
287
+
struct ep93xx_clk_priv *priv = ep93xx_priv_from(clk);
288
+
unsigned int pdiv, div;
289
+
u32 val;
290
+
291
+
regmap_read(priv->map, clk->reg, &val);
292
+
pdiv = (val >> EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) & GENMASK(1, 0);
293
+
div = val & GENMASK(6, 0);
294
+
if (!div)
295
+
return 0;
296
+
297
+
return DIV_ROUND_CLOSEST(parent_rate * 2, (pdiv + 3) * div);
298
+
}
299
+
300
+
static int ep93xx_ddiv_set_rate(struct clk_hw *hw, unsigned long rate,
301
+
unsigned long parent_rate)
302
+
{
303
+
struct ep93xx_clk *clk = ep93xx_clk_from(hw);
304
+
struct ep93xx_clk_priv *priv = ep93xx_priv_from(clk);
305
+
int pdiv, div, npdiv, ndiv;
306
+
unsigned long actual_rate, mclk_rate, rate_err = ULONG_MAX;
307
+
u32 val;
308
+
309
+
regmap_read(priv->map, clk->reg, &val);
310
+
mclk_rate = parent_rate * 2;
311
+
312
+
for (pdiv = 4; pdiv <= 6; pdiv++) {
313
+
div = DIV_ROUND_CLOSEST(mclk_rate, rate * pdiv);
314
+
if (!in_range(div, 1, 127))
315
+
continue;
316
+
317
+
actual_rate = DIV_ROUND_CLOSEST(mclk_rate, pdiv * div);
318
+
if (abs(actual_rate - rate) < rate_err) {
319
+
npdiv = pdiv - 3;
320
+
ndiv = div;
321
+
rate_err = abs(actual_rate - rate);
322
+
}
323
+
}
324
+
325
+
if (rate_err == ULONG_MAX)
326
+
return -EINVAL;
327
+
328
+
/*
329
+
* Clear old dividers.
330
+
* Bit 7 is reserved bit in all ClkDiv registers.
331
+
*/
332
+
val &= ~(GENMASK(9, 0) & ~BIT(7));
333
+
334
+
/* Set the new pdiv and div bits for the new clock rate */
335
+
val |= (npdiv << EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) | ndiv;
336
+
337
+
ep93xx_clk_write(priv, clk->reg, val);
338
+
339
+
return 0;
340
+
}
341
+
342
+
static const struct clk_ops clk_ddiv_ops = {
343
+
.enable = ep93xx_clk_enable,
344
+
.disable = ep93xx_clk_disable,
345
+
.is_enabled = ep93xx_clk_is_enabled,
346
+
.get_parent = ep93xx_mux_get_parent,
347
+
.set_parent = ep93xx_mux_set_parent_lock,
348
+
.determine_rate = ep93xx_mux_determine_rate,
349
+
.recalc_rate = ep93xx_ddiv_recalc_rate,
350
+
.set_rate = ep93xx_ddiv_set_rate,
351
+
};
352
+
353
+
static int ep93xx_clk_register_ddiv(struct ep93xx_clk *clk,
354
+
const char *name,
355
+
struct clk_parent_data *parent_data,
356
+
u8 num_parents,
357
+
unsigned int reg,
358
+
u8 bit_idx)
359
+
{
360
+
struct ep93xx_clk_priv *priv = ep93xx_priv_from(clk);
361
+
struct clk_init_data init = { };
362
+
363
+
init.name = name;
364
+
init.ops = &clk_ddiv_ops;
365
+
init.flags = 0;
366
+
init.parent_data = parent_data;
367
+
init.num_parents = num_parents;
368
+
369
+
clk->reg = reg;
370
+
clk->bit_idx = bit_idx;
371
+
clk->hw.init = &init;
372
+
373
+
return devm_clk_hw_register(priv->dev, &clk->hw);
374
+
}
375
+
376
+
static unsigned long ep93xx_div_recalc_rate(struct clk_hw *hw,
377
+
unsigned long parent_rate)
378
+
{
379
+
struct ep93xx_clk *clk = ep93xx_clk_from(hw);
380
+
struct ep93xx_clk_priv *priv = ep93xx_priv_from(clk);
381
+
u32 val;
382
+
u8 index;
383
+
384
+
regmap_read(priv->map, clk->reg, &val);
385
+
index = (val & clk->mask) >> clk->shift;
386
+
if (index >= clk->num_div)
387
+
return 0;
388
+
389
+
return DIV_ROUND_CLOSEST(parent_rate, clk->div[index]);
390
+
}
391
+
392
+
static long ep93xx_div_round_rate(struct clk_hw *hw, unsigned long rate,
393
+
unsigned long *parent_rate)
394
+
{
395
+
struct ep93xx_clk *clk = ep93xx_clk_from(hw);
396
+
unsigned long best = 0, now;
397
+
unsigned int i;
398
+
399
+
for (i = 0; i < clk->num_div; i++) {
400
+
if ((rate * clk->div[i]) == *parent_rate)
401
+
return rate;
402
+
403
+
now = DIV_ROUND_CLOSEST(*parent_rate, clk->div[i]);
404
+
if (!best || is_best(rate, now, best))
405
+
best = now;
406
+
}
407
+
408
+
return best;
409
+
}
410
+
411
+
static int ep93xx_div_set_rate(struct clk_hw *hw, unsigned long rate,
412
+
unsigned long parent_rate)
413
+
{
414
+
struct ep93xx_clk *clk = ep93xx_clk_from(hw);
415
+
struct ep93xx_clk_priv *priv = ep93xx_priv_from(clk);
416
+
unsigned int i;
417
+
u32 val;
418
+
419
+
regmap_read(priv->map, clk->reg, &val);
420
+
val &= ~clk->mask;
421
+
for (i = 0; i < clk->num_div; i++)
422
+
if (rate == DIV_ROUND_CLOSEST(parent_rate, clk->div[i]))
423
+
break;
424
+
425
+
if (i == clk->num_div)
426
+
return -EINVAL;
427
+
428
+
val |= i << clk->shift;
429
+
430
+
ep93xx_clk_write(priv, clk->reg, val);
431
+
432
+
return 0;
433
+
}
434
+
435
+
static const struct clk_ops ep93xx_div_ops = {
436
+
.enable = ep93xx_clk_enable,
437
+
.disable = ep93xx_clk_disable,
438
+
.is_enabled = ep93xx_clk_is_enabled,
439
+
.recalc_rate = ep93xx_div_recalc_rate,
440
+
.round_rate = ep93xx_div_round_rate,
441
+
.set_rate = ep93xx_div_set_rate,
442
+
};
443
+
444
+
static int ep93xx_register_div(struct ep93xx_clk *clk,
445
+
const char *name,
446
+
const struct clk_parent_data *parent_data,
447
+
unsigned int reg,
448
+
u8 enable_bit,
449
+
u8 shift,
450
+
u8 width,
451
+
const char *clk_divisors,
452
+
u8 num_div)
453
+
{
454
+
struct ep93xx_clk_priv *priv = ep93xx_priv_from(clk);
455
+
struct clk_init_data init = { };
456
+
457
+
init.name = name;
458
+
init.ops = &ep93xx_div_ops;
459
+
init.flags = 0;
460
+
init.parent_data = parent_data;
461
+
init.num_parents = 1;
462
+
463
+
clk->reg = reg;
464
+
clk->bit_idx = enable_bit;
465
+
clk->mask = GENMASK(shift + width - 1, shift);
466
+
clk->shift = shift;
467
+
clk->div = clk_divisors;
468
+
clk->num_div = num_div;
469
+
clk->hw.init = &init;
470
+
471
+
return devm_clk_hw_register(priv->dev, &clk->hw);
472
+
}
473
+
474
+
struct ep93xx_gate {
475
+
unsigned int idx;
476
+
unsigned int bit;
477
+
const char *name;
478
+
};
479
+
480
+
static const struct ep93xx_gate ep93xx_uarts[] = {
481
+
{ EP93XX_CLK_UART1, EP93XX_SYSCON_DEVCFG_U1EN, "uart1" },
482
+
{ EP93XX_CLK_UART2, EP93XX_SYSCON_DEVCFG_U2EN, "uart2" },
483
+
{ EP93XX_CLK_UART3, EP93XX_SYSCON_DEVCFG_U3EN, "uart3" },
484
+
};
485
+
486
+
static int ep93xx_uart_clock_init(struct ep93xx_clk_priv *priv)
487
+
{
488
+
struct clk_parent_data parent_data = { };
489
+
unsigned int i, idx, ret, clk_uart_div;
490
+
struct ep93xx_clk *clk;
491
+
u32 val;
492
+
493
+
regmap_read(priv->map, EP93XX_SYSCON_PWRCNT, &val);
494
+
if (val & EP93XX_SYSCON_PWRCNT_UARTBAUD)
495
+
clk_uart_div = 1;
496
+
else
497
+
clk_uart_div = 2;
498
+
499
+
priv->fixed[EP93XX_CLK_UART] =
500
+
devm_clk_hw_register_fixed_factor_index(priv->dev, "uart",
501
+
0, /* XTALI external clock */
502
+
0, 1, clk_uart_div);
503
+
parent_data.hw = priv->fixed[EP93XX_CLK_UART];
504
+
505
+
/* parenting uart gate clocks to uart clock */
506
+
for (i = 0; i < ARRAY_SIZE(ep93xx_uarts); i++) {
507
+
idx = ep93xx_uarts[i].idx - EP93XX_CLK_UART1;
508
+
clk = &priv->reg[idx];
509
+
clk->idx = idx;
510
+
ret = ep93xx_clk_register_gate(clk,
511
+
ep93xx_uarts[i].name,
512
+
&parent_data, CLK_SET_RATE_PARENT,
513
+
EP93XX_SYSCON_DEVCFG,
514
+
ep93xx_uarts[i].bit);
515
+
if (ret)
516
+
return dev_err_probe(priv->dev, ret,
517
+
"failed to register uart[%d] clock\n", i);
518
+
}
519
+
520
+
return 0;
521
+
}
522
+
523
+
static const struct ep93xx_gate ep93xx_dmas[] = {
524
+
{ EP93XX_CLK_M2M0, EP93XX_SYSCON_PWRCNT_DMA_M2M0, "m2m0" },
525
+
{ EP93XX_CLK_M2M1, EP93XX_SYSCON_PWRCNT_DMA_M2M1, "m2m1" },
526
+
{ EP93XX_CLK_M2P0, EP93XX_SYSCON_PWRCNT_DMA_M2P0, "m2p0" },
527
+
{ EP93XX_CLK_M2P1, EP93XX_SYSCON_PWRCNT_DMA_M2P1, "m2p1" },
528
+
{ EP93XX_CLK_M2P2, EP93XX_SYSCON_PWRCNT_DMA_M2P2, "m2p2" },
529
+
{ EP93XX_CLK_M2P3, EP93XX_SYSCON_PWRCNT_DMA_M2P3, "m2p3" },
530
+
{ EP93XX_CLK_M2P4, EP93XX_SYSCON_PWRCNT_DMA_M2P4, "m2p4" },
531
+
{ EP93XX_CLK_M2P5, EP93XX_SYSCON_PWRCNT_DMA_M2P5, "m2p5" },
532
+
{ EP93XX_CLK_M2P6, EP93XX_SYSCON_PWRCNT_DMA_M2P6, "m2p6" },
533
+
{ EP93XX_CLK_M2P7, EP93XX_SYSCON_PWRCNT_DMA_M2P7, "m2p7" },
534
+
{ EP93XX_CLK_M2P8, EP93XX_SYSCON_PWRCNT_DMA_M2P8, "m2p8" },
535
+
{ EP93XX_CLK_M2P9, EP93XX_SYSCON_PWRCNT_DMA_M2P9, "m2p9" },
536
+
};
537
+
538
+
static int ep93xx_dma_clock_init(struct ep93xx_clk_priv *priv)
539
+
{
540
+
struct clk_parent_data parent_data = { };
541
+
unsigned int i, idx;
542
+
543
+
parent_data.hw = priv->fixed[EP93XX_CLK_HCLK];
544
+
for (i = 0; i < ARRAY_SIZE(ep93xx_dmas); i++) {
545
+
idx = ep93xx_dmas[i].idx;
546
+
priv->fixed[idx] = devm_clk_hw_register_gate_parent_data(priv->dev,
547
+
ep93xx_dmas[i].name,
548
+
&parent_data, 0,
549
+
priv->base + EP93XX_SYSCON_PWRCNT,
550
+
ep93xx_dmas[i].bit,
551
+
0,
552
+
&priv->lock);
553
+
if (IS_ERR(priv->fixed[idx]))
554
+
return PTR_ERR(priv->fixed[idx]);
555
+
}
556
+
557
+
return 0;
558
+
}
559
+
560
+
static struct clk_hw *of_clk_ep93xx_get(struct of_phandle_args *clkspec, void *data)
561
+
{
562
+
struct ep93xx_clk_priv *priv = data;
563
+
unsigned int idx = clkspec->args[0];
564
+
565
+
if (idx < EP93XX_CLK_UART1)
566
+
return priv->fixed[idx];
567
+
568
+
if (idx <= EP93XX_CLK_I2S_LRCLK)
569
+
return &priv->reg[idx - EP93XX_CLK_UART1].hw;
570
+
571
+
return ERR_PTR(-EINVAL);
572
+
}
573
+
574
+
/*
575
+
* PLL rate = 14.7456 MHz * (X1FBD + 1) * (X2FBD + 1) / (X2IPD + 1) / 2^PS
576
+
*/
577
+
static unsigned long calc_pll_rate(u64 rate, u32 config_word)
578
+
{
579
+
rate *= ((config_word >> 11) & GENMASK(4, 0)) + 1; /* X1FBD */
580
+
rate *= ((config_word >> 5) & GENMASK(5, 0)) + 1; /* X2FBD */
581
+
do_div(rate, (config_word & GENMASK(4, 0)) + 1); /* X2IPD */
582
+
rate >>= (config_word >> 16) & GENMASK(1, 0); /* PS */
583
+
584
+
return rate;
585
+
}
586
+
587
+
static int ep93xx_plls_init(struct ep93xx_clk_priv *priv)
588
+
{
589
+
const char fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };
590
+
const char hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 };
591
+
const char pclk_divisors[] = { 1, 2, 4, 8 };
592
+
struct clk_parent_data xtali = { .index = 0 };
593
+
unsigned int clk_f_div, clk_h_div, clk_p_div;
594
+
unsigned long clk_pll1_rate, clk_pll2_rate;
595
+
struct device *dev = priv->dev;
596
+
struct clk_hw *hw, *pll1;
597
+
u32 value;
598
+
599
+
/* Determine the bootloader configured pll1 rate */
600
+
regmap_read(priv->map, EP93XX_SYSCON_CLKSET1, &value);
601
+
602
+
if (value & EP93XX_SYSCON_CLKSET1_NBYP1)
603
+
clk_pll1_rate = calc_pll_rate(EP93XX_EXT_CLK_RATE, value);
604
+
else
605
+
clk_pll1_rate = EP93XX_EXT_CLK_RATE;
606
+
607
+
pll1 = devm_clk_hw_register_fixed_rate_parent_data(dev, "pll1", &xtali,
608
+
0, clk_pll1_rate);
609
+
if (IS_ERR(pll1))
610
+
return PTR_ERR(pll1);
611
+
612
+
priv->fixed[EP93XX_CLK_PLL1] = pll1;
613
+
614
+
/* Initialize the pll1 derived clocks */
615
+
clk_f_div = fclk_divisors[(value >> 25) & GENMASK(2, 0)];
616
+
clk_h_div = hclk_divisors[(value >> 20) & GENMASK(2, 0)];
617
+
clk_p_div = pclk_divisors[(value >> 18) & GENMASK(1, 0)];
618
+
619
+
hw = devm_clk_hw_register_fixed_factor_parent_hw(dev, "fclk", pll1, 0, 1, clk_f_div);
620
+
if (IS_ERR(hw))
621
+
return PTR_ERR(hw);
622
+
623
+
priv->fixed[EP93XX_CLK_FCLK] = hw;
624
+
625
+
hw = devm_clk_hw_register_fixed_factor_parent_hw(dev, "hclk", pll1, 0, 1, clk_h_div);
626
+
if (IS_ERR(hw))
627
+
return PTR_ERR(hw);
628
+
629
+
priv->fixed[EP93XX_CLK_HCLK] = hw;
630
+
631
+
hw = devm_clk_hw_register_fixed_factor_parent_hw(dev, "pclk", hw, 0, 1, clk_p_div);
632
+
if (IS_ERR(hw))
633
+
return PTR_ERR(hw);
634
+
635
+
priv->fixed[EP93XX_CLK_PCLK] = hw;
636
+
637
+
/* Determine the bootloader configured pll2 rate */
638
+
regmap_read(priv->map, EP93XX_SYSCON_CLKSET2, &value);
639
+
if (!(value & EP93XX_SYSCON_CLKSET2_NBYP2))
640
+
clk_pll2_rate = EP93XX_EXT_CLK_RATE;
641
+
else if (value & EP93XX_SYSCON_CLKSET2_PLL2_EN)
642
+
clk_pll2_rate = calc_pll_rate(EP93XX_EXT_CLK_RATE, value);
643
+
else
644
+
clk_pll2_rate = 0;
645
+
646
+
hw = devm_clk_hw_register_fixed_rate_parent_data(dev, "pll2", &xtali,
647
+
0, clk_pll2_rate);
648
+
if (IS_ERR(hw))
649
+
return PTR_ERR(hw);
650
+
651
+
priv->fixed[EP93XX_CLK_PLL2] = hw;
652
+
653
+
return 0;
654
+
}
655
+
656
+
static int ep93xx_clk_probe(struct auxiliary_device *adev,
657
+
const struct auxiliary_device_id *id)
658
+
{
659
+
struct ep93xx_regmap_adev *rdev = to_ep93xx_regmap_adev(adev);
660
+
struct clk_parent_data xtali = { .index = 0 };
661
+
struct clk_parent_data ddiv_pdata[3] = { };
662
+
unsigned int clk_spi_div, clk_usb_div;
663
+
struct clk_parent_data pdata = {};
664
+
struct device *dev = &adev->dev;
665
+
struct ep93xx_clk_priv *priv;
666
+
struct ep93xx_clk *clk;
667
+
struct clk_hw *hw;
668
+
unsigned int idx;
669
+
int ret;
670
+
u32 value;
671
+
672
+
priv = devm_kzalloc(dev, struct_size(priv, reg, 10), GFP_KERNEL);
673
+
if (!priv)
674
+
return -ENOMEM;
675
+
676
+
spin_lock_init(&priv->lock);
677
+
priv->dev = dev;
678
+
priv->aux_dev = rdev;
679
+
priv->map = rdev->map;
680
+
priv->base = rdev->base;
681
+
682
+
ret = ep93xx_plls_init(priv);
683
+
if (ret)
684
+
return ret;
685
+
686
+
regmap_read(priv->map, EP93XX_SYSCON_CLKSET2, &value);
687
+
clk_usb_div = (value >> 28 & GENMASK(3, 0)) + 1;
688
+
hw = devm_clk_hw_register_fixed_factor_parent_hw(dev, "usb_clk",
689
+
priv->fixed[EP93XX_CLK_PLL2], 0, 1,
690
+
clk_usb_div);
691
+
if (IS_ERR(hw))
692
+
return PTR_ERR(hw);
693
+
694
+
priv->fixed[EP93XX_CLK_USB] = hw;
695
+
696
+
ret = ep93xx_uart_clock_init(priv);
697
+
if (ret)
698
+
return ret;
699
+
700
+
ret = ep93xx_dma_clock_init(priv);
701
+
if (ret)
702
+
return ret;
703
+
704
+
clk_spi_div = id->driver_data;
705
+
hw = devm_clk_hw_register_fixed_factor_index(dev, "ep93xx-spi.0",
706
+
0, /* XTALI external clock */
707
+
0, 1, clk_spi_div);
708
+
if (IS_ERR(hw))
709
+
return PTR_ERR(hw);
710
+
711
+
priv->fixed[EP93XX_CLK_SPI] = hw;
712
+
713
+
/* PWM clock */
714
+
hw = devm_clk_hw_register_fixed_factor_index(dev, "pwm_clk", 0, /* XTALI external clock */
715
+
0, 1, 1);
716
+
if (IS_ERR(hw))
717
+
return PTR_ERR(hw);
718
+
719
+
priv->fixed[EP93XX_CLK_PWM] = hw;
720
+
721
+
/* USB clock */
722
+
pdata.hw = priv->fixed[EP93XX_CLK_USB];
723
+
hw = devm_clk_hw_register_gate_parent_data(priv->dev, "ohci-platform", &pdata,
724
+
0, priv->base + EP93XX_SYSCON_PWRCNT,
725
+
EP93XX_SYSCON_PWRCNT_USH_EN, 0,
726
+
&priv->lock);
727
+
if (IS_ERR(hw))
728
+
return PTR_ERR(hw);
729
+
730
+
priv->fixed[EP93XX_CLK_USB] = hw;
731
+
732
+
ddiv_pdata[0].index = 0; /* XTALI external clock */
733
+
ddiv_pdata[1].hw = priv->fixed[EP93XX_CLK_PLL1];
734
+
ddiv_pdata[2].hw = priv->fixed[EP93XX_CLK_PLL2];
735
+
736
+
/* touchscreen/ADC clock */
737
+
idx = EP93XX_CLK_ADC - EP93XX_CLK_UART1;
738
+
clk = &priv->reg[idx];
739
+
clk->idx = idx;
740
+
ret = ep93xx_register_div(clk, "ep93xx-adc", &xtali,
741
+
EP93XX_SYSCON_KEYTCHCLKDIV,
742
+
EP93XX_SYSCON_KEYTCHCLKDIV_TSEN,
743
+
EP93XX_SYSCON_KEYTCHCLKDIV_ADIV,
744
+
1,
745
+
ep93xx_adc_divisors,
746
+
ARRAY_SIZE(ep93xx_adc_divisors));
747
+
748
+
749
+
/* keypad clock */
750
+
idx = EP93XX_CLK_KEYPAD - EP93XX_CLK_UART1;
751
+
clk = &priv->reg[idx];
752
+
clk->idx = idx;
753
+
ret = ep93xx_register_div(clk, "ep93xx-keypad", &xtali,
754
+
EP93XX_SYSCON_KEYTCHCLKDIV,
755
+
EP93XX_SYSCON_KEYTCHCLKDIV_KEN,
756
+
EP93XX_SYSCON_KEYTCHCLKDIV_KDIV,
757
+
1,
758
+
ep93xx_adc_divisors,
759
+
ARRAY_SIZE(ep93xx_adc_divisors));
760
+
761
+
/*
762
+
* On reset PDIV and VDIV is set to zero, while PDIV zero
763
+
* means clock disable, VDIV shouldn't be zero.
764
+
* So we set both video and i2s dividers to minimum.
765
+
* ENA - Enable CLK divider.
766
+
* PDIV - 00 - Disable clock
767
+
* VDIV - at least 2
768
+
*/
769
+
770
+
/* Check and enable video clk registers */
771
+
regmap_read(priv->map, EP93XX_SYSCON_VIDCLKDIV, &value);
772
+
value |= BIT(EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) | 2;
773
+
ep93xx_clk_write(priv, EP93XX_SYSCON_VIDCLKDIV, value);
774
+
775
+
/* Check and enable i2s clk registers */
776
+
regmap_read(priv->map, EP93XX_SYSCON_I2SCLKDIV, &value);
777
+
value |= BIT(EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) | 2;
778
+
779
+
/*
780
+
* Override the SAI_MSTR_CLK_CFG from the I2S block and use the
781
+
* I2SClkDiv Register settings. LRCLK transitions on the falling SCLK
782
+
* edge.
783
+
*/
784
+
value |= EP93XX_SYSCON_I2SCLKDIV_ORIDE | EP93XX_SYSCON_I2SCLKDIV_SPOL;
785
+
ep93xx_clk_write(priv, EP93XX_SYSCON_I2SCLKDIV, value);
786
+
787
+
/* video clk */
788
+
idx = EP93XX_CLK_VIDEO - EP93XX_CLK_UART1;
789
+
clk = &priv->reg[idx];
790
+
clk->idx = idx;
791
+
ret = ep93xx_clk_register_ddiv(clk, "ep93xx-fb",
792
+
ddiv_pdata, ARRAY_SIZE(ddiv_pdata),
793
+
EP93XX_SYSCON_VIDCLKDIV,
794
+
EP93XX_SYSCON_CLKDIV_ENABLE);
795
+
796
+
/* i2s clk */
797
+
idx = EP93XX_CLK_I2S_MCLK - EP93XX_CLK_UART1;
798
+
clk = &priv->reg[idx];
799
+
clk->idx = idx;
800
+
ret = ep93xx_clk_register_ddiv(clk, "mclk",
801
+
ddiv_pdata, ARRAY_SIZE(ddiv_pdata),
802
+
EP93XX_SYSCON_I2SCLKDIV,
803
+
EP93XX_SYSCON_CLKDIV_ENABLE);
804
+
805
+
/* i2s sclk */
806
+
idx = EP93XX_CLK_I2S_SCLK - EP93XX_CLK_UART1;
807
+
clk = &priv->reg[idx];
808
+
clk->idx = idx;
809
+
pdata.hw = &priv->reg[EP93XX_CLK_I2S_MCLK - EP93XX_CLK_UART1].hw;
810
+
ret = ep93xx_register_div(clk, "sclk", &pdata,
811
+
EP93XX_SYSCON_I2SCLKDIV,
812
+
EP93XX_SYSCON_I2SCLKDIV_SENA,
813
+
16, /* EP93XX_I2SCLKDIV_SDIV_SHIFT */
814
+
1, /* EP93XX_I2SCLKDIV_SDIV_WIDTH */
815
+
ep93xx_sclk_divisors,
816
+
ARRAY_SIZE(ep93xx_sclk_divisors));
817
+
818
+
/* i2s lrclk */
819
+
idx = EP93XX_CLK_I2S_LRCLK - EP93XX_CLK_UART1;
820
+
clk = &priv->reg[idx];
821
+
clk->idx = idx;
822
+
pdata.hw = &priv->reg[EP93XX_CLK_I2S_SCLK - EP93XX_CLK_UART1].hw;
823
+
ret = ep93xx_register_div(clk, "lrclk", &pdata,
824
+
EP93XX_SYSCON_I2SCLKDIV,
825
+
EP93XX_SYSCON_I2SCLKDIV_SENA,
826
+
17, /* EP93XX_I2SCLKDIV_LRDIV32_SHIFT */
827
+
2, /* EP93XX_I2SCLKDIV_LRDIV32_WIDTH */
828
+
ep93xx_lrclk_divisors,
829
+
ARRAY_SIZE(ep93xx_lrclk_divisors));
830
+
831
+
/* IrDa clk uses same pattern but no init code presents in original clock driver */
832
+
return devm_of_clk_add_hw_provider(priv->dev, of_clk_ep93xx_get, priv);
833
+
}
834
+
835
+
static const struct auxiliary_device_id ep93xx_clk_ids[] = {
836
+
{ .name = "soc_ep93xx.clk-ep93xx", .driver_data = 2, },
837
+
{ .name = "soc_ep93xx.clk-ep93xx.e2", .driver_data = 1, },
838
+
{ /* sentinel */ }
839
+
};
840
+
MODULE_DEVICE_TABLE(auxiliary, ep93xx_clk_ids);
841
+
842
+
static struct auxiliary_driver ep93xx_clk_driver = {
843
+
.probe = ep93xx_clk_probe,
844
+
.id_table = ep93xx_clk_ids,
845
+
};
846
+
module_auxiliary_driver(ep93xx_clk_driver);
847
+
848
+
MODULE_LICENSE("GPL");
849
+
MODULE_AUTHOR("Nikita Shubin <nikita.shubin@maquefel.me>");
850
+
MODULE_DESCRIPTION("Clock control for Cirrus EP93xx chips");
+231
-56
drivers/dma/ep93xx_dma.c
+231
-56
drivers/dma/ep93xx_dma.c
···
17
17
#include <linux/clk.h>
18
18
#include <linux/init.h>
19
19
#include <linux/interrupt.h>
20
+
#include <linux/dma-mapping.h>
20
21
#include <linux/dmaengine.h>
21
22
#include <linux/module.h>
22
23
#include <linux/mod_devicetable.h>
24
+
#include <linux/of_dma.h>
25
+
#include <linux/overflow.h>
23
26
#include <linux/platform_device.h>
24
27
#include <linux/slab.h>
25
-
26
-
#include <linux/platform_data/dma-ep93xx.h>
27
28
28
29
#include "dmaengine.h"
29
30
···
105
104
#define DMA_MAX_CHAN_BYTES 0xffff
106
105
#define DMA_MAX_CHAN_DESCRIPTORS 32
107
106
107
+
/*
108
+
* M2P channels.
109
+
*
110
+
* Note that these values are also directly used for setting the PPALLOC
111
+
* register.
112
+
*/
113
+
#define EP93XX_DMA_I2S1 0
114
+
#define EP93XX_DMA_I2S2 1
115
+
#define EP93XX_DMA_AAC1 2
116
+
#define EP93XX_DMA_AAC2 3
117
+
#define EP93XX_DMA_AAC3 4
118
+
#define EP93XX_DMA_I2S3 5
119
+
#define EP93XX_DMA_UART1 6
120
+
#define EP93XX_DMA_UART2 7
121
+
#define EP93XX_DMA_UART3 8
122
+
#define EP93XX_DMA_IRDA 9
123
+
/* M2M channels */
124
+
#define EP93XX_DMA_SSP 10
125
+
#define EP93XX_DMA_IDE 11
126
+
127
+
enum ep93xx_dma_type {
128
+
M2P_DMA,
129
+
M2M_DMA,
130
+
};
131
+
108
132
struct ep93xx_dma_engine;
109
133
static int ep93xx_dma_slave_config_write(struct dma_chan *chan,
110
134
enum dma_transfer_direction dir,
···
155
129
struct list_head node;
156
130
};
157
131
132
+
struct ep93xx_dma_chan_cfg {
133
+
u8 port;
134
+
enum dma_transfer_direction dir;
135
+
};
136
+
158
137
/**
159
138
* struct ep93xx_dma_chan - an EP93xx DMA M2P/M2M channel
160
139
* @chan: dmaengine API channel
161
140
* @edma: pointer to the engine device
162
141
* @regs: memory mapped registers
142
+
* @dma_cfg: channel number, direction
163
143
* @irq: interrupt number of the channel
164
144
* @clk: clock used by this channel
165
145
* @tasklet: channel specific tasklet used for callbacks
···
189
157
* descriptor in the chain. When a descriptor is moved to the @active queue,
190
158
* the first and chained descriptors are flattened into a single list.
191
159
*
192
-
* @chan.private holds pointer to &struct ep93xx_dma_data which contains
193
-
* necessary channel configuration information. For memcpy channels this must
194
-
* be %NULL.
195
160
*/
196
161
struct ep93xx_dma_chan {
197
162
struct dma_chan chan;
198
163
const struct ep93xx_dma_engine *edma;
199
164
void __iomem *regs;
165
+
struct ep93xx_dma_chan_cfg dma_cfg;
200
166
int irq;
201
167
struct clk *clk;
202
168
struct tasklet_struct tasklet;
···
246
216
struct ep93xx_dma_chan channels[] __counted_by(num_channels);
247
217
};
248
218
219
+
struct ep93xx_edma_data {
220
+
u32 id;
221
+
size_t num_channels;
222
+
};
223
+
249
224
static inline struct device *chan2dev(struct ep93xx_dma_chan *edmac)
250
225
{
251
226
return &edmac->chan.dev->device;
···
259
224
static struct ep93xx_dma_chan *to_ep93xx_dma_chan(struct dma_chan *chan)
260
225
{
261
226
return container_of(chan, struct ep93xx_dma_chan, chan);
227
+
}
228
+
229
+
static inline bool ep93xx_dma_chan_is_m2p(struct dma_chan *chan)
230
+
{
231
+
if (device_is_compatible(chan->device->dev, "cirrus,ep9301-dma-m2p"))
232
+
return true;
233
+
234
+
return !strcmp(dev_name(chan->device->dev), "ep93xx-dma-m2p");
235
+
}
236
+
237
+
/*
238
+
* ep93xx_dma_chan_direction - returns direction the channel can be used
239
+
*
240
+
* This function can be used in filter functions to find out whether the
241
+
* channel supports given DMA direction. Only M2P channels have such
242
+
* limitation, for M2M channels the direction is configurable.
243
+
*/
244
+
static inline enum dma_transfer_direction
245
+
ep93xx_dma_chan_direction(struct dma_chan *chan)
246
+
{
247
+
if (!ep93xx_dma_chan_is_m2p(chan))
248
+
return DMA_TRANS_NONE;
249
+
250
+
/* even channels are for TX, odd for RX */
251
+
return (chan->chan_id % 2 == 0) ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
262
252
}
263
253
264
254
/**
···
378
318
379
319
static int m2p_hw_setup(struct ep93xx_dma_chan *edmac)
380
320
{
381
-
struct ep93xx_dma_data *data = edmac->chan.private;
382
321
u32 control;
383
322
384
-
writel(data->port & 0xf, edmac->regs + M2P_PPALLOC);
323
+
writel(edmac->dma_cfg.port & 0xf, edmac->regs + M2P_PPALLOC);
385
324
386
325
control = M2P_CONTROL_CH_ERROR_INT | M2P_CONTROL_ICE
387
326
| M2P_CONTROL_ENABLE;
···
517
458
518
459
static int m2m_hw_setup(struct ep93xx_dma_chan *edmac)
519
460
{
520
-
const struct ep93xx_dma_data *data = edmac->chan.private;
521
461
u32 control = 0;
522
462
523
-
if (!data) {
463
+
if (edmac->dma_cfg.dir == DMA_MEM_TO_MEM) {
524
464
/* This is memcpy channel, nothing to configure */
525
465
writel(control, edmac->regs + M2M_CONTROL);
526
466
return 0;
527
467
}
528
468
529
-
switch (data->port) {
469
+
switch (edmac->dma_cfg.port) {
530
470
case EP93XX_DMA_SSP:
531
471
/*
532
472
* This was found via experimenting - anything less than 5
···
535
477
control = (5 << M2M_CONTROL_PWSC_SHIFT);
536
478
control |= M2M_CONTROL_NO_HDSK;
537
479
538
-
if (data->direction == DMA_MEM_TO_DEV) {
480
+
if (edmac->dma_cfg.dir == DMA_MEM_TO_DEV) {
539
481
control |= M2M_CONTROL_DAH;
540
482
control |= M2M_CONTROL_TM_TX;
541
483
control |= M2M_CONTROL_RSS_SSPTX;
···
551
493
* This IDE part is totally untested. Values below are taken
552
494
* from the EP93xx Users's Guide and might not be correct.
553
495
*/
554
-
if (data->direction == DMA_MEM_TO_DEV) {
496
+
if (edmac->dma_cfg.dir == DMA_MEM_TO_DEV) {
555
497
/* Worst case from the UG */
556
498
control = (3 << M2M_CONTROL_PWSC_SHIFT);
557
499
control |= M2M_CONTROL_DAH;
···
606
548
607
549
static void m2m_hw_submit(struct ep93xx_dma_chan *edmac)
608
550
{
609
-
struct ep93xx_dma_data *data = edmac->chan.private;
610
551
u32 control = readl(edmac->regs + M2M_CONTROL);
611
552
612
553
/*
···
631
574
control |= M2M_CONTROL_ENABLE;
632
575
writel(control, edmac->regs + M2M_CONTROL);
633
576
634
-
if (!data) {
577
+
if (edmac->dma_cfg.dir == DMA_MEM_TO_MEM) {
635
578
/*
636
579
* For memcpy channels the software trigger must be asserted
637
580
* in order to start the memcpy operation.
···
693
636
*/
694
637
if (ep93xx_dma_advance_active(edmac)) {
695
638
m2m_fill_desc(edmac);
696
-
if (done && !edmac->chan.private) {
639
+
if (done && edmac->dma_cfg.dir == DMA_MEM_TO_MEM) {
697
640
/* Software trigger for memcpy channel */
698
641
control = readl(edmac->regs + M2M_CONTROL);
699
642
control |= M2M_CONTROL_START;
···
924
867
static int ep93xx_dma_alloc_chan_resources(struct dma_chan *chan)
925
868
{
926
869
struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(chan);
927
-
struct ep93xx_dma_data *data = chan->private;
928
870
const char *name = dma_chan_name(chan);
929
871
int ret, i;
930
872
931
873
/* Sanity check the channel parameters */
932
874
if (!edmac->edma->m2m) {
933
-
if (!data)
875
+
if (edmac->dma_cfg.port < EP93XX_DMA_I2S1 ||
876
+
edmac->dma_cfg.port > EP93XX_DMA_IRDA)
934
877
return -EINVAL;
935
-
if (data->port < EP93XX_DMA_I2S1 ||
936
-
data->port > EP93XX_DMA_IRDA)
937
-
return -EINVAL;
938
-
if (data->direction != ep93xx_dma_chan_direction(chan))
878
+
if (edmac->dma_cfg.dir != ep93xx_dma_chan_direction(chan))
939
879
return -EINVAL;
940
880
} else {
941
-
if (data) {
942
-
switch (data->port) {
881
+
if (edmac->dma_cfg.dir != DMA_MEM_TO_MEM) {
882
+
switch (edmac->dma_cfg.port) {
943
883
case EP93XX_DMA_SSP:
944
884
case EP93XX_DMA_IDE:
945
-
if (!is_slave_direction(data->direction))
885
+
if (!is_slave_direction(edmac->dma_cfg.dir))
946
886
return -EINVAL;
947
887
break;
948
888
default:
···
947
893
}
948
894
}
949
895
}
950
-
951
-
if (data && data->name)
952
-
name = data->name;
953
896
954
897
ret = clk_prepare_enable(edmac->clk);
955
898
if (ret)
···
1366
1315
ep93xx_dma_advance_work(to_ep93xx_dma_chan(chan));
1367
1316
}
1368
1317
1369
-
static int __init ep93xx_dma_probe(struct platform_device *pdev)
1318
+
static struct ep93xx_dma_engine *ep93xx_dma_of_probe(struct platform_device *pdev)
1370
1319
{
1371
-
struct ep93xx_dma_platform_data *pdata = dev_get_platdata(&pdev->dev);
1320
+
const struct ep93xx_edma_data *data;
1321
+
struct device *dev = &pdev->dev;
1372
1322
struct ep93xx_dma_engine *edma;
1373
1323
struct dma_device *dma_dev;
1374
-
int ret, i;
1324
+
char dma_clk_name[5];
1325
+
int i;
1375
1326
1376
-
edma = kzalloc(struct_size(edma, channels, pdata->num_channels), GFP_KERNEL);
1327
+
data = device_get_match_data(dev);
1328
+
if (!data)
1329
+
return ERR_PTR(dev_err_probe(dev, -ENODEV, "No device match found\n"));
1330
+
1331
+
edma = devm_kzalloc(dev, struct_size(edma, channels, data->num_channels),
1332
+
GFP_KERNEL);
1377
1333
if (!edma)
1378
-
return -ENOMEM;
1334
+
return ERR_PTR(-ENOMEM);
1379
1335
1336
+
edma->m2m = data->id;
1337
+
edma->num_channels = data->num_channels;
1380
1338
dma_dev = &edma->dma_dev;
1381
-
edma->m2m = platform_get_device_id(pdev)->driver_data;
1382
-
edma->num_channels = pdata->num_channels;
1383
1339
1384
1340
INIT_LIST_HEAD(&dma_dev->channels);
1385
-
for (i = 0; i < pdata->num_channels; i++) {
1386
-
const struct ep93xx_dma_chan_data *cdata = &pdata->channels[i];
1341
+
for (i = 0; i < edma->num_channels; i++) {
1387
1342
struct ep93xx_dma_chan *edmac = &edma->channels[i];
1388
1343
1389
1344
edmac->chan.device = dma_dev;
1390
-
edmac->regs = cdata->base;
1391
-
edmac->irq = cdata->irq;
1345
+
edmac->regs = devm_platform_ioremap_resource(pdev, i);
1346
+
if (IS_ERR(edmac->regs))
1347
+
return edmac->regs;
1348
+
1349
+
edmac->irq = fwnode_irq_get(dev_fwnode(dev), i);
1350
+
if (edmac->irq < 0)
1351
+
return ERR_PTR(edmac->irq);
1352
+
1392
1353
edmac->edma = edma;
1393
1354
1394
-
edmac->clk = clk_get(NULL, cdata->name);
1355
+
if (edma->m2m)
1356
+
snprintf(dma_clk_name, sizeof(dma_clk_name), "m2m%u", i);
1357
+
else
1358
+
snprintf(dma_clk_name, sizeof(dma_clk_name), "m2p%u", i);
1359
+
1360
+
edmac->clk = devm_clk_get(dev, dma_clk_name);
1395
1361
if (IS_ERR(edmac->clk)) {
1396
-
dev_warn(&pdev->dev, "failed to get clock for %s\n",
1397
-
cdata->name);
1398
-
continue;
1362
+
dev_err_probe(dev, PTR_ERR(edmac->clk),
1363
+
"no %s clock found\n", dma_clk_name);
1364
+
return ERR_CAST(edmac->clk);
1399
1365
}
1400
1366
1401
1367
spin_lock_init(&edmac->lock);
···
1424
1356
list_add_tail(&edmac->chan.device_node,
1425
1357
&dma_dev->channels);
1426
1358
}
1359
+
1360
+
return edma;
1361
+
}
1362
+
1363
+
static bool ep93xx_m2p_dma_filter(struct dma_chan *chan, void *filter_param)
1364
+
{
1365
+
struct ep93xx_dma_chan *echan = to_ep93xx_dma_chan(chan);
1366
+
struct ep93xx_dma_chan_cfg *cfg = filter_param;
1367
+
1368
+
if (cfg->dir != ep93xx_dma_chan_direction(chan))
1369
+
return false;
1370
+
1371
+
echan->dma_cfg = *cfg;
1372
+
return true;
1373
+
}
1374
+
1375
+
static struct dma_chan *ep93xx_m2p_dma_of_xlate(struct of_phandle_args *dma_spec,
1376
+
struct of_dma *ofdma)
1377
+
{
1378
+
struct ep93xx_dma_engine *edma = ofdma->of_dma_data;
1379
+
dma_cap_mask_t mask = edma->dma_dev.cap_mask;
1380
+
struct ep93xx_dma_chan_cfg dma_cfg;
1381
+
u8 port = dma_spec->args[0];
1382
+
u8 direction = dma_spec->args[1];
1383
+
1384
+
if (port > EP93XX_DMA_IRDA)
1385
+
return NULL;
1386
+
1387
+
if (!is_slave_direction(direction))
1388
+
return NULL;
1389
+
1390
+
dma_cfg.port = port;
1391
+
dma_cfg.dir = direction;
1392
+
1393
+
return __dma_request_channel(&mask, ep93xx_m2p_dma_filter, &dma_cfg, ofdma->of_node);
1394
+
}
1395
+
1396
+
static bool ep93xx_m2m_dma_filter(struct dma_chan *chan, void *filter_param)
1397
+
{
1398
+
struct ep93xx_dma_chan *echan = to_ep93xx_dma_chan(chan);
1399
+
struct ep93xx_dma_chan_cfg *cfg = filter_param;
1400
+
1401
+
echan->dma_cfg = *cfg;
1402
+
1403
+
return true;
1404
+
}
1405
+
1406
+
static struct dma_chan *ep93xx_m2m_dma_of_xlate(struct of_phandle_args *dma_spec,
1407
+
struct of_dma *ofdma)
1408
+
{
1409
+
struct ep93xx_dma_engine *edma = ofdma->of_dma_data;
1410
+
dma_cap_mask_t mask = edma->dma_dev.cap_mask;
1411
+
struct ep93xx_dma_chan_cfg dma_cfg;
1412
+
u8 port = dma_spec->args[0];
1413
+
u8 direction = dma_spec->args[1];
1414
+
1415
+
if (!is_slave_direction(direction))
1416
+
return NULL;
1417
+
1418
+
switch (port) {
1419
+
case EP93XX_DMA_SSP:
1420
+
case EP93XX_DMA_IDE:
1421
+
break;
1422
+
default:
1423
+
return NULL;
1424
+
}
1425
+
1426
+
dma_cfg.port = port;
1427
+
dma_cfg.dir = direction;
1428
+
1429
+
return __dma_request_channel(&mask, ep93xx_m2m_dma_filter, &dma_cfg, ofdma->of_node);
1430
+
}
1431
+
1432
+
static int ep93xx_dma_probe(struct platform_device *pdev)
1433
+
{
1434
+
struct ep93xx_dma_engine *edma;
1435
+
struct dma_device *dma_dev;
1436
+
int ret;
1437
+
1438
+
edma = ep93xx_dma_of_probe(pdev);
1439
+
if (IS_ERR(edma))
1440
+
return PTR_ERR(edma);
1441
+
1442
+
dma_dev = &edma->dma_dev;
1427
1443
1428
1444
dma_cap_zero(dma_dev->cap_mask);
1429
1445
dma_cap_set(DMA_SLAVE, dma_dev->cap_mask);
···
1545
1393
}
1546
1394
1547
1395
ret = dma_async_device_register(dma_dev);
1548
-
if (unlikely(ret)) {
1549
-
for (i = 0; i < edma->num_channels; i++) {
1550
-
struct ep93xx_dma_chan *edmac = &edma->channels[i];
1551
-
if (!IS_ERR_OR_NULL(edmac->clk))
1552
-
clk_put(edmac->clk);
1553
-
}
1554
-
kfree(edma);
1396
+
if (ret)
1397
+
return ret;
1398
+
1399
+
if (edma->m2m) {
1400
+
ret = of_dma_controller_register(pdev->dev.of_node, ep93xx_m2m_dma_of_xlate,
1401
+
edma);
1555
1402
} else {
1556
-
dev_info(dma_dev->dev, "EP93xx M2%s DMA ready\n",
1557
-
edma->m2m ? "M" : "P");
1403
+
ret = of_dma_controller_register(pdev->dev.of_node, ep93xx_m2p_dma_of_xlate,
1404
+
edma);
1558
1405
}
1406
+
if (ret)
1407
+
goto err_dma_unregister;
1408
+
1409
+
dev_info(dma_dev->dev, "EP93xx M2%s DMA ready\n", edma->m2m ? "M" : "P");
1410
+
1411
+
return 0;
1412
+
1413
+
err_dma_unregister:
1414
+
dma_async_device_unregister(dma_dev);
1559
1415
1560
1416
return ret;
1561
1417
}
1418
+
1419
+
static const struct ep93xx_edma_data edma_m2p = {
1420
+
.id = M2P_DMA,
1421
+
.num_channels = 10,
1422
+
};
1423
+
1424
+
static const struct ep93xx_edma_data edma_m2m = {
1425
+
.id = M2M_DMA,
1426
+
.num_channels = 2,
1427
+
};
1428
+
1429
+
static const struct of_device_id ep93xx_dma_of_ids[] = {
1430
+
{ .compatible = "cirrus,ep9301-dma-m2p", .data = &edma_m2p },
1431
+
{ .compatible = "cirrus,ep9301-dma-m2m", .data = &edma_m2m },
1432
+
{ /* sentinel */ }
1433
+
};
1434
+
MODULE_DEVICE_TABLE(of, ep93xx_dma_of_ids);
1562
1435
1563
1436
static const struct platform_device_id ep93xx_dma_driver_ids[] = {
1564
1437
{ "ep93xx-dma-m2p", 0 },
···
1594
1417
static struct platform_driver ep93xx_dma_driver = {
1595
1418
.driver = {
1596
1419
.name = "ep93xx-dma",
1420
+
.of_match_table = ep93xx_dma_of_ids,
1597
1421
},
1598
1422
.id_table = ep93xx_dma_driver_ids,
1423
+
.probe = ep93xx_dma_probe,
1599
1424
};
1600
1425
1601
-
static int __init ep93xx_dma_module_init(void)
1602
-
{
1603
-
return platform_driver_probe(&ep93xx_dma_driver, ep93xx_dma_probe);
1604
-
}
1605
-
subsys_initcall(ep93xx_dma_module_init);
1426
+
module_platform_driver(ep93xx_dma_driver);
1606
1427
1607
1428
MODULE_AUTHOR("Mika Westerberg <mika.westerberg@iki.fi>");
1608
1429
MODULE_DESCRIPTION("EP93xx DMA driver");
+139
-220
drivers/gpio/gpio-ep93xx.c
+139
-220
drivers/gpio/gpio-ep93xx.c
···
12
12
#include <linux/init.h>
13
13
#include <linux/module.h>
14
14
#include <linux/platform_device.h>
15
+
#include <linux/interrupt.h>
15
16
#include <linux/io.h>
16
17
#include <linux/irq.h>
17
18
#include <linux/slab.h>
···
20
19
#include <linux/bitops.h>
21
20
#include <linux/seq_file.h>
22
21
23
-
#define EP93XX_GPIO_F_INT_STATUS 0x5c
24
-
#define EP93XX_GPIO_A_INT_STATUS 0xa0
25
-
#define EP93XX_GPIO_B_INT_STATUS 0xbc
26
-
27
-
/* Maximum value for gpio line identifiers */
28
-
#define EP93XX_GPIO_LINE_MAX 63
29
-
30
-
/* Number of GPIO chips in EP93XX */
31
-
#define EP93XX_GPIO_CHIP_NUM 8
32
-
33
-
/* Maximum value for irq capable line identifiers */
34
-
#define EP93XX_GPIO_LINE_MAX_IRQ 23
35
-
36
-
#define EP93XX_GPIO_A_IRQ_BASE 64
37
-
#define EP93XX_GPIO_B_IRQ_BASE 72
38
-
/*
39
-
* Static mapping of GPIO bank F IRQS:
40
-
* F0..F7 (16..24) to irq 80..87.
41
-
*/
42
-
#define EP93XX_GPIO_F_IRQ_BASE 80
43
-
44
22
struct ep93xx_gpio_irq_chip {
45
-
u8 irq_offset;
23
+
void __iomem *base;
46
24
u8 int_unmasked;
47
25
u8 int_enabled;
48
26
u8 int_type1;
···
30
50
};
31
51
32
52
struct ep93xx_gpio_chip {
53
+
void __iomem *base;
33
54
struct gpio_chip gc;
34
55
struct ep93xx_gpio_irq_chip *eic;
35
-
};
36
-
37
-
struct ep93xx_gpio {
38
-
void __iomem *base;
39
-
struct ep93xx_gpio_chip gc[EP93XX_GPIO_CHIP_NUM];
40
56
};
41
57
42
58
#define to_ep93xx_gpio_chip(x) container_of(x, struct ep93xx_gpio_chip, gc)
···
55
79
#define EP93XX_INT_RAW_STATUS_OFFSET 0x14
56
80
#define EP93XX_INT_DEBOUNCE_OFFSET 0x18
57
81
58
-
static void ep93xx_gpio_update_int_params(struct ep93xx_gpio *epg,
59
-
struct ep93xx_gpio_irq_chip *eic)
82
+
static void ep93xx_gpio_update_int_params(struct ep93xx_gpio_irq_chip *eic)
60
83
{
61
-
writeb_relaxed(0, epg->base + eic->irq_offset + EP93XX_INT_EN_OFFSET);
84
+
writeb_relaxed(0, eic->base + EP93XX_INT_EN_OFFSET);
62
85
63
86
writeb_relaxed(eic->int_type2,
64
-
epg->base + eic->irq_offset + EP93XX_INT_TYPE2_OFFSET);
87
+
eic->base + EP93XX_INT_TYPE2_OFFSET);
65
88
66
89
writeb_relaxed(eic->int_type1,
67
-
epg->base + eic->irq_offset + EP93XX_INT_TYPE1_OFFSET);
90
+
eic->base + EP93XX_INT_TYPE1_OFFSET);
68
91
69
92
writeb_relaxed(eic->int_unmasked & eic->int_enabled,
70
-
epg->base + eic->irq_offset + EP93XX_INT_EN_OFFSET);
93
+
eic->base + EP93XX_INT_EN_OFFSET);
71
94
}
72
95
73
96
static void ep93xx_gpio_int_debounce(struct gpio_chip *gc,
74
97
unsigned int offset, bool enable)
75
98
{
76
-
struct ep93xx_gpio *epg = gpiochip_get_data(gc);
77
99
struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
78
100
int port_mask = BIT(offset);
79
101
···
80
106
else
81
107
eic->int_debounce &= ~port_mask;
82
108
83
-
writeb(eic->int_debounce,
84
-
epg->base + eic->irq_offset + EP93XX_INT_DEBOUNCE_OFFSET);
109
+
writeb(eic->int_debounce, eic->base + EP93XX_INT_DEBOUNCE_OFFSET);
85
110
}
86
111
87
-
static void ep93xx_gpio_ab_irq_handler(struct irq_desc *desc)
112
+
static u32 ep93xx_gpio_ab_irq_handler(struct gpio_chip *gc)
88
113
{
89
-
struct gpio_chip *gc = irq_desc_get_handler_data(desc);
90
-
struct ep93xx_gpio *epg = gpiochip_get_data(gc);
91
-
struct irq_chip *irqchip = irq_desc_get_chip(desc);
114
+
struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
92
115
unsigned long stat;
93
116
int offset;
94
117
95
-
chained_irq_enter(irqchip, desc);
96
-
97
-
/*
98
-
* Dispatch the IRQs to the irqdomain of each A and B
99
-
* gpiochip irqdomains depending on what has fired.
100
-
* The tricky part is that the IRQ line is shared
101
-
* between bank A and B and each has their own gpiochip.
102
-
*/
103
-
stat = readb(epg->base + EP93XX_GPIO_A_INT_STATUS);
118
+
stat = readb(eic->base + EP93XX_INT_STATUS_OFFSET);
104
119
for_each_set_bit(offset, &stat, 8)
105
-
generic_handle_domain_irq(epg->gc[0].gc.irq.domain,
106
-
offset);
120
+
generic_handle_domain_irq(gc->irq.domain, offset);
107
121
108
-
stat = readb(epg->base + EP93XX_GPIO_B_INT_STATUS);
109
-
for_each_set_bit(offset, &stat, 8)
110
-
generic_handle_domain_irq(epg->gc[1].gc.irq.domain,
111
-
offset);
122
+
return stat;
123
+
}
112
124
113
-
chained_irq_exit(irqchip, desc);
125
+
static irqreturn_t ep93xx_ab_irq_handler(int irq, void *dev_id)
126
+
{
127
+
return IRQ_RETVAL(ep93xx_gpio_ab_irq_handler(dev_id));
114
128
}
115
129
116
130
static void ep93xx_gpio_f_irq_handler(struct irq_desc *desc)
117
131
{
118
-
/*
119
-
* map discontiguous hw irq range to continuous sw irq range:
120
-
*
121
-
* IRQ_EP93XX_GPIO{0..7}MUX -> EP93XX_GPIO_LINE_F{0..7}
122
-
*/
123
132
struct irq_chip *irqchip = irq_desc_get_chip(desc);
124
-
unsigned int irq = irq_desc_get_irq(desc);
125
-
int port_f_idx = (irq & 7) ^ 4; /* {20..23,48..51} -> {0..7} */
126
-
int gpio_irq = EP93XX_GPIO_F_IRQ_BASE + port_f_idx;
133
+
struct gpio_chip *gc = irq_desc_get_handler_data(desc);
134
+
struct gpio_irq_chip *gic = &gc->irq;
135
+
unsigned int parent = irq_desc_get_irq(desc);
136
+
unsigned int i;
127
137
128
138
chained_irq_enter(irqchip, desc);
129
-
generic_handle_irq(gpio_irq);
139
+
for (i = 0; i < gic->num_parents; i++)
140
+
if (gic->parents[i] == parent)
141
+
break;
142
+
143
+
if (i < gic->num_parents)
144
+
generic_handle_domain_irq(gc->irq.domain, i);
145
+
130
146
chained_irq_exit(irqchip, desc);
131
147
}
132
148
···
124
160
{
125
161
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
126
162
struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
127
-
struct ep93xx_gpio *epg = gpiochip_get_data(gc);
128
-
int port_mask = BIT(d->irq & 7);
163
+
int port_mask = BIT(irqd_to_hwirq(d));
129
164
130
165
if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
131
166
eic->int_type2 ^= port_mask; /* switch edge direction */
132
-
ep93xx_gpio_update_int_params(epg, eic);
167
+
ep93xx_gpio_update_int_params(eic);
133
168
}
134
169
135
-
writeb(port_mask, epg->base + eic->irq_offset + EP93XX_INT_EOI_OFFSET);
170
+
writeb(port_mask, eic->base + EP93XX_INT_EOI_OFFSET);
136
171
}
137
172
138
173
static void ep93xx_gpio_irq_mask_ack(struct irq_data *d)
139
174
{
140
175
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
141
176
struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
142
-
struct ep93xx_gpio *epg = gpiochip_get_data(gc);
143
-
int port_mask = BIT(d->irq & 7);
177
+
irq_hw_number_t hwirq = irqd_to_hwirq(d);
178
+
int port_mask = BIT(hwirq);
144
179
145
180
if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH)
146
181
eic->int_type2 ^= port_mask; /* switch edge direction */
147
182
148
183
eic->int_unmasked &= ~port_mask;
149
-
ep93xx_gpio_update_int_params(epg, eic);
184
+
ep93xx_gpio_update_int_params(eic);
150
185
151
-
writeb(port_mask, epg->base + eic->irq_offset + EP93XX_INT_EOI_OFFSET);
152
-
gpiochip_disable_irq(gc, irqd_to_hwirq(d));
186
+
writeb(port_mask, eic->base + EP93XX_INT_EOI_OFFSET);
187
+
gpiochip_disable_irq(gc, hwirq);
153
188
}
154
189
155
190
static void ep93xx_gpio_irq_mask(struct irq_data *d)
156
191
{
157
192
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
158
193
struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
159
-
struct ep93xx_gpio *epg = gpiochip_get_data(gc);
194
+
irq_hw_number_t hwirq = irqd_to_hwirq(d);
160
195
161
-
eic->int_unmasked &= ~BIT(d->irq & 7);
162
-
ep93xx_gpio_update_int_params(epg, eic);
163
-
gpiochip_disable_irq(gc, irqd_to_hwirq(d));
196
+
eic->int_unmasked &= ~BIT(hwirq);
197
+
ep93xx_gpio_update_int_params(eic);
198
+
gpiochip_disable_irq(gc, hwirq);
164
199
}
165
200
166
201
static void ep93xx_gpio_irq_unmask(struct irq_data *d)
167
202
{
168
203
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
169
204
struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
170
-
struct ep93xx_gpio *epg = gpiochip_get_data(gc);
205
+
irq_hw_number_t hwirq = irqd_to_hwirq(d);
171
206
172
-
gpiochip_enable_irq(gc, irqd_to_hwirq(d));
173
-
eic->int_unmasked |= BIT(d->irq & 7);
174
-
ep93xx_gpio_update_int_params(epg, eic);
207
+
gpiochip_enable_irq(gc, hwirq);
208
+
eic->int_unmasked |= BIT(hwirq);
209
+
ep93xx_gpio_update_int_params(eic);
175
210
}
176
211
177
212
/*
···
182
219
{
183
220
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
184
221
struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
185
-
struct ep93xx_gpio *epg = gpiochip_get_data(gc);
186
-
int offset = d->irq & 7;
187
-
int port_mask = BIT(offset);
222
+
irq_hw_number_t hwirq = irqd_to_hwirq(d);
223
+
int port_mask = BIT(hwirq);
188
224
irq_flow_handler_t handler;
189
225
190
-
gc->direction_input(gc, offset);
226
+
gc->direction_input(gc, hwirq);
191
227
192
228
switch (type) {
193
229
case IRQ_TYPE_EDGE_RISING:
···
212
250
case IRQ_TYPE_EDGE_BOTH:
213
251
eic->int_type1 |= port_mask;
214
252
/* set initial polarity based on current input level */
215
-
if (gc->get(gc, offset))
253
+
if (gc->get(gc, hwirq))
216
254
eic->int_type2 &= ~port_mask; /* falling */
217
255
else
218
256
eic->int_type2 |= port_mask; /* rising */
···
226
264
227
265
eic->int_enabled |= port_mask;
228
266
229
-
ep93xx_gpio_update_int_params(epg, eic);
267
+
ep93xx_gpio_update_int_params(eic);
230
268
231
269
return 0;
232
270
}
233
-
234
-
/*************************************************************************
235
-
* gpiolib interface for EP93xx on-chip GPIOs
236
-
*************************************************************************/
237
-
struct ep93xx_gpio_bank {
238
-
const char *label;
239
-
int data;
240
-
int dir;
241
-
int irq;
242
-
int base;
243
-
bool has_irq;
244
-
bool has_hierarchical_irq;
245
-
unsigned int irq_base;
246
-
};
247
-
248
-
#define EP93XX_GPIO_BANK(_label, _data, _dir, _irq, _base, _has_irq, _has_hier, _irq_base) \
249
-
{ \
250
-
.label = _label, \
251
-
.data = _data, \
252
-
.dir = _dir, \
253
-
.irq = _irq, \
254
-
.base = _base, \
255
-
.has_irq = _has_irq, \
256
-
.has_hierarchical_irq = _has_hier, \
257
-
.irq_base = _irq_base, \
258
-
}
259
-
260
-
static struct ep93xx_gpio_bank ep93xx_gpio_banks[] = {
261
-
/* Bank A has 8 IRQs */
262
-
EP93XX_GPIO_BANK("A", 0x00, 0x10, 0x90, 0, true, false, EP93XX_GPIO_A_IRQ_BASE),
263
-
/* Bank B has 8 IRQs */
264
-
EP93XX_GPIO_BANK("B", 0x04, 0x14, 0xac, 8, true, false, EP93XX_GPIO_B_IRQ_BASE),
265
-
EP93XX_GPIO_BANK("C", 0x08, 0x18, 0x00, 40, false, false, 0),
266
-
EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 0x00, 24, false, false, 0),
267
-
EP93XX_GPIO_BANK("E", 0x20, 0x24, 0x00, 32, false, false, 0),
268
-
/* Bank F has 8 IRQs */
269
-
EP93XX_GPIO_BANK("F", 0x30, 0x34, 0x4c, 16, false, true, EP93XX_GPIO_F_IRQ_BASE),
270
-
EP93XX_GPIO_BANK("G", 0x38, 0x3c, 0x00, 48, false, false, 0),
271
-
EP93XX_GPIO_BANK("H", 0x40, 0x44, 0x00, 56, false, false, 0),
272
-
};
273
271
274
272
static int ep93xx_gpio_set_config(struct gpio_chip *gc, unsigned offset,
275
273
unsigned long config)
···
264
342
GPIOCHIP_IRQ_RESOURCE_HELPERS,
265
343
};
266
344
267
-
static int ep93xx_gpio_add_bank(struct ep93xx_gpio_chip *egc,
268
-
struct platform_device *pdev,
269
-
struct ep93xx_gpio *epg,
270
-
struct ep93xx_gpio_bank *bank)
345
+
static int ep93xx_setup_irqs(struct platform_device *pdev,
346
+
struct ep93xx_gpio_chip *egc)
271
347
{
272
-
void __iomem *data = epg->base + bank->data;
273
-
void __iomem *dir = epg->base + bank->dir;
274
348
struct gpio_chip *gc = &egc->gc;
275
349
struct device *dev = &pdev->dev;
276
-
struct gpio_irq_chip *girq;
277
-
int err;
350
+
struct gpio_irq_chip *girq = &gc->irq;
351
+
int ret, irq, i;
352
+
void __iomem *intr;
278
353
279
-
err = bgpio_init(gc, dev, 1, data, NULL, NULL, dir, NULL, 0);
280
-
if (err)
281
-
return err;
354
+
intr = devm_platform_ioremap_resource_byname(pdev, "intr");
355
+
if (IS_ERR(intr))
356
+
return PTR_ERR(intr);
282
357
283
-
gc->label = bank->label;
284
-
gc->base = bank->base;
285
-
286
-
girq = &gc->irq;
287
-
if (bank->has_irq || bank->has_hierarchical_irq) {
288
-
gc->set_config = ep93xx_gpio_set_config;
289
-
egc->eic = devm_kcalloc(dev, 1,
290
-
sizeof(*egc->eic),
291
-
GFP_KERNEL);
292
-
if (!egc->eic)
293
-
return -ENOMEM;
294
-
egc->eic->irq_offset = bank->irq;
295
-
gpio_irq_chip_set_chip(girq, &gpio_eic_irq_chip);
296
-
}
297
-
298
-
if (bank->has_irq) {
299
-
int ab_parent_irq = platform_get_irq(pdev, 0);
300
-
301
-
girq->parent_handler = ep93xx_gpio_ab_irq_handler;
302
-
girq->num_parents = 1;
303
-
girq->parents = devm_kcalloc(dev, girq->num_parents,
304
-
sizeof(*girq->parents),
305
-
GFP_KERNEL);
306
-
if (!girq->parents)
307
-
return -ENOMEM;
308
-
girq->default_type = IRQ_TYPE_NONE;
309
-
girq->handler = handle_level_irq;
310
-
girq->parents[0] = ab_parent_irq;
311
-
girq->first = bank->irq_base;
312
-
}
313
-
314
-
/* Only bank F has especially funky IRQ handling */
315
-
if (bank->has_hierarchical_irq) {
316
-
int gpio_irq;
317
-
int i;
318
-
319
-
/*
320
-
* FIXME: convert this to use hierarchical IRQ support!
321
-
* this requires fixing the root irqchip to be hierarchical.
322
-
*/
323
-
girq->parent_handler = ep93xx_gpio_f_irq_handler;
324
-
girq->num_parents = 8;
325
-
girq->parents = devm_kcalloc(dev, girq->num_parents,
326
-
sizeof(*girq->parents),
327
-
GFP_KERNEL);
328
-
if (!girq->parents)
329
-
return -ENOMEM;
330
-
/* Pick resources 1..8 for these IRQs */
331
-
for (i = 0; i < girq->num_parents; i++) {
332
-
girq->parents[i] = platform_get_irq(pdev, i + 1);
333
-
gpio_irq = bank->irq_base + i;
334
-
irq_set_chip_data(gpio_irq, &epg->gc[5]);
335
-
irq_set_chip_and_handler(gpio_irq,
336
-
girq->chip,
337
-
handle_level_irq);
338
-
irq_clear_status_flags(gpio_irq, IRQ_NOREQUEST);
339
-
}
340
-
girq->default_type = IRQ_TYPE_NONE;
341
-
girq->handler = handle_level_irq;
342
-
girq->first = bank->irq_base;
343
-
}
344
-
345
-
return devm_gpiochip_add_data(dev, gc, epg);
346
-
}
347
-
348
-
static int ep93xx_gpio_probe(struct platform_device *pdev)
349
-
{
350
-
struct ep93xx_gpio *epg;
351
-
int i;
352
-
353
-
epg = devm_kzalloc(&pdev->dev, sizeof(*epg), GFP_KERNEL);
354
-
if (!epg)
358
+
gc->set_config = ep93xx_gpio_set_config;
359
+
egc->eic = devm_kzalloc(dev, sizeof(*egc->eic), GFP_KERNEL);
360
+
if (!egc->eic)
355
361
return -ENOMEM;
356
362
357
-
epg->base = devm_platform_ioremap_resource(pdev, 0);
358
-
if (IS_ERR(epg->base))
359
-
return PTR_ERR(epg->base);
363
+
egc->eic->base = intr;
364
+
gpio_irq_chip_set_chip(girq, &gpio_eic_irq_chip);
365
+
girq->num_parents = platform_irq_count(pdev);
366
+
if (girq->num_parents == 0)
367
+
return -EINVAL;
360
368
361
-
for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) {
362
-
struct ep93xx_gpio_chip *gc = &epg->gc[i];
363
-
struct ep93xx_gpio_bank *bank = &ep93xx_gpio_banks[i];
369
+
girq->parents = devm_kcalloc(dev, girq->num_parents, sizeof(*girq->parents),
370
+
GFP_KERNEL);
371
+
if (!girq->parents)
372
+
return -ENOMEM;
364
373
365
-
if (ep93xx_gpio_add_bank(gc, pdev, epg, bank))
366
-
dev_warn(&pdev->dev, "Unable to add gpio bank %s\n",
367
-
bank->label);
374
+
if (girq->num_parents == 1) { /* A/B irqchips */
375
+
irq = platform_get_irq(pdev, 0);
376
+
if (irq < 0)
377
+
return irq;
378
+
379
+
ret = devm_request_irq(dev, irq, ep93xx_ab_irq_handler,
380
+
IRQF_SHARED, gc->label, gc);
381
+
if (ret)
382
+
return dev_err_probe(dev, ret, "requesting IRQ: %d\n", irq);
383
+
384
+
girq->parents[0] = irq;
385
+
} else { /* F irqchip */
386
+
girq->parent_handler = ep93xx_gpio_f_irq_handler;
387
+
388
+
for (i = 0; i < girq->num_parents; i++) {
389
+
irq = platform_get_irq_optional(pdev, i);
390
+
if (irq < 0)
391
+
continue;
392
+
393
+
girq->parents[i] = irq;
394
+
}
395
+
396
+
girq->map = girq->parents;
368
397
}
398
+
399
+
girq->default_type = IRQ_TYPE_NONE;
400
+
/* TODO: replace with handle_bad_irq() once we are fully hierarchical */
401
+
girq->handler = handle_simple_irq;
369
402
370
403
return 0;
371
404
}
372
405
406
+
static int ep93xx_gpio_probe(struct platform_device *pdev)
407
+
{
408
+
struct ep93xx_gpio_chip *egc;
409
+
struct gpio_chip *gc;
410
+
void __iomem *data;
411
+
void __iomem *dir;
412
+
int ret;
413
+
414
+
egc = devm_kzalloc(&pdev->dev, sizeof(*egc), GFP_KERNEL);
415
+
if (!egc)
416
+
return -ENOMEM;
417
+
418
+
data = devm_platform_ioremap_resource_byname(pdev, "data");
419
+
if (IS_ERR(data))
420
+
return PTR_ERR(data);
421
+
422
+
dir = devm_platform_ioremap_resource_byname(pdev, "dir");
423
+
if (IS_ERR(dir))
424
+
return PTR_ERR(dir);
425
+
426
+
gc = &egc->gc;
427
+
ret = bgpio_init(gc, &pdev->dev, 1, data, NULL, NULL, dir, NULL, 0);
428
+
if (ret)
429
+
return dev_err_probe(&pdev->dev, ret, "unable to init generic GPIO\n");
430
+
431
+
gc->label = dev_name(&pdev->dev);
432
+
if (platform_irq_count(pdev) > 0) {
433
+
dev_dbg(&pdev->dev, "setting up irqs for %s\n", dev_name(&pdev->dev));
434
+
ret = ep93xx_setup_irqs(pdev, egc);
435
+
if (ret)
436
+
dev_err_probe(&pdev->dev, ret, "setup irqs failed");
437
+
}
438
+
439
+
return devm_gpiochip_add_data(&pdev->dev, gc, egc);
440
+
}
441
+
442
+
static const struct of_device_id ep93xx_gpio_match[] = {
443
+
{ .compatible = "cirrus,ep9301-gpio" },
444
+
{ /* sentinel */ }
445
+
};
446
+
373
447
static struct platform_driver ep93xx_gpio_driver = {
374
448
.driver = {
375
449
.name = "gpio-ep93xx",
450
+
.of_match_table = ep93xx_gpio_match,
376
451
},
377
452
.probe = ep93xx_gpio_probe,
378
453
};
+22
-52
drivers/input/keyboard/ep93xx_keypad.c
+22
-52
drivers/input/keyboard/ep93xx_keypad.c
···
6
6
*
7
7
* Based on the pxa27x matrix keypad controller by Rodolfo Giometti.
8
8
*
9
-
* NOTE:
10
-
*
11
-
* The 3-key reset is triggered by pressing the 3 keys in
12
-
* Row 0, Columns 2, 4, and 7 at the same time. This action can
13
-
* be disabled by setting the EP93XX_KEYPAD_DISABLE_3_KEY flag.
14
-
*
15
-
* Normal operation for the matrix does not autorepeat the key press.
16
-
* This action can be enabled by setting the EP93XX_KEYPAD_AUTOREPEAT
17
-
* flag.
18
9
*/
19
10
20
11
#include <linux/bits.h>
12
+
#include <linux/mod_devicetable.h>
21
13
#include <linux/module.h>
22
14
#include <linux/platform_device.h>
15
+
#include <linux/property.h>
23
16
#include <linux/interrupt.h>
24
17
#include <linux/clk.h>
25
18
#include <linux/io.h>
···
20
27
#include <linux/input/matrix_keypad.h>
21
28
#include <linux/slab.h>
22
29
#include <linux/soc/cirrus/ep93xx.h>
23
-
#include <linux/platform_data/keypad-ep93xx.h>
24
30
#include <linux/pm_wakeirq.h>
25
31
26
32
/*
···
53
61
#define KEY_REG_KEY1_MASK GENMASK(5, 0)
54
62
#define KEY_REG_KEY1_SHIFT 0
55
63
64
+
#define EP93XX_MATRIX_ROWS (8)
65
+
#define EP93XX_MATRIX_COLS (8)
66
+
56
67
#define EP93XX_MATRIX_SIZE (EP93XX_MATRIX_ROWS * EP93XX_MATRIX_COLS)
57
68
58
69
struct ep93xx_keypad {
59
-
struct ep93xx_keypad_platform_data *pdata;
60
70
struct input_dev *input_dev;
61
71
struct clk *clk;
72
+
unsigned int debounce;
73
+
u16 prescale;
62
74
63
75
void __iomem *mmio_base;
64
76
···
129
133
130
134
static void ep93xx_keypad_config(struct ep93xx_keypad *keypad)
131
135
{
132
-
struct ep93xx_keypad_platform_data *pdata = keypad->pdata;
133
136
unsigned int val = 0;
134
137
135
-
clk_set_rate(keypad->clk, pdata->clk_rate);
138
+
val |= (keypad->debounce << KEY_INIT_DBNC_SHIFT) & KEY_INIT_DBNC_MASK;
136
139
137
-
if (pdata->flags & EP93XX_KEYPAD_DISABLE_3_KEY)
138
-
val |= KEY_INIT_DIS3KY;
139
-
if (pdata->flags & EP93XX_KEYPAD_DIAG_MODE)
140
-
val |= KEY_INIT_DIAG;
141
-
if (pdata->flags & EP93XX_KEYPAD_BACK_DRIVE)
142
-
val |= KEY_INIT_BACK;
143
-
if (pdata->flags & EP93XX_KEYPAD_TEST_MODE)
144
-
val |= KEY_INIT_T2;
145
-
146
-
val |= ((pdata->debounce << KEY_INIT_DBNC_SHIFT) & KEY_INIT_DBNC_MASK);
147
-
148
-
val |= ((pdata->prescale << KEY_INIT_PRSCL_SHIFT) & KEY_INIT_PRSCL_MASK);
140
+
val |= (keypad->prescale << KEY_INIT_PRSCL_SHIFT) & KEY_INIT_PRSCL_MASK;
149
141
150
142
__raw_writel(val, keypad->mmio_base + KEY_INIT);
151
143
}
···
204
220
static DEFINE_SIMPLE_DEV_PM_OPS(ep93xx_keypad_pm_ops,
205
221
ep93xx_keypad_suspend, ep93xx_keypad_resume);
206
222
207
-
static void ep93xx_keypad_release_gpio_action(void *_pdev)
208
-
{
209
-
struct platform_device *pdev = _pdev;
210
-
211
-
ep93xx_keypad_release_gpio(pdev);
212
-
}
213
-
214
223
static int ep93xx_keypad_probe(struct platform_device *pdev)
215
224
{
225
+
struct device *dev = &pdev->dev;
216
226
struct ep93xx_keypad *keypad;
217
-
const struct matrix_keymap_data *keymap_data;
218
227
struct input_dev *input_dev;
219
228
int err;
220
229
221
230
keypad = devm_kzalloc(&pdev->dev, sizeof(*keypad), GFP_KERNEL);
222
231
if (!keypad)
223
232
return -ENOMEM;
224
-
225
-
keypad->pdata = dev_get_platdata(&pdev->dev);
226
-
if (!keypad->pdata)
227
-
return -EINVAL;
228
-
229
-
keymap_data = keypad->pdata->keymap_data;
230
-
if (!keymap_data)
231
-
return -EINVAL;
232
233
233
234
keypad->irq = platform_get_irq(pdev, 0);
234
235
if (keypad->irq < 0)
···
223
254
if (IS_ERR(keypad->mmio_base))
224
255
return PTR_ERR(keypad->mmio_base);
225
256
226
-
err = ep93xx_keypad_acquire_gpio(pdev);
227
-
if (err)
228
-
return err;
229
-
230
-
err = devm_add_action_or_reset(&pdev->dev,
231
-
ep93xx_keypad_release_gpio_action, pdev);
232
-
if (err)
233
-
return err;
234
-
235
257
keypad->clk = devm_clk_get(&pdev->dev, NULL);
236
258
if (IS_ERR(keypad->clk))
237
259
return PTR_ERR(keypad->clk);
260
+
261
+
device_property_read_u32(dev, "debounce-delay-ms", &keypad->debounce);
262
+
device_property_read_u16(dev, "cirrus,prescale", &keypad->prescale);
238
263
239
264
input_dev = devm_input_allocate_device(&pdev->dev);
240
265
if (!input_dev)
···
241
278
input_dev->open = ep93xx_keypad_open;
242
279
input_dev->close = ep93xx_keypad_close;
243
280
244
-
err = matrix_keypad_build_keymap(keymap_data, NULL,
281
+
err = matrix_keypad_build_keymap(NULL, NULL,
245
282
EP93XX_MATRIX_ROWS, EP93XX_MATRIX_COLS,
246
283
keypad->keycodes, input_dev);
247
284
if (err)
248
285
return err;
249
286
250
-
if (keypad->pdata->flags & EP93XX_KEYPAD_AUTOREPEAT)
287
+
if (device_property_read_bool(&pdev->dev, "autorepeat"))
251
288
__set_bit(EV_REP, input_dev->evbit);
252
289
input_set_drvdata(input_dev, keypad);
253
290
···
276
313
dev_pm_clear_wake_irq(&pdev->dev);
277
314
}
278
315
316
+
static const struct of_device_id ep93xx_keypad_of_ids[] = {
317
+
{ .compatible = "cirrus,ep9307-keypad" },
318
+
{ /* sentinel */ }
319
+
};
320
+
MODULE_DEVICE_TABLE(of, ep93xx_keypad_of_ids);
321
+
279
322
static struct platform_driver ep93xx_keypad_driver = {
280
323
.driver = {
281
324
.name = "ep93xx-keypad",
282
325
.pm = pm_sleep_ptr(&ep93xx_keypad_pm_ops),
326
+
.of_match_table = ep93xx_keypad_of_ids,
283
327
},
284
328
.probe = ep93xx_keypad_probe,
285
329
.remove_new = ep93xx_keypad_remove,
+6
drivers/mtd/nand/raw/Kconfig
+6
drivers/mtd/nand/raw/Kconfig
···
448
448
Enables support for the NAND controller found on Renesas R-Car
449
449
Gen3 and RZ/N1 SoC families.
450
450
451
+
config MTD_NAND_TS72XX
452
+
tristate "ts72xx NAND controller"
453
+
depends on ARCH_EP93XX && HAS_IOMEM
454
+
help
455
+
Enables support for NAND controller on ts72xx SBCs.
456
+
451
457
comment "Misc"
452
458
453
459
config MTD_SM_COMMON
+1
drivers/mtd/nand/raw/Makefile
+1
drivers/mtd/nand/raw/Makefile
···
34
34
obj-$(CONFIG_MTD_NAND_SH_FLCTL) += sh_flctl.o
35
35
obj-$(CONFIG_MTD_NAND_MXC) += mxc_nand.o
36
36
obj-$(CONFIG_MTD_NAND_SOCRATES) += socrates_nand.o
37
+
obj-$(CONFIG_MTD_NAND_TS72XX) += technologic-nand-controller.o
37
38
obj-$(CONFIG_MTD_NAND_TXX9NDFMC) += txx9ndfmc.o
38
39
obj-$(CONFIG_MTD_NAND_MPC5121_NFC) += mpc5121_nfc.o
39
40
obj-$(CONFIG_MTD_NAND_VF610_NFC) += vf610_nfc.o
+222
drivers/mtd/nand/raw/technologic-nand-controller.c
+222
drivers/mtd/nand/raw/technologic-nand-controller.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Technologic Systems TS72xx NAND controller driver
4
+
*
5
+
* Copyright (C) 2023 Nikita Shubin <nikita.shubin@maquefel.me>
6
+
*
7
+
* Derived from: plat_nand.c
8
+
* Author: Vitaly Wool <vitalywool@gmail.com>
9
+
*/
10
+
11
+
#include <linux/bits.h>
12
+
#include <linux/err.h>
13
+
#include <linux/io.h>
14
+
#include <linux/iopoll.h>
15
+
#include <linux/module.h>
16
+
#include <linux/platform_device.h>
17
+
#include <linux/slab.h>
18
+
19
+
#include <linux/mtd/mtd.h>
20
+
#include <linux/mtd/platnand.h>
21
+
22
+
#define TS72XX_NAND_CONTROL_ADDR_LINE BIT(22) /* 0xN0400000 */
23
+
#define TS72XX_NAND_BUSY_ADDR_LINE BIT(23) /* 0xN0800000 */
24
+
25
+
#define TS72XX_NAND_ALE BIT(0)
26
+
#define TS72XX_NAND_CLE BIT(1)
27
+
#define TS72XX_NAND_NCE BIT(2)
28
+
29
+
#define TS72XX_NAND_CTRL_CLE (TS72XX_NAND_NCE | TS72XX_NAND_CLE)
30
+
#define TS72XX_NAND_CTRL_ALE (TS72XX_NAND_NCE | TS72XX_NAND_ALE)
31
+
32
+
struct ts72xx_nand_data {
33
+
struct nand_controller controller;
34
+
struct nand_chip chip;
35
+
void __iomem *base;
36
+
void __iomem *ctrl;
37
+
void __iomem *busy;
38
+
};
39
+
40
+
static inline struct ts72xx_nand_data *chip_to_ts72xx(struct nand_chip *chip)
41
+
{
42
+
return container_of(chip, struct ts72xx_nand_data, chip);
43
+
}
44
+
45
+
static int ts72xx_nand_attach_chip(struct nand_chip *chip)
46
+
{
47
+
switch (chip->ecc.engine_type) {
48
+
case NAND_ECC_ENGINE_TYPE_ON_HOST:
49
+
return -EINVAL;
50
+
case NAND_ECC_ENGINE_TYPE_SOFT:
51
+
if (chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN)
52
+
chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
53
+
chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
54
+
fallthrough;
55
+
default:
56
+
return 0;
57
+
}
58
+
}
59
+
60
+
static void ts72xx_nand_ctrl(struct nand_chip *chip, u8 value)
61
+
{
62
+
struct ts72xx_nand_data *data = chip_to_ts72xx(chip);
63
+
unsigned char bits = ioread8(data->ctrl) & ~GENMASK(2, 0);
64
+
65
+
iowrite8(bits | value, data->ctrl);
66
+
}
67
+
68
+
static int ts72xx_nand_exec_instr(struct nand_chip *chip,
69
+
const struct nand_op_instr *instr)
70
+
{
71
+
struct ts72xx_nand_data *data = chip_to_ts72xx(chip);
72
+
unsigned int timeout_us;
73
+
u32 status;
74
+
int ret;
75
+
76
+
switch (instr->type) {
77
+
case NAND_OP_CMD_INSTR:
78
+
ts72xx_nand_ctrl(chip, TS72XX_NAND_CTRL_CLE);
79
+
iowrite8(instr->ctx.cmd.opcode, data->base);
80
+
ts72xx_nand_ctrl(chip, TS72XX_NAND_NCE);
81
+
break;
82
+
83
+
case NAND_OP_ADDR_INSTR:
84
+
ts72xx_nand_ctrl(chip, TS72XX_NAND_CTRL_ALE);
85
+
iowrite8_rep(data->base, instr->ctx.addr.addrs, instr->ctx.addr.naddrs);
86
+
ts72xx_nand_ctrl(chip, TS72XX_NAND_NCE);
87
+
break;
88
+
89
+
case NAND_OP_DATA_IN_INSTR:
90
+
ioread8_rep(data->base, instr->ctx.data.buf.in, instr->ctx.data.len);
91
+
break;
92
+
93
+
case NAND_OP_DATA_OUT_INSTR:
94
+
iowrite8_rep(data->base, instr->ctx.data.buf.in, instr->ctx.data.len);
95
+
break;
96
+
97
+
case NAND_OP_WAITRDY_INSTR:
98
+
timeout_us = instr->ctx.waitrdy.timeout_ms * 1000;
99
+
ret = readb_poll_timeout(data->busy, status, status & BIT(5), 0, timeout_us);
100
+
if (ret)
101
+
return ret;
102
+
103
+
break;
104
+
}
105
+
106
+
if (instr->delay_ns)
107
+
ndelay(instr->delay_ns);
108
+
109
+
return 0;
110
+
}
111
+
112
+
static int ts72xx_nand_exec_op(struct nand_chip *chip,
113
+
const struct nand_operation *op, bool check_only)
114
+
{
115
+
unsigned int i;
116
+
int ret;
117
+
118
+
if (check_only)
119
+
return 0;
120
+
121
+
for (i = 0; i < op->ninstrs; i++) {
122
+
ret = ts72xx_nand_exec_instr(chip, &op->instrs[i]);
123
+
if (ret)
124
+
return ret;
125
+
}
126
+
127
+
return 0;
128
+
}
129
+
130
+
static const struct nand_controller_ops ts72xx_nand_ops = {
131
+
.attach_chip = ts72xx_nand_attach_chip,
132
+
.exec_op = ts72xx_nand_exec_op,
133
+
};
134
+
135
+
static int ts72xx_nand_probe(struct platform_device *pdev)
136
+
{
137
+
struct ts72xx_nand_data *data;
138
+
struct fwnode_handle *child;
139
+
struct mtd_info *mtd;
140
+
int err;
141
+
142
+
data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
143
+
if (!data)
144
+
return -ENOMEM;
145
+
146
+
nand_controller_init(&data->controller);
147
+
data->controller.ops = &ts72xx_nand_ops;
148
+
data->chip.controller = &data->controller;
149
+
150
+
data->base = devm_platform_ioremap_resource(pdev, 0);
151
+
if (IS_ERR(data->base))
152
+
return PTR_ERR(data->base);
153
+
data->ctrl = data->base + TS72XX_NAND_CONTROL_ADDR_LINE;
154
+
data->busy = data->base + TS72XX_NAND_BUSY_ADDR_LINE;
155
+
156
+
child = fwnode_get_next_child_node(dev_fwnode(&pdev->dev), NULL);
157
+
if (!child)
158
+
return dev_err_probe(&pdev->dev, -ENXIO,
159
+
"ts72xx controller node should have exactly one child\n");
160
+
161
+
nand_set_flash_node(&data->chip, to_of_node(child));
162
+
mtd = nand_to_mtd(&data->chip);
163
+
mtd->dev.parent = &pdev->dev;
164
+
platform_set_drvdata(pdev, data);
165
+
166
+
/*
167
+
* This driver assumes that the default ECC engine should be TYPE_SOFT.
168
+
* Set ->engine_type before registering the NAND devices in order to
169
+
* provide a driver specific default value.
170
+
*/
171
+
data->chip.ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
172
+
173
+
/* Scan to find existence of the device */
174
+
err = nand_scan(&data->chip, 1);
175
+
if (err)
176
+
goto err_handle_put;
177
+
178
+
err = mtd_device_parse_register(mtd, NULL, NULL, NULL, 0);
179
+
if (err)
180
+
goto err_clean_nand;
181
+
182
+
return 0;
183
+
184
+
err_clean_nand:
185
+
nand_cleanup(&data->chip);
186
+
err_handle_put:
187
+
fwnode_handle_put(child);
188
+
return err;
189
+
}
190
+
191
+
static void ts72xx_nand_remove(struct platform_device *pdev)
192
+
{
193
+
struct ts72xx_nand_data *data = platform_get_drvdata(pdev);
194
+
struct fwnode_handle *fwnode = dev_fwnode(&pdev->dev);
195
+
struct nand_chip *chip = &data->chip;
196
+
int ret;
197
+
198
+
ret = mtd_device_unregister(nand_to_mtd(chip));
199
+
WARN_ON(ret);
200
+
nand_cleanup(chip);
201
+
fwnode_handle_put(fwnode);
202
+
}
203
+
204
+
static const struct of_device_id ts72xx_id_table[] = {
205
+
{ .compatible = "technologic,ts7200-nand" },
206
+
{ /* sentinel */ }
207
+
};
208
+
MODULE_DEVICE_TABLE(of, ts72xx_id_table);
209
+
210
+
static struct platform_driver ts72xx_nand_driver = {
211
+
.driver = {
212
+
.name = "ts72xx-nand",
213
+
.of_match_table = ts72xx_id_table,
214
+
},
215
+
.probe = ts72xx_nand_probe,
216
+
.remove_new = ts72xx_nand_remove,
217
+
};
218
+
module_platform_driver(ts72xx_nand_driver);
219
+
220
+
MODULE_AUTHOR("Nikita Shubin <nikita.shubin@maquefel.me>");
221
+
MODULE_DESCRIPTION("Technologic Systems TS72xx NAND controller driver");
222
+
MODULE_LICENSE("GPL");
+34
-31
drivers/net/ethernet/cirrus/ep93xx_eth.c
+34
-31
drivers/net/ethernet/cirrus/ep93xx_eth.c
···
16
16
#include <linux/ethtool.h>
17
17
#include <linux/interrupt.h>
18
18
#include <linux/moduleparam.h>
19
+
#include <linux/of.h>
19
20
#include <linux/platform_device.h>
20
21
#include <linux/delay.h>
21
22
#include <linux/io.h>
22
23
#include <linux/slab.h>
23
-
24
-
#include <linux/platform_data/eth-ep93xx.h>
25
24
26
25
#define DRV_MODULE_NAME "ep93xx-eth"
27
26
···
737
738
.ndo_set_mac_address = eth_mac_addr,
738
739
};
739
740
740
-
static struct net_device *ep93xx_dev_alloc(struct ep93xx_eth_data *data)
741
-
{
742
-
struct net_device *dev;
743
-
744
-
dev = alloc_etherdev(sizeof(struct ep93xx_priv));
745
-
if (dev == NULL)
746
-
return NULL;
747
-
748
-
eth_hw_addr_set(dev, data->dev_addr);
749
-
750
-
dev->ethtool_ops = &ep93xx_ethtool_ops;
751
-
dev->netdev_ops = &ep93xx_netdev_ops;
752
-
753
-
dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM;
754
-
755
-
return dev;
756
-
}
757
-
758
-
759
741
static void ep93xx_eth_remove(struct platform_device *pdev)
760
742
{
761
743
struct net_device *dev;
···
766
786
767
787
static int ep93xx_eth_probe(struct platform_device *pdev)
768
788
{
769
-
struct ep93xx_eth_data *data;
770
789
struct net_device *dev;
771
790
struct ep93xx_priv *ep;
772
791
struct resource *mem;
792
+
void __iomem *base_addr;
793
+
struct device_node *np;
794
+
u8 addr[ETH_ALEN];
795
+
u32 phy_id;
773
796
int irq;
774
797
int err;
775
798
776
799
if (pdev == NULL)
777
800
return -ENODEV;
778
-
data = dev_get_platdata(&pdev->dev);
779
801
780
802
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
781
803
irq = platform_get_irq(pdev, 0);
782
804
if (!mem || irq < 0)
783
805
return -ENXIO;
784
806
785
-
dev = ep93xx_dev_alloc(data);
807
+
base_addr = ioremap(mem->start, resource_size(mem));
808
+
if (!base_addr)
809
+
return dev_err_probe(&pdev->dev, -EIO, "Failed to ioremap ethernet registers\n");
810
+
811
+
np = of_parse_phandle(pdev->dev.of_node, "phy-handle", 0);
812
+
if (!np)
813
+
return dev_err_probe(&pdev->dev, -ENODEV, "Please provide \"phy-handle\"\n");
814
+
815
+
err = of_property_read_u32(np, "reg", &phy_id);
816
+
of_node_put(np);
817
+
if (err)
818
+
return dev_err_probe(&pdev->dev, -ENOENT, "Failed to locate \"phy_id\"\n");
819
+
820
+
dev = alloc_etherdev(sizeof(struct ep93xx_priv));
786
821
if (dev == NULL) {
787
822
err = -ENOMEM;
788
823
goto err_out;
789
824
}
825
+
826
+
memcpy_fromio(addr, base_addr + 0x50, ETH_ALEN);
827
+
eth_hw_addr_set(dev, addr);
828
+
dev->ethtool_ops = &ep93xx_ethtool_ops;
829
+
dev->netdev_ops = &ep93xx_netdev_ops;
830
+
dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM;
831
+
790
832
ep = netdev_priv(dev);
791
833
ep->dev = dev;
792
834
SET_NETDEV_DEV(dev, &pdev->dev);
···
824
822
goto err_out;
825
823
}
826
824
827
-
ep->base_addr = ioremap(mem->start, resource_size(mem));
828
-
if (ep->base_addr == NULL) {
829
-
dev_err(&pdev->dev, "Failed to ioremap ethernet registers\n");
830
-
err = -EIO;
831
-
goto err_out;
832
-
}
825
+
ep->base_addr = base_addr;
833
826
ep->irq = irq;
834
827
835
-
ep->mii.phy_id = data->phy_id;
828
+
ep->mii.phy_id = phy_id;
836
829
ep->mii.phy_id_mask = 0x1f;
837
830
ep->mii.reg_num_mask = 0x1f;
838
831
ep->mii.dev = dev;
···
854
857
return err;
855
858
}
856
859
860
+
static const struct of_device_id ep93xx_eth_of_ids[] = {
861
+
{ .compatible = "cirrus,ep9301-eth" },
862
+
{ /* sentinel */ }
863
+
};
864
+
MODULE_DEVICE_TABLE(of, ep93xx_eth_of_ids);
857
865
858
866
static struct platform_driver ep93xx_eth_driver = {
859
867
.probe = ep93xx_eth_probe,
860
868
.remove_new = ep93xx_eth_remove,
861
869
.driver = {
862
870
.name = "ep93xx-eth",
871
+
.of_match_table = ep93xx_eth_of_ids,
863
872
},
864
873
};
865
874
+7
drivers/pinctrl/Kconfig
+7
drivers/pinctrl/Kconfig
···
194
194
select PINMUX
195
195
select GENERIC_PINCONF
196
196
197
+
config PINCTRL_EP93XX
198
+
bool
199
+
depends on ARCH_EP93XX || COMPILE_TEST
200
+
select PINMUX
201
+
select GENERIC_PINCONF
202
+
select MFD_SYSCON
203
+
197
204
config PINCTRL_EQUILIBRIUM
198
205
tristate "Generic pinctrl and GPIO driver for Intel Lightning Mountain SoC"
199
206
depends on OF && HAS_IOMEM
+1
drivers/pinctrl/Makefile
+1
drivers/pinctrl/Makefile
···
23
23
obj-$(CONFIG_PINCTRL_DA9062) += pinctrl-da9062.o
24
24
obj-$(CONFIG_PINCTRL_DIGICOLOR) += pinctrl-digicolor.o
25
25
obj-$(CONFIG_PINCTRL_EQUILIBRIUM) += pinctrl-equilibrium.o
26
+
obj-$(CONFIG_PINCTRL_EP93XX) += pinctrl-ep93xx.o
26
27
obj-$(CONFIG_PINCTRL_EYEQ5) += pinctrl-eyeq5.o
27
28
obj-$(CONFIG_PINCTRL_GEMINI) += pinctrl-gemini.o
28
29
obj-$(CONFIG_PINCTRL_INGENIC) += pinctrl-ingenic.o
+1434
drivers/pinctrl/pinctrl-ep93xx.c
+1434
drivers/pinctrl/pinctrl-ep93xx.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Driver for the EP93xx pin controller
4
+
* based on linux/drivers/pinctrl/pinmux-gemini.c
5
+
*
6
+
* Copyright (C) 2022 Nikita Shubin <nikita.shubin@maquefel.me>
7
+
*
8
+
* This is a group-only pin controller.
9
+
*/
10
+
#include <linux/array_size.h>
11
+
#include <linux/err.h>
12
+
#include <linux/init.h>
13
+
#include <linux/io.h>
14
+
#include <linux/mfd/syscon.h>
15
+
#include <linux/property.h>
16
+
#include <linux/regmap.h>
17
+
#include <linux/seq_file.h>
18
+
#include <linux/slab.h>
19
+
20
+
#include <linux/soc/cirrus/ep93xx.h>
21
+
22
+
#include <linux/pinctrl/machine.h>
23
+
#include <linux/pinctrl/pinconf-generic.h>
24
+
#include <linux/pinctrl/pinconf.h>
25
+
#include <linux/pinctrl/pinctrl.h>
26
+
#include <linux/pinctrl/pinmux.h>
27
+
28
+
#include "pinctrl-utils.h"
29
+
30
+
#define DRIVER_NAME "pinctrl-ep93xx"
31
+
32
+
enum ep93xx_pinctrl_model {
33
+
EP93XX_9301_PINCTRL,
34
+
EP93XX_9307_PINCTRL,
35
+
EP93XX_9312_PINCTRL,
36
+
};
37
+
38
+
struct ep93xx_pmx {
39
+
struct device *dev;
40
+
struct pinctrl_dev *pctl;
41
+
struct ep93xx_regmap_adev *aux_dev;
42
+
struct regmap *map;
43
+
enum ep93xx_pinctrl_model model;
44
+
};
45
+
46
+
static void ep93xx_pinctrl_update_bits(struct ep93xx_pmx *pmx, unsigned int reg,
47
+
unsigned int mask, unsigned int val)
48
+
{
49
+
struct ep93xx_regmap_adev *aux = pmx->aux_dev;
50
+
51
+
aux->update_bits(aux->map, aux->lock, reg, mask, val);
52
+
}
53
+
54
+
struct ep93xx_pin_group {
55
+
struct pingroup grp;
56
+
u32 mask;
57
+
u32 value;
58
+
};
59
+
60
+
#define PMX_GROUP(_name, _pins, _mask, _value) \
61
+
{ \
62
+
.grp = PINCTRL_PINGROUP(_name, _pins, ARRAY_SIZE(_pins)), \
63
+
.mask = _mask, \
64
+
.value = _value, \
65
+
}
66
+
67
+
#define EP93XX_SYSCON_DEVCFG 0x80
68
+
69
+
/*
70
+
* There are several system configuration options selectable by the DeviceCfg and SysCfg
71
+
* registers. These registers provide the selection of several pin multiplexing options and also
72
+
* provide software access to the system reset configuration options. Please refer to the
73
+
* descriptions of the registers, “DeviceCfg” on page 5-25 and “SysCfg” on page 5-34, for a
74
+
* detailed explanation.
75
+
*/
76
+
#define EP93XX_SYSCON_DEVCFG_D1ONG BIT(30)
77
+
#define EP93XX_SYSCON_DEVCFG_D0ONG BIT(29)
78
+
#define EP93XX_SYSCON_DEVCFG_IONU2 BIT(28)
79
+
#define EP93XX_SYSCON_DEVCFG_GONK BIT(27)
80
+
#define EP93XX_SYSCON_DEVCFG_TONG BIT(26)
81
+
#define EP93XX_SYSCON_DEVCFG_MONG BIT(25)
82
+
#define EP93XX_SYSCON_DEVCFG_A2ONG BIT(22)
83
+
#define EP93XX_SYSCON_DEVCFG_A1ONG BIT(21)
84
+
#define EP93XX_SYSCON_DEVCFG_HONIDE BIT(11)
85
+
#define EP93XX_SYSCON_DEVCFG_GONIDE BIT(10)
86
+
#define EP93XX_SYSCON_DEVCFG_PONG BIT(9)
87
+
#define EP93XX_SYSCON_DEVCFG_EONIDE BIT(8)
88
+
#define EP93XX_SYSCON_DEVCFG_I2SONSSP BIT(7)
89
+
#define EP93XX_SYSCON_DEVCFG_I2SONAC97 BIT(6)
90
+
#define EP93XX_SYSCON_DEVCFG_RASONP3 BIT(4)
91
+
92
+
#define PADS_MASK (GENMASK(30, 25) | BIT(22) | BIT(21) | GENMASK(11, 6) | BIT(4))
93
+
#define PADS_MAXBIT 30
94
+
95
+
/* Ordered by bit index */
96
+
static const char * const ep93xx_padgroups[] = {
97
+
NULL, NULL, NULL, NULL,
98
+
"RasOnP3",
99
+
NULL,
100
+
"I2SonAC97",
101
+
"I2SonSSP",
102
+
"EonIDE",
103
+
"PonG",
104
+
"GonIDE",
105
+
"HonIDE",
106
+
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
107
+
"A1onG",
108
+
"A2onG",
109
+
NULL, NULL,
110
+
"MonG",
111
+
"TonG",
112
+
"GonK",
113
+
"IonU2",
114
+
"D0onG",
115
+
"D1onG",
116
+
};
117
+
118
+
/* ep9301, ep9302 */
119
+
static const struct pinctrl_pin_desc ep9301_pins[] = {
120
+
PINCTRL_PIN(1, "CSn[7]"),
121
+
PINCTRL_PIN(2, "CSn[6]"),
122
+
PINCTRL_PIN(3, "CSn[3]"),
123
+
PINCTRL_PIN(4, "CSn[2]"),
124
+
PINCTRL_PIN(5, "CSn[1]"),
125
+
PINCTRL_PIN(6, "AD[25]"),
126
+
PINCTRL_PIN(7, "vdd_ring"),
127
+
PINCTRL_PIN(8, "gnd_ring"),
128
+
PINCTRL_PIN(9, "AD[24]"),
129
+
PINCTRL_PIN(10, "SDCLK"),
130
+
PINCTRL_PIN(11, "AD[23]"),
131
+
PINCTRL_PIN(12, "vdd_core"),
132
+
PINCTRL_PIN(13, "gnd_core"),
133
+
PINCTRL_PIN(14, "SDWEn"),
134
+
PINCTRL_PIN(15, "SDCSn[3]"),
135
+
PINCTRL_PIN(16, "SDCSn[2]"),
136
+
PINCTRL_PIN(17, "SDCSn[1]"),
137
+
PINCTRL_PIN(18, "SDCSn[0]"),
138
+
PINCTRL_PIN(19, "vdd_ring"),
139
+
PINCTRL_PIN(20, "gnd_ring"),
140
+
PINCTRL_PIN(21, "RASn"),
141
+
PINCTRL_PIN(22, "CASn"),
142
+
PINCTRL_PIN(23, "DQMn[1]"),
143
+
PINCTRL_PIN(24, "DQMn[0]"),
144
+
PINCTRL_PIN(25, "AD[22]"),
145
+
PINCTRL_PIN(26, "AD[21]"),
146
+
PINCTRL_PIN(27, "vdd_ring"),
147
+
PINCTRL_PIN(28, "gnd_ring"),
148
+
PINCTRL_PIN(29, "DA[15]"),
149
+
PINCTRL_PIN(30, "AD[7]"),
150
+
PINCTRL_PIN(31, "DA[14]"),
151
+
PINCTRL_PIN(32, "AD[6]"),
152
+
PINCTRL_PIN(33, "DA[13]"),
153
+
PINCTRL_PIN(34, "vdd_core"),
154
+
PINCTRL_PIN(35, "gnd_core"),
155
+
PINCTRL_PIN(36, "AD[5]"),
156
+
PINCTRL_PIN(37, "DA[12]"),
157
+
PINCTRL_PIN(38, "AD[4]"),
158
+
PINCTRL_PIN(39, "DA[11]"),
159
+
PINCTRL_PIN(40, "AD[3]"),
160
+
PINCTRL_PIN(41, "vdd_ring"),
161
+
PINCTRL_PIN(42, "gnd_ring"),
162
+
PINCTRL_PIN(43, "DA[10]"),
163
+
PINCTRL_PIN(44, "AD[2]"),
164
+
PINCTRL_PIN(45, "DA[9]"),
165
+
PINCTRL_PIN(46, "AD[1]"),
166
+
PINCTRL_PIN(47, "DA[8]"),
167
+
PINCTRL_PIN(48, "AD[0]"),
168
+
PINCTRL_PIN(49, "vdd_ring"),
169
+
PINCTRL_PIN(50, "gnd_ring"),
170
+
PINCTRL_PIN(51, "NC"),
171
+
PINCTRL_PIN(52, "NC"),
172
+
PINCTRL_PIN(53, "vdd_ring"),
173
+
PINCTRL_PIN(54, "gnd_ring"),
174
+
PINCTRL_PIN(55, "AD[15]"),
175
+
PINCTRL_PIN(56, "DA[7]"),
176
+
PINCTRL_PIN(57, "vdd_core"),
177
+
PINCTRL_PIN(58, "gnd_core"),
178
+
PINCTRL_PIN(59, "AD[14]"),
179
+
PINCTRL_PIN(60, "DA[6]"),
180
+
PINCTRL_PIN(61, "AD[13]"),
181
+
PINCTRL_PIN(62, "DA[5]"),
182
+
PINCTRL_PIN(63, "AD[12]"),
183
+
PINCTRL_PIN(64, "DA[4]"),
184
+
PINCTRL_PIN(65, "AD[11]"),
185
+
PINCTRL_PIN(66, "vdd_ring"),
186
+
PINCTRL_PIN(67, "gnd_ring"),
187
+
PINCTRL_PIN(68, "DA[3]"),
188
+
PINCTRL_PIN(69, "AD[10]"),
189
+
PINCTRL_PIN(70, "DA[2]"),
190
+
PINCTRL_PIN(71, "AD[9]"),
191
+
PINCTRL_PIN(72, "DA[1]"),
192
+
PINCTRL_PIN(73, "AD[8]"),
193
+
PINCTRL_PIN(74, "DA[0]"),
194
+
PINCTRL_PIN(75, "DSRn"),
195
+
PINCTRL_PIN(76, "DTRn"),
196
+
PINCTRL_PIN(77, "TCK"),
197
+
PINCTRL_PIN(78, "TDI"),
198
+
PINCTRL_PIN(79, "TDO"),
199
+
PINCTRL_PIN(80, "TMS"),
200
+
PINCTRL_PIN(81, "vdd_ring"),
201
+
PINCTRL_PIN(82, "gnd_ring"),
202
+
PINCTRL_PIN(83, "BOOT[1]"),
203
+
PINCTRL_PIN(84, "BOOT[0]"),
204
+
PINCTRL_PIN(85, "gnd_ring"),
205
+
PINCTRL_PIN(86, "NC"),
206
+
PINCTRL_PIN(87, "EECLK"),
207
+
PINCTRL_PIN(88, "EEDAT"),
208
+
PINCTRL_PIN(89, "ASYNC"),
209
+
PINCTRL_PIN(90, "vdd_core"),
210
+
PINCTRL_PIN(91, "gnd_core"),
211
+
PINCTRL_PIN(92, "ASDO"),
212
+
PINCTRL_PIN(93, "SCLK1"),
213
+
PINCTRL_PIN(94, "SFRM1"),
214
+
PINCTRL_PIN(95, "SSPRX1"),
215
+
PINCTRL_PIN(96, "SSPTX1"),
216
+
PINCTRL_PIN(97, "GRLED"),
217
+
PINCTRL_PIN(98, "RDLED"),
218
+
PINCTRL_PIN(99, "vdd_ring"),
219
+
PINCTRL_PIN(100, "gnd_ring"),
220
+
PINCTRL_PIN(101, "INT[3]"),
221
+
PINCTRL_PIN(102, "INT[1]"),
222
+
PINCTRL_PIN(103, "INT[0]"),
223
+
PINCTRL_PIN(104, "RTSn"),
224
+
PINCTRL_PIN(105, "USBm[0]"),
225
+
PINCTRL_PIN(106, "USBp[0]"),
226
+
PINCTRL_PIN(107, "ABITCLK"),
227
+
PINCTRL_PIN(108, "CTSn"),
228
+
PINCTRL_PIN(109, "RXD[0]"),
229
+
PINCTRL_PIN(110, "RXD[1]"),
230
+
PINCTRL_PIN(111, "vdd_ring"),
231
+
PINCTRL_PIN(112, "gnd_ring"),
232
+
PINCTRL_PIN(113, "TXD[0]"),
233
+
PINCTRL_PIN(114, "TXD[1]"),
234
+
PINCTRL_PIN(115, "CGPIO[0]"),
235
+
PINCTRL_PIN(116, "gnd_core"),
236
+
PINCTRL_PIN(117, "PLL_GND"),
237
+
PINCTRL_PIN(118, "XTALI"),
238
+
PINCTRL_PIN(119, "XTALO"),
239
+
PINCTRL_PIN(120, "PLL_VDD"),
240
+
PINCTRL_PIN(121, "vdd_core"),
241
+
PINCTRL_PIN(122, "gnd_ring"),
242
+
PINCTRL_PIN(123, "vdd_ring"),
243
+
PINCTRL_PIN(124, "RSTOn"),
244
+
PINCTRL_PIN(125, "PRSTn"),
245
+
PINCTRL_PIN(126, "CSn[0]"),
246
+
PINCTRL_PIN(127, "gnd_core"),
247
+
PINCTRL_PIN(128, "vdd_core"),
248
+
PINCTRL_PIN(129, "gnd_ring"),
249
+
PINCTRL_PIN(130, "vdd_ring"),
250
+
PINCTRL_PIN(131, "ADC[4]"),
251
+
PINCTRL_PIN(132, "ADC[3]"),
252
+
PINCTRL_PIN(133, "ADC[2]"),
253
+
PINCTRL_PIN(134, "ADC[1]"),
254
+
PINCTRL_PIN(135, "ADC[0]"),
255
+
PINCTRL_PIN(136, "ADC_VDD"),
256
+
PINCTRL_PIN(137, "RTCXTALI"),
257
+
PINCTRL_PIN(138, "RTCXTALO"),
258
+
PINCTRL_PIN(139, "ADC_GND"),
259
+
PINCTRL_PIN(140, "EGPIO[11]"),
260
+
PINCTRL_PIN(141, "EGPIO[10]"),
261
+
PINCTRL_PIN(142, "EGPIO[9]"),
262
+
PINCTRL_PIN(143, "EGPIO[8]"),
263
+
PINCTRL_PIN(144, "EGPIO[7]"),
264
+
PINCTRL_PIN(145, "EGPIO[6]"),
265
+
PINCTRL_PIN(146, "EGPIO[5]"),
266
+
PINCTRL_PIN(147, "EGPIO[4]"),
267
+
PINCTRL_PIN(148, "EGPIO[3]"),
268
+
PINCTRL_PIN(149, "gnd_ring"),
269
+
PINCTRL_PIN(150, "vdd_ring"),
270
+
PINCTRL_PIN(151, "EGPIO[2]"),
271
+
PINCTRL_PIN(152, "EGPIO[1]"),
272
+
PINCTRL_PIN(153, "EGPIO[0]"),
273
+
PINCTRL_PIN(154, "ARSTn"),
274
+
PINCTRL_PIN(155, "TRSTn"),
275
+
PINCTRL_PIN(156, "ASDI"),
276
+
PINCTRL_PIN(157, "USBm[2]"),
277
+
PINCTRL_PIN(158, "USBp[2]"),
278
+
PINCTRL_PIN(159, "WAITn"),
279
+
PINCTRL_PIN(160, "EGPIO[15]"),
280
+
PINCTRL_PIN(161, "gnd_ring"),
281
+
PINCTRL_PIN(162, "vdd_ring"),
282
+
PINCTRL_PIN(163, "EGPIO[14]"),
283
+
PINCTRL_PIN(164, "EGPIO[13]"),
284
+
PINCTRL_PIN(165, "EGPIO[12]"),
285
+
PINCTRL_PIN(166, "gnd_core"),
286
+
PINCTRL_PIN(167, "vdd_core"),
287
+
PINCTRL_PIN(168, "FGPIO[3]"),
288
+
PINCTRL_PIN(169, "FGPIO[2]"),
289
+
PINCTRL_PIN(170, "FGPIO[1]"),
290
+
PINCTRL_PIN(171, "gnd_ring"),
291
+
PINCTRL_PIN(172, "vdd_ring"),
292
+
PINCTRL_PIN(173, "CLD"),
293
+
PINCTRL_PIN(174, "CRS"),
294
+
PINCTRL_PIN(175, "TXERR"),
295
+
PINCTRL_PIN(176, "TXEN"),
296
+
PINCTRL_PIN(177, "MIITXD[0]"),
297
+
PINCTRL_PIN(178, "MIITXD[1]"),
298
+
PINCTRL_PIN(179, "MIITXD[2]"),
299
+
PINCTRL_PIN(180, "MIITXD[3]"),
300
+
PINCTRL_PIN(181, "TXCLK"),
301
+
PINCTRL_PIN(182, "RXERR"),
302
+
PINCTRL_PIN(183, "RXDVAL"),
303
+
PINCTRL_PIN(184, "MIIRXD[0]"),
304
+
PINCTRL_PIN(185, "MIIRXD[1]"),
305
+
PINCTRL_PIN(186, "MIIRXD[2]"),
306
+
PINCTRL_PIN(187, "gnd_ring"),
307
+
PINCTRL_PIN(188, "vdd_ring"),
308
+
PINCTRL_PIN(189, "MIIRXD[3]"),
309
+
PINCTRL_PIN(190, "RXCLK"),
310
+
PINCTRL_PIN(191, "MDIO"),
311
+
PINCTRL_PIN(192, "MDC"),
312
+
PINCTRL_PIN(193, "RDn"),
313
+
PINCTRL_PIN(194, "WRn"),
314
+
PINCTRL_PIN(195, "AD[16]"),
315
+
PINCTRL_PIN(196, "AD[17]"),
316
+
PINCTRL_PIN(197, "gnd_core"),
317
+
PINCTRL_PIN(198, "vdd_core"),
318
+
PINCTRL_PIN(199, "HGPIO[2]"),
319
+
PINCTRL_PIN(200, "HGPIO[3]"),
320
+
PINCTRL_PIN(201, "HGPIO[4]"),
321
+
PINCTRL_PIN(202, "HGPIO[5]"),
322
+
PINCTRL_PIN(203, "gnd_ring"),
323
+
PINCTRL_PIN(204, "vdd_ring"),
324
+
PINCTRL_PIN(205, "AD[18]"),
325
+
PINCTRL_PIN(206, "AD[19]"),
326
+
PINCTRL_PIN(207, "AD[20]"),
327
+
PINCTRL_PIN(208, "SDCLKEN"),
328
+
};
329
+
330
+
static const unsigned int ssp_ep9301_pins[] = {
331
+
93, 94, 95, 96,
332
+
};
333
+
334
+
static const unsigned int ac97_ep9301_pins[] = {
335
+
89, 92, 107, 154, 156,
336
+
};
337
+
338
+
/*
339
+
* Note: The EP9307 processor has one PWM with one output, PWMOUT.
340
+
* Note: The EP9301, EP9302, EP9312, and EP9315 processors each have two PWMs with
341
+
* two outputs, PWMOUT and PWMO1. PWMO1 is an alternate function for EGPIO14.
342
+
*/
343
+
/* The GPIO14E (14) pin overlap with pwm1 */
344
+
static const unsigned int pwm_9301_pins[] = { 163 };
345
+
346
+
static const unsigned int gpio1a_9301_pins[] = { 163 };
347
+
348
+
/* ep9301/9302 have only 0 pin of GPIO C Port exposed */
349
+
static const unsigned int gpio2a_9301_pins[] = { 115 };
350
+
351
+
/* ep9301/9302 have only 4,5 pin of GPIO E Port exposed */
352
+
static const unsigned int gpio4a_9301_pins[] = { 97, 98 };
353
+
354
+
/* ep9301/9302 have only 4,5 pin of GPIO G Port exposed */
355
+
static const unsigned int gpio6a_9301_pins[] = { 87, 88 };
356
+
357
+
static const unsigned int gpio7a_9301_pins[] = { 199, 200, 201, 202 };
358
+
359
+
/* Groups for the ep9301/ep9302 SoC/package */
360
+
static const struct ep93xx_pin_group ep9301_pin_groups[] = {
361
+
PMX_GROUP("ssp", ssp_ep9301_pins, EP93XX_SYSCON_DEVCFG_I2SONSSP, 0),
362
+
PMX_GROUP("i2s_on_ssp", ssp_ep9301_pins, EP93XX_SYSCON_DEVCFG_I2SONSSP,
363
+
EP93XX_SYSCON_DEVCFG_I2SONSSP),
364
+
PMX_GROUP("ac97", ac97_ep9301_pins, EP93XX_SYSCON_DEVCFG_I2SONAC97, 0),
365
+
PMX_GROUP("i2s_on_ac97", ac97_ep9301_pins, EP93XX_SYSCON_DEVCFG_I2SONAC97,
366
+
EP93XX_SYSCON_DEVCFG_I2SONAC97),
367
+
PMX_GROUP("pwm1", pwm_9301_pins, EP93XX_SYSCON_DEVCFG_PONG, EP93XX_SYSCON_DEVCFG_PONG),
368
+
PMX_GROUP("gpio1agrp", gpio1a_9301_pins, EP93XX_SYSCON_DEVCFG_PONG, 0),
369
+
PMX_GROUP("gpio2agrp", gpio2a_9301_pins, EP93XX_SYSCON_DEVCFG_GONK,
370
+
EP93XX_SYSCON_DEVCFG_GONK),
371
+
PMX_GROUP("gpio4agrp", gpio4a_9301_pins, EP93XX_SYSCON_DEVCFG_EONIDE,
372
+
EP93XX_SYSCON_DEVCFG_EONIDE),
373
+
PMX_GROUP("gpio6agrp", gpio6a_9301_pins, EP93XX_SYSCON_DEVCFG_GONIDE,
374
+
EP93XX_SYSCON_DEVCFG_GONIDE),
375
+
PMX_GROUP("gpio7agrp", gpio7a_9301_pins, EP93XX_SYSCON_DEVCFG_HONIDE,
376
+
EP93XX_SYSCON_DEVCFG_HONIDE),
377
+
};
378
+
379
+
static const struct pinctrl_pin_desc ep9307_pins[] = {
380
+
/* Row A */
381
+
PINCTRL_PIN(0, "CSn[1]"), /* A1 */
382
+
PINCTRL_PIN(1, "CSn[7]"), /* A2 */
383
+
PINCTRL_PIN(2, "SDCLKEN"), /* A3 */
384
+
PINCTRL_PIN(3, "DA[31]"), /* A4 */
385
+
PINCTRL_PIN(4, "DA[29]"), /* A5 */
386
+
PINCTRL_PIN(5, "DA[27]"), /* A6 */
387
+
PINCTRL_PIN(6, "HGPIO[2]"), /* A7 */
388
+
PINCTRL_PIN(7, "RDn"), /* A8 */
389
+
PINCTRL_PIN(8, "MIIRXD[3]"), /* A9 */
390
+
PINCTRL_PIN(9, "RXDVAL"), /* A10 */
391
+
PINCTRL_PIN(10, "MIITXD[1]"), /* A11 */
392
+
PINCTRL_PIN(11, "CRS"), /* A12 */
393
+
PINCTRL_PIN(12, "FGPIO[7]"), /* A13 */
394
+
PINCTRL_PIN(13, "FGPIO[0]"), /* A14 */
395
+
PINCTRL_PIN(14, "WAITn"), /* A15 */
396
+
PINCTRL_PIN(15, "USBm[2]"), /* A16 */
397
+
PINCTRL_PIN(16, "ASDI"), /* A17 */
398
+
/* Row B */
399
+
PINCTRL_PIN(17, "AD[25]"), /* B1 */
400
+
PINCTRL_PIN(18, "CSn[2]"), /* B2 */
401
+
PINCTRL_PIN(19, "CSn[6]"), /* B3 */
402
+
PINCTRL_PIN(20, "AD[20]"), /* B4 */
403
+
PINCTRL_PIN(21, "DA[30]"), /* B5 */
404
+
PINCTRL_PIN(22, "AD[18]"), /* B6 */
405
+
PINCTRL_PIN(23, "HGPIO[3]"), /* B7 */
406
+
PINCTRL_PIN(24, "AD[17]"), /* B8 */
407
+
PINCTRL_PIN(25, "RXCLK"), /* B9 */
408
+
PINCTRL_PIN(26, "MIIRXD[1]"), /* B10 */
409
+
PINCTRL_PIN(27, "MIITXD[2]"), /* B11 */
410
+
PINCTRL_PIN(28, "TXEN"), /* B12 */
411
+
PINCTRL_PIN(29, "FGPIO[5]"), /* B13 */
412
+
PINCTRL_PIN(30, "EGPIO[15]"), /* B14 */
413
+
PINCTRL_PIN(31, "USBp[2]"), /* B15 */
414
+
PINCTRL_PIN(32, "ARSTn"), /* B16 */
415
+
PINCTRL_PIN(33, "ADC_VDD"), /* B17 */
416
+
/* Row C */
417
+
PINCTRL_PIN(34, "AD[23]"), /* C1 */
418
+
PINCTRL_PIN(35, "DA[26]"), /* C2 */
419
+
PINCTRL_PIN(36, "CSn[3]"), /* C3 */
420
+
PINCTRL_PIN(37, "DA[25]"), /* C4 */
421
+
PINCTRL_PIN(38, "AD[24]"), /* C5 */
422
+
PINCTRL_PIN(39, "AD[19]"), /* C6 */
423
+
PINCTRL_PIN(40, "HGPIO[5]"), /* C7 */
424
+
PINCTRL_PIN(41, "WRn"), /* C8 */
425
+
PINCTRL_PIN(42, "MDIO"), /* C9 */
426
+
PINCTRL_PIN(43, "MIIRXD[2]"), /* C10 */
427
+
PINCTRL_PIN(44, "TXCLK"), /* C11 */
428
+
PINCTRL_PIN(45, "MIITXD[0]"), /* C12 */
429
+
PINCTRL_PIN(46, "CLD"), /* C13 */
430
+
PINCTRL_PIN(47, "EGPIO[13]"), /* C14 */
431
+
PINCTRL_PIN(48, "TRSTn"), /* C15 */
432
+
PINCTRL_PIN(49, "Xp"), /* C16 */
433
+
PINCTRL_PIN(50, "Xm"), /* C17 */
434
+
/* Row D */
435
+
PINCTRL_PIN(51, "SDCSn[3]"), /* D1 */
436
+
PINCTRL_PIN(52, "DA[23]"), /* D2 */
437
+
PINCTRL_PIN(53, "SDCLK"), /* D3 */
438
+
PINCTRL_PIN(54, "DA[24]"), /* D4 */
439
+
PINCTRL_PIN(55, "HGPIO[7]"), /* D5 */
440
+
PINCTRL_PIN(56, "HGPIO[6]"), /* D6 */
441
+
PINCTRL_PIN(57, "A[28]"), /* D7 */
442
+
PINCTRL_PIN(58, "HGPIO[4]"), /* D8 */
443
+
PINCTRL_PIN(59, "AD[16]"), /* D9 */
444
+
PINCTRL_PIN(60, "MDC"), /* D10 */
445
+
PINCTRL_PIN(61, "RXERR"), /* D11 */
446
+
PINCTRL_PIN(62, "MIITXD[3]"), /* D12 */
447
+
PINCTRL_PIN(63, "EGPIO[12]"), /* D13 */
448
+
PINCTRL_PIN(64, "EGPIO[1]"), /* D14 */
449
+
PINCTRL_PIN(65, "EGPIO[0]"), /* D15 */
450
+
PINCTRL_PIN(66, "Ym"), /* D16 */
451
+
PINCTRL_PIN(67, "Yp"), /* D17 */
452
+
/* Row E */
453
+
PINCTRL_PIN(68, "SDCSn[2]"), /* E1 */
454
+
PINCTRL_PIN(69, "SDWEN"), /* E2 */
455
+
PINCTRL_PIN(70, "DA[22]"), /* E3 */
456
+
PINCTRL_PIN(71, "AD[3]"), /* E4 */
457
+
PINCTRL_PIN(72, "DA[15]"), /* E5 */
458
+
PINCTRL_PIN(73, "AD[21]"), /* E6 */
459
+
PINCTRL_PIN(74, "DA[17]"), /* E7 */
460
+
PINCTRL_PIN(75, "vddr"), /* E8 */
461
+
PINCTRL_PIN(76, "vddr"), /* E9 */
462
+
PINCTRL_PIN(77, "vddr"), /* E10 */
463
+
PINCTRL_PIN(78, "MIIRXD[0]"), /* E11 */
464
+
PINCTRL_PIN(79, "TXERR"), /* E12 */
465
+
PINCTRL_PIN(80, "EGPIO[2]"), /* E13 */
466
+
PINCTRL_PIN(81, "EGPIO[4]"), /* E14 */
467
+
PINCTRL_PIN(82, "EGPIO[3]"), /* E15 */
468
+
PINCTRL_PIN(83, "sXp"), /* E16 */
469
+
PINCTRL_PIN(84, "sXm"), /* E17 */
470
+
/* Row F */
471
+
PINCTRL_PIN(85, "RASn"), /* F1 */
472
+
PINCTRL_PIN(86, "SDCSn[1]"), /* F2 */
473
+
PINCTRL_PIN(87, "SDCSn[0]"), /* F3 */
474
+
PINCTRL_PIN(88, "DQMn[3]"), /* F4 */
475
+
PINCTRL_PIN(89, "AD[5]"), /* F5 */
476
+
PINCTRL_PIN(90, "gndr"), /* F6 */
477
+
PINCTRL_PIN(91, "gndr"), /* F7 */
478
+
PINCTRL_PIN(92, "gndr"), /* F8 */
479
+
PINCTRL_PIN(93, "vddc"), /* F9 */
480
+
PINCTRL_PIN(94, "vddc"), /* F10 */
481
+
PINCTRL_PIN(95, "gndr"), /* F11 */
482
+
PINCTRL_PIN(96, "EGPIO[7]"), /* F12 */
483
+
PINCTRL_PIN(97, "EGPIO[5]"), /* F13 */
484
+
PINCTRL_PIN(98, "ADC GND"), /* F14 */
485
+
PINCTRL_PIN(99, "EGPIO[6]"), /* F15 */
486
+
PINCTRL_PIN(100, "sYm"), /* F16 */
487
+
PINCTRL_PIN(101, "syp"), /* F17 */
488
+
/* Row G */
489
+
PINCTRL_PIN(102, "DQMn[0]"), /* G1 */
490
+
PINCTRL_PIN(103, "CASn"), /* G2 */
491
+
PINCTRL_PIN(104, "DA[21]"), /* G3 */
492
+
PINCTRL_PIN(105, "AD[22]"), /* G4 */
493
+
PINCTRL_PIN(106, "vddr"), /* G5 */
494
+
PINCTRL_PIN(107, "gndr"), /* G6 */
495
+
PINCTRL_PIN(108, "gndr"), /* G12 */
496
+
PINCTRL_PIN(109, "EGPIO[9]"), /* G13 */
497
+
PINCTRL_PIN(110, "EGPIO[10]"), /* G14 */
498
+
PINCTRL_PIN(111, "EGPIO[11]"), /* G15 */
499
+
PINCTRL_PIN(112, "RTCXTALO"), /* G16 */
500
+
PINCTRL_PIN(113, "RTCXTALI"), /* G17 */
501
+
/* Row H */
502
+
PINCTRL_PIN(114, "DA[18]"), /* H1 */
503
+
PINCTRL_PIN(115, "DA[20]"), /* H2 */
504
+
PINCTRL_PIN(116, "DA[19]"), /* H3 */
505
+
PINCTRL_PIN(117, "DA[16]"), /* H4 */
506
+
PINCTRL_PIN(118, "vddr"), /* H5 */
507
+
PINCTRL_PIN(119, "vddc"), /* H6 */
508
+
PINCTRL_PIN(120, "gndc"), /* H7 */
509
+
PINCTRL_PIN(121, "gndc"), /* H9 */
510
+
PINCTRL_PIN(122, "gndc"), /* H10 */
511
+
PINCTRL_PIN(123, "gndr"), /* H12 */
512
+
PINCTRL_PIN(124, "vddr"), /* H13 */
513
+
PINCTRL_PIN(125, "EGPIO[8]"), /* H14 */
514
+
PINCTRL_PIN(126, "PRSTN"), /* H15 */
515
+
PINCTRL_PIN(127, "COL[7]"), /* H16 */
516
+
PINCTRL_PIN(128, "RSTON"), /* H17 */
517
+
/* Row J */
518
+
PINCTRL_PIN(129, "AD[6]"), /* J1 */
519
+
PINCTRL_PIN(130, "DA[14]"), /* J2 */
520
+
PINCTRL_PIN(131, "AD[7]"), /* J3 */
521
+
PINCTRL_PIN(132, "DA[13]"), /* J4 */
522
+
PINCTRL_PIN(133, "vddr"), /* J5 */
523
+
PINCTRL_PIN(134, "vddc"), /* J6 */
524
+
PINCTRL_PIN(135, "gndc"), /* J8 */
525
+
PINCTRL_PIN(136, "gndc"), /* J10 */
526
+
PINCTRL_PIN(137, "vddc"), /* J12 */
527
+
PINCTRL_PIN(138, "vddr"), /* J13 */
528
+
PINCTRL_PIN(139, "COL[5]"), /* J14 */
529
+
PINCTRL_PIN(140, "COL[6]"), /* J15 */
530
+
PINCTRL_PIN(141, "CSn[0]"), /* J16 */
531
+
PINCTRL_PIN(142, "COL[3]"), /* J17 */
532
+
/* Row K */
533
+
PINCTRL_PIN(143, "AD[4]"), /* K1 */
534
+
PINCTRL_PIN(144, "DA[12]"), /* K2 */
535
+
PINCTRL_PIN(145, "DA[10]"), /* K3 */
536
+
PINCTRL_PIN(146, "DA[11]"), /* K4 */
537
+
PINCTRL_PIN(147, "vddr"), /* K5 */
538
+
PINCTRL_PIN(148, "gndr"), /* K6 */
539
+
PINCTRL_PIN(149, "gndc"), /* K8 */
540
+
PINCTRL_PIN(150, "gndc"), /* K9 */
541
+
PINCTRL_PIN(151, "gndc"), /* K10 */
542
+
PINCTRL_PIN(152, "vddc"), /* K12 */
543
+
PINCTRL_PIN(153, "COL[4]"), /* K13 */
544
+
PINCTRL_PIN(154, "PLL_VDD"), /* K14 */
545
+
PINCTRL_PIN(155, "COL[2]"), /* K15 */
546
+
PINCTRL_PIN(156, "COL[1]"), /* K16 */
547
+
PINCTRL_PIN(157, "COL[0]"), /* K17 */
548
+
/* Row L */
549
+
PINCTRL_PIN(158, "DA[9]"), /* L1 */
550
+
PINCTRL_PIN(159, "AD[2]"), /* L2 */
551
+
PINCTRL_PIN(160, "AD[1]"), /* L3 */
552
+
PINCTRL_PIN(161, "DA[8]"), /* L4 */
553
+
PINCTRL_PIN(162, "BLANK"), /* L5 */
554
+
PINCTRL_PIN(163, "gndr"), /* L6 */
555
+
PINCTRL_PIN(164, "gndr"), /* L7 */
556
+
PINCTRL_PIN(165, "ROW[7]"), /* L8 */
557
+
PINCTRL_PIN(166, "ROW[5]"), /* L9 */
558
+
PINCTRL_PIN(167, "PLL GND"), /* L10 */
559
+
PINCTRL_PIN(168, "XTALI"), /* L11 */
560
+
PINCTRL_PIN(169, "XTALO"), /* L12 */
561
+
/* Row M */
562
+
PINCTRL_PIN(170, "BRIGHT"), /* M1 */
563
+
PINCTRL_PIN(171, "AD[0]"), /* M2 */
564
+
PINCTRL_PIN(172, "DQMn[1]"), /* M3 */
565
+
PINCTRL_PIN(173, "DQMn[2]"), /* M4 */
566
+
PINCTRL_PIN(174, "P[17]"), /* M5 */
567
+
PINCTRL_PIN(175, "gndr"), /* M6 */
568
+
PINCTRL_PIN(176, "gndr"), /* M7 */
569
+
PINCTRL_PIN(177, "vddc"), /* M8 */
570
+
PINCTRL_PIN(178, "vddc"), /* M9 */
571
+
PINCTRL_PIN(179, "gndr"), /* M10 */
572
+
PINCTRL_PIN(180, "gndr"), /* M11 */
573
+
PINCTRL_PIN(181, "ROW[6]"), /* M12 */
574
+
PINCTRL_PIN(182, "ROW[4]"), /* M13 */
575
+
PINCTRL_PIN(183, "ROW[1]"), /* M14 */
576
+
PINCTRL_PIN(184, "ROW[0]"), /* M15 */
577
+
PINCTRL_PIN(185, "ROW[3]"), /* M16 */
578
+
PINCTRL_PIN(186, "ROW[2]"), /* M17 */
579
+
/* Row N */
580
+
PINCTRL_PIN(187, "P[14]"), /* N1 */
581
+
PINCTRL_PIN(188, "P[16]"), /* N2 */
582
+
PINCTRL_PIN(189, "P[15]"), /* N3 */
583
+
PINCTRL_PIN(190, "P[13]"), /* N4 */
584
+
PINCTRL_PIN(191, "P[12]"), /* N5 */
585
+
PINCTRL_PIN(192, "DA[5]"), /* N6 */
586
+
PINCTRL_PIN(193, "vddr"), /* N7 */
587
+
PINCTRL_PIN(194, "vddr"), /* N8 */
588
+
PINCTRL_PIN(195, "vddr"), /* N9 */
589
+
PINCTRL_PIN(196, "vddr"), /* N10 */
590
+
PINCTRL_PIN(197, "EECLK"), /* N11 */
591
+
PINCTRL_PIN(198, "ASDO"), /* N12 */
592
+
PINCTRL_PIN(199, "CTSn"), /* N13 */
593
+
PINCTRL_PIN(200, "RXD[0]"), /* N14 */
594
+
PINCTRL_PIN(201, "TXD[0]"), /* N15 */
595
+
PINCTRL_PIN(202, "TXD[1]"), /* N16 */
596
+
PINCTRL_PIN(203, "TXD[2]"), /* N17 */
597
+
/* Row P */
598
+
PINCTRL_PIN(204, "SPCLK"), /* P1 */
599
+
PINCTRL_PIN(205, "P[10]"), /* P2 */
600
+
PINCTRL_PIN(206, "P[11]"), /* P3 */
601
+
PINCTRL_PIN(207, "P[3]"), /* P4 */
602
+
PINCTRL_PIN(208, "AD[15]"), /* P5 */
603
+
PINCTRL_PIN(209, "AD[13]"), /* P6 */
604
+
PINCTRL_PIN(210, "AD[12]"), /* P7 */
605
+
PINCTRL_PIN(211, "DA[2]"), /* P8 */
606
+
PINCTRL_PIN(212, "AD[8]"), /* P9 */
607
+
PINCTRL_PIN(213, "TCK"), /* P10 */
608
+
PINCTRL_PIN(214, "BOOT[1]"), /* P11 */
609
+
PINCTRL_PIN(215, "EEDAT"), /* P12 */
610
+
PINCTRL_PIN(216, "GRLED"), /* P13 */
611
+
PINCTRL_PIN(217, "RDLED"), /* P14 */
612
+
PINCTRL_PIN(218, "GGPIO[2]"), /* P15 */
613
+
PINCTRL_PIN(219, "RXD[1]"), /* P16 */
614
+
PINCTRL_PIN(220, "RXD[2]"), /* P17 */
615
+
/* Row R */
616
+
PINCTRL_PIN(221, "P[9]"), /* R1 */
617
+
PINCTRL_PIN(222, "HSYNC"), /* R2 */
618
+
PINCTRL_PIN(223, "P[6]"), /* R3 */
619
+
PINCTRL_PIN(224, "P[5]"), /* R4 */
620
+
PINCTRL_PIN(225, "P[0]"), /* R5 */
621
+
PINCTRL_PIN(226, "AD[14]"), /* R6 */
622
+
PINCTRL_PIN(227, "DA[4]"), /* R7 */
623
+
PINCTRL_PIN(228, "DA[1]"), /* R8 */
624
+
PINCTRL_PIN(229, "DTRn"), /* R9 */
625
+
PINCTRL_PIN(230, "TDI"), /* R10 */
626
+
PINCTRL_PIN(231, "BOOT[0]"), /* R11 */
627
+
PINCTRL_PIN(232, "ASYNC"), /* R12 */
628
+
PINCTRL_PIN(233, "SSPTX[1]"), /* R13 */
629
+
PINCTRL_PIN(234, "PWMOUT"), /* R14 */
630
+
PINCTRL_PIN(235, "USBm[0]"), /* R15 */
631
+
PINCTRL_PIN(236, "ABITCLK"), /* R16 */
632
+
PINCTRL_PIN(237, "USBp[0]"), /* R17 */
633
+
/* Row T */
634
+
PINCTRL_PIN(238, "NC"), /* T1 */
635
+
PINCTRL_PIN(239, "NC"), /* T2 */
636
+
PINCTRL_PIN(240, "V_CSYNC"), /* T3 */
637
+
PINCTRL_PIN(241, "P[7]"), /* T4 */
638
+
PINCTRL_PIN(242, "P[2]"), /* T5 */
639
+
PINCTRL_PIN(243, "DA[7]"), /* T6 */
640
+
PINCTRL_PIN(244, "AD[11]"), /* T7 */
641
+
PINCTRL_PIN(245, "AD[9]"), /* T8 */
642
+
PINCTRL_PIN(246, "DSRn"), /* T9 */
643
+
PINCTRL_PIN(247, "TMS"), /* T10 */
644
+
PINCTRL_PIN(248, "gndr"), /* T11 */
645
+
PINCTRL_PIN(249, "SFRM[1]"), /* T12 */
646
+
PINCTRL_PIN(250, "INT[2]"), /* T13 */
647
+
PINCTRL_PIN(251, "INT[0]"), /* T14 */
648
+
PINCTRL_PIN(252, "USBp[1]"), /* T15 */
649
+
PINCTRL_PIN(253, "NC"), /* T16 */
650
+
PINCTRL_PIN(254, "NC"), /* T17 */
651
+
/* Row U */
652
+
PINCTRL_PIN(255, "NC"), /* U1 */
653
+
PINCTRL_PIN(256, "NC"), /* U2 */
654
+
PINCTRL_PIN(257, "P[8]"), /* U3 */
655
+
PINCTRL_PIN(258, "P[4]"), /* U4 */
656
+
PINCTRL_PIN(259, "P[1]"), /* U5 */
657
+
PINCTRL_PIN(260, "DA[6]"), /* U6 */
658
+
PINCTRL_PIN(261, "DA[3]"), /* U7 */
659
+
PINCTRL_PIN(262, "AD[10]"), /* U8 */
660
+
PINCTRL_PIN(263, "DA[0]"), /* U9 */
661
+
PINCTRL_PIN(264, "TDO"), /* U10 */
662
+
PINCTRL_PIN(265, "NC"), /* U11 */
663
+
PINCTRL_PIN(266, "SCLK[1]"), /* U12 */
664
+
PINCTRL_PIN(267, "SSPRX[1]"), /* U13 */
665
+
PINCTRL_PIN(268, "INT[1]"), /* U14 */
666
+
PINCTRL_PIN(269, "RTSn"), /* U15 */
667
+
PINCTRL_PIN(270, "USBm[1]"), /* U16 */
668
+
PINCTRL_PIN(271, "NC"), /* U17 */
669
+
};
670
+
671
+
static const unsigned int ssp_ep9307_pins[] = {
672
+
233, 249, 266, 267,
673
+
};
674
+
675
+
static const unsigned int ac97_ep9307_pins[] = {
676
+
16, 32, 198, 232, 236,
677
+
};
678
+
679
+
/* I can't find info on those - it's some internal state */
680
+
static const unsigned int raster_on_sdram0_pins[] = {
681
+
};
682
+
683
+
static const unsigned int raster_on_sdram3_pins[] = {
684
+
};
685
+
686
+
/* ROW[N] */
687
+
static const unsigned int gpio2a_9307_pins[] = {
688
+
165, 166, 181, 182, 183, 184, 185, 186,
689
+
};
690
+
691
+
/* COL[N] */
692
+
static const unsigned int gpio3a_9307_pins[] = {
693
+
127, 139, 140, 142, 153, 155, 156, 157,
694
+
};
695
+
696
+
static const unsigned int keypad_9307_pins[] = {
697
+
127, 139, 140, 142, 153, 155, 156, 157,
698
+
165, 166, 181, 182, 183, 184, 185, 186,
699
+
};
700
+
701
+
/* ep9307 have only 4,5 pin of GPIO E Port exposed */
702
+
static const unsigned int gpio4a_9307_pins[] = { 216, 217 };
703
+
704
+
/* ep9307 have only 2 pin of GPIO G Port exposed */
705
+
static const unsigned int gpio6a_9307_pins[] = { 219 };
706
+
707
+
static const unsigned int gpio7a_9307_pins[] = { 7, 24, 41, 56, 57, 59 };
708
+
709
+
static const struct ep93xx_pin_group ep9307_pin_groups[] = {
710
+
PMX_GROUP("ssp", ssp_ep9307_pins, EP93XX_SYSCON_DEVCFG_I2SONSSP, 0),
711
+
PMX_GROUP("i2s_on_ssp", ssp_ep9307_pins, EP93XX_SYSCON_DEVCFG_I2SONSSP,
712
+
EP93XX_SYSCON_DEVCFG_I2SONSSP),
713
+
PMX_GROUP("ac97", ac97_ep9307_pins, EP93XX_SYSCON_DEVCFG_I2SONAC97, 0),
714
+
PMX_GROUP("i2s_on_ac97", ac97_ep9301_pins, EP93XX_SYSCON_DEVCFG_I2SONAC97,
715
+
EP93XX_SYSCON_DEVCFG_I2SONAC97),
716
+
PMX_GROUP("rasteronsdram0grp", raster_on_sdram0_pins, EP93XX_SYSCON_DEVCFG_RASONP3, 0),
717
+
PMX_GROUP("rasteronsdram3grp", raster_on_sdram3_pins, EP93XX_SYSCON_DEVCFG_RASONP3,
718
+
EP93XX_SYSCON_DEVCFG_RASONP3),
719
+
PMX_GROUP("gpio2agrp", gpio2a_9307_pins, EP93XX_SYSCON_DEVCFG_GONK,
720
+
EP93XX_SYSCON_DEVCFG_GONK),
721
+
PMX_GROUP("gpio3agrp", gpio3a_9307_pins, EP93XX_SYSCON_DEVCFG_GONK,
722
+
EP93XX_SYSCON_DEVCFG_GONK),
723
+
PMX_GROUP("keypadgrp", keypad_9307_pins, EP93XX_SYSCON_DEVCFG_GONK, 0),
724
+
PMX_GROUP("gpio4agrp", gpio4a_9307_pins, EP93XX_SYSCON_DEVCFG_EONIDE,
725
+
EP93XX_SYSCON_DEVCFG_EONIDE),
726
+
PMX_GROUP("gpio6agrp", gpio6a_9307_pins, EP93XX_SYSCON_DEVCFG_GONIDE,
727
+
EP93XX_SYSCON_DEVCFG_GONIDE),
728
+
PMX_GROUP("gpio7agrp", gpio7a_9307_pins, EP93XX_SYSCON_DEVCFG_HONIDE,
729
+
EP93XX_SYSCON_DEVCFG_HONIDE),
730
+
};
731
+
732
+
/* ep9312, ep9315 */
733
+
static const struct pinctrl_pin_desc ep9312_pins[] = {
734
+
/* Row A */
735
+
PINCTRL_PIN(0, "CSN[7]"), /* A1 */
736
+
PINCTRL_PIN(1, "DA[28]"), /* A2 */
737
+
PINCTRL_PIN(2, "AD[18]"), /* A3 */
738
+
PINCTRL_PIN(3, "DD[8]"), /* A4 */
739
+
PINCTRL_PIN(4, "DD[4]"), /* A5 */
740
+
PINCTRL_PIN(5, "AD[17]"), /* A6 */
741
+
PINCTRL_PIN(6, "RDN"), /* A7 */
742
+
PINCTRL_PIN(7, "RXCLK"), /* A8 */
743
+
PINCTRL_PIN(8, "MIIRXD[0]"), /* A9 */
744
+
PINCTRL_PIN(9, "RXDVAL"), /* A10 */
745
+
PINCTRL_PIN(10, "MIITXD[2]"), /* A11 */
746
+
PINCTRL_PIN(11, "TXERR"), /* A12 */
747
+
PINCTRL_PIN(12, "CLD"), /* A13 */
748
+
PINCTRL_PIN(13, "NC"), /* A14 */
749
+
PINCTRL_PIN(14, "NC"), /* A15 */
750
+
PINCTRL_PIN(15, "NC"), /* A16 */
751
+
PINCTRL_PIN(16, "EGPIO[12]"), /* A17 */
752
+
PINCTRL_PIN(17, "EGPIO[15]"), /* A18 */
753
+
PINCTRL_PIN(18, "NC"), /* A19 */
754
+
PINCTRL_PIN(19, "NC"), /* A20 */
755
+
/* Row B */
756
+
PINCTRL_PIN(20, "CSN[2]"), /* B1 */
757
+
PINCTRL_PIN(21, "DA[31]"), /* B2 */
758
+
PINCTRL_PIN(22, "DA[30]"), /* B3 */
759
+
PINCTRL_PIN(23, "DA[27]"), /* B4 */
760
+
PINCTRL_PIN(24, "DD[7]"), /* B5 */
761
+
PINCTRL_PIN(25, "DD[3]"), /* B6 */
762
+
PINCTRL_PIN(26, "WRN"), /* B7 */
763
+
PINCTRL_PIN(27, "MDIO"), /* B8 */
764
+
PINCTRL_PIN(28, "MIIRXD[1]"), /* B9 */
765
+
PINCTRL_PIN(29, "RXERR"), /* B10 */
766
+
PINCTRL_PIN(30, "MIITXD[1]"), /* B11 */
767
+
PINCTRL_PIN(31, "CRS"), /* B12 */
768
+
PINCTRL_PIN(32, "NC"), /* B13 */
769
+
PINCTRL_PIN(33, "NC"), /* B14 */
770
+
PINCTRL_PIN(34, "NC"), /* B15 */
771
+
PINCTRL_PIN(35, "NC"), /* B16 */
772
+
PINCTRL_PIN(36, "EGPIO[13]"), /* B17 */
773
+
PINCTRL_PIN(37, "NC"), /* B18 */
774
+
PINCTRL_PIN(38, "WAITN"), /* B19 */
775
+
PINCTRL_PIN(39, "TRSTN"), /* B20 */
776
+
/* Row C */
777
+
PINCTRL_PIN(40, "CSN[1]"), /* C1 */
778
+
PINCTRL_PIN(41, "CSN[3]"), /* C2 */
779
+
PINCTRL_PIN(42, "AD[20]"), /* C3 */
780
+
PINCTRL_PIN(43, "DA[29]"), /* C4 */
781
+
PINCTRL_PIN(44, "DD[10]"), /* C5 */
782
+
PINCTRL_PIN(45, "DD[6]"), /* C6 */
783
+
PINCTRL_PIN(46, "DD[2]"), /* C7 */
784
+
PINCTRL_PIN(47, "MDC"), /* C8 */
785
+
PINCTRL_PIN(48, "MIIRXD[3]"), /* C9 */
786
+
PINCTRL_PIN(49, "TXCLK"), /* C10 */
787
+
PINCTRL_PIN(50, "MIITXD[0]"), /* C11 */
788
+
PINCTRL_PIN(51, "NC"), /* C12 */
789
+
PINCTRL_PIN(52, "NC"), /* C13 */
790
+
PINCTRL_PIN(53, "NC"), /* C14 */
791
+
PINCTRL_PIN(54, "NC"), /* C15 */
792
+
PINCTRL_PIN(55, "NC"), /* C16 */
793
+
PINCTRL_PIN(56, "NC"), /* C17 */
794
+
PINCTRL_PIN(57, "USBP[2]"), /* C18 */
795
+
PINCTRL_PIN(58, "IORDY"), /* C19 */
796
+
PINCTRL_PIN(59, "DMACKN"), /* C20 */
797
+
/* Row D */
798
+
PINCTRL_PIN(60, "AD[24]"), /* D1 */
799
+
PINCTRL_PIN(61, "DA[25]"), /* D2 */
800
+
PINCTRL_PIN(62, "DD[11]"), /* D3 */
801
+
PINCTRL_PIN(63, "SDCLKEN"), /* D4 */
802
+
PINCTRL_PIN(64, "AD[19]"), /* D5 */
803
+
PINCTRL_PIN(65, "DD[9]"), /* D6 */
804
+
PINCTRL_PIN(66, "DD[5]"), /* D7 */
805
+
PINCTRL_PIN(67, "AD[16]"), /* D8 */
806
+
PINCTRL_PIN(68, "MIIRXD[2]"), /* D9 */
807
+
PINCTRL_PIN(69, "MIITXD[3]"), /* D10 */
808
+
PINCTRL_PIN(70, "TXEN"), /* D11 */
809
+
PINCTRL_PIN(71, "NC"), /* D12 */
810
+
PINCTRL_PIN(72, "NC"), /* D13 */
811
+
PINCTRL_PIN(73, "NC"), /* D14 */
812
+
PINCTRL_PIN(74, "EGPIO[14]"), /* D15 */
813
+
PINCTRL_PIN(75, "NC"), /* D16 */
814
+
PINCTRL_PIN(76, "USBM[2]"), /* D17 */
815
+
PINCTRL_PIN(77, "ARSTN"), /* D18 */
816
+
PINCTRL_PIN(78, "DIORN"), /* D19 */
817
+
PINCTRL_PIN(79, "EGPIO[1]"), /* D20 */
818
+
/* Row E */
819
+
PINCTRL_PIN(80, "AD[23]"), /* E1 */
820
+
PINCTRL_PIN(81, "DA[23]"), /* E2 */
821
+
PINCTRL_PIN(82, "DA[26]"), /* E3 */
822
+
PINCTRL_PIN(83, "CSN[6]"), /* E4 */
823
+
PINCTRL_PIN(84, "GND"), /* E5 */
824
+
PINCTRL_PIN(85, "GND"), /* E6 */
825
+
PINCTRL_PIN(86, "CVDD"), /* E7 */
826
+
PINCTRL_PIN(87, "CVDD"), /* E8 */
827
+
PINCTRL_PIN(88, "RVDD"), /* E9 */
828
+
PINCTRL_PIN(89, "GND"), /* E10 */
829
+
PINCTRL_PIN(90, "GND"), /* E11 */
830
+
PINCTRL_PIN(91, "RVDD"), /* E12 */
831
+
PINCTRL_PIN(92, "CVDD"), /* E13 */
832
+
PINCTRL_PIN(93, "CVDD"), /* E14 */
833
+
PINCTRL_PIN(94, "GND"), /* E15 */
834
+
PINCTRL_PIN(95, "ASDI"), /* E16 */
835
+
PINCTRL_PIN(96, "DIOWN"), /* E17 */
836
+
PINCTRL_PIN(97, "EGPIO[0]"), /* E18 */
837
+
PINCTRL_PIN(98, "EGPIO[3]"), /* E19 */
838
+
PINCTRL_PIN(99, "EGPIO[5]"), /* E20 */
839
+
/* Row F */
840
+
PINCTRL_PIN(100, "SDCSN[3]"), /* F1 */
841
+
PINCTRL_PIN(101, "DA[22]"), /* F2 */
842
+
PINCTRL_PIN(102, "DA[24]"), /* F3 */
843
+
PINCTRL_PIN(103, "AD[25]"), /* F4 */
844
+
PINCTRL_PIN(104, "RVDD"), /* F5 */
845
+
PINCTRL_PIN(105, "GND"), /* F6 */
846
+
PINCTRL_PIN(106, "CVDD"), /* F7 */
847
+
PINCTRL_PIN(107, "CVDD"), /* F14 */
848
+
PINCTRL_PIN(108, "GND"), /* F15 */
849
+
PINCTRL_PIN(109, "GND"), /* F16 */
850
+
PINCTRL_PIN(110, "EGPIO[2]"), /* F17 */
851
+
PINCTRL_PIN(111, "EGPIO[4]"), /* F18 */
852
+
PINCTRL_PIN(112, "EGPIO[6]"), /* F19 */
853
+
PINCTRL_PIN(113, "EGPIO[8]"), /* F20 */
854
+
/* Row G */
855
+
PINCTRL_PIN(114, "SDCSN[0]"), /* G1 */
856
+
PINCTRL_PIN(115, "SDCSN[1]"), /* G2 */
857
+
PINCTRL_PIN(116, "SDWEN"), /* G3 */
858
+
PINCTRL_PIN(117, "SDCLK"), /* G4 */
859
+
PINCTRL_PIN(118, "RVDD"), /* G5 */
860
+
PINCTRL_PIN(119, "RVDD"), /* G6 */
861
+
PINCTRL_PIN(120, "RVDD"), /* G15 */
862
+
PINCTRL_PIN(121, "RVDD"), /* G16 */
863
+
PINCTRL_PIN(122, "EGPIO[7]"), /* G17 */
864
+
PINCTRL_PIN(123, "EGPIO[9]"), /* G18 */
865
+
PINCTRL_PIN(124, "EGPIO[10]"), /* G19 */
866
+
PINCTRL_PIN(125, "EGPIO[11]"), /* G20 */
867
+
/* Row H */
868
+
PINCTRL_PIN(126, "DQMN[3]"), /* H1 */
869
+
PINCTRL_PIN(127, "CASN"), /* H2 */
870
+
PINCTRL_PIN(128, "RASN"), /* H3 */
871
+
PINCTRL_PIN(129, "SDCSN[2]"), /* H4 */
872
+
PINCTRL_PIN(130, "CVDD"), /* H5 */
873
+
PINCTRL_PIN(131, "GND"), /* H8 */
874
+
PINCTRL_PIN(132, "GND"), /* H9 */
875
+
PINCTRL_PIN(133, "GND"), /* H10 */
876
+
PINCTRL_PIN(134, "GND"), /* H11 */
877
+
PINCTRL_PIN(135, "GND"), /* H12 */
878
+
PINCTRL_PIN(136, "GND"), /* H13 */
879
+
PINCTRL_PIN(137, "RVDD"), /* H16 */
880
+
PINCTRL_PIN(138, "RTCXTALO"), /* H17 */
881
+
PINCTRL_PIN(139, "ADC_VDD"), /* H18 */
882
+
PINCTRL_PIN(140, "ADC_GND"), /* H19 */
883
+
PINCTRL_PIN(141, "XP"), /* H20 */
884
+
/* Row J */
885
+
PINCTRL_PIN(142, "DA[21]"), /* J1 */
886
+
PINCTRL_PIN(143, "DQMN[0]"), /* J2 */
887
+
PINCTRL_PIN(144, "DQMN[1]"), /* J3 */
888
+
PINCTRL_PIN(145, "DQMN[2]"), /* J4 */
889
+
PINCTRL_PIN(146, "GND"), /* J5 */
890
+
PINCTRL_PIN(147, "GND"), /* J8 */
891
+
PINCTRL_PIN(148, "GND"), /* J9 */
892
+
PINCTRL_PIN(149, "GND"), /* J10 */
893
+
PINCTRL_PIN(150, "GND"), /* J11 */
894
+
PINCTRL_PIN(151, "GND"), /* J12 */
895
+
PINCTRL_PIN(152, "GND"), /* J13 */
896
+
PINCTRL_PIN(153, "CVDD"), /* J16 */
897
+
PINCTRL_PIN(154, "RTCXTALI"), /* J17 */
898
+
PINCTRL_PIN(155, "XM"), /* J18 */
899
+
PINCTRL_PIN(156, "YP"), /* J19 */
900
+
PINCTRL_PIN(157, "YM"), /* J20 */
901
+
/* Row K */
902
+
PINCTRL_PIN(158, "AD[22]"), /* K1 */
903
+
PINCTRL_PIN(159, "DA[20]"), /* K2 */
904
+
PINCTRL_PIN(160, "AD[21]"), /* K3 */
905
+
PINCTRL_PIN(161, "DA[19]"), /* K4 */
906
+
PINCTRL_PIN(162, "RVDD"), /* K5 */
907
+
PINCTRL_PIN(163, "GND"), /* K8 */
908
+
PINCTRL_PIN(164, "GND"), /* K9 */
909
+
PINCTRL_PIN(165, "GND"), /* K10 */
910
+
PINCTRL_PIN(166, "GND"), /* K11 */
911
+
PINCTRL_PIN(167, "GND"), /* K12 */
912
+
PINCTRL_PIN(168, "GND"), /* K13 */
913
+
PINCTRL_PIN(169, "CVDD"), /* K16 */
914
+
PINCTRL_PIN(170, "SYM"), /* K17 */
915
+
PINCTRL_PIN(171, "SYP"), /* K18 */
916
+
PINCTRL_PIN(172, "SXM"), /* K19 */
917
+
PINCTRL_PIN(173, "SXP"), /* K20 */
918
+
/* Row L */
919
+
PINCTRL_PIN(174, "DA[18]"), /* L1 */
920
+
PINCTRL_PIN(175, "DA[17]"), /* L2 */
921
+
PINCTRL_PIN(176, "DA[16]"), /* L3 */
922
+
PINCTRL_PIN(177, "DA[15]"), /* L4 */
923
+
PINCTRL_PIN(178, "GND"), /* L5 */
924
+
PINCTRL_PIN(179, "GND"), /* L8 */
925
+
PINCTRL_PIN(180, "GND"), /* L9 */
926
+
PINCTRL_PIN(181, "GND"), /* L10 */
927
+
PINCTRL_PIN(182, "GND"), /* L11 */
928
+
PINCTRL_PIN(183, "GND"), /* L12 */
929
+
PINCTRL_PIN(184, "GND"), /* L13 */
930
+
PINCTRL_PIN(185, "CVDD"), /* L16 */
931
+
PINCTRL_PIN(186, "COL[5]"), /* L17 */
932
+
PINCTRL_PIN(187, "COL[7]"), /* L18 */
933
+
PINCTRL_PIN(188, "RSTON"), /* L19 */
934
+
PINCTRL_PIN(189, "PRSTN"), /* L20 */
935
+
/* Row M */
936
+
PINCTRL_PIN(190, "AD[7]"), /* M1 */
937
+
PINCTRL_PIN(191, "DA[14]"), /* M2 */
938
+
PINCTRL_PIN(192, "AD[6]"), /* M3 */
939
+
PINCTRL_PIN(193, "AD[5]"), /* M4 */
940
+
PINCTRL_PIN(194, "CVDD"), /* M5 */
941
+
PINCTRL_PIN(195, "GND"), /* M8 */
942
+
PINCTRL_PIN(196, "GND"), /* M9 */
943
+
PINCTRL_PIN(197, "GND"), /* M10 */
944
+
PINCTRL_PIN(198, "GND"), /* M11 */
945
+
PINCTRL_PIN(199, "GND"), /* M12 */
946
+
PINCTRL_PIN(200, "GND"), /* M13 */
947
+
PINCTRL_PIN(201, "GND"), /* M16 */
948
+
PINCTRL_PIN(202, "COL[4]"), /* M17 */
949
+
PINCTRL_PIN(203, "COL[3]"), /* M18 */
950
+
PINCTRL_PIN(204, "COL[6]"), /* M19 */
951
+
PINCTRL_PIN(205, "CSN[0]"), /* M20 */
952
+
/* Row N */
953
+
PINCTRL_PIN(206, "DA[13]"), /* N1 */
954
+
PINCTRL_PIN(207, "DA[12]"), /* N2 */
955
+
PINCTRL_PIN(208, "DA[11]"), /* N3 */
956
+
PINCTRL_PIN(209, "AD[3]"), /* N4 */
957
+
PINCTRL_PIN(210, "CVDD"), /* N5 */
958
+
PINCTRL_PIN(211, "CVDD"), /* N6 */
959
+
PINCTRL_PIN(212, "GND"), /* N8 */
960
+
PINCTRL_PIN(213, "GND"), /* N9 */
961
+
PINCTRL_PIN(214, "GND"), /* N10 */
962
+
PINCTRL_PIN(215, "GND"), /* N11 */
963
+
PINCTRL_PIN(216, "GND"), /* N12 */
964
+
PINCTRL_PIN(217, "GND"), /* N13 */
965
+
PINCTRL_PIN(218, "GND"), /* N15 */
966
+
PINCTRL_PIN(219, "GND"), /* N16 */
967
+
PINCTRL_PIN(220, "XTALO"), /* N17 */
968
+
PINCTRL_PIN(221, "COL[0]"), /* N18 */
969
+
PINCTRL_PIN(222, "COL[1]"), /* N19 */
970
+
PINCTRL_PIN(223, "COL[2]"), /* N20 */
971
+
/* Row P */
972
+
PINCTRL_PIN(224, "AD[4]"), /* P1 */
973
+
PINCTRL_PIN(225, "DA[10]"), /* P2 */
974
+
PINCTRL_PIN(226, "DA[9]"), /* P3 */
975
+
PINCTRL_PIN(227, "BRIGHT"), /* P4 */
976
+
PINCTRL_PIN(228, "RVDD"), /* P5 */
977
+
PINCTRL_PIN(229, "RVDD"), /* P6 */
978
+
PINCTRL_PIN(230, "RVDD"), /* P15 */
979
+
PINCTRL_PIN(231, "RVDD"), /* P16 */
980
+
PINCTRL_PIN(232, "XTALI"), /* P17 */
981
+
PINCTRL_PIN(233, "PLL_VDD"), /* P18 */
982
+
PINCTRL_PIN(234, "ROW[6]"), /* P19 */
983
+
PINCTRL_PIN(235, "ROW[7]"), /* P20 */
984
+
/* Row R */
985
+
PINCTRL_PIN(236, "AD[2]"), /* R1 */
986
+
PINCTRL_PIN(237, "AD[1]"), /* R2 */
987
+
PINCTRL_PIN(238, "P[17]"), /* R3 */
988
+
PINCTRL_PIN(239, "P[14]"), /* R4 */
989
+
PINCTRL_PIN(240, "RVDD"), /* R5 */
990
+
PINCTRL_PIN(241, "RVDD"), /* R6 */
991
+
PINCTRL_PIN(242, "GND"), /* R7 */
992
+
PINCTRL_PIN(243, "CVDD"), /* R8 */
993
+
PINCTRL_PIN(244, "CVDD"), /* R13 */
994
+
PINCTRL_PIN(245, "GND"), /* R14 */
995
+
PINCTRL_PIN(246, "RVDD"), /* R15 */
996
+
PINCTRL_PIN(247, "RVDD"), /* R16 */
997
+
PINCTRL_PIN(248, "ROW[0]"), /* R17 */
998
+
PINCTRL_PIN(249, "ROW[3]"), /* R18 */
999
+
PINCTRL_PIN(250, "PLL_GND"), /* R19 */
1000
+
PINCTRL_PIN(251, "ROW[5]"), /* R20 */
1001
+
/* Row T */
1002
+
PINCTRL_PIN(252, "DA[8]"), /* T1 */
1003
+
PINCTRL_PIN(253, "BLANK"), /* T2 */
1004
+
PINCTRL_PIN(254, "P[13]"), /* T3 */
1005
+
PINCTRL_PIN(255, "SPCLK"), /* T4 */
1006
+
PINCTRL_PIN(256, "V_CSYNC"), /* T5 */
1007
+
PINCTRL_PIN(257, "DD[14]"), /* T6 */
1008
+
PINCTRL_PIN(258, "GND"), /* T7 */
1009
+
PINCTRL_PIN(259, "CVDD"), /* T8 */
1010
+
PINCTRL_PIN(260, "RVDD"), /* T9 */
1011
+
PINCTRL_PIN(261, "GND"), /* T10 */
1012
+
PINCTRL_PIN(262, "GND"), /* T11 */
1013
+
PINCTRL_PIN(263, "RVDD"), /* T12 */
1014
+
PINCTRL_PIN(264, "CVDD"), /* T13 */
1015
+
PINCTRL_PIN(265, "GND"), /* T14 */
1016
+
PINCTRL_PIN(266, "INT[0]"), /* T15 */
1017
+
PINCTRL_PIN(267, "USBM[1]"), /* T16 */
1018
+
PINCTRL_PIN(268, "RXD[0]"), /* T17 */
1019
+
PINCTRL_PIN(269, "TXD[2]"), /* T18 */
1020
+
PINCTRL_PIN(270, "ROW[2]"), /* T19 */
1021
+
PINCTRL_PIN(271, "ROW[4]"), /* T20 */
1022
+
/* Row U */
1023
+
PINCTRL_PIN(272, "AD[0]"), /* U1 */
1024
+
PINCTRL_PIN(273, "P[15]"), /* U2 */
1025
+
PINCTRL_PIN(274, "P[10]"), /* U3 */
1026
+
PINCTRL_PIN(275, "P[7]"), /* U4 */
1027
+
PINCTRL_PIN(276, "P[6]"), /* U5 */
1028
+
PINCTRL_PIN(277, "P[4]"), /* U6 */
1029
+
PINCTRL_PIN(278, "P[0]"), /* U7 */
1030
+
PINCTRL_PIN(279, "AD[13]"), /* U8 */
1031
+
PINCTRL_PIN(280, "DA[3]"), /* U9 */
1032
+
PINCTRL_PIN(281, "DA[0]"), /* U10 */
1033
+
PINCTRL_PIN(282, "DSRN"), /* U11 */
1034
+
PINCTRL_PIN(283, "BOOT[1]"), /* U12 */
1035
+
PINCTRL_PIN(284, "NC"), /* U13 */
1036
+
PINCTRL_PIN(285, "SSPRX1"), /* U14 */
1037
+
PINCTRL_PIN(286, "INT[1]"), /* U15 */
1038
+
PINCTRL_PIN(287, "PWMOUT"), /* U16 */
1039
+
PINCTRL_PIN(288, "USBM[0]"), /* U17 */
1040
+
PINCTRL_PIN(289, "RXD[1]"), /* U18 */
1041
+
PINCTRL_PIN(290, "TXD[1]"), /* U19 */
1042
+
PINCTRL_PIN(291, "ROW[1]"), /* U20 */
1043
+
/* Row V */
1044
+
PINCTRL_PIN(292, "P[16]"), /* V1 */
1045
+
PINCTRL_PIN(293, "P[11]"), /* V2 */
1046
+
PINCTRL_PIN(294, "P[8]"), /* V3 */
1047
+
PINCTRL_PIN(295, "DD[15]"), /* V4 */
1048
+
PINCTRL_PIN(296, "DD[13]"), /* V5 */
1049
+
PINCTRL_PIN(297, "P[1]"), /* V6 */
1050
+
PINCTRL_PIN(298, "AD[14]"), /* V7 */
1051
+
PINCTRL_PIN(299, "AD[12]"), /* V8 */
1052
+
PINCTRL_PIN(300, "DA[2]"), /* V9 */
1053
+
PINCTRL_PIN(301, "IDECS0N"), /* V10 */
1054
+
PINCTRL_PIN(302, "IDEDA[2]"), /* V11 */
1055
+
PINCTRL_PIN(303, "TDI"), /* V12 */
1056
+
PINCTRL_PIN(304, "GND"), /* V13 */
1057
+
PINCTRL_PIN(305, "ASYNC"), /* V14 */
1058
+
PINCTRL_PIN(306, "SSPTX1"), /* V15 */
1059
+
PINCTRL_PIN(307, "INT[2]"), /* V16 */
1060
+
PINCTRL_PIN(308, "RTSN"), /* V17 */
1061
+
PINCTRL_PIN(309, "USBP[0]"), /* V18 */
1062
+
PINCTRL_PIN(310, "CTSN"), /* V19 */
1063
+
PINCTRL_PIN(311, "TXD[0]"), /* V20 */
1064
+
/* Row W */
1065
+
PINCTRL_PIN(312, "P[12]"), /* W1 */
1066
+
PINCTRL_PIN(313, "P[9]"), /* W2 */
1067
+
PINCTRL_PIN(314, "DD[0]"), /* W3 */
1068
+
PINCTRL_PIN(315, "P[5]"), /* W4 */
1069
+
PINCTRL_PIN(316, "P[3]"), /* W5 */
1070
+
PINCTRL_PIN(317, "DA[7]"), /* W6 */
1071
+
PINCTRL_PIN(318, "DA[5]"), /* W7 */
1072
+
PINCTRL_PIN(319, "AD[11]"), /* W8 */
1073
+
PINCTRL_PIN(320, "AD[9]"), /* W9 */
1074
+
PINCTRL_PIN(321, "IDECS1N"), /* W10 */
1075
+
PINCTRL_PIN(322, "IDEDA[1]"), /* W11 */
1076
+
PINCTRL_PIN(323, "TCK"), /* W12 */
1077
+
PINCTRL_PIN(324, "TMS"), /* W13 */
1078
+
PINCTRL_PIN(325, "EECLK"), /* W14 */
1079
+
PINCTRL_PIN(326, "SCLK1"), /* W15 */
1080
+
PINCTRL_PIN(327, "GRLED"), /* W16 */
1081
+
PINCTRL_PIN(328, "INT[3]"), /* W17 */
1082
+
PINCTRL_PIN(329, "SLA[1]"), /* W18 */
1083
+
PINCTRL_PIN(330, "SLA[0]"), /* W19 */
1084
+
PINCTRL_PIN(331, "RXD[2]"), /* W20 */
1085
+
/* Row Y */
1086
+
PINCTRL_PIN(332, "HSYNC"), /* Y1 */
1087
+
PINCTRL_PIN(333, "DD[1]"), /* Y2 */
1088
+
PINCTRL_PIN(334, "DD[12]"), /* Y3 */
1089
+
PINCTRL_PIN(335, "P[2]"), /* Y4 */
1090
+
PINCTRL_PIN(336, "AD[15]"), /* Y5 */
1091
+
PINCTRL_PIN(337, "DA[6]"), /* Y6 */
1092
+
PINCTRL_PIN(338, "DA[4]"), /* Y7 */
1093
+
PINCTRL_PIN(339, "AD[10]"), /* Y8 */
1094
+
PINCTRL_PIN(340, "DA[1]"), /* Y9 */
1095
+
PINCTRL_PIN(341, "AD[8]"), /* Y10 */
1096
+
PINCTRL_PIN(342, "IDEDA[0]"), /* Y11 */
1097
+
PINCTRL_PIN(343, "DTRN"), /* Y12 */
1098
+
PINCTRL_PIN(344, "TDO"), /* Y13 */
1099
+
PINCTRL_PIN(345, "BOOT[0]"), /* Y14 */
1100
+
PINCTRL_PIN(346, "EEDAT"), /* Y15 */
1101
+
PINCTRL_PIN(347, "ASDO"), /* Y16 */
1102
+
PINCTRL_PIN(348, "SFRM1"), /* Y17 */
1103
+
PINCTRL_PIN(349, "RDLED"), /* Y18 */
1104
+
PINCTRL_PIN(350, "USBP[1]"), /* Y19 */
1105
+
PINCTRL_PIN(351, "ABITCLK"), /* Y20 */
1106
+
};
1107
+
1108
+
static const unsigned int ssp_ep9312_pins[] = {
1109
+
285, 306, 326, 348,
1110
+
};
1111
+
1112
+
static const unsigned int ac97_ep9312_pins[] = {
1113
+
77, 95, 305, 347, 351,
1114
+
};
1115
+
1116
+
static const unsigned int pwm_ep9312_pins[] = { 74 };
1117
+
1118
+
static const unsigned int gpio1a_ep9312_pins[] = { 74 };
1119
+
1120
+
static const unsigned int gpio2a_9312_pins[] = {
1121
+
234, 235, 248, 249, 251, 270, 271, 291,
1122
+
};
1123
+
1124
+
static const unsigned int gpio3a_9312_pins[] = {
1125
+
186, 187, 202, 203, 204, 221, 222, 223,
1126
+
};
1127
+
1128
+
static const unsigned int keypad_9312_pins[] = {
1129
+
186, 187, 202, 203, 204, 221, 222, 223,
1130
+
234, 235, 248, 249, 251, 270, 271, 291,
1131
+
};
1132
+
1133
+
static const unsigned int gpio4a_9312_pins[] = {
1134
+
78, 301, 302, 321, 322, 342,
1135
+
};
1136
+
1137
+
static const unsigned int gpio6a_9312_pins[] = {
1138
+
257, 295, 296, 334,
1139
+
};
1140
+
1141
+
static const unsigned int gpio7a_9312_pins[] = {
1142
+
4, 24, 25, 45, 46, 66, 314, 333,
1143
+
};
1144
+
1145
+
static const unsigned int ide_9312_pins[] = {
1146
+
78, 301, 302, 321, 322, 342, 257, 295,
1147
+
296, 334, 4, 24, 25, 45, 46, 66,
1148
+
314, 333,
1149
+
};
1150
+
1151
+
static const struct ep93xx_pin_group ep9312_pin_groups[] = {
1152
+
PMX_GROUP("ssp", ssp_ep9312_pins, EP93XX_SYSCON_DEVCFG_I2SONSSP, 0),
1153
+
PMX_GROUP("i2s_on_ssp", ssp_ep9312_pins, EP93XX_SYSCON_DEVCFG_I2SONSSP,
1154
+
EP93XX_SYSCON_DEVCFG_I2SONSSP),
1155
+
PMX_GROUP("pwm1", pwm_ep9312_pins, EP93XX_SYSCON_DEVCFG_PONG,
1156
+
EP93XX_SYSCON_DEVCFG_PONG),
1157
+
PMX_GROUP("gpio1agrp", gpio1a_ep9312_pins, EP93XX_SYSCON_DEVCFG_PONG, 0),
1158
+
PMX_GROUP("ac97", ac97_ep9312_pins, EP93XX_SYSCON_DEVCFG_I2SONAC97, 0),
1159
+
PMX_GROUP("i2s_on_ac97", ac97_ep9312_pins, EP93XX_SYSCON_DEVCFG_I2SONAC97,
1160
+
EP93XX_SYSCON_DEVCFG_I2SONAC97),
1161
+
PMX_GROUP("rasteronsdram0grp", raster_on_sdram0_pins, EP93XX_SYSCON_DEVCFG_RASONP3, 0),
1162
+
PMX_GROUP("rasteronsdram3grp", raster_on_sdram3_pins, EP93XX_SYSCON_DEVCFG_RASONP3,
1163
+
EP93XX_SYSCON_DEVCFG_RASONP3),
1164
+
PMX_GROUP("gpio2agrp", gpio2a_9312_pins, EP93XX_SYSCON_DEVCFG_GONK,
1165
+
EP93XX_SYSCON_DEVCFG_GONK),
1166
+
PMX_GROUP("gpio3agrp", gpio3a_9312_pins, EP93XX_SYSCON_DEVCFG_GONK,
1167
+
EP93XX_SYSCON_DEVCFG_GONK),
1168
+
PMX_GROUP("keypadgrp", keypad_9312_pins, EP93XX_SYSCON_DEVCFG_GONK, 0),
1169
+
PMX_GROUP("gpio4agrp", gpio4a_9312_pins, EP93XX_SYSCON_DEVCFG_EONIDE,
1170
+
EP93XX_SYSCON_DEVCFG_EONIDE),
1171
+
PMX_GROUP("gpio6agrp", gpio6a_9312_pins, EP93XX_SYSCON_DEVCFG_GONIDE,
1172
+
EP93XX_SYSCON_DEVCFG_GONIDE),
1173
+
PMX_GROUP("gpio7agrp", gpio7a_9312_pins, EP93XX_SYSCON_DEVCFG_HONIDE,
1174
+
EP93XX_SYSCON_DEVCFG_HONIDE),
1175
+
PMX_GROUP("idegrp", ide_9312_pins, EP93XX_SYSCON_DEVCFG_EONIDE |
1176
+
EP93XX_SYSCON_DEVCFG_GONIDE | EP93XX_SYSCON_DEVCFG_HONIDE, 0),
1177
+
};
1178
+
1179
+
static int ep93xx_get_groups_count(struct pinctrl_dev *pctldev)
1180
+
{
1181
+
struct ep93xx_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
1182
+
1183
+
switch (pmx->model) {
1184
+
case EP93XX_9301_PINCTRL:
1185
+
return ARRAY_SIZE(ep9301_pin_groups);
1186
+
case EP93XX_9307_PINCTRL:
1187
+
return ARRAY_SIZE(ep9307_pin_groups);
1188
+
case EP93XX_9312_PINCTRL:
1189
+
return ARRAY_SIZE(ep9312_pin_groups);
1190
+
default:
1191
+
return 0;
1192
+
}
1193
+
}
1194
+
1195
+
static const char *ep93xx_get_group_name(struct pinctrl_dev *pctldev,
1196
+
unsigned int selector)
1197
+
{
1198
+
struct ep93xx_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
1199
+
1200
+
switch (pmx->model) {
1201
+
case EP93XX_9301_PINCTRL:
1202
+
return ep9301_pin_groups[selector].grp.name;
1203
+
case EP93XX_9307_PINCTRL:
1204
+
return ep9307_pin_groups[selector].grp.name;
1205
+
case EP93XX_9312_PINCTRL:
1206
+
return ep9312_pin_groups[selector].grp.name;
1207
+
default:
1208
+
return NULL;
1209
+
}
1210
+
}
1211
+
1212
+
static int ep93xx_get_group_pins(struct pinctrl_dev *pctldev,
1213
+
unsigned int selector,
1214
+
const unsigned int **pins,
1215
+
unsigned int *num_pins)
1216
+
{
1217
+
struct ep93xx_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
1218
+
1219
+
switch (pmx->model) {
1220
+
case EP93XX_9301_PINCTRL:
1221
+
*pins = ep9301_pin_groups[selector].grp.pins;
1222
+
*num_pins = ep9301_pin_groups[selector].grp.npins;
1223
+
break;
1224
+
case EP93XX_9307_PINCTRL:
1225
+
*pins = ep9307_pin_groups[selector].grp.pins;
1226
+
*num_pins = ep9307_pin_groups[selector].grp.npins;
1227
+
break;
1228
+
case EP93XX_9312_PINCTRL:
1229
+
*pins = ep9312_pin_groups[selector].grp.pins;
1230
+
*num_pins = ep9312_pin_groups[selector].grp.npins;
1231
+
break;
1232
+
default:
1233
+
return -EINVAL;
1234
+
}
1235
+
1236
+
return 0;
1237
+
}
1238
+
1239
+
static const struct pinctrl_ops ep93xx_pctrl_ops = {
1240
+
.get_groups_count = ep93xx_get_groups_count,
1241
+
.get_group_name = ep93xx_get_group_name,
1242
+
.get_group_pins = ep93xx_get_group_pins,
1243
+
.dt_node_to_map = pinconf_generic_dt_node_to_map_all,
1244
+
.dt_free_map = pinconf_generic_dt_free_map,
1245
+
};
1246
+
1247
+
static const char * const spigrps[] = { "ssp" };
1248
+
static const char * const ac97grps[] = { "ac97" };
1249
+
static const char * const i2sgrps[] = { "i2s_on_ssp", "i2s_on_ac97" };
1250
+
static const char * const pwm1grps[] = { "pwm1" };
1251
+
static const char * const gpiogrps[] = { "gpio1agrp", "gpio2agrp", "gpio3agrp",
1252
+
"gpio4agrp", "gpio6agrp", "gpio7agrp" };
1253
+
static const char * const rastergrps[] = { "rasteronsdram0grp", "rasteronsdram3grp"};
1254
+
static const char * const keypadgrps[] = { "keypadgrp"};
1255
+
static const char * const idegrps[] = { "idegrp"};
1256
+
1257
+
static const struct pinfunction ep93xx_pmx_functions[] = {
1258
+
PINCTRL_PINFUNCTION("spi", spigrps, ARRAY_SIZE(spigrps)),
1259
+
PINCTRL_PINFUNCTION("ac97", ac97grps, ARRAY_SIZE(ac97grps)),
1260
+
PINCTRL_PINFUNCTION("i2s", i2sgrps, ARRAY_SIZE(i2sgrps)),
1261
+
PINCTRL_PINFUNCTION("pwm", pwm1grps, ARRAY_SIZE(pwm1grps)),
1262
+
PINCTRL_PINFUNCTION("keypad", keypadgrps, ARRAY_SIZE(keypadgrps)),
1263
+
PINCTRL_PINFUNCTION("pata", idegrps, ARRAY_SIZE(idegrps)),
1264
+
PINCTRL_PINFUNCTION("lcd", rastergrps, ARRAY_SIZE(rastergrps)),
1265
+
PINCTRL_PINFUNCTION("gpio", gpiogrps, ARRAY_SIZE(gpiogrps)),
1266
+
};
1267
+
1268
+
static int ep93xx_pmx_set_mux(struct pinctrl_dev *pctldev,
1269
+
unsigned int selector,
1270
+
unsigned int group)
1271
+
{
1272
+
struct ep93xx_pmx *pmx;
1273
+
const struct pinfunction *func;
1274
+
const struct ep93xx_pin_group *grp;
1275
+
u32 before, after, expected;
1276
+
unsigned long tmp;
1277
+
int i;
1278
+
1279
+
pmx = pinctrl_dev_get_drvdata(pctldev);
1280
+
1281
+
switch (pmx->model) {
1282
+
case EP93XX_9301_PINCTRL:
1283
+
grp = &ep9301_pin_groups[group];
1284
+
break;
1285
+
case EP93XX_9307_PINCTRL:
1286
+
grp = &ep9307_pin_groups[group];
1287
+
break;
1288
+
case EP93XX_9312_PINCTRL:
1289
+
grp = &ep9312_pin_groups[group];
1290
+
break;
1291
+
default:
1292
+
dev_err(pmx->dev, "invalid SoC type\n");
1293
+
return -ENODEV;
1294
+
}
1295
+
1296
+
func = &ep93xx_pmx_functions[selector];
1297
+
1298
+
dev_dbg(pmx->dev,
1299
+
"ACTIVATE function \"%s\" with group \"%s\" (mask=0x%x, value=0x%x)\n",
1300
+
func->name, grp->grp.name, grp->mask, grp->value);
1301
+
1302
+
regmap_read(pmx->map, EP93XX_SYSCON_DEVCFG, &before);
1303
+
ep93xx_pinctrl_update_bits(pmx, EP93XX_SYSCON_DEVCFG,
1304
+
grp->mask, grp->value);
1305
+
regmap_read(pmx->map, EP93XX_SYSCON_DEVCFG, &after);
1306
+
1307
+
dev_dbg(pmx->dev, "before=0x%x, after=0x%x, mask=0x%lx\n",
1308
+
before, after, PADS_MASK);
1309
+
1310
+
/* Which bits changed */
1311
+
before &= PADS_MASK;
1312
+
after &= PADS_MASK;
1313
+
expected = before & ~grp->mask;
1314
+
expected |= grp->value;
1315
+
expected &= PADS_MASK;
1316
+
1317
+
/* Print changed states */
1318
+
tmp = expected ^ after;
1319
+
for_each_set_bit(i, &tmp, PADS_MAXBIT) {
1320
+
bool enabled = expected & BIT(i);
1321
+
1322
+
dev_err(pmx->dev,
1323
+
"pin group %s could not be %s: probably a hardware limitation\n",
1324
+
ep93xx_padgroups[i], str_enabled_disabled(enabled));
1325
+
dev_err(pmx->dev,
1326
+
"DeviceCfg before: %08x, after %08x, expected %08x\n",
1327
+
before, after, expected);
1328
+
}
1329
+
1330
+
return tmp ? -EINVAL : 0;
1331
+
};
1332
+
1333
+
static int ep93xx_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
1334
+
{
1335
+
return ARRAY_SIZE(ep93xx_pmx_functions);
1336
+
}
1337
+
1338
+
static const char *ep93xx_pmx_get_func_name(struct pinctrl_dev *pctldev,
1339
+
unsigned int selector)
1340
+
{
1341
+
return ep93xx_pmx_functions[selector].name;
1342
+
}
1343
+
1344
+
static int ep93xx_pmx_get_groups(struct pinctrl_dev *pctldev,
1345
+
unsigned int selector,
1346
+
const char * const **groups,
1347
+
unsigned int * const num_groups)
1348
+
{
1349
+
*groups = ep93xx_pmx_functions[selector].groups;
1350
+
*num_groups = ep93xx_pmx_functions[selector].ngroups;
1351
+
return 0;
1352
+
}
1353
+
1354
+
static const struct pinmux_ops ep93xx_pmx_ops = {
1355
+
.get_functions_count = ep93xx_pmx_get_funcs_count,
1356
+
.get_function_name = ep93xx_pmx_get_func_name,
1357
+
.get_function_groups = ep93xx_pmx_get_groups,
1358
+
.set_mux = ep93xx_pmx_set_mux,
1359
+
};
1360
+
1361
+
static struct pinctrl_desc ep93xx_pmx_desc = {
1362
+
.name = DRIVER_NAME,
1363
+
.pctlops = &ep93xx_pctrl_ops,
1364
+
.pmxops = &ep93xx_pmx_ops,
1365
+
.owner = THIS_MODULE,
1366
+
};
1367
+
1368
+
static int ep93xx_pmx_probe(struct auxiliary_device *adev,
1369
+
const struct auxiliary_device_id *id)
1370
+
{
1371
+
struct ep93xx_regmap_adev *rdev = to_ep93xx_regmap_adev(adev);
1372
+
struct device *dev = &adev->dev;
1373
+
struct ep93xx_pmx *pmx;
1374
+
1375
+
/* Create state holders etc for this driver */
1376
+
pmx = devm_kzalloc(dev, sizeof(*pmx), GFP_KERNEL);
1377
+
if (!pmx)
1378
+
return -ENOMEM;
1379
+
1380
+
pmx->dev = dev;
1381
+
pmx->map = rdev->map;
1382
+
pmx->aux_dev = rdev;
1383
+
pmx->model = (enum ep93xx_pinctrl_model)(uintptr_t)id->driver_data;
1384
+
switch (pmx->model) {
1385
+
case EP93XX_9301_PINCTRL:
1386
+
ep93xx_pmx_desc.pins = ep9301_pins;
1387
+
ep93xx_pmx_desc.npins = ARRAY_SIZE(ep9301_pins);
1388
+
dev_info(dev, "detected 9301/9302 chip variant\n");
1389
+
break;
1390
+
case EP93XX_9307_PINCTRL:
1391
+
ep93xx_pmx_desc.pins = ep9307_pins;
1392
+
ep93xx_pmx_desc.npins = ARRAY_SIZE(ep9307_pins);
1393
+
dev_info(dev, "detected 9307 chip variant\n");
1394
+
break;
1395
+
case EP93XX_9312_PINCTRL:
1396
+
ep93xx_pmx_desc.pins = ep9312_pins;
1397
+
ep93xx_pmx_desc.npins = ARRAY_SIZE(ep9312_pins);
1398
+
dev_info(dev, "detected 9312/9315 chip variant\n");
1399
+
break;
1400
+
default:
1401
+
return dev_err_probe(dev, -EINVAL, "unknown pin control model: %u\n", pmx->model);
1402
+
}
1403
+
1404
+
/* using parent of_node to match in get_pinctrl_dev_from_of_node() */
1405
+
device_set_node(dev, dev_fwnode(adev->dev.parent));
1406
+
pmx->pctl = devm_pinctrl_register(dev, &ep93xx_pmx_desc, pmx);
1407
+
if (IS_ERR(pmx->pctl))
1408
+
return dev_err_probe(dev, PTR_ERR(pmx->pctl), "could not register pinmux driver\n");
1409
+
1410
+
return 0;
1411
+
};
1412
+
1413
+
static const struct auxiliary_device_id ep93xx_pinctrl_ids[] = {
1414
+
{
1415
+
.name = "soc_ep93xx.pinctrl-ep9301",
1416
+
.driver_data = (kernel_ulong_t)EP93XX_9301_PINCTRL,
1417
+
},
1418
+
{
1419
+
.name = "soc_ep93xx.pinctrl-ep9307",
1420
+
.driver_data = (kernel_ulong_t)EP93XX_9307_PINCTRL,
1421
+
},
1422
+
{
1423
+
.name = "soc_ep93xx.pinctrl-ep9312",
1424
+
.driver_data = (kernel_ulong_t)EP93XX_9312_PINCTRL,
1425
+
},
1426
+
{ /* sentinel */ }
1427
+
};
1428
+
MODULE_DEVICE_TABLE(auxiliary, ep93xx_pinctrl_ids);
1429
+
1430
+
static struct auxiliary_driver ep93xx_pmx_driver = {
1431
+
.probe = ep93xx_pmx_probe,
1432
+
.id_table = ep93xx_pinctrl_ids,
1433
+
};
1434
+
module_auxiliary_driver(ep93xx_pmx_driver);
+10
drivers/power/reset/Kconfig
+10
drivers/power/reset/Kconfig
···
75
75
Say Y here if you have a Broadcom STB board and you wish
76
76
to have restart support.
77
77
78
+
config POWER_RESET_EP93XX
79
+
bool "Cirrus EP93XX reset driver" if COMPILE_TEST
80
+
depends on MFD_SYSCON
81
+
default ARCH_EP93XX
82
+
help
83
+
This driver provides restart support for Cirrus EP93XX SoC.
84
+
85
+
Say Y here if you have a Cirrus EP93XX SoC and you wish
86
+
to have restart support.
87
+
78
88
config POWER_RESET_GEMINI_POWEROFF
79
89
bool "Cortina Gemini power-off driver"
80
90
depends on ARCH_GEMINI || COMPILE_TEST
+1
drivers/power/reset/Makefile
+1
drivers/power/reset/Makefile
···
7
7
obj-$(CONFIG_POWER_RESET_AXXIA) += axxia-reset.o
8
8
obj-$(CONFIG_POWER_RESET_BRCMKONA) += brcm-kona-reset.o
9
9
obj-$(CONFIG_POWER_RESET_BRCMSTB) += brcmstb-reboot.o
10
+
obj-$(CONFIG_POWER_RESET_EP93XX) += ep93xx-restart.o
10
11
obj-$(CONFIG_POWER_RESET_GEMINI_POWEROFF) += gemini-poweroff.o
11
12
obj-$(CONFIG_POWER_RESET_GPIO) += gpio-poweroff.o
12
13
obj-$(CONFIG_POWER_RESET_GPIO_RESTART) += gpio-restart.o
+84
drivers/power/reset/ep93xx-restart.c
+84
drivers/power/reset/ep93xx-restart.c
···
1
+
// SPDX-License-Identifier: GPL-2.0+
2
+
/*
3
+
* Cirrus EP93xx SoC reset driver
4
+
*
5
+
* Copyright (C) 2021 Nikita Shubin <nikita.shubin@maquefel.me>
6
+
*/
7
+
8
+
#include <linux/bits.h>
9
+
#include <linux/container_of.h>
10
+
#include <linux/delay.h>
11
+
#include <linux/errno.h>
12
+
#include <linux/mfd/syscon.h>
13
+
#include <linux/module.h>
14
+
#include <linux/mod_devicetable.h>
15
+
#include <linux/notifier.h>
16
+
#include <linux/reboot.h>
17
+
#include <linux/slab.h>
18
+
19
+
#include <linux/soc/cirrus/ep93xx.h>
20
+
21
+
#define EP93XX_SYSCON_DEVCFG 0x80
22
+
#define EP93XX_SYSCON_DEVCFG_SWRST BIT(31)
23
+
24
+
struct ep93xx_restart {
25
+
struct ep93xx_regmap_adev *aux_dev;
26
+
struct notifier_block restart_handler;
27
+
};
28
+
29
+
static int ep93xx_restart_handle(struct notifier_block *this,
30
+
unsigned long mode, void *cmd)
31
+
{
32
+
struct ep93xx_restart *priv =
33
+
container_of(this, struct ep93xx_restart, restart_handler);
34
+
struct ep93xx_regmap_adev *aux = priv->aux_dev;
35
+
36
+
/* Issue the reboot */
37
+
aux->update_bits(aux->map, aux->lock, EP93XX_SYSCON_DEVCFG,
38
+
EP93XX_SYSCON_DEVCFG_SWRST, EP93XX_SYSCON_DEVCFG_SWRST);
39
+
aux->update_bits(aux->map, aux->lock, EP93XX_SYSCON_DEVCFG,
40
+
EP93XX_SYSCON_DEVCFG_SWRST, 0);
41
+
42
+
return NOTIFY_DONE;
43
+
}
44
+
45
+
static int ep93xx_reboot_probe(struct auxiliary_device *adev,
46
+
const struct auxiliary_device_id *id)
47
+
{
48
+
struct ep93xx_regmap_adev *rdev = to_ep93xx_regmap_adev(adev);
49
+
struct device *dev = &adev->dev;
50
+
struct ep93xx_restart *priv;
51
+
int err;
52
+
53
+
if (!rdev->update_bits)
54
+
return -ENODEV;
55
+
56
+
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
57
+
if (!priv)
58
+
return -ENOMEM;
59
+
60
+
priv->aux_dev = rdev;
61
+
62
+
priv->restart_handler.notifier_call = ep93xx_restart_handle;
63
+
priv->restart_handler.priority = 128;
64
+
65
+
err = register_restart_handler(&priv->restart_handler);
66
+
if (err)
67
+
return dev_err_probe(dev, err, "can't register restart notifier\n");
68
+
69
+
return 0;
70
+
}
71
+
72
+
static const struct auxiliary_device_id ep93xx_reboot_ids[] = {
73
+
{
74
+
.name = "soc_ep93xx.reset-ep93xx",
75
+
},
76
+
{ /* sentinel */ }
77
+
};
78
+
MODULE_DEVICE_TABLE(auxiliary, ep93xx_reboot_ids);
79
+
80
+
static struct auxiliary_driver ep93xx_reboot_driver = {
81
+
.probe = ep93xx_reboot_probe,
82
+
.id_table = ep93xx_reboot_ids,
83
+
};
84
+
module_auxiliary_driver(ep93xx_reboot_driver);
+8
-18
drivers/pwm/pwm-ep93xx.c
+8
-18
drivers/pwm/pwm-ep93xx.c
···
17
17
*/
18
18
19
19
#include <linux/module.h>
20
+
#include <linux/mod_devicetable.h>
20
21
#include <linux/platform_device.h>
21
22
#include <linux/slab.h>
22
23
#include <linux/clk.h>
···
26
25
#include <linux/pwm.h>
27
26
28
27
#include <asm/div64.h>
29
-
30
-
#include <linux/soc/cirrus/ep93xx.h> /* for ep93xx_pwm_{acquire,release}_gpio() */
31
28
32
29
#define EP93XX_PWMx_TERM_COUNT 0x00
33
30
#define EP93XX_PWMx_DUTY_CYCLE 0x04
···
40
41
static inline struct ep93xx_pwm *to_ep93xx_pwm(struct pwm_chip *chip)
41
42
{
42
43
return pwmchip_get_drvdata(chip);
43
-
}
44
-
45
-
static int ep93xx_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
46
-
{
47
-
struct platform_device *pdev = to_platform_device(pwmchip_parent(chip));
48
-
49
-
return ep93xx_pwm_acquire_gpio(pdev);
50
-
}
51
-
52
-
static void ep93xx_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
53
-
{
54
-
struct platform_device *pdev = to_platform_device(pwmchip_parent(chip));
55
-
56
-
ep93xx_pwm_release_gpio(pdev);
57
44
}
58
45
59
46
static int ep93xx_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
···
140
155
}
141
156
142
157
static const struct pwm_ops ep93xx_pwm_ops = {
143
-
.request = ep93xx_pwm_request,
144
-
.free = ep93xx_pwm_free,
145
158
.apply = ep93xx_pwm_apply,
146
159
};
147
160
···
171
188
return 0;
172
189
}
173
190
191
+
static const struct of_device_id ep93xx_pwm_of_ids[] = {
192
+
{ .compatible = "cirrus,ep9301-pwm" },
193
+
{ /* sentinel */}
194
+
};
195
+
MODULE_DEVICE_TABLE(of, ep93xx_pwm_of_ids);
196
+
174
197
static struct platform_driver ep93xx_pwm_driver = {
175
198
.driver = {
176
199
.name = "ep93xx-pwm",
200
+
.of_match_table = ep93xx_pwm_of_ids,
177
201
},
178
202
.probe = ep93xx_pwm_probe,
179
203
};
+1
drivers/soc/Kconfig
+1
drivers/soc/Kconfig
+1
drivers/soc/Makefile
+1
drivers/soc/Makefile
+17
drivers/soc/cirrus/Kconfig
+17
drivers/soc/cirrus/Kconfig
···
1
+
# SPDX-License-Identifier: GPL-2.0-only
2
+
3
+
if ARCH_EP93XX
4
+
5
+
config EP93XX_SOC
6
+
bool "Cirrus EP93xx chips SoC"
7
+
select SOC_BUS
8
+
select AUXILIARY_BUS
9
+
default y
10
+
help
11
+
Enable support SoC for Cirrus EP93xx chips.
12
+
13
+
Cirrus EP93xx chips have several swlocked registers,
14
+
this driver provides locked access for reset, pinctrl
15
+
and clk devices implemented as auxiliary devices.
16
+
17
+
endif
+2
drivers/soc/cirrus/Makefile
+2
drivers/soc/cirrus/Makefile
+252
drivers/soc/cirrus/soc-ep93xx.c
+252
drivers/soc/cirrus/soc-ep93xx.c
···
1
+
// SPDX-License-Identifier: GPL-2.0+
2
+
/*
3
+
* SoC driver for Cirrus EP93xx chips.
4
+
* Copyright (C) 2022 Nikita Shubin <nikita.shubin@maquefel.me>
5
+
*
6
+
* Based on a rewrite of arch/arm/mach-ep93xx/core.c
7
+
* Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
8
+
* Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org>
9
+
*
10
+
* Thanks go to Michael Burian and Ray Lehtiniemi for their key
11
+
* role in the ep93xx Linux community.
12
+
*/
13
+
14
+
#include <linux/bits.h>
15
+
#include <linux/cleanup.h>
16
+
#include <linux/init.h>
17
+
#include <linux/mfd/syscon.h>
18
+
#include <linux/of.h>
19
+
#include <linux/of_fdt.h>
20
+
#include <linux/platform_device.h>
21
+
#include <linux/regmap.h>
22
+
#include <linux/slab.h>
23
+
#include <linux/spinlock.h>
24
+
#include <linux/sys_soc.h>
25
+
26
+
#include <linux/soc/cirrus/ep93xx.h>
27
+
28
+
#define EP93XX_SYSCON_DEVCFG 0x80
29
+
30
+
#define EP93XX_SWLOCK_MAGICK 0xaa
31
+
#define EP93XX_SYSCON_SWLOCK 0xc0
32
+
#define EP93XX_SYSCON_SYSCFG 0x9c
33
+
#define EP93XX_SYSCON_SYSCFG_REV_MASK GENMASK(31, 28)
34
+
#define EP93XX_SYSCON_SYSCFG_REV_SHIFT 28
35
+
36
+
struct ep93xx_map_info {
37
+
spinlock_t lock;
38
+
void __iomem *base;
39
+
struct regmap *map;
40
+
};
41
+
42
+
/*
43
+
* EP93xx System Controller software locked register write
44
+
*
45
+
* Logic safeguards are included to condition the control signals for
46
+
* power connection to the matrix to prevent part damage. In addition, a
47
+
* software lock register is included that must be written with 0xAA
48
+
* before each register write to change the values of the four switch
49
+
* matrix control registers.
50
+
*/
51
+
static void ep93xx_regmap_write(struct regmap *map, spinlock_t *lock,
52
+
unsigned int reg, unsigned int val)
53
+
{
54
+
guard(spinlock_irqsave)(lock);
55
+
56
+
regmap_write(map, EP93XX_SYSCON_SWLOCK, EP93XX_SWLOCK_MAGICK);
57
+
regmap_write(map, reg, val);
58
+
}
59
+
60
+
static void ep93xx_regmap_update_bits(struct regmap *map, spinlock_t *lock,
61
+
unsigned int reg, unsigned int mask,
62
+
unsigned int val)
63
+
{
64
+
guard(spinlock_irqsave)(lock);
65
+
66
+
regmap_write(map, EP93XX_SYSCON_SWLOCK, EP93XX_SWLOCK_MAGICK);
67
+
/* force write is required to clear swlock if no changes are made */
68
+
regmap_update_bits_base(map, reg, mask, val, NULL, false, true);
69
+
}
70
+
71
+
static void ep93xx_unregister_adev(void *_adev)
72
+
{
73
+
struct auxiliary_device *adev = _adev;
74
+
75
+
auxiliary_device_delete(adev);
76
+
auxiliary_device_uninit(adev);
77
+
}
78
+
79
+
static void ep93xx_adev_release(struct device *dev)
80
+
{
81
+
struct auxiliary_device *adev = to_auxiliary_dev(dev);
82
+
struct ep93xx_regmap_adev *rdev = to_ep93xx_regmap_adev(adev);
83
+
84
+
kfree(rdev);
85
+
}
86
+
87
+
static struct auxiliary_device __init *ep93xx_adev_alloc(struct device *parent,
88
+
const char *name,
89
+
struct ep93xx_map_info *info)
90
+
{
91
+
struct ep93xx_regmap_adev *rdev __free(kfree) = NULL;
92
+
struct auxiliary_device *adev;
93
+
int ret;
94
+
95
+
rdev = kzalloc(sizeof(*rdev), GFP_KERNEL);
96
+
if (!rdev)
97
+
return ERR_PTR(-ENOMEM);
98
+
99
+
rdev->map = info->map;
100
+
rdev->base = info->base;
101
+
rdev->lock = &info->lock;
102
+
rdev->write = ep93xx_regmap_write;
103
+
rdev->update_bits = ep93xx_regmap_update_bits;
104
+
105
+
adev = &rdev->adev;
106
+
adev->name = name;
107
+
adev->dev.parent = parent;
108
+
adev->dev.release = ep93xx_adev_release;
109
+
110
+
ret = auxiliary_device_init(adev);
111
+
if (ret)
112
+
return ERR_PTR(ret);
113
+
114
+
return &no_free_ptr(rdev)->adev;
115
+
}
116
+
117
+
static int __init ep93xx_controller_register(struct device *parent, const char *name,
118
+
struct ep93xx_map_info *info)
119
+
{
120
+
struct auxiliary_device *adev;
121
+
int ret;
122
+
123
+
adev = ep93xx_adev_alloc(parent, name, info);
124
+
if (IS_ERR(adev))
125
+
return PTR_ERR(adev);
126
+
127
+
ret = auxiliary_device_add(adev);
128
+
if (ret) {
129
+
auxiliary_device_uninit(adev);
130
+
return ret;
131
+
}
132
+
133
+
return devm_add_action_or_reset(parent, ep93xx_unregister_adev, adev);
134
+
}
135
+
136
+
static unsigned int __init ep93xx_soc_revision(struct regmap *map)
137
+
{
138
+
unsigned int val;
139
+
140
+
regmap_read(map, EP93XX_SYSCON_SYSCFG, &val);
141
+
val &= EP93XX_SYSCON_SYSCFG_REV_MASK;
142
+
val >>= EP93XX_SYSCON_SYSCFG_REV_SHIFT;
143
+
return val;
144
+
}
145
+
146
+
static const char __init *ep93xx_get_soc_rev(unsigned int rev)
147
+
{
148
+
switch (rev) {
149
+
case EP93XX_CHIP_REV_D0:
150
+
return "D0";
151
+
case EP93XX_CHIP_REV_D1:
152
+
return "D1";
153
+
case EP93XX_CHIP_REV_E0:
154
+
return "E0";
155
+
case EP93XX_CHIP_REV_E1:
156
+
return "E1";
157
+
case EP93XX_CHIP_REV_E2:
158
+
return "E2";
159
+
default:
160
+
return "unknown";
161
+
}
162
+
}
163
+
164
+
static const char *pinctrl_names[] __initconst = {
165
+
"pinctrl-ep9301", /* EP93XX_9301_SOC */
166
+
"pinctrl-ep9307", /* EP93XX_9307_SOC */
167
+
"pinctrl-ep9312", /* EP93XX_9312_SOC */
168
+
};
169
+
170
+
static int __init ep93xx_syscon_probe(struct platform_device *pdev)
171
+
{
172
+
enum ep93xx_soc_model model;
173
+
struct ep93xx_map_info *map_info;
174
+
struct soc_device_attribute *attrs;
175
+
struct soc_device *soc_dev;
176
+
struct device *dev = &pdev->dev;
177
+
struct regmap *map;
178
+
void __iomem *base;
179
+
unsigned int rev;
180
+
int ret;
181
+
182
+
model = (enum ep93xx_soc_model)(uintptr_t)device_get_match_data(dev);
183
+
184
+
map = device_node_to_regmap(dev->of_node);
185
+
if (IS_ERR(map))
186
+
return PTR_ERR(map);
187
+
188
+
base = devm_platform_ioremap_resource(pdev, 0);
189
+
if (IS_ERR(base))
190
+
return PTR_ERR(base);
191
+
192
+
attrs = devm_kzalloc(dev, sizeof(*attrs), GFP_KERNEL);
193
+
if (!attrs)
194
+
return -ENOMEM;
195
+
196
+
rev = ep93xx_soc_revision(map);
197
+
198
+
attrs->machine = of_flat_dt_get_machine_name();
199
+
attrs->family = "Cirrus Logic EP93xx";
200
+
attrs->revision = ep93xx_get_soc_rev(rev);
201
+
202
+
soc_dev = soc_device_register(attrs);
203
+
if (IS_ERR(soc_dev))
204
+
return PTR_ERR(soc_dev);
205
+
206
+
map_info = devm_kzalloc(dev, sizeof(*map_info), GFP_KERNEL);
207
+
if (!map_info)
208
+
return -ENOMEM;
209
+
210
+
spin_lock_init(&map_info->lock);
211
+
map_info->map = map;
212
+
map_info->base = base;
213
+
214
+
ret = ep93xx_controller_register(dev, pinctrl_names[model], map_info);
215
+
if (ret)
216
+
dev_err(dev, "registering pinctrl controller failed\n");
217
+
218
+
/*
219
+
* EP93xx SSP clock rate was doubled in version E2. For more information
220
+
* see section 6 "2x SSP (Synchronous Serial Port) Clock – Revision E2 only":
221
+
* http://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf
222
+
*/
223
+
if (rev == EP93XX_CHIP_REV_E2)
224
+
ret = ep93xx_controller_register(dev, "clk-ep93xx.e2", map_info);
225
+
else
226
+
ret = ep93xx_controller_register(dev, "clk-ep93xx", map_info);
227
+
if (ret)
228
+
dev_err(dev, "registering clock controller failed\n");
229
+
230
+
ret = ep93xx_controller_register(dev, "reset-ep93xx", map_info);
231
+
if (ret)
232
+
dev_err(dev, "registering reset controller failed\n");
233
+
234
+
return 0;
235
+
}
236
+
237
+
static const struct of_device_id ep9301_syscon_of_device_ids[] = {
238
+
{ .compatible = "cirrus,ep9301-syscon", .data = (void *)EP93XX_9301_SOC },
239
+
{ .compatible = "cirrus,ep9302-syscon", .data = (void *)EP93XX_9301_SOC },
240
+
{ .compatible = "cirrus,ep9307-syscon", .data = (void *)EP93XX_9307_SOC },
241
+
{ .compatible = "cirrus,ep9312-syscon", .data = (void *)EP93XX_9312_SOC },
242
+
{ .compatible = "cirrus,ep9315-syscon", .data = (void *)EP93XX_9312_SOC },
243
+
{ /* sentinel */ }
244
+
};
245
+
246
+
static struct platform_driver ep9301_syscon_driver = {
247
+
.driver = {
248
+
.name = "ep9301-syscon",
249
+
.of_match_table = ep9301_syscon_of_device_ids,
250
+
},
251
+
};
252
+
builtin_platform_driver_probe(ep9301_syscon_driver, ep93xx_syscon_probe);
+23
-45
drivers/spi/spi-ep93xx.c
+23
-45
drivers/spi/spi-ep93xx.c
···
18
18
#include <linux/err.h>
19
19
#include <linux/delay.h>
20
20
#include <linux/device.h>
21
+
#include <linux/dma-direction.h>
22
+
#include <linux/dma-mapping.h>
21
23
#include <linux/dmaengine.h>
22
24
#include <linux/bitops.h>
23
25
#include <linux/interrupt.h>
24
26
#include <linux/module.h>
27
+
#include <linux/property.h>
25
28
#include <linux/platform_device.h>
26
29
#include <linux/sched.h>
27
30
#include <linux/scatterlist.h>
28
31
#include <linux/spi/spi.h>
29
-
30
-
#include <linux/platform_data/dma-ep93xx.h>
31
-
#include <linux/platform_data/spi-ep93xx.h>
32
32
33
33
#define SSPCR0 0x0000
34
34
#define SSPCR0_SPO BIT(6)
···
76
76
* frame decreases this level and sending one frame increases it.
77
77
* @dma_rx: RX DMA channel
78
78
* @dma_tx: TX DMA channel
79
-
* @dma_rx_data: RX parameters passed to the DMA engine
80
-
* @dma_tx_data: TX parameters passed to the DMA engine
81
79
* @rx_sgt: sg table for RX transfers
82
80
* @tx_sgt: sg table for TX transfers
83
81
* @zeropage: dummy page used as RX buffer when only TX buffer is passed in by
···
90
92
size_t fifo_level;
91
93
struct dma_chan *dma_rx;
92
94
struct dma_chan *dma_tx;
93
-
struct ep93xx_dma_data dma_rx_data;
94
-
struct ep93xx_dma_data dma_tx_data;
95
95
struct sg_table rx_sgt;
96
96
struct sg_table tx_sgt;
97
97
void *zeropage;
···
571
575
return 0;
572
576
}
573
577
574
-
static bool ep93xx_spi_dma_filter(struct dma_chan *chan, void *filter_param)
578
+
static int ep93xx_spi_setup_dma(struct device *dev, struct ep93xx_spi *espi)
575
579
{
576
-
if (ep93xx_dma_chan_is_m2p(chan))
577
-
return false;
578
-
579
-
chan->private = filter_param;
580
-
return true;
581
-
}
582
-
583
-
static int ep93xx_spi_setup_dma(struct ep93xx_spi *espi)
584
-
{
585
-
dma_cap_mask_t mask;
586
580
int ret;
587
581
588
582
espi->zeropage = (void *)get_zeroed_page(GFP_KERNEL);
589
583
if (!espi->zeropage)
590
584
return -ENOMEM;
591
585
592
-
dma_cap_zero(mask);
593
-
dma_cap_set(DMA_SLAVE, mask);
594
-
595
-
espi->dma_rx_data.port = EP93XX_DMA_SSP;
596
-
espi->dma_rx_data.direction = DMA_DEV_TO_MEM;
597
-
espi->dma_rx_data.name = "ep93xx-spi-rx";
598
-
599
-
espi->dma_rx = dma_request_channel(mask, ep93xx_spi_dma_filter,
600
-
&espi->dma_rx_data);
601
-
if (!espi->dma_rx) {
602
-
ret = -ENODEV;
586
+
espi->dma_rx = dma_request_chan(dev, "rx");
587
+
if (IS_ERR(espi->dma_rx)) {
588
+
ret = dev_err_probe(dev, PTR_ERR(espi->dma_rx), "rx DMA setup failed");
603
589
goto fail_free_page;
604
590
}
605
591
606
-
espi->dma_tx_data.port = EP93XX_DMA_SSP;
607
-
espi->dma_tx_data.direction = DMA_MEM_TO_DEV;
608
-
espi->dma_tx_data.name = "ep93xx-spi-tx";
609
-
610
-
espi->dma_tx = dma_request_channel(mask, ep93xx_spi_dma_filter,
611
-
&espi->dma_tx_data);
612
-
if (!espi->dma_tx) {
613
-
ret = -ENODEV;
592
+
espi->dma_tx = dma_request_chan(dev, "tx");
593
+
if (IS_ERR(espi->dma_tx)) {
594
+
ret = dev_err_probe(dev, PTR_ERR(espi->dma_tx), "tx DMA setup failed");
614
595
goto fail_release_rx;
615
596
}
616
597
···
620
647
static int ep93xx_spi_probe(struct platform_device *pdev)
621
648
{
622
649
struct spi_controller *host;
623
-
struct ep93xx_spi_info *info;
624
650
struct ep93xx_spi *espi;
625
651
struct resource *res;
626
652
int irq;
627
653
int error;
628
-
629
-
info = dev_get_platdata(&pdev->dev);
630
-
if (!info) {
631
-
dev_err(&pdev->dev, "missing platform data\n");
632
-
return -EINVAL;
633
-
}
634
654
635
655
irq = platform_get_irq(pdev, 0);
636
656
if (irq < 0)
···
679
713
goto fail_release_host;
680
714
}
681
715
682
-
if (info->use_dma && ep93xx_spi_setup_dma(espi))
716
+
error = ep93xx_spi_setup_dma(&pdev->dev, espi);
717
+
if (error == -EPROBE_DEFER)
718
+
goto fail_release_host;
719
+
720
+
if (error)
683
721
dev_warn(&pdev->dev, "DMA setup failed. Falling back to PIO\n");
684
722
685
723
/* make sure that the hardware is disabled */
686
724
writel(0, espi->mmio + SSPCR1);
687
725
726
+
device_set_node(&host->dev, dev_fwnode(&pdev->dev));
688
727
error = devm_spi_register_controller(&pdev->dev, host);
689
728
if (error) {
690
729
dev_err(&pdev->dev, "failed to register SPI host\n");
···
717
746
ep93xx_spi_release_dma(espi);
718
747
}
719
748
749
+
static const struct of_device_id ep93xx_spi_of_ids[] = {
750
+
{ .compatible = "cirrus,ep9301-spi" },
751
+
{ /* sentinel */ }
752
+
};
753
+
MODULE_DEVICE_TABLE(of, ep93xx_spi_of_ids);
754
+
720
755
static struct platform_driver ep93xx_spi_driver = {
721
756
.driver = {
722
757
.name = "ep93xx-spi",
758
+
.of_match_table = ep93xx_spi_of_ids,
723
759
},
724
760
.probe = ep93xx_spi_probe,
725
761
.remove_new = ep93xx_spi_remove,
+8
drivers/watchdog/ts72xx_wdt.c
+8
drivers/watchdog/ts72xx_wdt.c
···
12
12
*/
13
13
14
14
#include <linux/platform_device.h>
15
+
#include <linux/mod_devicetable.h>
15
16
#include <linux/module.h>
16
17
#include <linux/watchdog.h>
17
18
#include <linux/io.h>
···
161
160
return 0;
162
161
}
163
162
163
+
static const struct of_device_id ts72xx_wdt_of_ids[] = {
164
+
{ .compatible = "technologic,ts7200-wdt" },
165
+
{ /* sentinel */ }
166
+
};
167
+
MODULE_DEVICE_TABLE(of, ts72xx_wdt_of_ids);
168
+
164
169
static struct platform_driver ts72xx_wdt_driver = {
165
170
.probe = ts72xx_wdt_probe,
166
171
.driver = {
167
172
.name = "ts72xx-wdt",
173
+
.of_match_table = ts72xx_wdt_of_ids,
168
174
},
169
175
};
170
176
+46
include/dt-bindings/clock/cirrus,ep9301-syscon.h
+46
include/dt-bindings/clock/cirrus,ep9301-syscon.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
2
+
#ifndef DT_BINDINGS_CIRRUS_EP93XX_CLOCK_H
3
+
#define DT_BINDINGS_CIRRUS_EP93XX_CLOCK_H
4
+
5
+
#define EP93XX_CLK_PLL1 0
6
+
#define EP93XX_CLK_PLL2 1
7
+
8
+
#define EP93XX_CLK_FCLK 2
9
+
#define EP93XX_CLK_HCLK 3
10
+
#define EP93XX_CLK_PCLK 4
11
+
12
+
#define EP93XX_CLK_UART 5
13
+
#define EP93XX_CLK_SPI 6
14
+
#define EP93XX_CLK_PWM 7
15
+
#define EP93XX_CLK_USB 8
16
+
17
+
#define EP93XX_CLK_M2M0 9
18
+
#define EP93XX_CLK_M2M1 10
19
+
20
+
#define EP93XX_CLK_M2P0 11
21
+
#define EP93XX_CLK_M2P1 12
22
+
#define EP93XX_CLK_M2P2 13
23
+
#define EP93XX_CLK_M2P3 14
24
+
#define EP93XX_CLK_M2P4 15
25
+
#define EP93XX_CLK_M2P5 16
26
+
#define EP93XX_CLK_M2P6 17
27
+
#define EP93XX_CLK_M2P7 18
28
+
#define EP93XX_CLK_M2P8 19
29
+
#define EP93XX_CLK_M2P9 20
30
+
31
+
#define EP93XX_CLK_UART1 21
32
+
#define EP93XX_CLK_UART2 22
33
+
#define EP93XX_CLK_UART3 23
34
+
35
+
#define EP93XX_CLK_ADC 24
36
+
#define EP93XX_CLK_ADC_EN 25
37
+
38
+
#define EP93XX_CLK_KEYPAD 26
39
+
40
+
#define EP93XX_CLK_VIDEO 27
41
+
42
+
#define EP93XX_CLK_I2S_MCLK 28
43
+
#define EP93XX_CLK_I2S_SCLK 29
44
+
#define EP93XX_CLK_I2S_LRCLK 30
45
+
46
+
#endif /* DT_BINDINGS_CIRRUS_EP93XX_CLOCK_H */
-94
include/linux/platform_data/dma-ep93xx.h
-94
include/linux/platform_data/dma-ep93xx.h
···
1
-
/* SPDX-License-Identifier: GPL-2.0 */
2
-
#ifndef __ASM_ARCH_DMA_H
3
-
#define __ASM_ARCH_DMA_H
4
-
5
-
#include <linux/types.h>
6
-
#include <linux/dmaengine.h>
7
-
#include <linux/dma-mapping.h>
8
-
9
-
/*
10
-
* M2P channels.
11
-
*
12
-
* Note that these values are also directly used for setting the PPALLOC
13
-
* register.
14
-
*/
15
-
#define EP93XX_DMA_I2S1 0
16
-
#define EP93XX_DMA_I2S2 1
17
-
#define EP93XX_DMA_AAC1 2
18
-
#define EP93XX_DMA_AAC2 3
19
-
#define EP93XX_DMA_AAC3 4
20
-
#define EP93XX_DMA_I2S3 5
21
-
#define EP93XX_DMA_UART1 6
22
-
#define EP93XX_DMA_UART2 7
23
-
#define EP93XX_DMA_UART3 8
24
-
#define EP93XX_DMA_IRDA 9
25
-
/* M2M channels */
26
-
#define EP93XX_DMA_SSP 10
27
-
#define EP93XX_DMA_IDE 11
28
-
29
-
/**
30
-
* struct ep93xx_dma_data - configuration data for the EP93xx dmaengine
31
-
* @port: peripheral which is requesting the channel
32
-
* @direction: TX/RX channel
33
-
* @name: optional name for the channel, this is displayed in /proc/interrupts
34
-
*
35
-
* This information is passed as private channel parameter in a filter
36
-
* function. Note that this is only needed for slave/cyclic channels. For
37
-
* memcpy channels %NULL data should be passed.
38
-
*/
39
-
struct ep93xx_dma_data {
40
-
int port;
41
-
enum dma_transfer_direction direction;
42
-
const char *name;
43
-
};
44
-
45
-
/**
46
-
* struct ep93xx_dma_chan_data - platform specific data for a DMA channel
47
-
* @name: name of the channel, used for getting the right clock for the channel
48
-
* @base: mapped registers
49
-
* @irq: interrupt number used by this channel
50
-
*/
51
-
struct ep93xx_dma_chan_data {
52
-
const char *name;
53
-
void __iomem *base;
54
-
int irq;
55
-
};
56
-
57
-
/**
58
-
* struct ep93xx_dma_platform_data - platform data for the dmaengine driver
59
-
* @channels: array of channels which are passed to the driver
60
-
* @num_channels: number of channels in the array
61
-
*
62
-
* This structure is passed to the DMA engine driver via platform data. For
63
-
* M2P channels, contract is that even channels are for TX and odd for RX.
64
-
* There is no requirement for the M2M channels.
65
-
*/
66
-
struct ep93xx_dma_platform_data {
67
-
struct ep93xx_dma_chan_data *channels;
68
-
size_t num_channels;
69
-
};
70
-
71
-
static inline bool ep93xx_dma_chan_is_m2p(struct dma_chan *chan)
72
-
{
73
-
return !strcmp(dev_name(chan->device->dev), "ep93xx-dma-m2p");
74
-
}
75
-
76
-
/**
77
-
* ep93xx_dma_chan_direction - returns direction the channel can be used
78
-
* @chan: channel
79
-
*
80
-
* This function can be used in filter functions to find out whether the
81
-
* channel supports given DMA direction. Only M2P channels have such
82
-
* limitation, for M2M channels the direction is configurable.
83
-
*/
84
-
static inline enum dma_transfer_direction
85
-
ep93xx_dma_chan_direction(struct dma_chan *chan)
86
-
{
87
-
if (!ep93xx_dma_chan_is_m2p(chan))
88
-
return DMA_TRANS_NONE;
89
-
90
-
/* even channels are for TX, odd for RX */
91
-
return (chan->chan_id % 2 == 0) ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
92
-
}
93
-
94
-
#endif /* __ASM_ARCH_DMA_H */
-10
include/linux/platform_data/eth-ep93xx.h
-10
include/linux/platform_data/eth-ep93xx.h
-32
include/linux/platform_data/keypad-ep93xx.h
-32
include/linux/platform_data/keypad-ep93xx.h
···
1
-
/* SPDX-License-Identifier: GPL-2.0 */
2
-
#ifndef __KEYPAD_EP93XX_H
3
-
#define __KEYPAD_EP93XX_H
4
-
5
-
struct matrix_keymap_data;
6
-
7
-
/* flags for the ep93xx_keypad driver */
8
-
#define EP93XX_KEYPAD_DISABLE_3_KEY (1<<0) /* disable 3-key reset */
9
-
#define EP93XX_KEYPAD_DIAG_MODE (1<<1) /* diagnostic mode */
10
-
#define EP93XX_KEYPAD_BACK_DRIVE (1<<2) /* back driving mode */
11
-
#define EP93XX_KEYPAD_TEST_MODE (1<<3) /* scan only column 0 */
12
-
#define EP93XX_KEYPAD_AUTOREPEAT (1<<4) /* enable key autorepeat */
13
-
14
-
/**
15
-
* struct ep93xx_keypad_platform_data - platform specific device structure
16
-
* @keymap_data: pointer to &matrix_keymap_data
17
-
* @debounce: debounce start count; terminal count is 0xff
18
-
* @prescale: row/column counter pre-scaler load value
19
-
* @flags: see above
20
-
*/
21
-
struct ep93xx_keypad_platform_data {
22
-
struct matrix_keymap_data *keymap_data;
23
-
unsigned int debounce;
24
-
unsigned int prescale;
25
-
unsigned int flags;
26
-
unsigned int clk_rate;
27
-
};
28
-
29
-
#define EP93XX_MATRIX_ROWS (8)
30
-
#define EP93XX_MATRIX_COLS (8)
31
-
32
-
#endif /* __KEYPAD_EP93XX_H */
-15
include/linux/platform_data/spi-ep93xx.h
-15
include/linux/platform_data/spi-ep93xx.h
···
1
-
/* SPDX-License-Identifier: GPL-2.0 */
2
-
#ifndef __ASM_MACH_EP93XX_SPI_H
3
-
#define __ASM_MACH_EP93XX_SPI_H
4
-
5
-
struct spi_device;
6
-
7
-
/**
8
-
* struct ep93xx_spi_info - EP93xx specific SPI descriptor
9
-
* @use_dma: use DMA for the transfers
10
-
*/
11
-
struct ep93xx_spi_info {
12
-
bool use_dma;
13
-
};
14
-
15
-
#endif /* __ASM_MACH_EP93XX_SPI_H */
+24
-23
include/linux/soc/cirrus/ep93xx.h
+24
-23
include/linux/soc/cirrus/ep93xx.h
···
2
2
#ifndef _SOC_EP93XX_H
3
3
#define _SOC_EP93XX_H
4
4
5
-
struct platform_device;
5
+
struct regmap;
6
+
struct spinlock_t;
7
+
8
+
enum ep93xx_soc_model {
9
+
EP93XX_9301_SOC,
10
+
EP93XX_9307_SOC,
11
+
EP93XX_9312_SOC,
12
+
};
13
+
14
+
#include <linux/auxiliary_bus.h>
15
+
#include <linux/compiler_types.h>
16
+
#include <linux/container_of.h>
6
17
7
18
#define EP93XX_CHIP_REV_D0 3
8
19
#define EP93XX_CHIP_REV_D1 4
···
21
10
#define EP93XX_CHIP_REV_E1 6
22
11
#define EP93XX_CHIP_REV_E2 7
23
12
24
-
#ifdef CONFIG_ARCH_EP93XX
25
-
int ep93xx_pwm_acquire_gpio(struct platform_device *pdev);
26
-
void ep93xx_pwm_release_gpio(struct platform_device *pdev);
27
-
int ep93xx_ide_acquire_gpio(struct platform_device *pdev);
28
-
void ep93xx_ide_release_gpio(struct platform_device *pdev);
29
-
int ep93xx_keypad_acquire_gpio(struct platform_device *pdev);
30
-
void ep93xx_keypad_release_gpio(struct platform_device *pdev);
31
-
int ep93xx_i2s_acquire(void);
32
-
void ep93xx_i2s_release(void);
33
-
unsigned int ep93xx_chip_revision(void);
13
+
struct ep93xx_regmap_adev {
14
+
struct auxiliary_device adev;
15
+
struct regmap *map;
16
+
void __iomem *base;
17
+
spinlock_t *lock;
18
+
void (*write)(struct regmap *map, spinlock_t *lock, unsigned int reg,
19
+
unsigned int val);
20
+
void (*update_bits)(struct regmap *map, spinlock_t *lock,
21
+
unsigned int reg, unsigned int mask, unsigned int val);
22
+
};
34
23
35
-
#else
36
-
static inline int ep93xx_pwm_acquire_gpio(struct platform_device *pdev) { return 0; }
37
-
static inline void ep93xx_pwm_release_gpio(struct platform_device *pdev) {}
38
-
static inline int ep93xx_ide_acquire_gpio(struct platform_device *pdev) { return 0; }
39
-
static inline void ep93xx_ide_release_gpio(struct platform_device *pdev) {}
40
-
static inline int ep93xx_keypad_acquire_gpio(struct platform_device *pdev) { return 0; }
41
-
static inline void ep93xx_keypad_release_gpio(struct platform_device *pdev) {}
42
-
static inline int ep93xx_i2s_acquire(void) { return 0; }
43
-
static inline void ep93xx_i2s_release(void) {}
44
-
static inline unsigned int ep93xx_chip_revision(void) { return 0; }
45
-
46
-
#endif
24
+
#define to_ep93xx_regmap_adev(_adev) \
25
+
container_of((_adev), struct ep93xx_regmap_adev, adev)
47
26
48
27
#endif
-9
sound/soc/cirrus/Kconfig
-9
sound/soc/cirrus/Kconfig
···
31
31
32
32
endif # if SND_EP93XX_SOC_I2S
33
33
34
-
config SND_EP93XX_SOC_EDB93XX
35
-
tristate "SoC Audio support for Cirrus Logic EDB93xx boards"
36
-
depends on SND_EP93XX_SOC && (MACH_EDB9301 || MACH_EDB9302 || MACH_EDB9302A || MACH_EDB9307A || MACH_EDB9315A)
37
-
select SND_EP93XX_SOC_I2S
38
-
select SND_SOC_CS4271_I2C if I2C
39
-
select SND_SOC_CS4271_SPI if SPI_MASTER
40
-
help
41
-
Say Y or M here if you want to add support for I2S audio on the
42
-
Cirrus Logic EDB93xx boards.
-4
sound/soc/cirrus/Makefile
-4
sound/soc/cirrus/Makefile
-116
sound/soc/cirrus/edb93xx.c
-116
sound/soc/cirrus/edb93xx.c
···
1
-
// SPDX-License-Identifier: GPL-2.0-or-later
2
-
/*
3
-
* SoC audio for EDB93xx
4
-
*
5
-
* Copyright (c) 2010 Alexander Sverdlin <subaparts@yandex.ru>
6
-
*
7
-
* This driver support CS4271 codec being master or slave, working
8
-
* in control port mode, connected either via SPI or I2C.
9
-
* The data format accepted is I2S or left-justified.
10
-
* DAPM support not implemented.
11
-
*/
12
-
13
-
#include <linux/platform_device.h>
14
-
#include <linux/module.h>
15
-
#include <linux/soc/cirrus/ep93xx.h>
16
-
#include <sound/core.h>
17
-
#include <sound/pcm.h>
18
-
#include <sound/soc.h>
19
-
#include <asm/mach-types.h>
20
-
21
-
static int edb93xx_hw_params(struct snd_pcm_substream *substream,
22
-
struct snd_pcm_hw_params *params)
23
-
{
24
-
struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
25
-
struct snd_soc_dai *codec_dai = snd_soc_rtd_to_codec(rtd, 0);
26
-
struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
27
-
int err;
28
-
unsigned int mclk_rate;
29
-
unsigned int rate = params_rate(params);
30
-
31
-
/*
32
-
* According to CS4271 datasheet we use MCLK/LRCK=256 for
33
-
* rates below 50kHz and 128 for higher sample rates
34
-
*/
35
-
if (rate < 50000)
36
-
mclk_rate = rate * 64 * 4;
37
-
else
38
-
mclk_rate = rate * 64 * 2;
39
-
40
-
err = snd_soc_dai_set_sysclk(codec_dai, 0, mclk_rate,
41
-
SND_SOC_CLOCK_IN);
42
-
if (err)
43
-
return err;
44
-
45
-
return snd_soc_dai_set_sysclk(cpu_dai, 0, mclk_rate,
46
-
SND_SOC_CLOCK_OUT);
47
-
}
48
-
49
-
static const struct snd_soc_ops edb93xx_ops = {
50
-
.hw_params = edb93xx_hw_params,
51
-
};
52
-
53
-
SND_SOC_DAILINK_DEFS(hifi,
54
-
DAILINK_COMP_ARRAY(COMP_CPU("ep93xx-i2s")),
55
-
DAILINK_COMP_ARRAY(COMP_CODEC("spi0.0", "cs4271-hifi")),
56
-
DAILINK_COMP_ARRAY(COMP_PLATFORM("ep93xx-i2s")));
57
-
58
-
static struct snd_soc_dai_link edb93xx_dai = {
59
-
.name = "CS4271",
60
-
.stream_name = "CS4271 HiFi",
61
-
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
62
-
SND_SOC_DAIFMT_CBC_CFC,
63
-
.ops = &edb93xx_ops,
64
-
SND_SOC_DAILINK_REG(hifi),
65
-
};
66
-
67
-
static struct snd_soc_card snd_soc_edb93xx = {
68
-
.name = "EDB93XX",
69
-
.owner = THIS_MODULE,
70
-
.dai_link = &edb93xx_dai,
71
-
.num_links = 1,
72
-
};
73
-
74
-
static int edb93xx_probe(struct platform_device *pdev)
75
-
{
76
-
struct snd_soc_card *card = &snd_soc_edb93xx;
77
-
int ret;
78
-
79
-
ret = ep93xx_i2s_acquire();
80
-
if (ret)
81
-
return ret;
82
-
83
-
card->dev = &pdev->dev;
84
-
85
-
ret = snd_soc_register_card(card);
86
-
if (ret) {
87
-
dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n",
88
-
ret);
89
-
ep93xx_i2s_release();
90
-
}
91
-
92
-
return ret;
93
-
}
94
-
95
-
static void edb93xx_remove(struct platform_device *pdev)
96
-
{
97
-
struct snd_soc_card *card = platform_get_drvdata(pdev);
98
-
99
-
snd_soc_unregister_card(card);
100
-
ep93xx_i2s_release();
101
-
}
102
-
103
-
static struct platform_driver edb93xx_driver = {
104
-
.driver = {
105
-
.name = "edb93xx-audio",
106
-
},
107
-
.probe = edb93xx_probe,
108
-
.remove = edb93xx_remove,
109
-
};
110
-
111
-
module_platform_driver(edb93xx_driver);
112
-
113
-
MODULE_AUTHOR("Alexander Sverdlin <subaparts@yandex.ru>");
114
-
MODULE_DESCRIPTION("ALSA SoC EDB93xx");
115
-
MODULE_LICENSE("GPL");
116
-
MODULE_ALIAS("platform:edb93xx-audio");
-19
sound/soc/cirrus/ep93xx-i2s.c
-19
sound/soc/cirrus/ep93xx-i2s.c
···
24
24
#include <sound/initval.h>
25
25
#include <sound/soc.h>
26
26
27
-
#include <linux/platform_data/dma-ep93xx.h>
28
27
#include <linux/soc/cirrus/ep93xx.h>
29
28
30
29
#include "ep93xx-pcm.h"
···
77
78
void __iomem *regs;
78
79
struct snd_dmaengine_dai_dma_data dma_params_rx;
79
80
struct snd_dmaengine_dai_dma_data dma_params_tx;
80
-
};
81
-
82
-
static struct ep93xx_dma_data ep93xx_i2s_dma_data[] = {
83
-
[SNDRV_PCM_STREAM_PLAYBACK] = {
84
-
.name = "i2s-pcm-out",
85
-
.port = EP93XX_DMA_I2S1,
86
-
.direction = DMA_MEM_TO_DEV,
87
-
},
88
-
[SNDRV_PCM_STREAM_CAPTURE] = {
89
-
.name = "i2s-pcm-in",
90
-
.port = EP93XX_DMA_I2S1,
91
-
.direction = DMA_DEV_TO_MEM,
92
-
},
93
81
};
94
82
95
83
static inline void ep93xx_i2s_write_reg(struct ep93xx_i2s_info *info,
···
183
197
static int ep93xx_i2s_dai_probe(struct snd_soc_dai *dai)
184
198
{
185
199
struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai);
186
-
187
-
info->dma_params_tx.filter_data =
188
-
&ep93xx_i2s_dma_data[SNDRV_PCM_STREAM_PLAYBACK];
189
-
info->dma_params_rx.filter_data =
190
-
&ep93xx_i2s_dma_data[SNDRV_PCM_STREAM_CAPTURE];
191
200
192
201
snd_soc_dai_init_dma_data(dai, &info->dma_params_tx,
193
202
&info->dma_params_rx);
+1
-18
sound/soc/cirrus/ep93xx-pcm.c
+1
-18
sound/soc/cirrus/ep93xx-pcm.c
···
18
18
#include <sound/soc.h>
19
19
#include <sound/dmaengine_pcm.h>
20
20
21
-
#include <linux/platform_data/dma-ep93xx.h>
22
-
23
21
#include "ep93xx-pcm.h"
24
22
25
23
static const struct snd_pcm_hardware ep93xx_pcm_hardware = {
···
33
35
.fifo_size = 32,
34
36
};
35
37
36
-
static bool ep93xx_pcm_dma_filter(struct dma_chan *chan, void *filter_param)
37
-
{
38
-
struct ep93xx_dma_data *data = filter_param;
39
-
40
-
if (data->direction == ep93xx_dma_chan_direction(chan)) {
41
-
chan->private = data;
42
-
return true;
43
-
}
44
-
45
-
return false;
46
-
}
47
-
48
38
static const struct snd_dmaengine_pcm_config ep93xx_dmaengine_pcm_config = {
49
39
.pcm_hardware = &ep93xx_pcm_hardware,
50
-
.compat_filter_fn = ep93xx_pcm_dma_filter,
51
40
.prealloc_buffer_size = 131072,
52
41
};
53
42
54
43
int devm_ep93xx_pcm_platform_register(struct device *dev)
55
44
{
56
45
return devm_snd_dmaengine_pcm_register(dev,
57
-
&ep93xx_dmaengine_pcm_config,
58
-
SND_DMAENGINE_PCM_FLAG_NO_DT |
59
-
SND_DMAENGINE_PCM_FLAG_COMPAT);
46
+
&ep93xx_dmaengine_pcm_config, 0);
60
47
}
61
48
EXPORT_SYMBOL_GPL(devm_ep93xx_pcm_platform_register);
62
49