Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie:
"Aome amdgpu, one i915, one ttm and one hlcdc, nothing too scary.
All seems fine for about this time"
* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux:
drm/ttm: recognize ARM64 arch in ioprot handler
drm/amdgpu/cz/dpm: properly report UVD and VCE clock levels
drm/amdgpu/cz: implement voltage validation properly
drm/amdgpu: add VCE harvesting instance query
drm/amdgpu: implement VCE 3.0 harvesting support (v4)
drm/amdgpu/dce10: Re-set VBLANK interrupt state when enabling a CRTC
drm/amdgpu/dce11: Re-set VBLANK interrupt state when enabling a CRTC
drm: Stop resetting connector state to unknown
drm/i915: Use two 32bit reads for select 64bit REG_READ ioctls
drm: atmel-hlcdc: fix vblank initial state
+153
-33
+4
drivers/gpu/drm/amd/amdgpu/amdgpu.h
+4
drivers/gpu/drm/amd/amdgpu/amdgpu.h
···
1614
1614
#define AMDGPU_MAX_VCE_HANDLES 16
1615
1615
#define AMDGPU_VCE_FIRMWARE_OFFSET 256
1616
1616
1617
+
#define AMDGPU_VCE_HARVEST_VCE0 (1 << 0)
1618
+
#define AMDGPU_VCE_HARVEST_VCE1 (1 << 1)
1619
+
1617
1620
struct amdgpu_vce {
1618
1621
struct amdgpu_bo *vcpu_bo;
1619
1622
uint64_t gpu_addr;
···
1629
1626
const struct firmware *fw; /* VCE firmware */
1630
1627
struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS];
1631
1628
struct amdgpu_irq_src irq;
1629
+
unsigned harvest_config;
1632
1630
};
1633
1631
1634
1632
/*
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
···
459
459
memcpy(&dev_info.cu_bitmap[0], &cu_info.bitmap[0], sizeof(cu_info.bitmap));
460
460
dev_info.vram_type = adev->mc.vram_type;
461
461
dev_info.vram_bit_width = adev->mc.vram_width;
462
+
dev_info.vce_harvest_config = adev->vce.harvest_config;
462
463
463
464
return copy_to_user(out, &dev_info,
464
465
min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0;
+53
-15
drivers/gpu/drm/amd/amdgpu/cz_dpm.c
+53
-15
drivers/gpu/drm/amd/amdgpu/cz_dpm.c
···
494
494
amdgpu_free_extended_power_table(adev);
495
495
}
496
496
497
+
#define ixSMUSVI_NB_CURRENTVID 0xD8230044
498
+
#define CURRENT_NB_VID_MASK 0xff000000
499
+
#define CURRENT_NB_VID__SHIFT 24
500
+
#define ixSMUSVI_GFX_CURRENTVID 0xD8230048
501
+
#define CURRENT_GFX_VID_MASK 0xff000000
502
+
#define CURRENT_GFX_VID__SHIFT 24
503
+
497
504
static void
498
505
cz_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
499
506
struct seq_file *m)
500
507
{
508
+
struct cz_power_info *pi = cz_get_pi(adev);
501
509
struct amdgpu_clock_voltage_dependency_table *table =
502
510
&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
503
-
u32 current_index =
504
-
(RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
505
-
TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK) >>
506
-
TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT;
507
-
u32 sclk, tmp;
508
-
u16 vddc;
511
+
struct amdgpu_uvd_clock_voltage_dependency_table *uvd_table =
512
+
&adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
513
+
struct amdgpu_vce_clock_voltage_dependency_table *vce_table =
514
+
&adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
515
+
u32 sclk_index = REG_GET_FIELD(RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX),
516
+
TARGET_AND_CURRENT_PROFILE_INDEX, CURR_SCLK_INDEX);
517
+
u32 uvd_index = REG_GET_FIELD(RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX_2),
518
+
TARGET_AND_CURRENT_PROFILE_INDEX_2, CURR_UVD_INDEX);
519
+
u32 vce_index = REG_GET_FIELD(RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX_2),
520
+
TARGET_AND_CURRENT_PROFILE_INDEX_2, CURR_VCE_INDEX);
521
+
u32 sclk, vclk, dclk, ecclk, tmp;
522
+
u16 vddnb, vddgfx;
509
523
510
-
if (current_index >= NUM_SCLK_LEVELS) {
511
-
seq_printf(m, "invalid dpm profile %d\n", current_index);
524
+
if (sclk_index >= NUM_SCLK_LEVELS) {
525
+
seq_printf(m, "invalid sclk dpm profile %d\n", sclk_index);
512
526
} else {
513
-
sclk = table->entries[current_index].clk;
514
-
tmp = (RREG32_SMC(ixSMU_VOLTAGE_STATUS) &
515
-
SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL_MASK) >>
516
-
SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL__SHIFT;
517
-
vddc = cz_convert_8bit_index_to_voltage(adev, (u16)tmp);
518
-
seq_printf(m, "power level %d sclk: %u vddc: %u\n",
519
-
current_index, sclk, vddc);
527
+
sclk = table->entries[sclk_index].clk;
528
+
seq_printf(m, "%u sclk: %u\n", sclk_index, sclk);
529
+
}
530
+
531
+
tmp = (RREG32_SMC(ixSMUSVI_NB_CURRENTVID) &
532
+
CURRENT_NB_VID_MASK) >> CURRENT_NB_VID__SHIFT;
533
+
vddnb = cz_convert_8bit_index_to_voltage(adev, (u16)tmp);
534
+
tmp = (RREG32_SMC(ixSMUSVI_GFX_CURRENTVID) &
535
+
CURRENT_GFX_VID_MASK) >> CURRENT_GFX_VID__SHIFT;
536
+
vddgfx = cz_convert_8bit_index_to_voltage(adev, (u16)tmp);
537
+
seq_printf(m, "vddnb: %u vddgfx: %u\n", vddnb, vddgfx);
538
+
539
+
seq_printf(m, "uvd %sabled\n", pi->uvd_power_gated ? "dis" : "en");
540
+
if (!pi->uvd_power_gated) {
541
+
if (uvd_index >= CZ_MAX_HARDWARE_POWERLEVELS) {
542
+
seq_printf(m, "invalid uvd dpm level %d\n", uvd_index);
543
+
} else {
544
+
vclk = uvd_table->entries[uvd_index].vclk;
545
+
dclk = uvd_table->entries[uvd_index].dclk;
546
+
seq_printf(m, "%u uvd vclk: %u dclk: %u\n", uvd_index, vclk, dclk);
547
+
}
548
+
}
549
+
550
+
seq_printf(m, "vce %sabled\n", pi->vce_power_gated ? "dis" : "en");
551
+
if (!pi->vce_power_gated) {
552
+
if (vce_index >= CZ_MAX_HARDWARE_POWERLEVELS) {
553
+
seq_printf(m, "invalid vce dpm level %d\n", vce_index);
554
+
} else {
555
+
ecclk = vce_table->entries[vce_index].ecclk;
556
+
seq_printf(m, "%u vce ecclk: %u\n", vce_index, ecclk);
557
+
}
520
558
}
521
559
}
522
560
+4
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+4
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
···
2632
2632
struct drm_device *dev = crtc->dev;
2633
2633
struct amdgpu_device *adev = dev->dev_private;
2634
2634
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2635
+
unsigned type;
2635
2636
2636
2637
switch (mode) {
2637
2638
case DRM_MODE_DPMS_ON:
···
2641
2640
dce_v10_0_vga_enable(crtc, true);
2642
2641
amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2643
2642
dce_v10_0_vga_enable(crtc, false);
2643
+
/* Make sure VBLANK interrupt is still enabled */
2644
+
type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
2645
+
amdgpu_irq_update(adev, &adev->crtc_irq, type);
2644
2646
drm_vblank_post_modeset(dev, amdgpu_crtc->crtc_id);
2645
2647
dce_v10_0_crtc_load_lut(crtc);
2646
2648
break;
+4
drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+4
drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
···
2631
2631
struct drm_device *dev = crtc->dev;
2632
2632
struct amdgpu_device *adev = dev->dev_private;
2633
2633
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2634
+
unsigned type;
2634
2635
2635
2636
switch (mode) {
2636
2637
case DRM_MODE_DPMS_ON:
···
2640
2639
dce_v11_0_vga_enable(crtc, true);
2641
2640
amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2642
2641
dce_v11_0_vga_enable(crtc, false);
2642
+
/* Make sure VBLANK interrupt is still enabled */
2643
+
type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
2644
+
amdgpu_irq_update(adev, &adev->crtc_irq, type);
2643
2645
drm_vblank_post_modeset(dev, amdgpu_crtc->crtc_id);
2644
2646
dce_v11_0_crtc_load_lut(crtc);
2645
2647
break;
+48
drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
+48
drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
···
35
35
#include "oss/oss_2_0_d.h"
36
36
#include "oss/oss_2_0_sh_mask.h"
37
37
#include "gca/gfx_8_0_d.h"
38
+
#include "smu/smu_7_1_2_d.h"
39
+
#include "smu/smu_7_1_2_sh_mask.h"
38
40
39
41
#define GRBM_GFX_INDEX__VCE_INSTANCE__SHIFT 0x04
40
42
#define GRBM_GFX_INDEX__VCE_INSTANCE_MASK 0x10
···
114
112
115
113
mutex_lock(&adev->grbm_idx_mutex);
116
114
for (idx = 0; idx < 2; ++idx) {
115
+
116
+
if (adev->vce.harvest_config & (1 << idx))
117
+
continue;
118
+
117
119
if(idx == 0)
118
120
WREG32_P(mmGRBM_GFX_INDEX, 0,
119
121
~GRBM_GFX_INDEX__VCE_INSTANCE_MASK);
···
196
190
return 0;
197
191
}
198
192
193
+
#define ixVCE_HARVEST_FUSE_MACRO__ADDRESS 0xC0014074
194
+
#define VCE_HARVEST_FUSE_MACRO__SHIFT 27
195
+
#define VCE_HARVEST_FUSE_MACRO__MASK 0x18000000
196
+
197
+
static unsigned vce_v3_0_get_harvest_config(struct amdgpu_device *adev)
198
+
{
199
+
u32 tmp;
200
+
unsigned ret;
201
+
202
+
if (adev->flags & AMDGPU_IS_APU)
203
+
tmp = (RREG32_SMC(ixVCE_HARVEST_FUSE_MACRO__ADDRESS) &
204
+
VCE_HARVEST_FUSE_MACRO__MASK) >>
205
+
VCE_HARVEST_FUSE_MACRO__SHIFT;
206
+
else
207
+
tmp = (RREG32_SMC(ixCC_HARVEST_FUSES) &
208
+
CC_HARVEST_FUSES__VCE_DISABLE_MASK) >>
209
+
CC_HARVEST_FUSES__VCE_DISABLE__SHIFT;
210
+
211
+
switch (tmp) {
212
+
case 1:
213
+
ret = AMDGPU_VCE_HARVEST_VCE0;
214
+
break;
215
+
case 2:
216
+
ret = AMDGPU_VCE_HARVEST_VCE1;
217
+
break;
218
+
case 3:
219
+
ret = AMDGPU_VCE_HARVEST_VCE0 | AMDGPU_VCE_HARVEST_VCE1;
220
+
break;
221
+
default:
222
+
ret = 0;
223
+
}
224
+
225
+
return ret;
226
+
}
227
+
199
228
static int vce_v3_0_early_init(void *handle)
200
229
{
201
230
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
231
+
232
+
adev->vce.harvest_config = vce_v3_0_get_harvest_config(adev);
233
+
234
+
if ((adev->vce.harvest_config &
235
+
(AMDGPU_VCE_HARVEST_VCE0 | AMDGPU_VCE_HARVEST_VCE1)) ==
236
+
(AMDGPU_VCE_HARVEST_VCE0 | AMDGPU_VCE_HARVEST_VCE1))
237
+
return -ENOENT;
202
238
203
239
vce_v3_0_set_ring_funcs(adev);
204
240
vce_v3_0_set_irq_funcs(adev);
+1
drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
+1
drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
+6
-6
drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c
+6
-6
drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c
···
313
313
314
314
pm_runtime_enable(dev->dev);
315
315
316
+
ret = drm_vblank_init(dev, 1);
317
+
if (ret < 0) {
318
+
dev_err(dev->dev, "failed to initialize vblank\n");
319
+
goto err_periph_clk_disable;
320
+
}
321
+
316
322
ret = atmel_hlcdc_dc_modeset_init(dev);
317
323
if (ret < 0) {
318
324
dev_err(dev->dev, "failed to initialize mode setting\n");
···
326
320
}
327
321
328
322
drm_mode_config_reset(dev);
329
-
330
-
ret = drm_vblank_init(dev, 1);
331
-
if (ret < 0) {
332
-
dev_err(dev->dev, "failed to initialize vblank\n");
333
-
goto err_periph_clk_disable;
334
-
}
335
323
336
324
pm_runtime_get_sync(dev->dev);
337
325
ret = drm_irq_install(dev, dc->hlcdc->irq);
+1
-4
drivers/gpu/drm/drm_crtc.c
+1
-4
drivers/gpu/drm/drm_crtc.c
···
5398
5398
if (encoder->funcs->reset)
5399
5399
encoder->funcs->reset(encoder);
5400
5400
5401
-
list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5402
-
connector->status = connector_status_unknown;
5403
-
5401
+
list_for_each_entry(connector, &dev->mode_config.connector_list, head)
5404
5402
if (connector->funcs->reset)
5405
5403
connector->funcs->reset(connector);
5406
-
}
5407
5404
}
5408
5405
EXPORT_SYMBOL(drm_mode_config_reset);
5409
5406
+19
-7
drivers/gpu/drm/i915/intel_uncore.c
+19
-7
drivers/gpu/drm/i915/intel_uncore.c
···
1274
1274
struct drm_i915_private *dev_priv = dev->dev_private;
1275
1275
struct drm_i915_reg_read *reg = data;
1276
1276
struct register_whitelist const *entry = whitelist;
1277
+
unsigned size;
1278
+
u64 offset;
1277
1279
int i, ret = 0;
1278
1280
1279
1281
for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
1280
-
if (entry->offset == reg->offset &&
1282
+
if (entry->offset == (reg->offset & -entry->size) &&
1281
1283
(1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
1282
1284
break;
1283
1285
}
···
1287
1285
if (i == ARRAY_SIZE(whitelist))
1288
1286
return -EINVAL;
1289
1287
1288
+
/* We use the low bits to encode extra flags as the register should
1289
+
* be naturally aligned (and those that are not so aligned merely
1290
+
* limit the available flags for that register).
1291
+
*/
1292
+
offset = entry->offset;
1293
+
size = entry->size;
1294
+
size |= reg->offset ^ offset;
1295
+
1290
1296
intel_runtime_pm_get(dev_priv);
1291
1297
1292
-
switch (entry->size) {
1298
+
switch (size) {
1299
+
case 8 | 1:
1300
+
reg->val = I915_READ64_2x32(offset, offset+4);
1301
+
break;
1293
1302
case 8:
1294
-
reg->val = I915_READ64(reg->offset);
1303
+
reg->val = I915_READ64(offset);
1295
1304
break;
1296
1305
case 4:
1297
-
reg->val = I915_READ(reg->offset);
1306
+
reg->val = I915_READ(offset);
1298
1307
break;
1299
1308
case 2:
1300
-
reg->val = I915_READ16(reg->offset);
1309
+
reg->val = I915_READ16(offset);
1301
1310
break;
1302
1311
case 1:
1303
-
reg->val = I915_READ8(reg->offset);
1312
+
reg->val = I915_READ8(offset);
1304
1313
break;
1305
1314
default:
1306
-
MISSING_CASE(entry->size);
1307
1315
ret = -EINVAL;
1308
1316
goto out;
1309
1317
}
+2
-1
drivers/gpu/drm/ttm/ttm_bo_util.c
+2
-1
drivers/gpu/drm/ttm/ttm_bo_util.c
···
490
490
else if (boot_cpu_data.x86 > 3)
491
491
tmp = pgprot_noncached(tmp);
492
492
#endif
493
-
#if defined(__ia64__) || defined(__arm__) || defined(__powerpc__)
493
+
#if defined(__ia64__) || defined(__arm__) || defined(__aarch64__) || \
494
+
defined(__powerpc__)
494
495
if (caching_flags & TTM_PL_FLAG_WC)
495
496
tmp = pgprot_writecombine(tmp);
496
497
else
+2
include/uapi/drm/amdgpu_drm.h
+2
include/uapi/drm/amdgpu_drm.h
+8
include/uapi/drm/i915_drm.h
+8
include/uapi/drm/i915_drm.h
···
1070
1070
__u64 offset;
1071
1071
__u64 val; /* Return value */
1072
1072
};
1073
+
/* Known registers:
1074
+
*
1075
+
* Render engine timestamp - 0x2358 + 64bit - gen7+
1076
+
* - Note this register returns an invalid value if using the default
1077
+
* single instruction 8byte read, in order to workaround that use
1078
+
* offset (0x2538 | 1) instead.
1079
+
*
1080
+
*/
1073
1081
1074
1082
struct drm_i915_reset_stats {
1075
1083
__u32 ctx_id;