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drm/amd/pm/powerplay/smumgr: Fix PCIeBootLinkLevel value on Fiji

Previously this was initialized with zero which represented PCIe Gen
1.0 instead of using the
maximum value from the speed table which is the behaviour of all other
smumgr implementations.

Fixes: 18edef19ea44 ("drm/amd/powerplay: implement fw image related smu interface for Fiji.")
Signed-off-by: John Smith <itistotalbotnet@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit c52238c9fb414555c68340cd80e487d982c1921c)

authored by

John Smith and committed by
Alex Deucher 07a13f91 238d468d

+1 -1
+1 -1
drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
··· 2024 2024 table->VoltageResponseTime = 0; 2025 2025 table->PhaseResponseTime = 0; 2026 2026 table->MemoryThermThrottleEnable = 1; 2027 - table->PCIeBootLinkLevel = 0; /* 0:Gen1 1:Gen2 2:Gen3*/ 2027 + table->PCIeBootLinkLevel = (uint8_t) (data->dpm_table.pcie_speed_table.count); 2028 2028 table->PCIeGenInterval = 1; 2029 2029 table->VRConfig = 0; 2030 2030